Semiconductor device manufacturing method and plasma processing method

Abstract

The present disclosure provides technology whereby after performing vertical etching of a metal layer comprising a work function metal and a gate embedding metal in a metal gate cutting process for selectively etching a gate laminate film with respect to a gate side wall spacer and an interlayer insulating film for a source-drain region, it is possible to protect the side wall by means of a first insulating film, remove the residue of the metal layer exposed on a lower part of a cut region, additionally protect the side wall of the cut region by means of a second insulating film, and remove a gate insulating film exposed on a bottom part of the cut region. The present disclosure additionally provides technology that makes it possible to continuously execute this series of steps in the same device.

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a plasma processing method. [Background technology]

[0002] To continuously improve the functionality and performance of integrated circuit chips, there is a continuing demand for higher integration of transistors. To date, higher integration of transistors has been achieved primarily by miniaturizing transistor elements. To achieve element miniaturization while maintaining or improving transistor performance, numerous improvements have been made to transistor structures and the materials that make up transistors. These improvements include, for example, the reduction in the size of the source and drain regions in metal oxide semiconductor field effect transistors (MOSFETs). These include the introduction of strain into the drain region, the introduction of high dielectric gate insulating films and metals, and a change in device structure from a planar type to a fin type with a three-dimensional structure. As miniaturization progresses further, it is predicted that the channel will become a wire-like or sheet-like laminate, and the periphery of the channel will be covered with a gate, resulting in a gate-all-around FET (GAA).

[0003] These improvements are due to the short channel effect that occurs when transistor size is reduced, i.e., leakage current between the source and drain electrodes, which are closer together, even when the transistor is off. This technology was introduced to suppress the phenomenon of short-channel effect, which is a technological improvement that allows for transistor miniaturization while preventing the degradation of transistor characteristics due to the short-channel effect. However, as miniaturization continues, the short-channel effect will eventually become unavoidable, making further miniaturization difficult.

[0004] To solve the above problems, transistor high integration techniques that do not rely solely on transistor miniaturization are beginning to be applied. The most effective technique is to reduce the distance between transistors. In conventional integration, the distance between adjacent transistors has been reduced at roughly the same rate as the reduction in transistor size, but by reducing the transistor spacing even more than the rate of reduction in transistor size, even higher integration is possible. In other words, even if the speed of transistor miniaturization slows, the high integration speed of transistors can be maintained by reducing the spacing between transistors even more than the rate of transistor size miniaturization. However, since the reduction in transistor spacing requires changes to the layout rules that are determined taking into account transistor characteristics, yield, etc., a corresponding change in the process is required. The reduction in transistor spacing and the accompanying change in process are called DTCO (Design and Technology Co-Optimization), and are currently This will become a technological concept that will become even more important as transistor integration increases.

[0005] Non-Patent Document 1 describes a metal gate cut technology, which is one of the DTCO technologies. This technology involves burying a high-k gate insulating film, a work function control metal, and a gate buried metal in the gate region, and then vertically etching the gate. Conventionally, the gate cut process has been carried out using polycrystalline silicon (poly-Si) The dummy gate is cut, and the cut area is filled with an insulating film. Then, the poly-Si dummy gate is Remove the gate stacked film (gate insulating film / work function metal / gate buried metal) In the conventional method, a gate insulating film is embedded between the Fin channel of a FinFET or the sheet channel of a GAA FET and the insulating film plug formed in the cut region. Since it is necessary to fill the layer film, the distance between the channel and the plug needs to be at least twice the total thickness of the gate stack film. Since the gate cut process will be performed later, the above channel-plug spacing is In other words, it is possible to reduce the distance between transistors via insulating film plugs without reducing the transistor size.

[0006] Patent Document 1 discloses a specific example of the metal gate cut process. In the FinFET process with a gate electrode, after forming the Fin channel, element isolation insulating film, dummy gate, gate sidewall spacer, source and drain, and interlayer insulating film in the source and drain region, the dummy gate is removed and replaced with a gate stacked film, and then the gate stacked film is cut by dry etching using a gate cut mask. At this time, the gate buried metal, work function metal, and gate insulating film that make up the gate stacked film are removed from the insulating film that makes up the periphery of the gate. This is done selectively to etch the gate sidewall spacers and the interlayer insulating film in the source and drain regions. By using selective etching conditions, it is possible to etch only the gate even if the gate cut mask extends beyond the gate in the direction perpendicular to the gate. In other words, it is not necessary to match the gate cut mask width in the direction perpendicular to the gate to the gate length, i.e., the gate wiring width, allowing for a mask design with ample margin.

[0007] Patent Document 2 discloses a specific example of the metal gate cut process, in which etching for gate cutting is performed under non-selective conditions with respect to the peripheral insulating film. When vertically etching the gate stack film, the gate sidewall spacers and the interlayer insulating film in the source / drain regions exposed in areas not covered by the gate cut mask are etched simultaneously with the gate stack film. By simultaneously etching the gate sidewalls, it is possible to suppress the generation of residues of the gate stack film that tend to remain on the gate sidewalls. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] European Patent Application Publication No. 3836226 [Patent Document 2] US Patent Application Publication No. 2020 / 0135472 [Non-patent literature]

[0009] [Non-Patent Document 1] A. Greene, et al., “Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction”, Proceedings of VLSI Symposium 2019, 2019, pp. T144~T145 Summary of the Invention [Problem to be solved by the invention]

[0010] When applying the metal gate cut process disclosed in Patent Document 1, vertical etching of the gate stacked film is selectively performed on the gate sidewall spacer and the interlayer insulating film in the source / drain region, so hole processing is required to open the area surrounded by the gate cut width and gate length (gate wiring width). This results in etching with a large aspect ratio, and the gate stacked film is likely to remain at the bottom of the hole. In particular, the film deposited on the sidewall of the spacer is even more difficult to remove at the bottom of the hole. The film deposited on the sidewall of the spacer, such as a work function metal or gate buried metal, is likely to remain along the sidewall of the spacer. If the metal film remains as an etching residue, the cut gates may be electrically connected to each other at the bottom of the cut region, which may cause an electrical short circuit.

[0011] In the metal gate cut process disclosed in Patent Document 2, the gate stack film, gate sidewall spacers adjacent to the gate, and the interlayer insulating film in the source / drain regions are simultaneously etched. Therefore, the etched area during gate cut has a linear shape extending vertically toward the gate. Compared to the hole-shaped process described in Patent Document 1, the aspect ratio is lower, making etching the gate stack film easier. In particular, since the gate sidewall spacers are simultaneously etched, the gate stack film remains on the spacer sidewalls, eliminating the possibility of complete removal of the gate stack film. This prevents electrical shorts between the cut gates. However, since the interlayer insulating film in the source / drain regions is also simultaneously etched, shortening the distance between the channel and the cut region also etchs part of the epitaxial layer constituting the source / drain, reducing the surface area and volume of the source / drain. This raises concerns about reduced contact area and contact resistance when connecting a metal contact layer to the source / drain. Furthermore, since the epitaxial growth layer often has the role of applying strain to the source and drain to improve the mobility of carriers propagating through the channel, there is a concern that the amount of strain will decrease if the epitaxial growth layer is partially removed by etching, resulting in deterioration of transistor characteristics. Furthermore, if the epitaxial growth layer is exposed during the process and etching damages the exposed surface, there is a possibility that defects will occur in the epitaxial layer in subsequent processes. Therefore, in order to eliminate these concerns, it becomes necessary to widen the distance between the channel and the gate cut region to some extent. That is, in the metal gate cut process disclosed in Patent Document 2, the channel-gate cut region, which leads to high integration of transistors, is There is a concern that reducing the distance between the transistor regions may result in a trade-off between transistor characteristics and process reproducibility.

[0012] The present disclosure provides a metal gate cut process that selectively etches a gate stack film relative to gate sidewall spacers and interlayer insulating films in source and drain regions, and achieves a work function metal The present disclosure aims to provide a technology that can vertically etch a metal layer consisting of a gate insulating film and a gate buried metal, protect the sidewalls with a first insulating film, remove the residue of the metal layer exposed at the bottom of the cut region, and further protect the sidewalls of the cut region with a second insulating film and remove the gate insulating film exposed at the bottom of the cut region.The present disclosure also aims to provide a technology that can continuously perform these series of steps using the same equipment. [Means for solving the problem]

[0013] A brief summary of representative aspects of this disclosure is as follows.

[0014] One embodiment of the present disclosure includes: A method for manufacturing a semiconductor device having a fin-shaped, wire-shaped, or sheet-shaped channel, in which a gate stacked film formed by stacking a gate insulating film and a metal layer is formed on the channel, by vertically cutting the gate stacked film to insulate and separate gate structures from each other with an insulating film, the method comprising the steps of: a first step of etching the metal layer in the vertical direction to form a cut region; a second step of depositing a first protective insulating film on a side wall of the cut region; a third step of anisotropically etching the first protective insulating film to expose the gate insulating film in the cut region; and a third step of isotropically etching the metal layer to form a gate insulating film. a fourth step of removing a part of a layer; a fifth step of depositing a second protective insulating film different from the first protective insulating film on a sidewall of the cut region; a sixth step of anisotropically etching the second protective insulating film to expose the gate insulating film in the cut region; and a seventh step of removing the exposed part of the gate insulating film in the cut region, wherein the gate structure is formed from the gate stack film and is oriented in a direction perpendicular to the orientation direction of the channel, and gate sidewall spacers are formed on the sidewalls of the gate structure. [Effects of the Invention]

[0015] According to one embodiment of the present disclosure, in a metal gate cut process, it is possible to prevent the gate stack film from remaining on the sidewall of the spacer while maintaining conditions for selectively etching the gate stack film with respect to the gate sidewall spacer and the interlayer insulating film of the source / drain region. That is, the distance between the Fin channel of a FinFET or the sheet-like channel of a GAA FET and the gate cut region can be reduced. Furthermore, the device characteristics allow multiple steps for implementing the metal gate cut process to be performed in a continuous process using the same device, making it possible to suppress an increase in the number of process steps.

[0016] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a bird's-eye view showing the manufacturing steps of a metal gate cut process in the FET of Example 1. FIG. [Figure 2]1A to 1C are plan views showing the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 3A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 3B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 4A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 4B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 5A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 5B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 6A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 6B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 7A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 7B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 8A]1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 8B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 9A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 9B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 10A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 10B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 11A] 1A to 1C are cross-sectional views of the gate region of a transistor in a direction parallel to the gate, illustrating the manufacturing steps of the metal gate cut process in the FET of Example 1. [Figure 11B] 4A to 4C are cross-sectional views of a gate cut region in a direction perpendicular to the gate, illustrating the manufacturing steps of a metal gate cut process in the FET of Example 1. [Figure 12] FIG. 1 is a flow diagram of a manufacturing process of a metal gate cut process in the FET of Example 1. [Figure 13A] 10 is a cross-sectional view of the gate region of the transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 1. FIG. [Figure 13B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in the FET of Example 1. FIG. [Figure 14A]10 is a cross-sectional view of the gate region of the transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 1. FIG. [Figure 14B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in the FET of Example 1. FIG. [Figure 15A] 10 is a cross-sectional view of the gate region of the transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 1. FIG. [Figure 15B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in the FET of Example 1. FIG. [Figure 16] FIG. 1 is a diagram illustrating an example of the configuration of a plasma processing apparatus. [Figure 17A] 10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 2. FIG. [Figure 17B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET according to Example 2. FIG. [Figure 18A] 10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 2. FIG. [Figure 18B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET according to Example 2. FIG. [Figure 19A] 10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 2. FIG. [Figure 19B]10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET according to Example 2. FIG. [Figure 20] FIG. 10 is a flow diagram of the manufacturing steps of a metal gate cut process in the FET of Example 2. [Figure 21A] 10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 3. FIG. [Figure 21B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET according to Example 3. FIG. [Figure 22A] 10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 3. FIG. [Figure 22B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET according to Example 3. FIG. [Figure 23A] 10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 4. FIG. [Figure 23B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET of Example 4. FIG. [Figure 24A] 10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 4. FIG. [Figure 24B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET of Example 4. FIG. [Figure 25A]10 is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, illustrating a gate insulating film removal step in the metal gate cut process in the FET of Example 4. FIG. [Figure 25B] 10 is a cross-sectional view of a gate cut region of a transistor in a direction perpendicular to the gate, illustrating a gate insulating film removal step in a metal gate cut process in a FET of Example 4. FIG. [Figure 26] FIG. 10 is a flow diagram of the manufacturing steps of the metal gate cut process in the FET of Example 4. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the examples described below, and various modifications are possible within the scope of its technical concept. In all drawings used to explain the examples, components having the same function are designated by the same reference numerals, and repeated description of such components may be omitted. It goes without saying that many modifications are possible to the contents disclosed as the present examples, such as changing the combination of materials and manufacturing processes. The drawings are not necessarily drawn to scale, and important parts are depicted schematically to emphasize the logic. The drawings may be more schematic than the actual embodiment for clarity of explanation, but they are merely examples and do not limit the interpretation of the present disclosure. [Example]

[0019] In Example 1, a metal gate cut process in a manufacturing process (a semiconductor device manufacturing method or a plasma processing method) of a Fin type FET (Fin type Field Effect Transistor) or a Gate All Around type FET (Gate All Around type Field Effect Transistor) as a semiconductor device, and a process in which a plurality of sidewall protective films made of different materials are stacked in the above process, thereby selectively etching a gate stacked film containing metal relative to surrounding films and removing metal residues in the cut region, will be described in detail. First, the above process will be described using Figures 1, 2, 3A to 11A, 3B to 11B, 12, 13A to 15A, and 13B to 15B. The semiconductor device manufacturing method or plasma processing method described in this example is a method for forming a fin-shaped channel in a gate formation region, or a thin wire-shaped or ... This is a method for forming a Fin-type FET or a GAA-type FET having a sheet-like channel, a gate cut between the channels, and the cut region being insulated and separated by an insulating film.

[0020] 1 and 2 are a bird's-eye view and a plan view, respectively, of a structure immediately before the metal gate cut process in the manufacturing process of a FinFET or a GAAFET. FIGS. 3A to 11A are cross-sectional views of the gate region of a transistor in a direction parallel to the gate (line AA' in FIGS. 1 and 2), showing a series of steps in the metal gate cut process, excluding the step of removing the gate insulating film remaining on the gate sidewall spacers. FIGS. 3B to 11B are cross-sectional views of the gate cut region in a direction perpendicular to the gate (line BB' in FIGS. 1 and 2), showing a series of steps in the metal gate cut process, excluding the step of removing the gate insulating film remaining on the gate sidewall spacers. FIG. 12 is a flow diagram of the series of manufacturing steps shown in FIGS. 3A to 11A and 3B to 11B. FIGS. 13A to 15A are cross-sectional views of the gate region of a transistor in a direction parallel to the gate (line AA' in FIGS. 1 and 2), showing the step of removing the gate insulating film remaining on the gate sidewall spacers after the metal gate cut process shown in FIG. 12. 13B to 15B are cross-sectional views of the gate cut region (line BB' in FIGS. 1 and 2) in a direction perpendicular to the gate, showing the step of removing the gate insulating film remaining on the gate sidewall spacer after the metal gate cut process shown in FIG.

[0021] In FIG. 1, a single crystal semiconductor substrate 1 has a periodic or equivalent line pattern. On the semiconductor substrate 1, an element isolation (STI: Shallow Trench Isolation) insulating film (STI insulating film) constituting an element isolation region is formed. The height of the STI insulating film 2 is set so that the fin channel is partially exposed. The gate region oriented in the direction perpendicular to the fin channel is formed on the STI insulating film 2. The STI insulating film 2 is provided on the fin-type channel exposed on the upper portion thereof with a gate insulating film 3, a work The function metal 4 and the gate buried metal 5 are stacked in this order. A gate sidewall spacer 6 is formed on the sidewall, and the STI insulating film 2 and the gate sidewall spacer An etching stopper layer 7 and an interlayer insulating film 8 for the source / drain region are deposited on the region surrounded by the spacer 6. A hard mask layer 9 with a patterned gate cut region is formed on the gate stacked film consisting of the gate insulating film 3, work function metal 4, and gate buried metal 5, as well as on the gate sidewall spacer 6, etching stopper layer 7, and interlayer insulating film 8 for the source / drain region. In other words, the gate structure is formed by The fin-type channel is oriented in a direction perpendicular to the direction of the fin-type channel. The channel structure can be configured to include fin-, wire-, or sheet-like channels on a semiconductor substrate.

[0022] The semiconductor substrate 1 may be made of, for example, silicon (Si), or may be made of silicon germanium (Si) on Si. The substrate may be a silicon germanium (SiGe) substrate, or a silicon on insulator (SOI) substrate using a laminated film of an insulating film such as silicon oxide (SiO2) and a silicon layer on a silicon substrate. The process for forming the fin-type channel is patterning using lithography technology. A technique is used in which the substrate is etched in the vertical direction after etching. For patterning, when a laser using argon fluoride gas (ArF) as a light source is used, for example, self-aligned double patterning (SADP) can be used if the pattern period is, for example, 40 nm or more and 80 nm or less. Also, self-aligned quadruple patterning (SAQP) can be used if the pattern period is, for example, 20 nm or more and 40 nm or less. Furthermore, when extreme ultraviolet (EUV) exposure with a wavelength of 13.5 nm is performed, single exposure can be used if the pattern period is, for example, 40 nm or more. (Single Patterning) can be used. The pattern period is, for example, 20 nm or more and 40 nm or more. In the case of FinFET, one transistor is composed of one or more Fin channels, but the two Fin channels shown in Figure 1 belong to different transistors. In this case, The distance between the two fin-type channels is designed to be wider than the minimum distance between the patterns, and is formed by removing one or more fins by etching after forming the pattern structure.

[0023] The STI insulating film 2 is formed by depositing an insulating film such as an SiO2 film, a silicon oxynitride film (SiON), or a silicon carbon oxide film (SiCO) by chemical vapor deposition (CVD). The insulating film 2 is then etched back until a part of the fin-type channel is exposed.

[0024] The gate sidewall spacers 6 are formed on the sidewalls of a dummy gate (not shown). The dummy gate is formed by depositing an insulating film of SiO2 or the like on the Fin-type channel and the STI insulating film 2. A dummy gate insulating film consisting of amorphous silicon or polycrystalline silicon is deposited, and a periodic or equivalent line pattern oriented perpendicular to the fin channel is formed. The patterning is performed by single exposure using the ArF light source or SA. The DP technique is used depending on the pattern period. The size of the gate pattern is preferably set, for example, in the range of 40 nm to 70 nm for the gate pitch and 10 nm to 30 nm for the width of the dummy gate, i.e., the gate length. On the dummy gate, a low dielectric constant film such as a SiON film, a silicon carbon oxynitride film (SiOCN), or a SiCO film is formed by using a CVD method or the like, and then etched back. The gate sidewall spacer 6 is obtained. The thickness of the gate sidewall spacer 6 is, for example, in the range of 5 nm to 15 nm. It would be good to adjust it to.

[0025] The etching stopper layer 7 and the interlayer insulating film 8 in the source / drain region form the source / drain (not shown) of the transistor after the gate sidewall spacer 6 is formed. The sidewall spacer 6 and the STI insulating film 2 are sequentially stacked on the region surrounded by the sidewall spacer 6 and the STI insulating film 2. The etching stopper layer 7 can be obtained by depositing a silicon nitride film (SiN), a silicon carbon nitride film (SiCN), a SiOCN film, a SiON film, or the like using a CVD method or the like. The thickness of the etching stopper layer 7 is preferably adjusted to, for example, a range of 2 nm to 10 nm. The interlayer insulating film 8 is formed so as to fill the source-drain region surrounded by the gate sidewall spacers 6 outside the gate region, and is made of a material such as an SiO2 film, an SiON film, or an SiOCN film. It is preferable to use a CVD method or the like as the film formation method.

[0026] A gate stacked film consisting of a gate insulating film 3, a work function metal 4, and a gate buried metal 5 is formed on the fin channel after removing the dummy gate and the dummy gate insulating film. The dummy gate is removed by chemical mechanical polishing ( The dummy gate is exposed using CMP (Chemical Mechanical Polishing), and the dummy gate is The gate stacked film is formed by, for example, a CVD method or an ALD (Atomic Layer Deposition) method. The gate insulating film 3 may be made of a high dielectric material such as hafnium oxide (HfO2) or aluminum oxide (Al2O3), or a laminated film of these high dielectric materials. The thickness may be adjusted in the range of 1 nm to 3 nm, for example. The work function metal 4 is determined in consideration of the target transistor performance or the conductivity type of the transistor. For example, the work function metal 4 that determines the threshold voltage of a p-type FET may be titanium nitride (TiN) or tantalum. It is preferable to use a nitride film (TaN) or a metal compound having a work function equivalent to these. The work function metal 4 that determines the threshold voltage of the n-type FET is, for example, titanium aluminum (TiAl). Or TiAl containing carbon (C), oxygen (O), nitrogen (N), etc., or metals equivalent to these. It is recommended to use a metal compound having a work function of The gate burying metal 5 is deposited for the purpose of reducing the metal resistance in the gate. For example, a material such as tungsten (W) can be used.

[0027] After forming the gate stacked film, the work function metal 4 or the gate buried metal 5 is deposited. The surface is planarized using CMP as a mask, and a hard mask 9 is deposited. A resist (not shown) is deposited on the hard mask 9, and patterning is performed through the resist to open the gate cut region. The resist is then removed to obtain the structure shown in Figure 1. Here, the resist is preferably a three-layer resist consisting of a spin-on carbon film, a spin-on glass film, and an organic resist. The spin-on carbon film is an organic film mainly composed of carbon, and the spin-on glass film is an organic film containing Si and oxygen. Typically, in processing using a three-layer resist, the spin-on glass film is etched using the resist, and the spin-on carbon film is etched using the spin-on glass film as a mask. After that, the resist and the spin-on glass film are removed, and the spin-on carbon film is used as a mask. In this case, the hard mask 9 is mainly composed of the spin-on carbon film. The mask 9 may be an insulating film such as an SiO2 film or a silicon nitride film (Si3N4). In this case, a three-layer resist is deposited on the hard mask 9, and then patterned, and the hard mask is etched. The three-layer resist is then removed by processing to obtain the structure shown in Figure 1. The gate cut pattern is oriented in a direction perpendicular to the gate, and after patterning, the surfaces of the gate sidewall spacer 6, etching stopper layer 7, and interlayer insulating film 8 may be exposed together with the gate stacked film. The bit width may be set in the range of 10 nm to 30 nm, for example.

[0028] Although FIG. 1 shows an example of a configuration using a Fin-type FET, a GAA-type FET may also be used. In this case, the channel has a structure in which wire-shaped or sheet-shaped semiconductor layers are stacked. The stacked channel structure is, for example, a Fin-type FET using a stacked film in which Si layers and SiGe layers are repeatedly and alternately formed. After removing the dummy gate and the dummy gate insulating film, the SiGe layer is selectively etched away relative to the Si layer.

[0029] 2 shows a plan view of the bird's-eye view shown in FIG. 1 viewed from above. In the gate region sandwiched between different gate sidewall spacers 6, a gate insulating film 3, a work function metal 4, and a gate buried metal 5 are sequentially formed from the sidewalls of the gate sidewall spacers 6 to fill the gate. Outside the gate sidewall spacers 6, an etching stopper layer 7 and an interlayer insulating film 8 for the source / drain region are formed. In the region opened by the hard mask 9, the gate sidewall spacer 6, gate insulating film 3, work function metal 4, gate buried metal 5, etching stop It is preferable that the insulating layer 7 and the interlayer insulating film 8 are exposed.

[0030] 3A and 3B are cross-sectional views of the gate region of the transistor in the direction parallel to the gate (line AA' in FIGS. 1 and 2) and the gate cut region in the direction perpendicular to the gate (line BB' in FIGS. 1 and 2), respectively, in the structures shown in FIGS. 1 and 2. As shown in FIG. 3B, the gate region surrounded by the gate sidewall spacer 6 has a shape that widens near the bottom. This is because the dummy gate pattern that serves as the base when the gate sidewall spacer 6 is formed is This is because the thin film tends to have a tapered shape with a wide base when processed using dry etching.

[0031] From the structure shown in FIGS. 3A and 3B, the gate buried metal 5 and the work function metal 4 are Then, an anisotropic etch is formed in the vertical direction along the gate cut pattern opened by the hard mask 9. The structure shown in Figures 4A and 4B is obtained by etching the gate buried metal 5 and the work function metal 4. For anisotropic etching of the gate buried metal 5 and the work function metal 4, for example, tetrafluoromethane (CF4), trifluoromethane (CHF3), or boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), or other halogen-based gases, or mixed gases of these, or mixed gases of these with oxygen (O2), nitrogen (N2), argon (Ar), helium (He), or methane (CH4), etc. may be used. The etching is performed by removing the hard mask 9, the gate sidewall spacer 6, the etching stopper layer 7, and the silicon dioxide film. The etching is performed under conditions that result in selective etching of the interlayer insulating film 8 of the source / drain region. For example, when selectively etching the gate buried metal 5, the gate buried metal 5 is formed by etching the W-centered metal. When the work function metal 4 is made of a material that is different from the work function metal 4, it is recommended to use a mixture of CHF3 and O2 or a gas equivalent to that. For example, if the work function metal 4 is TiAl or TiAl with C, O, N, etc., it is recommended to use a mixture of CF4 and O2, Cl2 and Ar, or Cl2, O2, or He. When the work function metal 4 is made of a material containing CF4, the etching gas may be a mixture of CF4 and Cl2, a mixture of CF4 and HCl, or a mixture of these gases with Ar, He, N2, etc. 4A and 4B corresponds to gate metal vertical etching 101 in the process flow diagram of FIG. 12. The gate metal vertical etching 101 is performed by etching the gate insulating film 3 as a stopper. Therefore, as shown in FIG. 4A, after the etching, the upper surface of the gate insulating film 3 is exposed at the bottom of the gate cut region. The gate sidewall spacer 6 has a tapered shape with a wider base near the bottom. After the gate metal vertical etching 101, the work function metal 4 and the gate buried metal 5 tend to remain in the tapered portion.

[0032] In FIG. 5A and FIG. 5B, the ALD (Atomic Layer Deposition) method The first protective insulating film 10 is deposited by a film forming technique using the hard mask 9. The upper surface and sidewall of the gate insulating film 3, the sidewall of the gate buried metal 5, and the work The protective insulating film 10 is deposited on the sidewalls of the function metal 4, the upper surface of the gate sidewall spacer 6, the upper surface of the etching stopper layer 7, and the upper surface of the interlayer insulating film 8 in the source / drain region. The materials are the hard mask 9, the gate insulating film 3, the gate sidewall spacer 6, the etching stopper In consideration of the etching selectivity with respect to the layer 7, the interlayer insulating film 8, etc., it is desirable that the insulating film contains nitrogen, for example, a Si3N4 film or a SiON film equivalent thereto. The thickness is controlled to, for example, about 2 nm to 3 nm. The ALD method has the advantage that a thin film can be formed with good control even on a complex shape with many irregularities. When the protective insulating film 10 is a Si3N4 film formed by the ALD method, for example, bis(tert-butylamino)silane (Bis(tertbutylamino)silane: BTBAS), bis(diethylamino)silane (Bis(DiEthylAmino)Silane: BDEAS), or dichlorosilane (SiH2Cl2) is used as the Si source, and N2 gas or a mixed gas of N2 gas and hydrogen gas (H2), or a gas containing nitrogen such as ammonia (NH3) gas is used as the nitrogen source. The protective insulating film 10 may be a film that does not contain nitrogen, such as SiO2, or may be formed by a CVD method or the like. The gate height in the direction perpendicular to the substrate is designed to be in the range of approximately 50 nm to 200 nm. is about 10 nm to 30 nm, but as transistors become more highly integrated, the gate cut width shrinks, resulting in an etching pattern with a pattern width of about 10 nm and a depth of about 200 nm. When the protective insulating film 10 is formed on such a narrow and deep pattern, it is expected that the film thickness in the vertical direction at the bottom of the groove (t2 in FIG. 5A, t2' in FIG. 5B) will be thicker than the film thickness in the horizontal direction on the sidewall (t1 in FIG. 5A, t1' in FIG. 5B). If the horizontal film thickness t1 or t1' of the protective insulating film 10 on the pattern sidewall is, for example, 2 nm to 3 nm, the vertical film thickness at the bottom of the groove will be The film thickness t2 or t2' in the perpendicular direction is expected to be, for example, 3 nm to 6 nm. This step shown in B corresponds to the first protective insulating film deposition 102 in the process flow diagram of FIG. 12, and is similar to that shown in FIG. Following the gate metal vertical etching 101 shown in FIGS. 4A and 4B, It is best to do this consecutively.

[0033] 6A and 6B, the protective insulating film 10 is etched in the vertical direction. The etching is performed by etching the hard mask 9, the gate insulating film 3, the gate sidewall spacers 6, and the etching step. The etching is performed under selective etching conditions for the top layer 7 and the interlayer insulating film 8. For example, when the protective insulating film 10 is a Si3N4 film, the etching gas used is a gas in which Cl2 or the like is added to a mixed gas of a halogen-based gas such as CF4 or octafluorocyclobutane (C4F8) and O2, or a gas equivalent thereto. By this etching, the upper surface of the gate insulating film 3 is exposed at the bottom of the gate cut region. In this etching, attention is paid to exposing the upper surface of the gate insulating film 3, taking into consideration the thickness of the protective insulating film 10 in the vertical direction at the bottom of the groove, and after etching, the gate sidewall spacer 10 is removed. The etching time is determined so that the upper end of the protective insulating film 10 in contact with the gate electrode 6 is positioned between the upper and lower ends of the hard mask 9. Since the vertical film thickness of the protective insulating film 10 at the bottom of the groove is thicker than the horizontal film thickness of the protective insulating film 10 at the sidewall of the groove, the protective insulating film 10 at the sidewall is also partially etched away at the bottom of the groove after etching, and the work function metal is left on the sidewall of the cut gate. The gate sidewall spacer 6 is partially exposed on the sidewall of the gate electrode 4 and the gate buried metal 5 (FIG. 6A), and the work function metal 4 is partially exposed on the sidewall of the gate sidewall spacer 6 (FIG. 6B). As shown in FIGS. 6A and 6B, the angle θ1 and θ1' formed by the side wall of the cut gate (FIG. 6A) and the side wall of the gate side wall spacer 6 (FIG. 6B) and the eaves are both acute angles of 90 degrees or less. 6A and 6B corresponds to the first protective insulating film vertical etching 103 in the process flow diagram of FIG. 12, and may be performed continuously in the chamber of the same apparatus following the first protective insulating film deposition 102 shown in FIGS. 5A and 5B.

[0034] Following the above process, the work function metal 4 is partially removed by isotropic etching to obtain the structure shown in Figures 7A and 7B. Gate buried metal 5, hard mask 9, and gate sidewall spacer 6, etching stopper It is preferable to perform etching under conditions that allow selective etching of the layer 7 and the interlayer insulating film 8, and that allow the work function metal 4 to be isotropically etched. For example, if the work function metal 4 is TiN or In the case of TaN, etc., it is recommended to use a mixture of Cl2, O2 and He, a mixture of Cl2 and Ar, or a mixture of CF4 and O2. When the work function metal 4 is TiAl or TiAl containing C, O, N, etc. When the gate insulating film 3 is made of a material, the etching gas may be, for example, a mixed gas of CF4 and Cl2, a mixed gas of CF4 and HCl, or a mixed gas of these gases with Ar, He, N2, etc. This etching removes the work function metal 4 remaining on the gate sidewall spacer 6 via the gate insulating film 3 (Fig. 7B). The etching amount in this process is adjusted to about 1 to 2 times the film thickness of the work function metal 4, and the etching time is controlled so that the work function metal 4 on the channel is not removed. Note that in Figs. 7A and 7B, the work function metal 4 is In Figure 6B, the work function metal 4 is removed in addition to the gate electrode. If the gate buried metal 5 also remains on the sidewall of the sidewall spacer 6, the remaining gate buried metal 5 is also removed in this step. This corresponds to the work function control metal film isotropic etching 104 shown in FIG. 6A and FIG. 6B. It is preferable that this be performed in succession in the chamber of the same equipment following the protective insulating film vertical etching 103. stomach.

[0035] In FIGS. 8A and 8B, the second protective insulating film 11 is deposited on the first protective insulating film 10 using the ALD method. By this step, a laminated film of the protective insulating film composed of the first protective insulating film 10 and the second protective insulating film 11 is formed. In the laminated film of the protective insulating film, the lower layer side is the first protective insulating film 10, and the upper layer side is the second protective insulating film 11. The insulating film material of the second protective insulating film 11 is different from the insulating film material of the first protective insulating film 10. The second protective insulating film 11 covers the side walls and the upper surface of the first protective insulating film 10, the upper surface and side walls of the hard mask 9, the upper surface and side walls of the gate insulating film 3, the side walls of the gate-embedded metal 5, the side walls of the work function metal 4, the upper surface of the gate sidewall spacer 6, the upper surface of the etching stopper layer 7, and the upper surface of the interlayer insulating film 8 of the source / drain region. The horizontal film thickness of the second protective insulating film 11 (t3 in FIG. 8A and t3' in FIG. 8B) is preferably set to be equal (t3 = t1, t3' = t1') or thinner (t3 < t1, t3' < t1') than the horizontal film thickness t1 or t1' of the first protective insulating film 10. When the film thicknesses t1 and t1' are, for example, 2 nm to 3 nm, it is desirable that the film thicknesses t3 and t3' be, for example, 1 nm to 3 nm. The second protective insulating film 11 is also deposited on the eaves formed below the first protective insulating film 10 and on the side walls of the work function metal 4 and the gate-embedded metal 5 (FIG. 8A) and on the side walls of the gate insulating film 3 (FIG. 8B) in the lower region of the first protective insulating film 10 that is exposed up to the steps shown in FIGS. 7A and 7B. Also, since the second protective insulating film 1 is deposited isotropically , in the lower part of the eaves of the first protective insulating film 10, film formation in the vertical direction from the lower part of the eaves and the side walls of the work function metal 4 and the gate-embedded metal 5 (FIG. 8A) or the side walls of the gate insulating film 3 (FIG. 8B) The film formation in the horizontal direction from overlaps, and the horizontal film thickness of the second protective insulating film 11 (t4 in FIG. 8A and t4' in FIG. 8B) is thicker than the horizontal film thickness of the second protective insulating film 11 on the sidewalls of the first protective insulating film 10 (t3 in FIG. 8A and t3' in FIG. 8B). However, it is formed thinner than the sum of the film thickness t3 (or t3') and the film thickness t1 (or t1') (t3 < t4 < t3 + t1, t3' < t4' < t3' + t1'). Also, by setting the film thicknesses t3 and t3' to be thinner than the film thicknesses t1 and t1', the vertical film thickness of the second protective insulating film 11 on the gate insulating film 3 (t5 in FIG. 8A and t5' in FIG. 8B) is equal to the sum of the film thickness t3 (or t3') and the film thickness t1 (or t1') (t3 + t1 = t5, t3' + t1' = t5'), or smaller than the sum of the film thickness t3 (or t3') and the film thickness t1 (or t1') (t3 + t1 > t5, t3' + t1' > t5'). For the second protective insulating film 11, a film that can be deposited isotropically with good controllability even for a more finely and complex-shaped unevenness is used. The second protective insulating film 11 is, for example, an aluminum oxide (Al2O3) film or an aluminum oxynitride (AlON) film equivalent thereto and so on. When forming the Al2O3 film, for the raw material of aluminum (Al), for example, trimethyl aluminum (Trimethylaluminum [TMA]: Al(CH3)3) is used, and for the raw material of oxygen, vaporized water (H2O) is preferably used. The precursor composed of Al(CH3)3 has high reactivity with the hydroxyl groups (OH groups) formed on the surface by the supply of H2O, so it is possible to form the Al2O3 film with a good coverage rate even on a surface having unevenness. Therefore, the Al2O3 film is also deposited isotropically inside the patterns of FIGS. 8A and 8B having narrow openings. Incidentally, the second protective insulating film 11 may use a film such as an oxide film or a nitride film that does not use Al, and may be deposited by a CVD method or the like. The present process shown in FIGS. 8A and 8B corresponds to the second protective insulating film deposition 105 in the process flow diagram of FIG. 12 and is preferably continuously performed in the same chamber following the work function control metal film isotropic etching 104 shown in FIGS. 7A and 7B. ​

[0036] Next, in the steps shown in FIGS. 9A and 9B, the second protective insulating film 11 is etched in the vertical direction. The above etching is a selective etching condition for the first protective insulating film 10, the hard mask 9, the gate insulating film 3, the gate sidewall spacer 6, the etching stopper layer 7, and the interlayer insulating film 8. For example, when the second protective insulating film 11 is an Al2O3 film, the etching gas may be, for example, BCl3, a mixed gas of BCl3 and Cl2, or a gas obtained by mixing argon Ar, N2, or O2 with these, or a gas similar thereto. By this etching, the upper surface of the gate insulating film 3 is exposed. As shown in FIG. 8A, in the eaves portion formed by the first protective insulating film 10, the horizontal film thickness of the second protective insulating film 11 is formed thinner than the total horizontal film thickness of the first protective insulating film 10 and the second protective insulating film 11 above the eaves (t4 < t3 + t1). Therefore, in this etching step, at the lower part of the eaves, the side wall of the second protective insulating film 11 is substantially protected by the eaves formed by the first protective insulating film 10. Even when ions generated from the etching gas are incident on the substrate 1 obliquely from the vertical direction, the ions are reflected substantially by the side wall of the first protective insulating film 10 and change the angle (a1 in FIG. 9A). Therefore, the etching gas ions do not reach the side wall of the second protective insulating film 11 in the lower part of the eaves, and in the lower part of the eaves, the second protective insulating film 11 is not etched. By the above process, it becomes possible to open the upper part of the gate insulating film 3 while protecting the work function metal 4 and the gate embedded metal 5 on the side wall of the cut region. The present step shown in FIGS. 9A and 9B corresponds to the second protective insulating film vertical etching 106 in the process flow diagram of FIG. 12, and it is preferably continuously performed in the chamber of the same apparatus following the second protective insulating film deposition 105 shown in FIGS. 8A and 8B. Incidentally, FIG. 12 ​​The cycle process shown in steps 102-103 and 105-106 (gases and film formation conditions may be changed) is not limited to two cycles, and may be repeated multiple times. In other words, if the combination of the film formation process (102, 105) and the etching process (103, 106) is considered as one cycle process, in FIG. 12, the combination of the film formation process and the etching process is performed in two cycles (the first cycle is steps 102 and 103, and the second cycle is steps 105 and 106), and step 104 of removing the work function metal 4 is sandwiched between the first cycle process and the second cycle process. The first cycle process (steps 102 and 103) and In the second cycle process (steps 105 and 106), the gas and film forming conditions may be changed. The number of cycle processes is not limited to two, and may be repeated multiple times to form multiple cycles. In this case, step 104 for removing the work function metal 4 is performed once. Alternatively, it may be performed multiple times, but it is not necessarily required to perform it every time between each cycle process.

[0037] 10A and 10B, the gate insulating film 3 is isotropically etched. The etching is performed under selective etching conditions for the second protective insulating film 11, the first protective insulating film 10, the hard mask 9, the STI insulating film 2, the gate sidewall spacer 6, the etching stopper layer 7, and the interlayer insulating film 8. During this etching, the work function metal 4 and the gate buried metal 5 Since the side walls of the metals (4, 5) are covered with the first protective insulating film 10 and the second protective insulating film 11, there is no need to consider the etching selectivity for these metals (4, 5). Alternatively, a mixed gas of Cl2, hydrogen bromide (HBr) and O2, or a gas equivalent thereto may be used. The etching amount in this step is adjusted to about 1 to 2 times the film thickness of the gate insulating film 3, and The etching time is controlled so that the gate insulating film 3 on the panel is not removed. This step shown in FIG. 10B corresponds to the gate insulating film isotropic etching 107 in the process flow diagram of FIG. 12, and may be performed continuously in the chamber of the same device following the second protective insulating film vertical etching 106 shown in FIGS. 9A and 9B.

[0038] 11A and 11B, the second protective insulating film 11 and the first protective insulating film 10 are sequentially removed by isotropic etching. The etching of the second protective insulating film 11 is performed under selective etching conditions for the first protective insulating film 10, hard mask 9, gate insulating film 3, work function metal 4, gate buried metal 5, STI insulating film 2, gate sidewall spacer 6, etching stopper layer 7, and interlayer insulating film 8. For example, when the second protective insulating film 11 is an Al2O3 film, the etching gas It is preferable to use a mixed gas of O2, BCl3, and Ar, or a gas equivalent thereto, for the etching. This etching is performed for a time 1 to 2 times longer than the etching time required to etch the second protective insulating film 11 by the thickness thereof, under conditions in which the second protective insulating film 11 is almost completely removed. After the second protective insulating film 11, the first protective insulating film 10 is removed by isotropic etching. This etching is performed under selective etching conditions for the hard mask 9, gate insulating film 3, work function metal 4, gate buried metal 5, STI insulating film 2, gate sidewall spacer 6, etching stopper layer 7, and interlayer insulating film 8. For example, when the protective insulating film 10 is a Si3N4 film, the etching gas For this purpose, gases such as CHF3, difluoromethane (CH2F2), or fluoromethane (CH3F) are used. Or a mixture of fluorocarbon gases such as CF4 or C4F8 and H2, or As in the etching of the second protective insulating film 11, this etching is performed for a time that is one to two times the etching time required to etch the first protective insulating film 10 by the thickness thereof, under conditions that allow almost all of the first protective insulating film 10 to be removed. This process removes the sidewalls of the work function metal 4, the sidewalls of the gate buried metal 5 (FIG. 11A), and the gate The sidewalls of the gate insulating film 3 on the gate sidewall spacers 6 (FIG. 11B) are exposed. The sidewalls of the work function metal 4 and the gate buried metal 5 (FIG. 11A) exposed in this step are The width of the cut pattern opening of the work function metal 4 and the gate insulating film 3 is The cut pattern covered with the metal 5 has a wider opening width and a curved shape. This shape contributes to good embedding properties and isotropic film deposition when a plug structure is formed by filling the cut region with an insulating film in the subsequent process, so that the film density of the insulating film for forming the plug is kept constant at the bottom of the cut region. This has the effect of suppressing the occurrence of cavities in the plug due to a decrease in film density. This process shown in FIGS. 11A and 11B corresponds to the first / second protective insulating film isotropic etching 108 in the process flow diagram of FIG. 12, and is performed by a channel etching process using the same equipment following the gate insulating film isotropic etching 107 shown in FIGS. 10A and 10B. That is, the gate metal vertical etching 101 (FIGS. 4A and 4B) to the first / second protective insulating film isotropic etching 108 (FIGS. 11A and 11B) in FIG. 12 are preferably performed successively. B) can be performed continuously in the chamber of the same device.

[0039] By carrying out a process consisting of this series of steps, in the metal gate cutting process using selective etching in a Fin FET or GAA FET, it is possible to cut the gate without generating metal residues such as the work function metal 4 or the gate buried metal 5 on the sidewall of the gate sidewall spacer 6 within the gate cut region, and it is possible to shorten the distance between the plug that insulates and separates the gates and the FET channel.

[0040] Considering the insulating properties and process stability of the insulating film plug formed in the gate cut region, the gate insulating film 3 remaining on the sidewall of the gate sidewall spacer 6 in the gate cut region may be removed before the insulating film plug is formed. In this case, following the steps shown in FIGS. 11A and 11B, the gate insulating film 3 may be removed by isotropic etching in the same apparatus. 3A to 15A and 13B to 15B, the gate insulating film 3 remaining on the sidewalls of the gate sidewall spacer 6 may be removed while protecting the gate insulating film 3 opened below the gate cut region.

[0041] While protecting the gate insulating film 3 opened under the gate cut region, In the process of removing the gate insulating film 3 remaining on the sidewall of the gate sidewall spacer 6, first, the groove formed by the gate cut region is filled with a coating film such as a spin-on carbon film, which is an organic film, and then the carbon film is etched by a certain amount in the vertical direction to obtain the structure shown in Figures 13A and 13B. Here, the carbon film 12 is etched so that the upper end of the etched carbon film 12 is higher than the boundary position between the work function metal 4 and the gate insulating film 3 on the sidewall of the gate cut region, and so that a part of the gate insulating film 3 remaining on the sidewall of the gate sidewall spacer 6 is exposed. The gate insulating film 3 remaining on the sidewall of the gate sidewall spacer 6 is preferably exposed to a position as deep as possible in the gate cut region. Therefore, after etching the carbon film 12, the height of the carbon film 12 remaining on the STI insulating film 2 is adjusted to be equal to the thickness of the gate insulating film 3. When the thickness is 1 nm to 3 nm, it is preferable to adjust it to about 3 nm to 10 nm. By this process, the gate insulating film 3 (FIG. 13A) existing under the work function metal 4 is protected by the carbon film 12. .

[0042] In the steps shown in FIGS. 14A and 14B, the gate insulating film 3 is isotropically etched to form a gate insulating film. The gate insulating film 3 remaining on the side walls of the gate sidewall spacers 6 is removed (FIG. 14B). The above etching is performed under selective etching conditions for the hard mask 9, the STI insulating film 2, the work function metal 4, the gate buried metal 5, the gate sidewall spacers 6, the etching stopper layer 7, and the interlayer insulating film 8. The etching may be wet etching or dry etching. When wet etching is performed, for example, if the gate insulating film 3 is made of HfO2, A solution such as hydrofluoric acid (HF) is used. When dry etching is performed, a mixed gas of Cl2, HBr, and O2, or a gas equivalent thereto, is used as the etching gas. The etching amount in this process is adjusted to about 1 to 5 times the film thickness of the gate insulating film 3, and the gate insulating film on the channel is The etching time is controlled so that the insulating film 3 is not removed.

[0043] 15A and 15B, the carbon film 12 is removed by ashing, for example, in an oxygen plasma atmosphere. The steps from the vertical etching step of the carbon film 12 shown in FIGS. 13A and 13B to the removal step of the carbon film 12 shown in FIGS. 15A and 15B are preferably performed consecutively in the chamber of the same apparatus. The apparatus used in this step may be the same apparatus that performs the steps from gate metal vertical etching 101 (FIGS. 4A and 4B) to first / second protective insulating film isotropic etching 108 (FIGS. 11A and 11B) in FIG. 12.

[0044] By using a plasma processing apparatus equipped with an ALD film formation function and anisotropic and isotropic etching control function, gate metal vertical etching 101 (FIG. 4A, FIG. 4B) of FIG. The integrated process from the first / second protective insulating film isotropic etching 108 (FIGS. 11A and 11B) to the first / second protective insulating film isotropic etching 109 (FIGS. 11A and 11B) and the integrated process from the carbon film 12 vertical etching (FIGS. 13A and 13B) to the carbon film 12 removal etching (FIGS. 15A and 15B) can be performed continuously in the same plasma processing apparatus. The plasma processing apparatus can be an etching apparatus using inductively coupled plasma (ICP), an etching apparatus using capacitively coupled plasma (CCP), or an etching apparatus using microwave electron cyclotron. The etching apparatus may be either an etching apparatus using ECR (Electron Cyclotron Resonance) plasma or an etching apparatus using ECR (Electron Cyclotron Resonance) plasma.

[0045] As an example, FIG. 16 shows the structure of a plasma processing apparatus 200 using microwave ECR plasma. The plasma processing apparatus 200 has a processing chamber 201, which is evacuated to a vacuum. The gas inlet 202 is connected to a vacuum exhaust system (not shown), and the gas inlet 202 is connected to a vacuum exhaust system (not shown) during plasma processing. The inside of the chamber 201 is kept at a vacuum of about 0.1 Pa to 10 Pa. A window 203 is provided, which has the role of transmitting microwaves and sealing the processing chamber 201 airtight, and a perforated plate 204 is provided to block ions. The perforated plate 204 divides the processing chamber 201 into an upper portion 201A of the processing chamber 201 and a lower portion 201B of the processing chamber 201. The window 203 is made of a material that transmits microwaves, and a dielectric material such as quartz is used. The perforated plate 204 has a plurality of holes, The plate 204 may be made of a dielectric material such as quartz or alumina.

[0046] The gas supply mechanism includes a gas source 205, a gas supply device 206, and a gas inlet 207. The gas source 205 has a plurality of gases required for the process. The gas supply device 206 has a control valve for controlling the supply and cutoff of gases and a mass flow controller for controlling the gas flow rate. The gas inlet 207 is provided between the window portion 203 and the porous plate 204. are.

[0047] A waveguide 209 for propagating electromagnetic waves is connected to the upper part of the processing chamber 201. A high frequency power supply 208 for plasma generation, which is a high frequency power supply, is connected to the The high frequency power supply 208 is a power supply for generating electromagnetic waves for generating plasma, and is, for example, The microwaves used are those with a frequency of 2.45 GHz. The microwave propagates through the waveguide 209 and enters the processing chamber 201. The microwaves are incident perpendicularly into the processing chamber 201 by having a vertical waveguide extending in the direction perpendicular to the processing chamber 201 and a waveguide converter that also serves as a corner for bending the direction of the microwaves by 90 degrees. The microwaves propagate vertically within the processing chamber 201 via the window 203. A magnetic field generating coil 210 disposed on the outer periphery of the processing chamber 201 forms a magnetic field in the processing chamber 201. The microwaves generated from the plasma generating high frequency power supply 208 are The cross wave generates a high density plasma in the processing chamber 201 by interacting with the magnetic field generated by the magnetic field generating coil 210 .

[0048] A sample stage 212 is disposed below the processing chamber 201, facing the window 203. The sample stage 212 is made of, for example, aluminum or titanium. The sample stage 212 holds a semiconductor substrate 211, which is a sample, on its upper surface. Here, the waveguide 209, processing chamber 201, sample stage 212, and semiconductor substrate The central axes of the plates 211 are aligned. By applying a DC voltage, the semiconductor substrate 211 is electrostatically attracted to the sample stage 212. Furthermore, the sample stage 212 is provided with an electrode for controlling the isotropy and anisotropy of etching. To achieve this, a high frequency voltage is applied from the high frequency bias power supply 213. The frequency may be, for example, 400 kHz.

[0049] Each mechanism of the plasma processing apparatus 200 is controlled by a control signal 221 from a control unit 220. The control unit 220 controls each mechanism to perform a predetermined operation using a control signal 221 in accordance with the processing conditions (anisotropic etching, isotropic etching, ALD film formation, etc.) executed by the plasma processing apparatus 200. The control unit 220 controls each mechanism by issuing an execution command. The high frequency power supply 208 is controlled to control the ON / OFF of the electromagnetic waves for generating plasma. The control unit 220 also controls the gas supply mechanism to adjust the type and flow rate of the gas introduced into the processing chamber 201. The control unit 220 also controls the high frequency bias power supply 213 to adjust the bias voltage of the semiconductor substrate on the sample stage 212. The intensity of the high frequency voltage applied to the plate 211 is controlled.

[0050] When anisotropic etching is performed using the plasma processing apparatus 200, the control unit 220 controls the magnetic field generating coil 210 so that plasma is generated in the lower portion 201B of the processing chamber 201 below the porous plate 204. Since the porous plate 204 is made of a dielectric material, the microwaves pass through the porous plate 204 and interact with a magnetic field in the lower part 201B of the processing chamber 201 to generate plasma. Furthermore, a high-frequency bias is applied to the sample stage 212 on which the Si substrate 1 serving as the semiconductor substrate 211 is placed. This allows ions in the plasma to be attracted to the Si substrate 1 without being blocked by the porous plate 204 or the like, enabling anisotropic etching that maintains perpendicularity.

[0051] When isotropic etching is performed using the present plasma processing apparatus 200, the control unit 220 controls the magnetic field generating coil 210 so that the plasma generation position is located in the upper portion 201A of the processing chamber 201 above the porous plate 204. In the plasma generated in the upper part 201A of the processing chamber 201, ions are blocked by the porous plate 204, so only radicals in the plasma are supplied to the lower part 201B of the processing chamber 201. Isotropic etching using radicals becomes possible.

[0052] When forming a film by the ALD method using the plasma processing apparatus 200, it is preferable to apply the following cycle process under the control of the control unit 220. For example, when forming a Si3N4 film by the ALD method, In this case, the Si source BTBAS or BDEAS, or the gas SiH2Cl2 is used. When BTBAS or BDEAS is used, the liquid source is vaporized and sent to the gas line as a gas. The gas source is sent to the processing chamber 201 together with the carrier gas Ar, and the Si It is adsorbed on the substrate surface as a precursor. Then, it is purged using a purge gas such as Ar gas. Then, unnecessary precursors in the processing chamber 201 are exhausted. Then, N2 gas or a mixture of N2 gas and H2 gas is Gas containing nitrogen, such as NH3 gas, is introduced into the processing chamber 201 to generate plasma, which reacts with the surface of the substrate. After this, an inert gas such as Ar is introduced into the processing chamber 201 again to purge the processing chamber 201, and unnecessary gases in the processing chamber 201 are exhausted. Through this series of processes, the atomic In theory, a Si3N4 film with an atomic layer thickness is deposited on the substrate surface. By repeating this process (performing a cycle process), a thin insulating film is formed by the ALD method. For example, when forming an Al2O3 film by the ALD method, It is advisable to use Al(CH3)3 as the source of the oxygen and vaporized H2O as the source of the oxygen, and to carry out the same cycle process as in the case of Si3N4 to form an Al2O3 film. [Example]

[0053] In Example 2, there is provided a method for continuously performing, in the metal gate cutting process of Example 1, a series of steps from cutting the metal gate shown in the flow of FIG. 12 to the step of removing the gate insulating film 3 remaining on the sidewall of the gate sidewall spacer 6 shown in FIGS. 13A and 13B to 15A and 15B in a chamber of the same device.

[0054] 17A to 19A are cross-sectional views of a transistor gate region (taken along line AA' in FIGS. 1 and 2 of Example 1) in a direction parallel to the gate, showing a series of steps for removing the gate insulating film remaining on the gate sidewall spacer in the metal gate cut process. FIGS. 17B to 19B are cross-sectional views of a gate cut region (taken along line BB' in FIGS. 1 and 2 of Example 1) in a direction perpendicular to the gate, showing a series of steps for removing the gate insulating film remaining on the gate sidewall spacer in the metal gate cut process. FIG. 20 is a flow diagram showing a series of manufacturing steps using the same apparatus, from the metal gate cut process shown in FIG. 12 of Example 1 to the steps for removing the gate insulating film remaining on the gate sidewall spacer shown in FIGS. 17A to 19A and 17B to 19B.

[0055] A third protective insulating film 310 is deposited on the structure shown in FIGS. 11A and 11B of Example 1 by a film formation technique using the ALD method or the like, to obtain the structure shown in FIGS. 17A and 17B. The insulating film 310 covers the upper surface and sidewall of the hard mask 309, the upper surface and sidewall of the gate insulating film 303, and the gate insulating film 304. The sidewalls of the gate buried metal 305, the sidewalls of the work function metal 304, and the gate sidewall spacer The protective insulating film 310 is deposited on the upper surface of the source / drain region 306, the upper surface of the etching stopper layer 307, and the upper surface of the interlayer insulating film 308 in the source / drain region. It is preferable that the protective insulating film 310 is made of a SiON film, a SiO2 film, an Al2O3 film, or the like. In this case, the Si source is, for example, BTBAS, BDEAS, or SiH2Cl2, and the nitrogen source is N2 Gas, a mixture of N2 gas and hydrogen H2 gas, or NH3 gas, etc. are used. 5B, the gate insulating film 310 is deposited in this step. The hole region has a width of about 10 nm to 30 nm and a depth of about 50 nm to 200 nm, and is a narrow and deep hole. Therefore, at the bottom of the gate cut region, the film formation from the sidewall and bottom surface contributes, and the film thickness of the third protective insulating film 310 in the vertical direction at the bottom is It is assumed that the thickness of the third insulating film 310 in the horizontal direction is thicker than that of the protective insulating film 310. If the horizontal thickness of the protective insulating film 310 is set to, for example, 2 nm to 3 nm, the third protective film at the bottom of the groove The thickness of the protective insulating film 310 in the vertical direction is, for example, 3 nm to 6 nm. The thickness of the third protective insulating film 310 in the vertical direction from the bottom of the region is The phenomenon that the insulating film 310 becomes thicker than the horizontal film thickness can be prevented by controlling the plasma conditions of the ALD method. For example, when forming a Si3N4 film as the third protective insulating film 310, after supplying a Si source gas to the substrate to form a Si precursor on the substrate surface, when a nitrogen-containing gas is turned into plasma to react with the substrate surface, by controlling conditions such as a high frequency bias applied to the substrate, it is possible to promote only the formation of a Si3N4 film in the vertical direction on the substrate 301. As a result, the formation of the third protective insulating film 310 in the vertical direction from the bottom of the gate cut region can be promoted. The thickness of the third protective insulating film 310 on the sidewall of the pattern can be made thicker than the thickness of the third protective insulating film 310 in the horizontal direction. In this case, the thickness of the third protective insulating film 310 on the top surface of the structure, such as the top surface of the hard mask 309, is also thicker than the horizontal thickness of the third protective insulating film 310 on the sidewalls of the pattern. If the horizontal film thickness of the third protective insulating film 310 on the pattern sidewall is, for example, 2 nm to 3 nm, 17A and 17B corresponds to deposition of third protective insulating film 409 in the process flow diagram of FIG. 20, and may be performed continuously in the chamber of the same apparatus following a series of steps from gate metal vertical etching 401 to isotropic etching of first / second protective insulating films 408 (corresponding to the continuous steps from 101 to 108 in FIG. 12 of Example 1).

[0056] In the steps shown in FIGS. 18A and 18B, the third protective insulating film 310 is isotropically etched. The third protective insulating film 310 deposited on the side wall of the gate cut region is removed by the above etching. This etching is performed under selective etching conditions for the hard mask 309, gate insulating film 303, work function metal 304, gate buried metal 305, gate sidewall spacer 306, etching stopper layer 307, and interlayer insulating film 308. For example, when the third protective insulating film 310 is a Si3N4 film, it is preferable to use a gas such as CHF3, CH2F2, or CH3F as the etching gas, or a mixed gas of a gas such as CF4 or C4F8 with H2, or a gas equivalent thereto. This etching is performed under conditions such that the third protective insulating film 310 remains on the bottom surface of the gate cut region after etching. Furthermore, The etching amount is adjusted so that the upper end of the third protective insulating film 310 remaining after etching is higher than the boundary position between the work function metal 304 and the gate insulating film 303 on the sidewall of the gate cut region. For example, when the thickness of the gate insulating film 303 is 1 nm to 3 nm, the bottom of the gate cut region The etching time is adjusted so that the thickness of the third protective insulating film 310 remaining in the portion is about 3 nm to 7 nm. The etching time may be adjusted to 1 to 1.5 times the thickness of the formed third protective insulating film 310. The amount of the third protective insulating film 310 formed and the etching amount are adjusted so that the above condition is met when the thickness is doubled. This step adjusts the amount of the gate insulating film 303 present under the work function metal 304. The film is protected by the third protective insulating film 310. This step shown in FIGS. 18A and 18B is This corresponds to the third protective insulating film isotropic etching 410 in the process flow diagram of 20, and is shown in FIGS. 17A and 17B. Following the deposition of the third protective insulating film 409 shown in FIG. 17B, this is performed continuously in the chamber of the same device. It would be good if you could.

[0057] 17A and 17B, and 18A and 18B can be considered to correspond to the step of forming the bottom protection insulating film. The step of forming the bottom protection insulating film is performed by forming the third protection insulating film 310. The third protective insulating film 310 is isotropically etched to form a gate cut region. This is a forming step of forming the third protective insulating film 310 so that only the bottom of the gate cut region is protected by the third protective insulating film 310. The third protective insulating film 310 is formed so as to protect only the bottom of the gate cut region. Therefore, the third protective insulating film 310 that protects the bottom of the gate cut region is called a bottom protective insulating film. 13A and 13B can also be regarded as a bottom protective insulating film, similar to the third protective insulating film 310.

[0058] Next, in the process shown in FIGS. 19A and 19B, the gate insulating film 303 is isotropically etched. The gate insulating film 303 remaining on the side walls of the gate sidewall spacers 306 is removed (FIG. 19B). The above etching is performed under selective etching conditions for the third protective insulating film 310, hard mask 309, STI insulating film 302, work function metal 304, gate buried metal 305, gate sidewall spacers 306, etching stopper layer 307, and interlayer insulating film 308. When dry etching is performed for this etching, for example, when the gate insulating film 303 is made of HfO2, the etching gas may contain: For example, a mixed gas of Cl2, HBr, and O2, or a gas similar to these, is used. The etching amount in this process is adjusted to about 1 to 5 times the film thickness of the gate insulating film 303, and the gate insulating film on the channel is The etching time is controlled so that the insulating film 303 is not removed. This process corresponds to the gate insulating film removal etching 411 in the process flow diagram of FIG. 20. Following the isotropic etching 410 of the third protective insulating film shown in FIGS. 8A and 18B, It is recommended that this be done consecutively by multiple members.

[0059] Following the steps shown in FIGS. 19A and 19B, the third protective insulating film 310 is isotropically etched. This etching removes the hard mask 309, the gate insulating film 303, and the work function metal. 304, a gate buried metal 305, an STI insulating film 302, and a gate sidewall spacer 306, and etching The etching is performed under selective etching conditions for the stopper layer 307 and the interlayer insulating film 308. For example, when the third protective insulating film 310 is a Si3N4 film, the etching gas is CHF3, CH2F2, or CH3F. Alternatively, a mixture of CF4, C4F8, or other gases with H2, or a gas equivalent thereto, may be used. This etching is performed to a thickness required to etch the third protective insulating film 310 by the thickness of the film. Etching is performed for a time that is one to two times the etching time, and the third protective insulating film 310 is almost completely removed. This step corresponds to the third protective insulating film isotropic etching 412 in the process flow diagram of Fig. 20, and may be performed continuously in the chamber of the same device following the gate insulating film removal etching 411 shown in Figs. 19A and 19B. This step provides a structure equivalent to the structure shown in Figs. 15A and 15B of Example 1.

[0060] In this embodiment, the process flow shown in FIG. 20 starts from gate metal vertical etching 401. The steps up to the third protective insulating film isotropic etching 412 are performed in a continuous process in the chamber of the same equipment. That is, the metal gate cut process shown in the flow of FIG. 12 in the first embodiment and the subsequent process of removing the gate insulating film 303 remaining on the sidewalls of the gate sidewall spacers 306 can be performed as a series of continuous processes in the same equipment without removing the substrate from the equipment. [Example]

[0061] In the third embodiment, in the metal gate cutting process in the first embodiment, the metal remaining on the sidewall of the gate sidewall spacer 6 shown in FIGS. 13A, 13B to 15A and 15B is removed. In the process of removing the gate insulating film 3, the work function metal 4 in the gate cut region A method for protecting the sidewalls of the gate buried metal 5 is provided.

[0062] 21A to 22A are cross-sectional views of a gate region of a transistor in a direction parallel to the gate (line AA' in FIGS. 1 and 2 of Example 1), showing a series of steps for removing the gate insulating film remaining on the gate sidewall spacers in the metal gate cut process. 21B to 22B are cross-sectional views of a gate cut region in a direction perpendicular to the gate (line BB' in FIGS. 1 and 2 of Example 1), showing a series of steps for removing the gate insulating film remaining on the gate sidewall spacers in the metal gate cut process.

[0063] 10A and 10B of Example 1, the grooves formed by the gate cut region are filled with a coating film such as a spin-on carbon film, and the carbon film is then etched by a certain amount in the vertical direction to obtain the structure shown in Figures 21A and 21B. Here, the upper end of the carbon film 512 after etching is positioned higher than the boundary position between the work function metal 504 and the gate insulating film 503 on the sidewall of the gate cut region, and is positioned so that the second protective insulating film 511 is exposed. For example, the etching amount of the carbon film 512 is adjusted as follows. The height of the carbon film 512 remaining on top is preferably adjusted to about 3 nm to 20 nm. By this step, the gate insulating film 503 present below the work function metal 504 is protected by the carbon film 512.

[0064] In the process shown in FIGS. 22A and 22B, the gate insulating film 503 is etched, and the gate sidewall The gate insulating film 503 remaining on the sidewall of the spacer 506 is removed (FIG. 22B). The above etching removes the carbon film 512, the second protective insulating film 511, the first protective insulating film 510, the hard mask 509, the STI insulating film 502, the gate sidewall spacer 506, the etching stopper layer 507, and the interlayer insulating film 508. The gate insulating film 503 is selectively etched in the horizontal direction. To avoid this, this etching is mainly performed under vertical etching conditions using dry etching, and only the residue that cannot be removed by vertical etching alone is removed by isotropic etching. For example, if the gate insulating film 503 is HfO2, a mixed gas of Cl2, HBr, and O2, or a gas equivalent thereto, is used for vertical etching and isotropic etching. In order to enhance the etching efficiency, a carbon-based material is applied to the material other than the gate insulating film 503. The gate insulating film 503 is selectively deposited and etched while protecting the materials. In this case, gases such as CH4 and CHF3 may be used in the deposition process of the carbon-based material. The etching amount of the insulating film 503 is adjusted to about 1 to 5 times the film thickness of the gate insulating film 503, and the etching time and vertical etching time are adjusted so that the gate insulating film 503 on the channel is not removed. Control the balance.

[0065] Next, the carbon film 512 is removed by ashing, for example, in an oxygen plasma atmosphere. Furthermore, second protective insulating film 511 and first protective insulating film 510 are sequentially removed by isotropic etching, thereby obtaining a structure equivalent to the structure shown in FIGS. 15A and 15B of Example 1.

[0066] From the vertical etching process of the carbon film 512 shown in FIGS. 21A and 21B, The steps up to the step of sequentially removing the protective insulating film 511 and the first protective insulating film 510 are preferably performed continuously in the chamber of the same device. The device used at this time is a device that performs gate metal vertical etching (corresponding to the step 101 in FIG. 12 of the first embodiment) through gate insulating film isotropic etching (corresponding to the step 101 in FIG. 12 of the first embodiment). The apparatus for carrying out the steps up to step 107 in FIG. 12 may be the same as the apparatus for carrying out the steps up to step 107 in FIG.

[0067] In this embodiment, the gate insulating film remaining on the gate sidewall spacer 506 in the gate cut region is During the etching to remove the insulating film 503, the sidewall of the work function metal 504 and the gate buried gold The sidewalls of the metal 505 are protected by the second protective insulating film 511 and the first protective insulating film 510. This makes it possible to avoid etching the layers (504, 505). [Example]

[0068] In Example 4, there is provided a method for continuously performing, in the metal gate cutting process in Example 3, a series of steps for cutting the metal gate (corresponding to a series of steps from 101 to 107 in FIG. 12 in Example 1), a step for removing the gate insulating film 503 remaining on the sidewall of the gate sidewall spacer 506 (FIGS. 22A and 22B in Example 3), and a step for removing the second protective insulating film 511 and the first protective insulating film 510, all in a chamber of the same device.

[0069] 23A to 25A are cross-sectional views of the gate region of a transistor in a direction parallel to the gate (taken along line AA' in FIGS. 1 and 2 of Example 1), showing a series of steps for removing the gate insulating film remaining on the gate sidewall spacer in the metal gate cut process. 23B to 25B are cross-sectional views of the gate cut region in a direction perpendicular to the gate (taken along line BB' in FIGS. 1 and 2 of Example 1), showing a series of steps for removing the gate insulating film remaining on the gate sidewall spacer in the metal gate cut process. 26 is a flow diagram showing a series of steps for cutting the metal gate (corresponding to a series of steps 101 to 107 in FIG. 12 of Example 1), from removing the gate insulating film remaining on the sidewall of the gate sidewall spacer, to further removing the second protective insulating film and the first protective insulating film, all performed in a single manufacturing process using the same equipment.

[0070] A third protective insulating film 612 is deposited on the structure shown in FIGS. 10A and 10B of Example 1 by a film formation technique using the ALD method or the like, to obtain the structure shown in FIGS. 23A and 23B. The insulating film 612 is formed on the upper surface and sidewalls of the hard mask 609, the sidewalls and upper surface of the first protective insulating film 610, and The protective insulating film 612 is deposited on the sidewalls and top surface of the second protective insulating film 611, the top surface and sidewalls of the gate insulating film 603, the top surface of the gate sidewall spacer 606, the top surface of the etching stopper layer 607, and the top surface of the interlayer insulating film 608 in the source / drain region. The material of the protective insulating film 612 is, for example, a Si3N4 film or a similar material. The protective insulating film 612 may be, for example, a Si3N4 film, a SiO2 film, an Al2O3 film, or the like. In this case, for example, BTBAS, BDEAS, or SiH2Cl2 is used as the Si raw material, and N2 gas or a mixed gas of N2 gas and hydrogen H2 gas, or NH3 gas, etc. is used as the nitrogen raw material. The gate cut region where the third protective insulating film 612 is deposited in this process has a depth of about 50 nm to 200 nm, and it is expected that the width will be even narrower (about 5 nm to 20 nm) than in the case of FIGS. 17A and 17B of Example 2 (about 10 nm to 30 nm). Such a narrow and deep pattern At the bottom of the gate cut region, the film thickness of the third protective insulating film 612 in the vertical direction at the bottom is thicker than the film thickness in the horizontal direction on the pattern sidewalls, due to the contribution of film formation from the sidewalls and bottom surface. If the horizontal thickness of the third protective insulating film 612 on the pattern sidewalls is, for example, 2 nm to 3 nm, the vertical thickness at the bottom of the groove will be, for example, 3 nm to 6 nm. In this way, the thickness of the third protective insulating film 612 in the vertical direction from the bottom of the gate cut region is The phenomenon that the thickness of the third protective insulating film 612 on the pattern sidewall becomes thicker than the horizontal thickness is due to the above-mentioned By controlling the plasma conditions of the ALD method, it can be intentionally generated. By using the method shown in Example 2, the horizontal direction of the third protective insulating film 612 on the pattern sidewall can be When the film thickness is set to, for example, 2 nm to 3 nm, the film thickness of the third protective insulating film 612 in the vertical direction at the bottom of the groove is It is possible to increase the thickness to, for example, 5 nm to 10 nm or more. This step shown in FIG. 23B corresponds to the third protective insulating film deposition 708 in the process flow diagram of FIG. 26. It is preferable that this step be performed continuously in the chamber of the same device following a series of steps from gate metal vertical etching 701 to gate insulating film isotropic etching 707 (corresponding to the continuous steps from 101 to 107 in FIG. 12 of Example 1).

[0071] In the process shown in FIGS. 24A and 24B, the third protective insulating film 612 is isotropically etched. The third protective insulating film 612 deposited on the side wall of the gate cut region is removed by the above etching. The hard mask 609, the first protective insulating film 610, the second protective insulating film 611, and the gate sidewall The spacer 606, the etching stopper layer 607, and the interlayer insulating film 608 are selectively etched under the following conditions: For example, when the third protective insulating film 612 is a Si3N4 film, the etching gas may be CHF3, CH2F2, or Alternatively, gas such as CH3F may be used, or a mixture of gas such as CF4 or C4F8 with H2, or It is advisable to use a gas similar to these. This etching is performed under conditions such that the third protective insulating film 612 remains on the bottom surface of the gate cut region after etching. The upper end of the third protective insulating film 612 is in contact with the work function metal 604 on the side wall of the gate cut region. The etching amount is adjusted so that the position is higher than the boundary position of the gate insulating film 603. For example, when the thickness of the gate insulating film 603 is 1 nm to 3 nm, the third insulating film remaining at the bottom of the gate cut region The etching time may be adjusted so that the thickness of the protective insulating film 612 is about 3 nm to 7 nm. When the etching time is set to 1 to 1.5 times the thickness of the formed third protective insulating film 612, The amount of the third protective insulating film 612 to be formed and the amount of etching are adjusted so that the above conditions are met. By this process, the gate insulating film 603 existing under the work function metal 604 becomes a third protective insulating film. The process shown in FIGS. 24A and 24B is the same as the process flow shown in FIG. This corresponds to the third protective insulating film isotropic etching 709 shown in FIG. 23A and FIG. 23B. It is preferable that the third protective insulating film deposition 708 be performed in succession in the chamber of the same device. The third protective insulating film 612, like the third protective insulating film 310, can also be considered as a bottom protective insulating film.

[0072] Next, in the process shown in FIGS. 25A and 25B, the gate insulating film 603 is etched. The gate insulating film 603 remaining on the sidewall of the gate sidewall spacer 606 is removed (FIG. 25B). The above etching removes the third protective insulating film 612, the second protective insulating film 611, the first protective insulating film 610, the hard insulating film 612, and the gate insulating film 603 (FIG. 25C). a gate mask 609, an STI insulating film 602, a gate sidewall spacer 606, an etching stopper layer 607, This is done under selective etching conditions for the interlayer insulating film 608. In order to avoid excessive etching of the gate insulating film 603 in the horizontal direction, this etching is mainly done under vertical etching conditions using dry etching, and only residues that cannot be removed by vertical etching alone are removed by isotropic etching. For example, when the gate insulating film 603 is HfO2, the vertical etching and isotropic etching are In order to further increase the etching selectivity with other materials, the above etching is performed by etching only the carbon-based material on the gate insulating film 603 and other materials. It is selectively deposited on other materials and etched away from the gate insulating film 603 while protecting those materials. In this case, it is preferable to use gas such as CH4 or CHF3 in the deposition process of the carbon-based material. The etching amount of the gate insulating film 603 by etching is adjusted to about 1 to 5 times the film thickness of the gate insulating film 603, and the etching time and vertical etching are adjusted so that the gate insulating film 603 on the channel is not removed. This step shown in FIGS. 25A and 25B corresponds to the gate insulating film removal etching 710 in the process flow diagram of FIG. 26, and is performed in the same manner as in FIGS. 24A and 24B. Following the third protective insulating film isotropic etching 709, It would be good if you could.

[0073] Next, the third protective insulating film 612, the second protective insulating film 611, and the first protective insulating film 610 are By sequentially removing these films using isotropic etching, a structure equivalent to the structure shown in Figures 15A and 15B of Example 1 is obtained. The etching removal techniques for each film are the same as those in Examples 1 to 3. This process corresponds to the first / second / third protective insulating film isotropic etching 711 in the process flow diagram of Figure 26, and may be performed continuously in the chamber of the same device following the gate insulating film removal etching 710 shown in Figures 25A and 25B. In this embodiment, the process flow shown in FIG. 26 is performed from gate metal vertical etching 701 to the The first, second and third protective insulating film isotropic etching 711 are performed continuously in the chamber of the same device. That is, from the series of steps of cutting the metal gate in the third embodiment (corresponding to the series of steps from 101 to 107 in FIG. 12 in the first embodiment), the sidewalls of the gate sidewall spacer 506 can be cut. The process of removing the gate insulating film 503 remaining on the substrate (FIGS. 22A and 22B of the third embodiment) and the process of removing the gate insulating film 503 remaining on the substrate (FIG. 22A and FIG. 22B of the third embodiment) are also performed. The steps up to the step of removing the second protective insulating film 511 and the first protective insulating film 510 can be performed as a series of continuous steps in the same apparatus without removing the substrate from the apparatus. [Explanation of symbols]

[0074] 1, 301, 501, 601: semiconductor substrate; 2, 302, 502, 602: shallow trench isolation (STI) insulating film; 3, 303, 503, 603: high-k gate insulating film; 4, 304, 504, 604: work function control metal; 5, 305, 505, 605: gate buried metal; 6, 306, 506, 606: gate sidewall spacer; 7, 307, 507, 607: etching stopper layer; 8, 308, 508, 608: source / drain region interlayer insulating film; 9, 309, 509, 609: hard mask layer; 10, 510, 610: first protective insulating film; 11, 511, 611: second protective insulating film, 12, 512: carbon film, 310, 612: third protective insulating film film, 101, 401, 701: gate metal vertical etching process, 102, 402, 702: first protective insulating film deposition process, 103, 403, 703: first protective insulating film vertical etching process, 104, 404, 704: work function control metal film isotropic etching process, 105, 405, 705: second protective insulating film deposition process, 106, 406, 706: second protective insulating film vertical etching process, 107, 407, 707: gate insulating film isotropic etching process 108, 408: first / second protective insulating film isotropic etching process; 409, 708: third protective insulating film isotropic etching process; Protective insulating film deposition step, 410, 709: third protective insulating film isotropic etching step, 411, 710: gate insulating film removal etching step, 412: third protective insulating film isotropic etching step, 710: first / second Second / third protective insulating film isotropic etching process, 201: processing chamber (chamber), 201A: processing chamber upper region, 201B: processing chamber lower region, 202: vacuum exhaust port, 203: window portion, 204: perforated plate, 205: gas source, 206: gas supply device, 207: gas inlet port, 208: high frequency power supply for plasma generation, 209: waveguide, 210: magnetic field generating coil, 211: semiconductor substrate, 212: sample stage, 213: high frequency bias power supply, 220: control unit, 221: control signal, t1: horizontal film thickness of the first protective insulating film on the metal gate cut cross section sidewall, t1': horizontal film thickness of the first protective insulating film on the gate sidewall spacer sidewall, t2, t2': vertical film thickness of the first protective insulating film at the bottom of the gate cut region, t3: horizontal film thickness of the second protective insulating film on the sidewall of the cross section of the metal gate cut, t3': horizontal film thickness of the second protective insulating film on the sidewall of the gate sidewall spacer, t4: horizontal film thickness of the second protective insulating film on the sidewall of the cross section of the metal gate cut under the overhang formed by the first protective insulating film at the bottom of the gate cut region, t4': horizontal film thickness of the second protective insulating film on the sidewall of the gate sidewall spacer under the overhang formed by the first protective insulating film at the bottom of the gate cut region, t5, t5': vertical film thickness of the second protective insulating film at the bottom of the gate cut region, θ1: thickness of the sidewall of the cross section of the metal gate cut and the first protective insulating film after etching θ1': the angle between the sidewall of the gate sidewall spacer and the bottom surface of the protective insulating film Angle formed by the bottom surface of the protective insulating film, a1: ion irradiation path during etching of the second protective insulating film.

Claims

1. A method for manufacturing a semiconductor device having a fin-shaped, wire-shaped, or sheet-shaped channel, in which a gate stack film formed by stacking a gate insulating film and a metal layer is formed on the channel, by vertically cutting the gate stack film to insulate and separate gate structures with an insulating film, comprising: a first step of vertically etching the metal layer to form a cut region; a second step of depositing a first protective insulating film on a sidewall of the cut region; a third step of anisotropically etching the first protective insulating film to expose the gate insulating film in the cut region; a fourth step of removing a portion of the metal layer by isotropic etching; a fifth step of depositing a second protective insulating film different from the first protective insulating film on a sidewall of the cut region; a sixth step of anisotropically etching the second protective insulating film to expose the gate insulating film in the cut region; a seventh step of removing a part of the gate insulating film exposed in the cut region, the gate structure is formed from the gate stack and is oriented perpendicular to the channel; A method of manufacturing a semiconductor device, wherein gate sidewall spacers are formed on the sidewalls of the gate structure.

2. 2. The method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, comprising the steps of: continuously performing the first step through the seventh step in the same plasma processing apparatus.

3. 2. The method for manufacturing a semiconductor device according to claim 1, the first protective insulating film is made of a silicon nitride film, 4. A method for manufacturing a semiconductor device, wherein the second protective insulating film is made of an aluminum oxide film.

4. 2. The method for manufacturing a semiconductor device according to claim 1, a gate insulating film formed on the sidewall of the gate stacked film, the sidewall being exposed in the third step; a gate insulating film formed on the sidewall of the gate stacked film;

5. 2. The method for manufacturing a semiconductor device according to claim 1, a second protective insulating film formed on the first insulating film and a second protective insulating film formed on the second insulating film;

6. 6. The method for manufacturing a semiconductor device according to claim 5, a ninth step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by isotropic etching after the eighth step;

7. 6. The method for manufacturing a semiconductor device according to claim 5, a ninth step of applying an organic film after the eighth step; a tenth step of etching the applied organic film in a direction perpendicular to the semiconductor substrate, and controlling an etching amount so that the gate insulating film on the sidewalls of the gate sidewall spacers is exposed and the upper surface of the etched organic film is positioned higher than the height of the gate insulating film under the metal layer; an eleventh step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by isotropic etching; A method for manufacturing a semiconductor device, further comprising a twelfth step of removing the organic film.

8. 6. The method for manufacturing a semiconductor device according to claim 5, a ninth step of isotropically etching the formed insulating film after the eighth step to form a bottom protection insulating film for protecting the bottom of the cut region; a tenth step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by isotropic etching; 11. A method for manufacturing a semiconductor device, further comprising an eleventh step of removing the bottom protection insulating film by isotropic etching.

9. 2. The method for manufacturing a semiconductor device according to claim 1, an eighth step of applying an organic film after the seventh step; a ninth step of etching the applied organic film in a direction perpendicular to the semiconductor substrate, and controlling the amount of etching so that a part of a laminated film formed by laminating the first protective insulating film and the second protective insulating film is exposed and the upper surface of the organic film is positioned higher than the height of the gate insulating film below the metal layer; a tenth step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by anisotropic etching and isotropic etching; an eleventh step of removing the organic film; A method for manufacturing a semiconductor device, further comprising a twelfth step of removing the laminated film by isotropic etching.

10. 2. The method for manufacturing a semiconductor device according to claim 1, an eighth step of isotropically etching the formed third protective insulating film after the seventh step to form a bottom protective insulating film for protecting the bottom of the cut region; a ninth step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by anisotropic etching and isotropic etching; a tenth step of removing the bottom protection insulating film by isotropic etching; 11. A method for manufacturing a semiconductor device, further comprising an eleventh step of removing a laminate film in which the first protective insulating film and the second protective insulating film are laminated by isotropic etching.

11. 1. A plasma processing method for insulating and isolating gate structures from each other by an insulating film by vertically cutting a gate stack film of a semiconductor device having a fin-shaped, wire-shaped, or sheet-shaped channel, the gate stack film being formed on the channel and including a gate insulating film and a metal layer, the method comprising: a first step of vertically etching the metal layer to form a cut region; a second step of depositing a first protective insulating film on a sidewall of the cut region; a third step of anisotropically etching the first protective insulating film to expose the gate insulating film in the cut region; a fourth step of removing a portion of the metal layer by isotropic etching; a fifth step of depositing a second protective insulating film different from the first protective insulating film on a sidewall of the cut region; a sixth step of anisotropically etching the second protective insulating film to expose the gate insulating film in the cut region; a seventh step of removing a part of the gate insulating film exposed in the cut region, the gate structure is formed from the gate stack and is oriented perpendicular to the channel; A plasma processing method, wherein gate sidewall spacers are formed on the sidewalls of the gate structure.

12. 12. The plasma processing method according to claim 11, an eighth step of removing a laminated film in which the first protective insulating film and the second protective insulating film are laminated by isotropic etching; A plasma processing method, characterized in that the first step to the eighth step are carried out successively in the same plasma processing apparatus.

13. 13. The plasma processing method according to claim 12, a ninth step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by isotropic etching;

14. 13. The plasma processing method according to claim 12, a ninth step of isotropically etching the formed third protective insulating film to form a bottom protective insulating film for protecting the bottom of the cut region; a tenth step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by isotropic etching; The plasma processing method further comprises an eleventh step of removing the bottom protection insulating film by isotropic etching.

15. 12. The plasma processing method according to claim 11, an eighth step of isotropically etching the deposited third protective insulating film to form a bottom protective insulating film for protecting the bottom of the cut region; a ninth step of removing the gate insulating film on the sidewalls of the gate sidewall spacers by anisotropic etching and isotropic etching; a tenth step of removing the bottom protection insulating film by isotropic etching; The plasma processing method further comprises an eleventh step of removing a laminated film in which the first protective insulating film and the second protective insulating film are laminated by isotropic etching.

16. 16. The plasma processing method according to claim 14, A plasma processing method, comprising depositing the first protective insulating film and the second protective insulating film by an ALD method.

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