Display device manufacturing method

Abstract

To provide a display device manufacturing method capable of improving reliability.SOLUTION: In a display device manufacturing method according to an embodiment, a first thin film is formed over a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first thin film of the second sub-pixel is removed, a second thin film is formed over the first sub-pixel, the second sub-pixel, and the third sub-pixel, the second thin films of the first sub-pixel and the third subpixel are removed, the first thin film of the third sub-pixel is removed, a third thin film is formed over the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the third thin films of the first sub-pixel and the second sub-pixel are removed.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION An embodiment of the present invention relates to a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. Such display elements are susceptible to deterioration due to moisture, and therefore a technology for reliably sealing the display elements is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a method for manufacturing a display device that can improve reliability. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a display device includes the steps of: a first resist that exposes the first thin film of the second subpixel and covers the first thin film of the first subpixel and the third subpixel; a second resist that uses the first resist as a mask to remove the first thin film of the second subpixel; a second resist that uses the first resist as a mask to remove the first thin film; a second resist that uses the first resist as a mask to form a second thin film that includes a second light-emitting layer over the first subpixel, the second subpixel, and the third subpixel; a second resist that exposes the second thin film of the first subpixel and the third subpixel and covers the second thin film of the second subpixel; the second thin film of the first subpixel and the third subpixel is removed, the second resist is removed, a third resist is formed to expose the first thin film of the third subpixel and to cover the first thin film of the first subpixel and the second thin film of the second subpixel, the first thin film of the third subpixel is removed using the third resist as a mask, the third resist is removed, a third thin film including a third light-emitting layer is formed across the first subpixel, the second subpixel, and the third subpixel, a fourth resist is formed to expose the third thin film of the first subpixel and the second subpixel and to cover the third thin film of the third subpixel, the third thin film of the first subpixel and the second subpixel is removed using the fourth resist as a mask, and the fourth resist is removed. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the display element 20. As shown in FIG. [Figure 5]FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. [Figure 6] FIG. 6 is a flow diagram illustrating an example of a thin film formation process. [Figure 7] FIG. 7 is a diagram for explaining the step of preparing the processing substrate SUB. [Figure 8] FIG. 8 is a diagram illustrating the step of forming the first thin film 31. As shown in FIG. [Figure 9] FIG. 9 is a diagram illustrating the step of forming the first resist 41. As shown in FIG. [Figure 10] FIG. 10 is a diagram illustrating a step of etching using the first resist 41 as a mask. [Figure 11] FIG. 11 is a diagram illustrating the step of removing the first resist 41. As shown in FIG. [Figure 12] FIG. 12 is a diagram illustrating the step of forming the second thin film 32. As shown in FIG. [Figure 13] FIG. 13 is a diagram illustrating the step of forming the second resist 42. As shown in FIG. [Figure 14] FIG. 14 is a diagram illustrating a step of etching using the second resist 42 as a mask. [Figure 15] FIG. 15 is a diagram illustrating the step of removing the second resist 42. As shown in FIG. [Figure 16] FIG. 16 is a diagram illustrating the step of forming the third resist 43. As shown in FIG. [Figure 17] FIG. 17 is a diagram illustrating a step of etching using the third resist 43 as a mask. [Figure 18] FIG. 18 is a diagram illustrating the step of removing the third resist 43. As shown in FIG. [Figure 19] FIG. 19 is a diagram illustrating the step of forming the third thin film 33. As shown in FIG. [Figure 20] FIG. 20 is a diagram illustrating the step of forming the fourth resist 44. As shown in FIG. [Figure 21] FIG. 21 is a diagram illustrating a step of etching using the fourth resist 44 as a mask. [Figure 22] FIG. 22 is a diagram illustrating the step of removing the fourth resist 44. As shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually orthogonal X-, Y-, and Z-axes are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0009] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0010] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA, both of which are disposed on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0013] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0014] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0015] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0016] The display elements 20 are organic light-emitting diodes (OLEDs) that function as light-emitting elements and may be referred to as organic EL elements. For example, the subpixel SP1 includes a display element 20 that emits light in the red wavelength range, the subpixel SP2 includes a display element 20 that emits light in the green wavelength range, and the subpixel SP3 includes a display element 20 that emits light in the blue wavelength range.

[0017] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. 2, the subpixels SP1 and SP2 are aligned in the second direction Y. Furthermore, the subpixels SP1 and SP2 are aligned in the first direction X with the subpixel SP3.

[0018] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0019] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0020] In the display area DA, ribs 5 and partition walls 6 are arranged. The ribs 5 have openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, opening AP2 is larger than opening AP1, and opening AP3 is larger than opening AP2.

[0021] The partitions 6 overlap the ribs 5 in a plan view. The partitions 6 have a plurality of first partitions 6x extending in the first direction X and a plurality of second partitions 6y extending in the second direction Y. The plurality of first partitions 6x are respectively arranged between the openings AP1 and AP2 adjacent to each other in the second direction Y and between two openings AP3 adjacent to each other in the second direction Y. The second partitions 6y are respectively arranged between the openings AP1 and AP3 adjacent to each other in the first direction X and between the openings AP2 and AP3 adjacent to each other in the first direction X.

[0022] 2, the first partition 6x and the second partition 6y are connected to each other. As a result, the partition 6 as a whole is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition 6 has openings in the subpixels SP1, SP2, and SP3, similar to the rib 5.

[0023] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with aperture AP3.

[0024] In the example of FIG. 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. The peripheral edges of the lower electrodes LE1, LE2, and LE3 overlap the ribs 5. The outline of the upper electrode UE1 roughly matches the outline of the organic layer OR1, and the peripheral edges of the upper electrode UE1 and the organic layer OR1 overlap the partition walls 6. The outline of the upper electrode UE2 roughly matches the outline of the organic layer OR2, and the peripheral edges of the upper electrode UE2 and the organic layer OR2 overlap the partition walls 6. The outline of the upper electrode UE3 roughly matches the outline of the organic layer OR3, and the peripheral edges of the upper electrode UE3 and the organic layer OR3 overlap the partition walls 6.

[0025] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 20 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 20 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 20 of the subpixel SP3. The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element 20. The upper electrodes UE1, UE2, and UE3 correspond to, for example, the cathode of the display element 20, or a common electrode.

[0026] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0027] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0028] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12. The rib 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.

[0029] The partition 6 includes a lower portion (stem) 61 disposed on the rib 5, and an upper portion (cap) 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61 in FIG. 3. Such a shape of the partition 6 can also be said to be overhanging.

[0030] 2 includes a first portion OR1a and a second portion OR1b spaced apart from each other, as shown in FIG. 3. The first portion OR1a contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps a part of the rib 5. The second portion OR1b is located on the upper portion 62. 2 includes a first portion UE1a and a second portion UE1b spaced apart from each other, as shown in FIG. 3. The first portion UE1a faces the lower electrode LE1 and is located on the first portion OR1a. The first portion UE1a contacts a side surface of the lower portion 61. The second portion UE1b is located above the partition wall 6 and on the second portion OR1b.

[0031] 2 includes a first portion OR2a and a second portion OR2b spaced apart from each other, as shown in Fig. 3. The first portion OR2a contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps a part of the rib 5. The second portion OR2b is located on the upper portion 62. 2 includes a first portion UE2a and a second portion UE2b spaced apart from each other, as shown in FIG. 3. The first portion UE2a faces the lower electrode LE2 and is located on the first portion OR2a. The first portion UE2a contacts a side surface of the lower portion 61. The second portion UE2b is located above the partition wall 6 and on the second portion OR2b.

[0032] 2 includes a first portion OR3a and a second portion OR3b spaced apart from each other, as shown in FIG. 3. The first portion OR3a contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps a part of the rib 5. The second portion OR3b is located on the upper portion 62. 2 includes a first portion UE3a and a second portion UE3b spaced apart from each other, as shown in FIG. 3. The first portion UE3a faces the lower electrode LE3 and is located on the first portion OR3a. The first portion UE3a contacts a side surface of the lower portion 61. The second portion UE3b is located above the partition wall 6 and on the second portion OR3b.

[0033] In the example shown in FIG. 3, the subpixels SP1, SP2, and SP3 include cap layers (optical adjustment layers) CP1, CP2, and CP3 for adjusting the optical properties of the light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0034] The cap layer CP1 includes a first portion CP1a and a second portion CP1b spaced apart from each other. The first portion CP1a is located in the opening AP1 and above the first portion UE1a. The second portion CP1b is located above the partition wall 6 and above the second portion UE1b.

[0035] The cap layer CP2 includes a first portion CP2a and a second portion CP2b spaced apart from each other. The first portion CP2a is located in the opening AP2 and above the first portion UE2a. The second portion CP2b is located above the partition wall 6 and above the second portion UE2b.

[0036] The cap layer CP3 includes a first portion CP3a and a second portion CP3b spaced apart from each other. The first portion CP3a is located in the opening AP3 and above the first portion UE3a. The second portion CP3b is located above the partition wall 6 and above the second portion UE3b.

[0037] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE1 continuously covers the components of the subpixel SP1, including the first portion CP1a, the partition wall 6, and the second portion CP1b. The sealing layer SE2 continuously covers the components of the subpixel SP2, including the first portion CP2a, the partition wall 6, and the second portion CP2b. The sealing layer SE3 continuously covers the components of the subpixel SP3, including the first portion CP3a, the partition wall 6, and the second portion CP3b.

[0038] 3, the second portion OR1b, the second portion UE1b, the second portion CP1b, and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the second portion OR3b, the second portion UE3b, the second portion CP3b, and the sealing layer SE3 on the partition wall 6. In addition, the second portion OR2b, the second portion UE2b, the second portion CP2b, and the sealing layer SE2 on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart from the second portion OR3b, the second portion UE3b, the second portion CP3b, and the sealing layer SE3 on the partition wall 6.

[0039] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. Furthermore, the sealing layer 14 is covered with a resin layer 15.

[0040] The insulating layer 12 is made of an organic material. The rib 5 and the sealing layers 14, SE1, SE2, and SE3 are made of an inorganic material such as silicon nitride (SiNx). The thickness of the rib 5 made of an inorganic material is sufficiently smaller than the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness of the rib 5 is 200 nm or more and 400 nm or less.

[0041] The lower portion 61 of the partition wall 6 is made of a conductive material. Both the lower portion 61 and the upper portion 62 of the partition wall 6 may be conductive.

[0042] The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive material such as ITO, or may have a laminated structure of a metal material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). The upper electrodes UE1, UE2, and UE3 may be formed of a transparent conductive material such as ITO.

[0043] When the potential of the lower electrodes LE1, LE2, LE3 is relatively higher than the potential of the upper electrodes UE1, UE2, UE3, the lower electrodes LE1, LE2, LE3 correspond to anodes and the upper electrodes UE1, UE2, UE3 correspond to cathodes. Also, when the potential of the upper electrodes UE1, UE2, UE3 is relatively higher than the potential of the lower electrodes LE1, LE2, LE3, the upper electrodes UE1, UE2, UE3 correspond to anodes and the lower electrodes LE1, LE2, LE3 correspond to cathodes.

[0044] The organic layers OR1, OR2, and OR3 each include a plurality of functional layers and a light-emitting layer, where the light-emitting layers included in each of the organic layers OR1, OR2, and OR3 are made of materials that emit light in different wavelength ranges.

[0045] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These thin films have different refractive indices. The material of the thin films constituting the multilayer structure is different from the material of the upper electrodes UE1, UE2, and UE3 and also different from the material of the sealing layers SE1, SE2, and SE3. The cap layers CP1, CP2, and CP3 may be omitted.

[0046] A common voltage is supplied to the partition 6. This common voltage is supplied to the first portions UE1a, UE2a, and UE3a of the upper electrodes in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 included in the subpixels SP1, SP2, and SP3, respectively.

[0047] When a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer in the first portion OR1a of the organic layer OR1 emits light in the red wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer in the first portion OR2a of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer in the first portion OR3a of the organic layer OR3 emits light in the blue wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] FIG. 4 is a diagram showing an example of the configuration of the display element 20. As shown in FIG. The lower electrode LE shown in Fig. 4 corresponds to each of the lower electrodes LE1, LE2, and LE3 in Fig. 3. The organic layer OR shown in Fig. 4 corresponds to each of the organic layers OR1, OR2, and OR3 in Fig. 3. The upper electrode UE shown in Fig. 4 corresponds to each of the upper electrodes UE1, UE2, and UE3 in Fig. 3.

[0050] The organic layer OR includes a carrier adjustment layer CA1, an emitting layer EM, and a carrier adjustment layer CA2. The carrier adjustment layer CA1 is located between the lower electrode LE and the emitting layer EM, and the carrier adjustment layer CA2 is located between the emitting layer EM and the upper electrode UE. The carrier adjustment layers CA1 and CA2 each include multiple functional layers. The following description will be given taking as an example a case where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode.

[0051] The carrier adjustment layer CA1 includes, as functional layers, a hole injection layer F11, a hole transport layer F12, an electron blocking layer F13, etc. The hole injection layer F11 is disposed on the lower electrode LE, the hole transport layer F12 is disposed on the hole injection layer F11, the electron blocking layer F13 is disposed on the hole transport layer F12, and the light-emitting layer EM is disposed on the electron blocking layer F13.

[0052] The carrier adjustment layer CA2 includes, as functional layers, a hole blocking layer F21, an electron transport layer F22, an electron injection layer F23, etc. The hole blocking layer F21 is disposed on the light-emitting layer EM, the electron transport layer F22 is disposed on the hole blocking layer F21, the electron injection layer F23 is disposed on the electron transport layer F22, and the upper electrode UE is disposed on the electron injection layer F23.

[0053] In addition to the above-mentioned functional layers, the carrier adjustment layers CA1 and CA2 may include other functional layers such as a carrier generation layer as necessary, or at least one of the above-mentioned functional layers may be omitted.

[0054] Next, an example of a method for manufacturing the display device DSP will be described.

[0055] FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. The manufacturing method shown here roughly includes the steps of: preparing a processing substrate SUB having the first subpixel SPα, the second subpixel SPβ, and the third subpixel SPγ (step ST1); forming a display element 21 for the first subpixel SPα (step ST2); forming a display element 22 for the second subpixel SPβ (step ST3); and forming a display element 23 for the third subpixel SPγ (step ST4). Note that the first subpixel SPα, the second subpixel SPβ, and the third subpixel SPγ here are any of the subpixels SP1, SP2, and SP3 described above.

[0056] In step ST1, first, a processing substrate SUB is prepared on which the lower electrodes LE, the ribs 5, and the partition walls 6 are formed on the substrate 10. Details will be described later.

[0057] In step ST2, first, the first thin film 31 is formed on the processing substrate SUB (step ST21). Then, a first resist 41 patterned into a predetermined shape is formed on the first thin film 31 (step ST22). Then, a portion of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST23). Then, the first resist 41 is removed (step ST24). As a result, the display element 21 having the first thin film 31 of the predetermined shape is formed in the first subpixel SPα.

[0058] In step ST3, first, a second thin film 32 is formed on the processing substrate SUB (step ST31). Then, a second resist 42 patterned into a predetermined shape is formed on the second thin film 32 (step ST32). Then, a portion of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST33). Then, the second resist 42 is removed (step ST34). Thereafter, a third resist 43 patterned into a predetermined shape is formed on the remaining first thin film 31 and second thin film 32 (step ST35). Then, a portion of the first thin film 31 is removed by etching using the third resist 43 as a mask (step ST36). Then, the third resist 43 is removed (step ST37). As a result, the display element 22 having the second thin film 32 of a predetermined shape is formed in the second subpixel SPβ.

[0059] In step ST4, first, the third thin film 33 is formed on the processing substrate SUB (step ST41). Then, a fourth resist 44 patterned into a predetermined shape is formed on the third thin film 33 (step ST42). Then, a portion of the third thin film 33 is removed by etching using the fourth resist 44 as a mask (step ST43). Then, the fourth resist 44 is removed (step ST44). As a result, the display element 23 having the third thin film 33 of the predetermined shape is formed in the third subpixel SPγ.

[0060] 6 is a flow diagram illustrating an example of a thin film formation process. Each of the first thin film 31, second thin film 32, and third thin film 33 described here includes an organic layer OR, an upper electrode UE, and a sealing layer SE. The organic layer OR also includes multiple functional layers as shown in FIG.

[0061] The step of forming the first thin film 31 (step ST21), the step of forming the second thin film 32 (step ST31), and the step of forming the third thin film 33 (step ST41) each include the following steps.

[0062] First, a material for forming the hole injection layer F11 is evaporated onto the processing substrate SUB (step ST211). This forms the hole injection layer F11 in contact with the lower electrode LE. The lower electrode LE here corresponds to any one of the lower electrodes LE1, LE2, and LE3.

[0063] Thereafter, a material for forming the hole transport layer F12 is evaporated on the hole injection layer F11 (step ST212), thereby forming the hole transport layer F12 in contact with the hole injection layer F11.

[0064] Thereafter, a material for forming the electron blocking layer F13 is evaporated on the hole transport layer F12 (step ST213), thereby forming the electron blocking layer F13 in contact with the hole transport layer F12.

[0065] Thereafter, a material for forming the emitting layer EM is vapor-deposited on the electron-blocking layer F13 (step ST214), thereby forming the emitting layer EM in contact with the electron-blocking layer F13.

[0066] Thereafter, a material for forming the hole-blocking layer F21 is vapor-deposited on the light-emitting layer EM (step ST215), thereby forming the hole-blocking layer F21 in contact with the light-emitting layer EM.

[0067] Thereafter, a material for forming the electron transport layer F22 is evaporated on the hole blocking layer F21 (step ST216), thereby forming the electron transport layer F22 in contact with the hole blocking layer F21.

[0068] Thereafter, a material for forming the electron injection layer F23 is vapor-deposited on the electron transport layer F22 (step ST217). This forms the electron injection layer F23 in contact with the electron transport layer F22. The organic layer OR is formed by a series of steps from step ST211 to step ST217. The organic layer OR here corresponds to any one of the organic layers OR1, OR2, and OR3 described above.

[0069] Thereafter, a material for forming the upper electrode UE is vapor-deposited on the electron injection layer F23 (step ST218). As a result, the upper electrode UE is formed in contact with the electron injection layer F23 and the lower portion 61 of the partition wall 6, and covering the organic layer OR. The upper electrode UE here corresponds to any one of the upper electrodes UE1, UE2, and UE3 described above.

[0070] Thereafter, a material for forming the cap layer CP is evaporated on the upper electrode UE (step ST219). As a result, the cap layer CP is formed in contact with the upper electrode UE. The cap layer CP here corresponds to any one of the cap layers CP1, CP2, and CP3 described above.

[0071] Thereafter, a sealing layer SE is formed to cover the upper electrode UE, the cap layer CP, and the partition wall 6 (step ST220). The sealing layer SE here corresponds to any one of the sealing layers SE1, SE2, and SE3 described above.

[0072] At least one of the above steps ST211 to ST213 and at least one of the above steps ST215 to ST217 may be omitted. In addition to the above steps ST211 to ST217, a process for forming a functional layer constituting the organic layer may be added.

[0073] Steps ST1 to ST4 will be specifically described below.

[0074] 7 , the process of preparing the process substrate SUB in step ST1 includes the steps of forming, above the substrate 10, a first lower electrode LEα of the first subpixel SPα, a second lower electrode LEβ of the second subpixel SPβ, and a third lower electrode LEγ of the third subpixel SPγ; forming a rib 5 having openings APα, APβ, and APγ that overlap with the first lower electrode LEα, the second lower electrode LEβ, and the third lower electrode LEγ, respectively; and forming a partition wall 6 including a lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61 and protruding from a side surface of the lower portion 61. Here, the rib 5 is formed of an inorganic material, and the lower portion 61 is formed of a conductive material. Note that in the drawings referred to in the following description, the substrate 10 and the circuit layer 11 below the insulating layer 12 are not shown.

[0075] 8, a first thin film 31 is formed across the first subpixel SPα, the second subpixel SPβ, and the third subpixel SPγ. The process of forming the first thin film 31 includes the steps of forming a first organic layer OR11 including a first light-emitting layer EM1 that emits light of a first color, forming a first upper electrode UE11 on the first organic layer OR11, forming a first cap layer CP11 on the first upper electrode UE11, and forming a first sealing layer SE11 on the first cap layer CP11. The first sealing layer SE11 here is made of an inorganic material.

[0076] The first organic layer OR11 is formed on each of the first lower electrode LEα, the second lower electrode LEβ, and the third lower electrode LEγ, and is also formed on an upper portion 62 of the partition wall 6. The portion of the first organic layer OR11 formed on the upper portion 62 is separated from the portions formed on the lower electrodes.

[0077] The first upper electrode UE11 is formed on the first organic layer OR11 directly above the first lower electrode LEα, the second lower electrode LEβ, and the third lower electrode LEγ, and is in contact with the lower portion 61 of the partition wall 6. The first upper electrode UE11 is also formed on the first organic layer OR11 directly above the upper portion 62. In one example, the first upper electrode UE11 covers the first organic layer OR11. The portion of the first upper electrode UE11 formed directly above the upper portion 62 is spaced from the portions formed directly above each lower electrode.

[0078] The first cap layer CP11 is formed on the first upper electrode UE11 directly above the first lower electrode LEα, the second lower electrode LEβ, and the third lower electrode LEγ, and is also formed on the first upper electrode UE11 directly above the upper portion 62. The portion of the first cap layer CP11 formed directly above the upper portion 62 is separated from the portions formed directly above each lower electrode.

[0079] The first sealing layer SE11 is formed so as to cover the first cap layer CP11 and the partition wall 6. That is, the first sealing layer SE11 is formed on the first cap layer CP11 directly above the first lower electrode LEα, the second lower electrode LEβ, and the third lower electrode LEγ, and is also formed on the first cap layer CP11 directly above the upper portion 62. The portion of the first sealing layer SE11 formed directly above the upper portion 62 is connected to the portions formed directly above the lower electrodes.

[0080] 9, in step ST22, a first resist 41 is formed. The first resist 41 is formed so as to expose the first thin film 31 of the second subpixel SPβ and to cover the first thin films 31 of the first subpixel SPα and the third subpixel SPγ. That is, in the first subpixel SPα and the third subpixel SPγ, the first resist 41 is in contact with the first sealing layer SE11. In addition, in the second subpixel SPβ, the first sealing layer SE11 is exposed from the first resist 41.

[0081] An edge of the first resist 41 overlaps approximately the center of the partition wall 6. That is, on the partition wall 6 between the first subpixel SPα and the second subpixel SPβ, the first resist 41 is disposed on the first subpixel SPα side, and exposes the first sealing layer SE11 on the second subpixel SPβ side. On the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, the first resist 41 is disposed on the third subpixel SPγ side, and exposes the first sealing layer SE11 on the second subpixel SPβ side.

[0082] 10, etching is performed using the first resist 41 as a mask to remove the first thin film 31 of the second subpixel SPβ that is exposed from the first resist 41. That is, the first sealing layer SE11, the first cap layer CP11, the first upper electrode UE11, and the first organic layer OR11 of the second subpixel SPβ are removed. As a result, the second lower electrode LEβ of the second subpixel SPβ is exposed, and the rib 5 surrounding the second lower electrode LEβ is also exposed.

[0083] Furthermore, on the partition wall 6 between the first subpixel SPα and the second subpixel SPβ, part of the first sealing layer SE11, part of the first cap layer CP11, part of the first upper electrode UE11, and part of the first organic layer OR11 are removed, thereby exposing the second subpixel SPβ side of the upper part 62.

[0084] Furthermore, on the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, part of the first sealing layer SE11, part of the first cap layer CP11, part of the first upper electrode UE11, and part of the first organic layer OR11 are removed, thereby exposing the second subpixel SPβ side of the upper part 62.

[0085] 11, the first resist 41 is removed, thereby exposing the first sealing layer SE11 of the first subpixel SPα and the third subpixel SPγ. Through steps ST21 to ST24, the display element 21 is formed in the first subpixel SPα. The display element 21 is composed of a first lower electrode LEα, a first organic layer OR11, a first upper electrode UE11, and a first cap layer CP11. The display element 21 is also covered with the first sealing layer SE11.

[0086] 12, a second thin film 32 is formed over the first subpixel SPα, the second subpixel SPβ, and the third subpixel SPγ. The process of forming the second thin film 32 includes the steps of forming a second organic layer OR12 including a second light-emitting layer EM2 that emits light of a second color different from the first color, forming a second upper electrode UE12 on the second organic layer OR12, forming a second cap layer CP12 on the second upper electrode UE12, and forming a second sealing layer SE12 on the second cap layer CP12. The second sealing layer SE12 here is formed from the same inorganic material as the first sealing layer SE11.

[0087] The second organic layer OR12 is formed on the second lower electrode LEβ, and is also formed on the first sealing layer SE11 of the first subpixel SPα and the third subpixel SPγ. The second organic layer OR12 is also formed on an upper portion 62 of the partition wall 6. The portion of the second organic layer OR12 formed on the upper portion 62 is connected to the portion formed directly above the first lower electrode LEα and the portion formed directly above the third lower electrode LEγ, but is separated from the portion formed on the second lower electrode LEβ.

[0088] The second upper electrode UE12 is formed on the second organic layer OR12 directly above the second lower electrode LEβ and is in contact with the lower portion 61 of the partition wall 6. The second upper electrode UE12 is also formed on the second organic layer OR12 directly above the upper portion 62. In one example, the second upper electrode UE12 covers the second organic layer OR12 in the second subpixel SPβ. The portion of the second upper electrode UE12 formed directly above the upper portion 62 is connected to the portion formed directly above the first lower electrode LEα and the portion formed directly above the third lower electrode LEγ, but is spaced apart from the portion formed directly above the second lower electrode LEβ.

[0089] The second cap layer CP12 is formed on the second upper electrode UE12 directly above the second lower electrode LEβ, and is also formed on the second upper electrode UE12 directly above the upper portion 62. The portion of the second cap layer CP12 formed directly above the upper portion 62 is connected to the portion formed directly above the first lower electrode LEα and the portion formed directly above the third lower electrode LEγ, but is spaced apart from the portion formed directly above the second lower electrode LEβ.

[0090] The second sealing layer SE12 is formed so as to cover the second cap layer CP12 and the partition wall 6. That is, the second sealing layer SE12 is formed on the second cap layer CP12 directly above the first lower electrode LEα, the second lower electrode LEβ, and the third lower electrode LEγ, and is also formed on the second cap layer CP12 directly above the upper portion 62. The portion of the second sealing layer SE12 formed directly above the upper portion 62 is connected to the portions formed directly above the lower electrodes.

[0091] 13, the second resist 42 is formed. The second resist 42 is formed so as to expose the second thin film 32 of the first subpixel SPα and the third subpixel SPγ and to cover the second thin film 32 of the second subpixel SPβ. That is, in the second subpixel SPβ, the second resist 42 is in contact with the second sealing layer SE12. In addition, in the first subpixel SPα and the third subpixel SPγ, the second sealing layer SE12 is exposed from the second resist 42.

[0092] An edge of the second resist 42 overlaps approximately the center of the partition wall 6. That is, on the partition wall 6 between the first subpixel SPα and the second subpixel SPβ, the second resist 42 is disposed on the second subpixel SPβ side, exposing the second sealing layer SE12 on the first subpixel SPα side. Also, on the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, the second resist 42 is disposed on the second subpixel SPβ side, exposing the second sealing layer SE12 on the third subpixel SPγ side.

[0093] 14, etching is performed using the second resist 42 as a mask to remove the second thin film 32 of the first subpixel SPα and the third subpixel SPγ that is exposed from the second resist 42. That is, the second sealing layer SE12, the second cap layer CP12, the second upper electrode UE12, and the second organic layer OR12 of the first subpixel SPα and the third subpixel SPγ are removed. As a result, the first sealing layer SE11 of the first subpixel SPα and the third subpixel SPγ is exposed.

[0094] Also, on the partition wall 6 between the first subpixel SPα and the second subpixel SPβ, part of the second sealing layer SE12, part of the second cap layer CP12, part of the second upper electrode UE12, and part of the second organic layer OR12 are removed. Furthermore, a portion of the second sealing layer SE12, a portion of the second cap layer CP12, a portion of the second upper electrode UE12, and a portion of the second organic layer OR12 are removed from the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ. In the example shown, the first thin film 31 and the second thin film 32 are separated from each other on the partition wall 6. That is, the second sealing layer SE12, the second cap layer CP12, the second upper electrode UE12, and the second organic layer OR12 remaining on the partition wall 6 are separated from the first sealing layer SE11, the first cap layer CP11, the first upper electrode UE11, and the first organic layer OR11 remaining on the partition wall 6.

[0095] Subsequently, in step ST34, as shown in FIG. 15, the second resist 42 is removed. This exposes the second sealing layer SE12 of the second subpixel SPβ. Through steps ST31 to ST34, the display element 22 is formed in the second subpixel SPβ. The display element 22 is composed of the second lower electrode LEβ, the second organic layer OR12, the second upper electrode UE12, and the second cap layer CP12. The display element 22 is also covered with the second sealing layer SE12.

[0096] 16, the third resist 43 is formed. The third resist 43 is formed so as to expose the first thin film 31 of the third subpixel SPγ and to cover the first thin film 31 of the first subpixel SPα and the second thin film 32 of the second subpixel SPβ. That is, in the first subpixel SPα, the third resist 43 is in contact with the first sealing layer SE11. In addition, in the second subpixel SPβ, the third resist 43 is in contact with the second sealing layer SE12. In addition, in the third subpixel SPγ, the first sealing layer SE11 is exposed from the third resist 43. In addition, the third resist 43 covers the first thin film 31 and the second thin film 32 on the partition wall 6 between the first subpixel SPα and the second subpixel SPβ.

[0097] An edge of the second resist 42 overlaps approximately the center of the partition wall 6. That is, on the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, the third resist 43 is disposed on the second subpixel SPβ side, and exposes the first sealing layer SE11 on the third subpixel SPγ side.

[0098] 17, in step ST36, etching is performed using the third resist 43 as a mask to remove the first thin film 31 of the third subpixel SPγ that is exposed from the third resist 43. That is, the first sealing layer SE11, the first cap layer CP11, the first upper electrode UE11, and the first organic layer OR11 of the third subpixel SPγ are removed. As a result, the third lower electrode LEγ of the third subpixel SPγ is exposed, and the rib 5 surrounding the third lower electrode LEγ is also exposed.

[0099] Furthermore, on the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, part of the first sealing layer SE11, part of the first cap layer CP11, part of the first upper electrode UE11, and part of the first organic layer OR11 are removed, thereby exposing the third subpixel SPγ side of the upper part 62.

[0100] 18, the third resist 43 is removed, thereby exposing the first sealing layer SE11 of the first subpixel SPα and the second sealing layer SE12 of the second subpixel SPβ.

[0101] 19 , the third thin film 33 is formed over the first subpixel SPα, the second subpixel SPβ, and the third subpixel SPγ. The process of forming the third thin film 33 includes the steps of forming a third organic layer OR13 including a third light-emitting layer EM3 that emits light of a third color different from the first color and the second color, forming a third upper electrode UE13 on the third organic layer OR13, forming a third cap layer CP13 on the third upper electrode UE13, and forming a third sealing layer SE13 on the third cap layer CP13. The third sealing layer SE13 here is formed of the same inorganic material as the first sealing layer SE11 and the second sealing layer SE12.

[0102] The third organic layer OR13 is formed on the third lower electrode LEγ, and is also formed on the first sealing layer SE11 of the first subpixel SPα and on the second sealing layer SE12 of the second subpixel SPβ. The third organic layer OR13 is also formed on the upper portion 62 of the partition wall 6. On the partition wall 6 between the first subpixel SPα and the second subpixel SPβ, the third organic layer OR13 covers the first thin film 31 and the second thin film 32 and is connected to the portion formed directly on the first lower electrode LEα and the portion formed directly on the second lower electrode LEβ. On the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, the portion of the third organic layer OR13 formed on the upper portion 62 is connected to the portion formed directly on the second lower electrode LEβ but is separated from the portion formed on the third lower electrode LEγ.

[0103] The third upper electrode UE13 is formed on the third organic layer OR13 directly above the third lower electrode LEγ and is in contact with the lower portion 61 of the partition wall 6. The third upper electrode UE13 is also formed on the third organic layer OR13 directly above the upper portion 62. In one example, the third upper electrode UE13 covers the third organic layer OR13 in the third subpixel SPγ. The portion of the third upper electrode UE13 formed directly above the upper portion 62 is connected to the portion formed directly above the second lower electrode LEβ, but is spaced apart from the portion formed directly above the third lower electrode LEγ.

[0104] The third cap layer CP13 is formed on the third upper electrode UE13 immediately above the third lower electrode LEγ, and is also formed on the third upper electrode UE13 immediately above the upper portion 62. The portion of the third cap layer CP13 formed immediately above the upper portion 62 is connected to the portion formed immediately above the second lower electrode LEβ, but is spaced apart from the portion formed immediately above the third lower electrode LEγ.

[0105] The third sealing layer SE13 is formed so as to cover the third cap layer CP13 and the partition wall 6. That is, the third sealing layer SE13 is formed on the third cap layer CP13 directly above the first lower electrode LEα, the second lower electrode LEβ, and the third lower electrode LEγ, and is also formed on the third cap layer CP13 directly above the upper portion 62. The portion of the third sealing layer SE13 formed directly above the upper portion 62 is connected to the portions formed directly above the lower electrodes.

[0106] 20, a fourth resist 44 is formed. The fourth resist 44 is formed so as to expose the third thin film 33 in the first subpixel SPα and the second subpixel SPβ and to cover the third thin film 33 in the third subpixel SPγ. That is, in the third subpixel SPγ, the fourth resist 44 is in contact with the third sealing layer SE13. In addition, in the first subpixel SPα and the second subpixel SPβ, the third sealing layer SE13 is exposed from the fourth resist 44.

[0107] An edge of the fourth resist 44 overlaps approximately the center of the partition wall 6. That is, on the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, the fourth resist 44 is disposed on the third subpixel SPγ side, and exposes the third sealing layer SE13 on the second subpixel SPβ side.

[0108] 21, etching is performed using the fourth resist 44 as a mask to remove the third thin film 33 of the first subpixel SPα and the second subpixel SPβ that is exposed from the fourth resist 44. That is, the third sealing layer SE13, the third cap layer CP13, the third upper electrode UE13, and the third organic layer OR13 of the first subpixel SPα and the second subpixel SPβ are removed. As a result, the first sealing layer SE11 of the first subpixel SPα and the second sealing layer SE12 of the second subpixel SPβ are exposed.

[0109] Furthermore, the third sealing layer SE13, the third cap layer CP13, the third upper electrode UE13, and the third organic layer OR13 are removed from the partition wall 6 between the first subpixel SPα and the second subpixel SPβ.

[0110] Furthermore, on the partition wall 6 between the second subpixel SPβ and the third subpixel SPγ, a part of the third sealing layer SE13, a part of the third cap layer CP13, a part of the third upper electrode UE13, and a part of the third organic layer OR13 are removed. In the example shown, on the partition wall 6, the second thin film 32 and the third thin film 33 are separated.

[0111] Subsequently, in step ST44, as shown in FIG. 22, the fourth resist 44 is removed. This exposes the third sealing layer SE13 of the third subpixel SPγ. Through steps ST41 to ST44, the display element 23 is formed in the third subpixel SPγ. The display element 23 is composed of a third lower electrode LEγ, a third organic layer OR13, a third upper electrode UE13, and a third cap layer CP13. The display element 23 is also covered with the third sealing layer SE13.

[0112] Through the above steps, the display element 21 is formed in the first subpixel SPα, the display element 22 is formed in the second subpixel SPβ, and the display element 23 is formed in the third subpixel SPγ.

[0113] According to this embodiment, damage to the rib 5 caused by multiple etching processes can be suppressed. For example, the rib 5 surrounding the second lower electrode LEβ is exposed when the first thin film 31 is etched as shown in FIG. 10, but is not exposed by etching in the previous and subsequent steps. Furthermore, the rib 5 surrounding the third lower electrode LEγ is exposed when the first thin film 31 is etched as shown in FIG. 17, but is not exposed by etching in the previous and subsequent steps. Therefore, the formation of undesired holes (water penetration paths) penetrating the rib 5 to the insulating layer 12 is suppressed. This improves reliability.

[0114] For example, in the above example, if the first subpixel SPα corresponds to the above subpixel SP1, the first lower electrode LEα corresponds to the lower electrode LE1, the first organic layer OR11 corresponds to the organic layer OR1 having the first portion OR1a and the second portion OR1b, the first upper electrode UE11 corresponds to the upper electrode UE1 having the first portion UE1a and the second portion CP1b, the first cap layer CP11 corresponds to the cap layer CP1 having the first portion CP1a and the second portion CP1b, and the first sealing layer SE11 corresponds to the sealing layer SE1.

[0115] As described above, according to this embodiment, it is possible to provide a method for manufacturing a display device that can improve reliability and manufacturing yield.

[0116] All display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display device manufacturing method described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0117] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0118] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0119] DSP…display device 10...Substrate 12...Insulating layer 5...Rib 6...Partition wall 61...Lower portion 62...Upper portion SP1, SP2, SP3, SPα, SPβ, SPγ...subpixels 20, 21, 22, 23...Display element (organic EL element) LE, LE1, LE2, LE3, LEα, LEβ, LEγ...lower electrode (anode) UE, UE1, UE2, UE3, UE11, UE12, UE13...Upper electrode (cathode) OR,OR1,OR2,OR3,OR11,OR12,OR13...Organic layer CP, CP1, CP2, CP3, CP11, CP12, CP13...cap layer SE, SE1, SE2, SE3, SE11, SE12, SE13...Sealing layer

Claims

1. providing a processing substrate having first, second, and third subpixels; forming a first thin film including a first light-emitting layer across the first subpixel, the second subpixel, and the third subpixel; forming a first resist that exposes the first thin film of the second subpixel and covers the first thin films of the first subpixel and the third subpixel; removing the first thin film of the second subpixel using the first resist as a mask; removing the first resist; forming a second thin film including a second light-emitting layer across the first subpixel, the second subpixel, and the third subpixel; forming a second resist that exposes the second thin film of the first subpixel and the third subpixel and covers the second thin film of the second subpixel; removing the second thin film of the first subpixel and the third subpixel using the second resist as a mask; removing the second resist; forming a third resist that exposes the first thin film of the third subpixel and covers the first thin film of the first subpixel and the second thin film of the second subpixel; removing the first thin film of the third subpixel using the third resist as a mask; removing the third resist; forming a third thin film including a third light-emitting layer across the first subpixel, the second subpixel, and the third subpixel; forming a fourth resist that exposes the third thin film of the first subpixel and the second subpixel and covers the third thin film of the third subpixel; removing the third thin film of the first subpixel and the second subpixel using the fourth resist as a mask; removing the fourth resist.

2. In the step of preparing the processing substrate, forming a first lower electrode of the first sub-pixel, a second lower electrode of the second sub-pixel, and a third lower electrode of the third sub-pixel above a substrate; forming a rib having an opening overlapping with each of the first lower electrode, the second lower electrode, and the third lower electrode; The method of claim 1 , further comprising forming a partition wall including a lower portion disposed on the rib and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion.

3. The method for manufacturing a display device according to claim 2 , wherein the ribs are made of an inorganic material.

4. The method for manufacturing a display device according to claim 2 , wherein the lower portion of the partition wall is formed of a conductive material.

5. In the steps of forming the first thin film, the second thin film, and the third thin film, forming an organic layer, forming an upper electrode on the organic layer; forming a cap layer on the upper electrode; The method for manufacturing a display device according to claim 1 , further comprising forming a sealing layer on the cap layer.

6. The method for manufacturing a display device according to claim 5 , wherein the sealing layer is made of an inorganic material.

7. In the step of forming the first thin film, forming a first organic layer including the first light-emitting layer on the first lower electrode, the second lower electrode, and the third lower electrode; forming a first upper electrode on the first organic layer; forming a first cap layer on the first upper electrode; The method for manufacturing a display device according to claim 2 , further comprising forming a first sealing layer on the first cap layer.

8. In the step of forming the second thin film, forming a second organic layer including the second light-emitting layer on the second lower electrode and on the first sealing layer of the first subpixel and the third subpixel; forming a second upper electrode on the second organic layer; forming a second cap layer on the second upper electrode; The method for manufacturing a display device according to claim 7 , further comprising forming a second sealing layer on the second cap layer.

9. In the step of forming the third thin film, forming a third organic layer including the third light-emitting layer on the third lower electrode, on the first sealing layer of the first subpixel, and on the second sealing layer of the second subpixel; forming a third upper electrode on the third organic layer; forming a third cap layer on the third upper electrode; The method for manufacturing a display device according to claim 8 , further comprising forming a third sealing layer on the third cap layer.

10. The method for manufacturing a display device according to claim 9 , wherein the first sealing layer, the second sealing layer, and the third sealing layer are formed of the same inorganic material.

11. the lower portion of the partition wall is formed of a conductive material; The method for manufacturing a display device according to claim 9 , wherein the first upper electrode, the second upper electrode, and the third upper electrode are each in contact with the lower portion.

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