Semiconductor device and manufacturing method thereof

Abstract

To provide a highly-reliable manufacturing method for semiconductor devices capable of suppressing positional deviation of components at a time of soldering, and forming a bonding layer of uniform thickness.SOLUTION: A method includes the steps of: preparing an insulated circuit board 1 having a conductive plate 12; by partially fixing a plate-like bonding material 2x on the conductive plate 12, positioning the bonding material 2x horizontally; placing a semiconductor chip 3 on the bonding material 2x; and forming a bonding layer that bonds the insulated circuit board 1 and the semiconductor chip 3 by heating and melting the bonding material 2x.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device such as a power module and a method for manufacturing the same. [Background technology]

[0002] A power module is a package of power semiconductor chips, such as insulated gate bipolar transistors (IGBTs) and diodes, in an external case. The components of a power module are internally assembled by laminating and integrating the semiconductor chips, insulating circuit board, and metal base, and then bonding them to a resin external case to form an integrated structure.

[0003] In recent years, progress has been made in improving the characteristics of semiconductor chips mounted inside, such as reducing losses, and current density per unit area has been increasing year by year. On the other hand, in application devices such as inverters, there is a demand for cost reduction relative to the power rating. Therefore, power modules are required to have improved reliability in high-temperature operation in order to enable high-power density operation.

[0004] The internal assembly of a power module is integrated by soldering. Soldering involves stacking a joining material made of solder and the materials to be joined, then passing them through a heating furnace, where the joining material is heated to a temperature above the melting point of the joining material and melted. If non-tacky sheet solder is used as the joining material, the stacked components may become misaligned due to vibrations during transportation before and after passing through the furnace.

[0005] To avoid misalignment of the stacked members, the stacked members are positioned using a jig having an opening capable of holding the stacked members inside.

[0006] Patent document 1 also discloses a method for manufacturing a semiconductor device, which includes the steps of arranging a semiconductor element having a first solder and a second solder joined to a back electrode by ultrasonic vibration, and a metal plate having a recess for accommodating the first solder, with part of the first solder accommodated in the recess, and, after the arrangement, melting the second solder to solder-bond the semiconductor element and the metal plate.

[0007] Patent document 2 also discloses a method for manufacturing a semiconductor device in which a chip and a lead frame are temporarily assembled with a solid solder block interposed therebetween, and a protrusion that protrudes in one direction is formed on the solder block. This protrusion is inserted into a solder supply hole in the lead frame to temporarily assemble the chip and the lead frame, and then the assembly is placed in a reflow furnace to melt the solder block and then solidify it, thereby joining the chip and the lead frame.

[0008] Patent document 3 also discloses a method for manufacturing a module, in which a first solder having a plate portion including a first surface and a second surface and a first protrusion portion protruding from the plate portion toward the first surface is prepared, a first joined member having a recess for inserting the first protrusion portion is provided on the first surface side, and the first solder and the first joined member are reflowed with the first protrusion portion inserted into the recess.

[0009] Furthermore, Patent Document 4 discloses a semiconductor device in which, on the surface of a thick metal block bonded to a metal foil-bonded insulating substrate, protrusions are formed around the bonding area of ​​a semiconductor chip as chip positioning means, and further, protrusions for controlling the solder height under the chip are formed within the bonding area of ​​the semiconductor chip. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-5559 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-131735 [Patent Document 3] Japanese Patent Application Publication No. 2018-182025 [Patent Document 4] Japanese Patent Application Laid-Open No. 2010-165764 Summary of the Invention [Problem to be solved by the invention]

[0011] The opening of the positioning jig needs to have a certain clearance so that it does not come into contact with and compress the component more than necessary when the component thermally expands during the heating process. The presence of this clearance causes slight horizontal misalignment of the component inside the opening, which causes uneven solder wetting within the horizontal plane and leads to problems such as the component tilting.

[0012] As mentioned above, the current density per unit area has been increasing in recent years, resulting in a significant decrease in the chip area relative to the required current rating. On the other hand, since the clearance of the positioning jig is determined by the processing accuracy and not the opening width, large diameter chips are relatively stable, but small diameter chips tend to tilt significantly after soldering.

[0013] When components are joined at an angle, the thickness of the joining layer becomes uneven, resulting in areas where the joining layer is thinner than when it is uniform, which reduces the ability to withstand thermal stress, potentially impairing environmental reliability, operational reliability, and other aspects of reliability.

[0014] In view of the above problems, the present invention aims to provide a highly reliable semiconductor device and a manufacturing method thereof that can prevent misalignment of components during solder joining and form a joining layer of uniform thickness. [Means for solving the problem]

[0015] One aspect of the present invention is a semiconductor device comprising: (a) an insulated circuit board having a conductive plate with a recessed portion formed on a main surface thereof; (b) a semiconductor chip disposed opposite the main surface of the conductive plate; and (c) a bonding layer disposed between the conductive plate and the semiconductor chip, the bonding layer having a protruding portion inserted into the recessed portion.

[0016] Another aspect of the present invention is a method for manufacturing a semiconductor device, including: (a) preparing an insulated circuit board having a conductive plate; (b) horizontally positioning a plate-shaped bonding material by partially fixing the bonding material on the conductive plate; placing a semiconductor chip on the bonding material; and heating and melting the bonding material to form a bonding layer that bonds the insulated circuit board and the semiconductor chip. [Effects of the Invention]

[0017] According to the present invention, it is possible to prevent misalignment of components during soldering, to form a bonding layer of uniform thickness, and to provide a highly reliable semiconductor device and a method for manufacturing the same. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Figure 3] 1A to 1C are plan views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 4] 4 is a cross-sectional view of the process as seen from the direction AA in FIG. 3. [Figure 5] 5 is a plan view showing a process subsequent to FIGS. 3 and 4 in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 6] 6 is a cross-sectional view of the process as seen from the direction AA in FIG. 5. [Figure 7] 7A to 7C are plan views illustrating steps subsequent to FIGS. 5 and 6 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8A to 8C are cross-sectional views of the process steps taken along the AA direction in FIG. 7. [Figure 9] 9 is a plan view showing a process subsequent to FIGS. 7 and 8 in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 10] 5A to 5C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 11]10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second modification of the first embodiment. [Figure 12] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a third modification of the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along the AA direction in FIG. [Figure 14] 14A to 14C are cross-sectional views illustrating steps subsequent to FIGS. 12 and 13 in the method for manufacturing a semiconductor device according to a third modified example of the first embodiment. [Figure 15] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 16] FIG. 16 is a cross-sectional view taken along the AA direction in FIG. [Figure 17] 10A to 10C are plan views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] 18A to 18C are cross-sectional views illustrating steps subsequent to FIG. 17 in the method for manufacturing the semiconductor device according to the second embodiment. [Figure 19] FIG. 10 is a plan view of a semiconductor device according to a modified example of the second embodiment. [Figure 20] 10A to 10C are plan views illustrating steps in a method for manufacturing a semiconductor device according to a modified example of the second embodiment. [Figure 21] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 22] 22 is a cross-sectional view taken along the AA direction in FIG. 21. [Figure 23] 10A to 10C are plan views illustrating steps in a method for manufacturing a semiconductor device according to a third embodiment. [Figure 24] 24 is a plan view showing a process subsequent to FIG. 23 in the method for manufacturing the semiconductor device according to the third embodiment. [Figure 25] FIG. 25 is a cross-sectional view taken along the AA direction in FIG. 24. [Figure 26] 26 is a plan view showing a process subsequent to FIGS. 24 and 25 in the method for manufacturing the semiconductor device according to the third embodiment. FIG. [Figure 27] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first modified example of the third embodiment. [Figure 28] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second modification of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] Each embodiment will be described below with reference to the drawings. In the drawings, identical or similar parts are designated by the same or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, each embodiment shown below exemplifies an apparatus and method for embodying the technical concept of the present invention, and the technical concept of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components described below.

[0020] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0021] (First embodiment) Fig. 1 is a plan view of the semiconductor device according to the first embodiment, and Fig. 2 is a cross-sectional view taken along the line AA in Fig. 1. As shown in Figs. 1 and 2, the semiconductor device according to the first embodiment is a power module including an insulating circuit board (wiring board) 1, a semiconductor chip (power semiconductor chip) 3 disposed opposite the main surface (top surface) of the insulating circuit board 1, and a bonding layer 2 disposed between the insulating circuit board 1 and the semiconductor chip 3.

[0022] 1 and 2, a metal base and heat dissipation fins may be provided on the underside of the insulating circuit board 1. The insulating circuit board 1 and the semiconductor chip 3 may be housed in an outer case made of resin. The inside of the outer case may be filled with a sealing resin to seal the insulating circuit board 1 and the semiconductor chip 3.

[0023] The insulating circuit board 1 is formed, for example, from a direct copper bond (DCB) board or an active metal brazing (AMB) board. The insulating circuit board 1 includes an insulating plate 11, a conductive plate (circuit board) 12 arranged on the upper surface of the insulating plate 11, and a conductive plate (heat sink) 13 arranged on the lower surface of the insulating plate 11. As shown in Fig. 2, recesses 12a and 12b are formed on the main surface (upper surface) of the conductive plate 12.

[0024] Insulating plate 11 is made of a ceramic substrate made of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc., or a resin insulating plate made of a polymer material, etc. Conductive plates 12 and 13 are made of conductive foils made of, for example, copper (Cu), aluminum (Al), etc.

[0025] The semiconductor chip 3 is disposed facing the main surface (top surface) of the conductive plate 12. A bottom electrode of the semiconductor chip 3, made of gold (Au) or the like, is bonded to the conductive plate 12 via a bonding layer 2. The semiconductor chip 3 may be, for example, an insulated gate bipolar transistor (IGBT), a field effect transistor (FET), a static induction (SI) thyristor, a gate turn-off (GTO) thyristor, or a free wheel diode (FWD). The semiconductor chip 3 may be a unipolar device or a bipolar device. The semiconductor chip 3 may be formed of, for example, a silicon (Si) substrate, or a compound semiconductor substrate made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), gallium oxide (Ga2O3), or diamond (C).

[0026] 1 and 2 illustrate an example in which one semiconductor chip 3 is included, but the number of semiconductor chips can be set appropriately depending on the current capacity of the power module, etc., and two or more semiconductor chips may be included. When two or more semiconductor chips are included, the semiconductor chips may be the same type or different types. As shown in FIG. 1, the semiconductor chip 3 has a rectangular planar pattern. The size of the semiconductor chip 3 is, for example, approximately 3 mm square or more and 20 mm square or less, but is not limited to this.

[0027] 2, the bonding layer 2 is disposed between the conductive plate 12 of the insulating circuit board 1 and the semiconductor chip 3, and bonds (fixes) the conductive plate 12 and the semiconductor chip 3. For example, tin-antimony (SnSb)-based or tin-silver (SnAg)-based solder can be used as the bonding layer 2.

[0028] The lower surface of the bonding layer 2 is provided with protrusions (convex portions) 21a, 21b. The convex portions 21a, 21b of the bonding layer 2 are inserted into the concave portions 12a, 12b of the conductive plate 12. A thickness t1 of the portion of the bonding layer 2 where the convex portions 21a, 21b are formed is thicker than a thickness t2 of the portion of the bonding layer 2 where the convex portions 21a, 21b are not formed. The convex portions 21a, 21b are configured, for example, in a cylindrical shape, but are not limited thereto. The convex portions 21a, 21b may be configured, for example, in a conical shape, a polygonal pillar shape, a polygonal pyramid shape, or the like. The shape of the concave portions 12a, 12b of the conductive plate 12 is also not particularly limited as long as the convex portions 21a, 21b can be inserted therein.

[0029] The bonding layer 2 has, for example, a rectangular planar pattern, but is not limited to this. The bonding layer 2 may also have a planar pattern, for example, a circular pattern. Here, the outer edge of the bonding layer 2 is assumed to coincide with the outer edge of the semiconductor chip 3 shown in FIG. 1. The outer edge of the bonding layer 2 may be located outside the outer edge of the semiconductor chip 3, or may be located inside the outer edge of the semiconductor chip 3. In other words, the size of the bonding layer 2 may be larger or smaller than the size of the semiconductor chip 3.

[0030] 1, protrusions 21a to 21d provided on the lower surface of the bonding layer 2 are schematically shown by dashed lines. The protrusions 21a to 21d are provided in four locations closer to the corners of the rectangle formed by the planar pattern of the bonding layer 2, inside the outer periphery of the planar pattern of the bonding layer 2. Although not shown, the conductive plate 12 is further provided with recesses corresponding to the protrusions 21c and 21d of the bonding layer 2, respectively, and the protrusions 21c and 21d of the bonding layer 2 are inserted into the corresponding recesses of the conductive plate 12.

[0031] There is no particular limitation on the positions of the convex portions 21a to 21d of the bonding layer 2. The bonding layer 2 may have at least one convex portion, and may have two, three, five or more convex portions.

[0032] Next, a method for manufacturing (assembling) the semiconductor device according to the first embodiment will be described. First, an insulating circuit board 1 having a conductive plate 12 with recesses 12a to 12d formed therein is prepared, as shown in Figures 3 and 4. The recesses 12a to 12d of the conductive plate 12 can be formed by cutting using a tool such as a drill, laser irradiation, or the like.

[0033] On the other hand, as shown in FIGS. 5 and 6, a bonding material 2x (also referred to as "preform solder," "solder plate," or "solder pellet") made of solid solder formed into a plate shape is prepared. Recesses 22a to 22d are formed on the upper surface of the bonding material 2x, and protrusions 23a and 23b are formed on the lower surface of the bonding material 2x. The recesses 22a and 22b are formed at positions overlapping with the protrusions 23a and 23b. Note that protrusions (not shown) are formed on the lower surface of the bonding material 2x at positions overlapping with the recesses 22c and 22d. The recesses 22a to 22d and the protrusions 23a and 23b can be formed by, for example, plastically deforming the bonding material 2x having flat upper and lower surfaces that have been rolled using a mold or the like. Note that, depending on the processing method of the bonding material 2x, the recesses 22a to 22d may not be formed on the upper surface of the bonding material 2x, and the upper surface of the bonding material 2x may be flat.

[0034] Next, as shown in FIGS. 7 and 8, a bonding material 2x having an upper surface with recesses 22a-22d and a lower surface with protrusions 23a and 23b is placed on the insulating circuit board 1 having the conductive plate 12 with recesses 12a and 12b. At this time, the protrusions 23a and 23b on the lower surface of the bonding material 2x are inserted (engaged) with the recesses 12a and 12b of the conductive plate 12 to be fixed (locked). Although not shown, the protrusions on the lower surface of the bonding material 2x formed in positions overlapping the recesses 22c and 22d are also inserted and fixed into the recesses 12c and 12d of the conductive plate 12. This positions the bonding material 2x horizontally. The bonding material 2x is held horizontally by the recesses 23a and 23b on the lower surface of the bonding material 2x engaging with the recesses 12a and 12b of the conductive plate 12, resulting in uniform contact with the upper surface of the conductive plate 12.

[0035] 9, the semiconductor chip 3 is placed and stacked on the bonding material 2x. At this time, the bonding material 2x is positioned horizontally and is in uniform contact (close contact) with the upper surface of the conductive plate 12, so that the holding surface of the semiconductor chip 3 placed on the bonding material 2x is unlikely to tilt.

[0036] Next, the laminate of the insulating circuit board 1, bonding material 2x, and semiconductor chip 3 is transported to a heating furnace. Even if it is affected by vibrations and the like that occur during this transport, the insulating circuit board 1, bonding material 2x, and semiconductor chip 3 tend to maintain uniform surface contact with each other. In the heating furnace, the bonding material 2x is heated and melted to form a bonding layer 2 that bonds the insulating circuit board 1 and the semiconductor chip 3. Thereafter, the insulating circuit board 1 and the semiconductor chip 3 are housed in an external case and sealed with sealing resin, and a heat dissipation base and heat dissipation fins are attached to the underside of the insulating circuit board 1, thereby completing the semiconductor device according to the first embodiment.

[0037] According to the method for manufacturing a semiconductor device in accordance with the first embodiment, the convex portions 23a and 23b on the lower surface of the bonding material 2x are inserted into the concave portions 12a and 12b of the conductive plate 12, thereby enabling positioning within the horizontal plane of the bonding material 2x placed on the upper surface of the insulating circuit board 1. Therefore, even if the bonding material 2x is affected by vibrations during transport to a heating furnace, displacement of the bonding material 2x on the lower surface of the semiconductor chip 3 is suppressed, and consequently, displacement of the semiconductor chip 3 can also be suppressed.

[0038] When using a positioning jig that holds components using a frame or the like, clearance is required between the bonding material 2x and the semiconductor chip 3 and the frame. Therefore, even slight misalignment of the bonding material 2x and the semiconductor chip 3 can cause the bonding material 2x and the semiconductor chip 3 to tilt. In contrast, the semiconductor device manufacturing method according to the first embodiment eliminates slight misalignment of the bonding material 2x and the semiconductor chip 3, enabling uniform contact between the bonding material 2x and the semiconductor chip 3 to be maintained. When the temperature is increased in a heating furnace, the solder begins to melt and wet the bonded components uniformly across the surface. Therefore, even in a completely melted state, the semiconductor chip 3 is less likely to become unstable, and the conductive plate 12 and the semiconductor chip 3 that sandwich the bonding material 2x can be bonded while maintaining a horizontal state. This allows for the formation of a bonding layer 2 with a uniform thickness.

[0039] By making the thickness of the bonding layer 2, which is subjected to load during high-temperature operation, uniform, it is possible to reduce thin, weak parts in the bonding layer 2 that are caused by uneven thickness. This makes it possible to improve the reliability tolerance of the bonding layer 2, thereby improving the reliability of the semiconductor device.

[0040] Furthermore, in mounting configurations with complex upper structures such as lead frame wiring, the positioning function of carbon jigs, etc., can be limited to positioning between the lead frame and the substrate, thereby reducing the number of processing points for jigs, etc. Furthermore, tilting of the semiconductor chip 3 and the lead frame can be prevented, making it possible to uniform the thickness of the bonding layer between the insulating circuit board 1 and the semiconductor chip 3, and between the semiconductor chip 3 and the lead frame, thereby improving reliability.

[0041] <First Modification of First Embodiment> 7 and 8, the method for manufacturing a semiconductor device according to the first embodiment illustrates a case in which a bonding material 2x having a lower surface with protrusions 23a and 23b is placed on an insulating circuit board 1 having a conductive plate 12 with recesses 12a and 12b, and the protrusions 23a and 23b of the bonding material 2x are inserted into the recesses 12a and 12b of the conductive plate 12. However, as shown in FIG. 10, a bonding material 2x having flat upper and lower surfaces may be placed on an insulating circuit board 1 having a conductive plate 12 with recesses 12a and 12b.

[0042] In this case, in the state shown in Fig. 10, by locally pressurizing the bonding material 2x using a tool, convex portions 23a, 23b are formed on the lower surface of the bonding material 2x as shown in Fig. 7 and Fig. 8, and the bonding material 2x is inserted into the concave portions 12a, 12b of the conductive plate 12. This allows the bonding material 2x to be positioned in the horizontal direction. Since the other procedures are the same as those in the method for manufacturing the semiconductor device according to the first embodiment, redundant explanations will be omitted.

[0043] <Second Modification of First Embodiment> 8, the method for manufacturing a semiconductor device according to the first embodiment illustrates a case in which a bonding material 2x having a lower surface with protrusions 23a and 23b is placed on an insulating circuit board 1 having a conductive plate 12 with recesses 12a and 12b formed to a predetermined depth in the conductive plate 12, and the protrusions 23a and 23b of the bonding material 2x are inserted into the recesses 12a and 12b of the conductive plate 12. However, as shown in FIG. 11, the recesses 12a and 12b of the conductive plate 12 may penetrate the conductive plate 12, exposing part of the upper surface of the insulating plate 11.

[0044] 11, the bonding material 2x can be positioned in the horizontal direction by inserting the convex portions 21a and 21b of the bonding material 2x into the concave portions 12a and 12b of the conductive plate 12. The other steps are the same as those in the method for manufacturing the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0045] <Third Modification of First Embodiment> In the method for manufacturing a semiconductor device according to the first embodiment, as shown in Figures 3 and 4, a case has been exemplified in which dot-shaped (spot-shaped) recesses 12a to 12d are formed in the conductive plate 12 of the insulating circuit board 1. However, the planar pattern of the recesses 12a to 12d is not limited to dot-shaped (spot-shaped). For example, as shown in Figures 12 and 13, groove-shaped recesses 12a and 12b may be formed in the conductive plate 12. The recesses 12a and 12b have a planar pattern of, for example, stripes extending parallel to one another.

[0046] In this case, as shown in Fig. 14, groove-shaped protrusions 23a corresponding to the recesses 12a are formed in the bonding material 2x. Although not shown, groove-shaped protrusions corresponding to the recesses 12b are also formed in the bonding material 2x. Then, by mounting the bonding material 2x on the insulating circuit board 1 and inserting the protrusions 21a of the bonding material 2x into the recesses 12a of the conductive plate 12, the bonding material 2x can be positioned in the horizontal direction. The other steps are the same as those in the method for manufacturing the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0047] (Second embodiment) 15 and 16, the semiconductor device according to the second embodiment is similar to the semiconductor device according to the first embodiment in that it includes an insulating circuit board 1, a semiconductor chip 3 disposed opposite the upper surface of the insulating circuit board 1, and a bonding layer 2 disposed between the insulating circuit board 1 and the semiconductor chip 3. However, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that a protrusion 21a of the bonding layer 2 is provided on the outer periphery of the bonding layer 2.

[0048] The thickness t1 of the outer peripheral portion where the protrusions 21a of the bonding layer 2 are provided is thicker than the thickness t2 of the central portion where the protrusions 21a of the bonding layer 2 are not provided. In FIG. 15, the planar pattern of the protrusions 21a of the bonding layer 2 is schematically shown by dashed lines. The protrusions 21a of the bonding layer 2 have an annular (frame-shaped) planar pattern. The recesses 12a provided in the conductive plate 12 of the insulating circuit board 1 have an annular (frame-shaped) planar pattern at positions overlapping the protrusions 21a of the bonding layer 2. The protrusions 21a of the bonding layer 2 are inserted into the recesses 12a of the conductive plate 12. The other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted.

[0049] In the semiconductor device according to the second embodiment, stress is more likely to concentrate in the outer periphery of the bonding layer 2 than in the central portion, which makes it more likely for cracks to occur, but by providing the protrusions 21a in the outer periphery of the bonding layer 2, the thickness t1 of the outer periphery of the bonding layer 2 can be made thicker than the thickness t2 of the central portion, preventing the cracks from progressing. This improves durability in terms of environmental reliability.

[0050] Next, a method for manufacturing a semiconductor device according to a second embodiment will be described. In the method for manufacturing a semiconductor device according to the second embodiment, as shown in FIG. 17, an annular (frame-shaped) recess 12a is formed in the conductive plate 12 of the insulating circuit board 1 by cutting or the like using a tool. Then, as shown in FIG. 18, a bonding material 2x having an annular (frame-shaped) protrusion 23a on its underside corresponding to the recess 12a is placed on the insulating circuit board 1. At this time, the protrusion 21a of the bonding material 2x is inserted into the recess 12a of the conductive plate 12, thereby allowing the bonding material 2x to be positioned horizontally. Note that, depending on the processing method for the bonding material 2x, a recess may be formed on the upper surface of the bonding material 2x at a position overlapping the protrusion 23a. The other steps of the method for manufacturing a semiconductor device according to the second embodiment are the same as those of the method for manufacturing a semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0051] According to the manufacturing method of the semiconductor device of the second embodiment, the horizontal positioning of the bonding material 2x can be performed by inserting the convex portion 21a of the bonding material 2x into the concave portion 12a of the conductive plate 12, so that it is possible to suppress misalignment of the bonding material 2x and the semiconductor chip 3 even if they are affected by vibrations during transportation, etc.

[0052] <Modification of the second embodiment> 15, the semiconductor device according to the second embodiment has been exemplified as having the protruding portion 21a of the bonding layer 2 formed in a ring shape (frame shape) on the outer periphery of the bonding layer 2. However, as shown in FIG. 19, the protruding portions 21a to 21d of the bonding layer 2 may be formed at the four corners of the rectangular outer periphery formed by the planar pattern of the bonding layer 2.

[0053] According to the semiconductor device of the modified example of the second embodiment, by providing the protrusions 21a to 21d at the corners of the outer periphery of the bonding layer 2, the thickness of the corners of the outer periphery of the bonding layer 2 can be made relatively thick, thereby preventing the propagation of cracks that tend to occur at the corners of the outer periphery of the bonding layer 2. Therefore, durability related to environmental reliability can be improved.

[0054] In a method for manufacturing a semiconductor device according to a modification of the second embodiment, as shown in Fig. 20, recesses 12a-12d are formed in conductive plate 12 of insulating circuit board 1 at positions where protrusions 21a-21d of bonding layer 2 shown in Fig. 19 are to be inserted. Then, by inserting protrusions 21a-21d of the bonding material in a solid state before heating and melting bonding layer 2 shown in Fig. 19 into recesses 12a-12d of conductive plate 12, bonding material 2x can be positioned in the horizontal direction.

[0055] (Third embodiment) 21 and 22, the semiconductor device according to the third embodiment is similar to the semiconductor device according to the first embodiment in that it includes an insulating circuit board 1, a semiconductor chip 3 disposed opposite the upper surface of the insulating circuit board 1, and a bonding layer 2 disposed between the insulating circuit board 1 and the semiconductor chip 3. However, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that columnar partially molten portions (alloy layers) 24a-24d are provided in the bonding layer 2, and the protruding portions on the lower surface of the bonding layer 2 are composed of the partially molten portions 24a-24d.

[0056] The partially melted portions 24a-24d can be formed by laser welding (laser spot welding) to the solid bonding material before heating and melting the bonding layer 2 during the manufacture of the semiconductor device according to the third embodiment. The partially melted portions 24a-24d are made of an alloy layer formed by melting and solidifying the material of the bonding layer 2 and the material of the conductive plate 12. For example, if the material of the conductive plate 12 is copper (Cu), the partially melted portions 24a-24d are regions containing a higher concentration of copper (Cu) than the bonding layer 2.

[0057] 22 illustrates an example in which the partially melted portions 24a to 24d penetrate the bonding layer 2 and the upper ends of the partially melted portions 24a to 24d coincide with the upper surface of the bonding layer 2, but is not limited to this. For example, the partially melted portions 24a to 24d may not penetrate the bonding layer 2 and the upper ends of the partially melted portions 24a to 24d may be located inside the bonding layer 2. The lower ends of the partially melted portions 24a to 24d protrude from the lower surface of the bonding layer 2 to form convex portions. Concave portions of the conductive plate 12 are provided at positions corresponding to the convex portions at the lower ends of the partially melted portions 24a to 24d.

[0058] In FIG. 21, the partially melted portions 24a to 24d are schematically shown by dashed lines. The partially melted portions 24a to 24d are provided at the four corners of the rectangle formed by the planar pattern of the bonding layer 2. The partially melted portions 24a to 24d have a dot-like (spot-like) planar pattern. The number of the partially melted portions 24a to 24d is not limited to four, and they may be provided at one to three or five or more locations. The positions at which the partially melted portions 24a to 24d are arranged are also not particularly limited. The other configurations of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0059] Next, a method for manufacturing a semiconductor device according to the third embodiment will be described. In the method for manufacturing a semiconductor device according to the third embodiment, as shown in Fig. 23, an insulating circuit board 1 having a conductive plate 12 with a flat upper surface is prepared, and a bonding material 2x having flat upper and lower surfaces is prepared. Then, the bonding material 2x is placed on the conductive plate 12 of the insulating circuit board 1.

[0060] 24 and 25, a part of the bonding material 2x and a part of the conductive plate 12 are melted by laser welding to form partially melted portions (nuggets) 24a to 24d. In laser welding, heat is input from the top surface of the bonding material 2x to the inside by spot spraying. This partially and firmly bonds the bonding material 2x and the conductive plate 12, and the bonding material 2x can be positioned in the horizontal direction.

[0061] Next, as shown in Fig. 26, a semiconductor chip 3 is mounted on the bonding material 2x. Thereafter, the stack of the insulating circuit board 1, bonding material 2x, and semiconductor chip 3 is carried to a heating furnace. The bonding material 2x is heated and melted in the heating furnace to form a bonding layer 2 that bonds the insulating circuit board 1 and the semiconductor chip 3. Other steps in the method for manufacturing a semiconductor device according to the third embodiment are the same as those in the method for manufacturing a semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0062] According to the method for manufacturing a semiconductor device in accordance with the third embodiment, by forming partially melted portions 24a to 24d in the bonding material 2x by laser welding, it is possible to prevent displacement of the bonding material 2x and the semiconductor chip 3 due to vibration during transport to a heating furnace of a stack of the insulating circuit board 1, the bonding material 2x, and the semiconductor chip 3. Furthermore, after transport to the heating furnace, even during solder bonding in the heating furnace, which involves full melting of the bonding material 2x, it is possible to prevent displacement of the bonding material 2x and the semiconductor chip 3 due to the partially melted portions 24a to 24d.

[0063] As shown in FIG. 8, a bonding material 2x having a lower surface with protrusions 23a and 23b may be placed on an insulating circuit board 1 having a conductive plate 12 with recesses 12a and 12b, and the protrusions 23a and 23b of the bonding material 2x may be inserted into the recesses 12a and 12b to fix the bonding material 2x, followed by laser welding.

[0064] <First Modification of Third Embodiment> In the method for manufacturing a semiconductor device according to the third embodiment, as shown in Fig. 23, a bonding material 2x having flat upper and lower surfaces is placed on an insulating circuit board 1, and then laser welding is performed. However, as shown in Fig. 27, before laser welding, recesses 25a and 25b may be formed on the upper surface of the bonding material 2x at positions where heat is to be input by laser welding. The recesses 25a and 25b can be formed by subjecting the bonding material 2x having flat upper and lower surfaces to plastic processing or stamping, for example.

[0065] According to the method for manufacturing a semiconductor device according to the first modification of the third embodiment, the recesses 25a and 25b are provided on the upper surface of the bonding material 2x, thereby improving local light collection, and therefore reducing the power of the laser for forming the partially melted portions 24a to 24d, thereby improving the laser irradiation efficiency.

[0066] <Second Modification of Third Embodiment> In the semiconductor device manufacturing method according to the third embodiment, as shown in FIG. 23, a bonding material 2x having flat upper and lower surfaces is placed on an insulating circuit board 1, followed by laser welding. However, as shown in FIG. 28, metal layers 4a and 4b may be formed on the upper surface of the bonding material 2x at positions where heat is to be applied by laser welding before laser welding. Materials that can be used for the metal layers 4a and 4b include nickel (Ni), palladium (Pd), platinum (Pt), and silver (Ag). The metal layers 4a and 4b may be formed by depositing a metal layer over the entire upper surface of the bonding material 2x by, for example, sputtering or vapor deposition, and then selectively removing portions of the metal layer using a mask.

[0067] According to the manufacturing method of the semiconductor device related to the second modified example of the third embodiment, by locally forming the metal layers 4a, 4b on the upper surface of the bonding material 2x, it is possible to improve the heat input efficiency during laser welding and to improve the laser irradiation efficiency.

[0068] (Other embodiments) As described above, the present invention has been described with reference to the first to third embodiments, but the descriptions and drawings that form part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0069] For example, the configurations disclosed in the first to third embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0070] 1...Insulated circuit board 2x…bonding material 3. Semiconductor chip 4a,4b...metal layer 11...Insulating plate 12...Conductive plate 12a~12d...Concave 13...Conductive plate 21a~21d...Convex part 22a~22d...recesses 23a, 23b...Convex part 24a to 24d: Partially molten area (alloy layer) 25a, 25b...recessed portion

Claims

1. an insulating circuit board having a conductive plate with a recessed portion formed on a main surface thereof; a semiconductor chip disposed opposite to a main surface of the conductive plate; a bonding layer provided between the conductive plate and the semiconductor chip, the bonding layer having a protrusion inserted into the recess; Equipped with The semiconductor device is characterized in that the protrusion is formed by a partially melted portion of the bonding layer and the conductive plate.

2. 2. The semiconductor device according to claim 1, wherein the protrusion is provided inside the outer periphery of the bonding layer.

3. 2. The semiconductor device according to claim 1, wherein the protrusion is provided on the outer periphery of the bonding layer.

4. providing an insulating circuit board having a conductive plate; a step of partially fixing a plate-shaped bonding material on the conductive plate to position the bonding material in a horizontal direction; placing a semiconductor chip on the bonding material; a step of heating and melting the bonding material to form a bonding layer that bonds the insulating circuit board and the semiconductor chip; Including, A method for manufacturing a semiconductor device, wherein the step of positioning the bonding material in the horizontal direction includes joining a part of the conductive plate and a part of the bonding material by laser welding.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein, before the laser welding, a recess is formed on the upper surface of the joining material at a position where heat is input by the laser welding.

6. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of selectively forming a metal layer on the upper surface of the joining material at a position where heat is input by the laser welding, before the laser welding.

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