Amplification equipment, radar equipment

Abstract

To suppress the negative effects of a failed amplifier.SOLUTION: An amplification device includes a plurality of amplification units that amplify high-frequency signals, a power supply main line common to the plurality of amplification units, a plurality of power branch lines branching from the power supply main line, a protection unit that is arranged for a power branch line connected to the amplification unit and cuts off the power branch line on the basis of a drive current flowing from the power branch line to the amplification unit, and a power supply control unit that is connected between the amplification unit and the protection unit and controls the supply of drive voltage to the amplification unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a technique for amplifying a high frequency signal. [Background technology]

[0002] Patent Document 1 discloses a power amplifier that amplifies a high-frequency signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-175333 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, there is one amplifier in the final stage, but there may be multiple amplifiers in the final stage. If power is supplied to the multiple amplifiers through a common supply line, a malfunctioning amplifier may have an adverse effect.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an amplifier apparatus and method that reduces the adverse effects of a failed amplifier in a plurality of amplifiers. [Means for solving the problem]

[0006] The amplification device of the present invention includes a plurality of amplification units that amplify high-frequency signals, a main power supply line common to the plurality of amplification units, a plurality of power supply branch lines branching off from the main power supply line, a protection unit that is arranged on the power supply branch lines connected to the amplification units and that cuts off the power supply branch lines based on drive current flowing from the power supply branch lines to the amplification units, and a power supply control unit that is connected between the amplification units and the protection unit and that controls the supply of drive voltage to the amplification units. [Effects of the Invention]

[0007] According to the present invention, the adverse effects of a failed amplifier can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of one amplifier circuit that constitutes a final stage amplifier section according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of the final stage amplifier unit according to the embodiment of the present invention. [Figure 3] FIG. 3A is a circuit diagram showing the operating state of the amplifier circuit in a normal state, and FIG. 3B is a circuit diagram showing the operating state of the amplifier circuit in an abnormal state. [Figure 4] FIG. 4 is a flowchart showing a fail-safe process according to an embodiment of the present invention. [Figure 5] FIG. 5 is a functional block diagram showing a configuration of a transmission device according to an embodiment of the present invention. [Figure 6] FIG. 6 is a circuit diagram showing another example of an amplifier circuit according to an embodiment of the present invention. [Figure 7] FIG. 7 is a circuit diagram showing the configuration of the fault number detection unit. [Figure 8] FIG. 8 is a flowchart showing the fail-safe process and the first transmission control according to the embodiment of the present invention. [Figure 9] FIG. 9 is a flowchart showing the fail-safe process and the second transmission control according to the embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing an example of a control table for the second transmission control of the present invention. [Figure 11] FIG. 11 is a flowchart showing an example of a process for generating a monitoring signal for determination. DETAILED DESCRIPTION OF THE INVENTION

[0009] An amplifier device, a transmitter, and an amplification method according to an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram showing the configuration of one amplifier circuit constituting a final stage amplifier unit according to an embodiment of the present invention. Fig. 2 is a circuit diagram showing the configuration of a final stage amplifier unit according to an embodiment of the present invention. Fig. 3(A) is a circuit diagram showing the operating state of the amplifier circuit under normal conditions, and Fig. 3(B) is a circuit diagram showing the operating state of the amplifier circuit under abnormal conditions.

[0010] (Configuration of the final stage amplifier) First, the configuration of the final stage amplifier unit will be described with reference to Fig. 2. As shown in Fig. 2, the final stage amplifier unit 20 includes four amplifier circuits 21-24, three dividers 201-203, three combiners 204-206, and a power supply line 90. The amplifier circuits 21-24 are specifically amplifier circuits using semiconductors. The dividers 201-203 are specifically configured using microstrip lines, for example. The combiners 204-206 are specifically configured using microstrip lines, for example.

[0011] Divider 201 is connected to divider 202 and divider 203. Divider 202 is connected to amplifier circuit 21 and amplifier circuit 22. Divider 203 is connected to amplifier circuit 23 and amplifier circuit 24.

[0012] The combiner 204 is connected to the amplifier circuit 21 and the amplifier circuit 22. The combiner 205 is connected to the amplifier circuit 23 and the amplifier circuit 24. The combiner 206 is connected to the combiner 204 and the combiner 205.

[0013] Divider 201 divides the input high-frequency signal and outputs the divided signal to divider 202 and divider 203. Divider 202 divides the input high-frequency signal from divider 201 and outputs the divided signal to amplifier circuit 21 and amplifier circuit 22. Divider 203 divides the input high-frequency signal from divider 201 and outputs the divided signal to amplifier circuit 23 and amplifier circuit 24.

[0014] Combiner 204 combines the high-frequency signal amplified by amplifier circuit 21 and the high-frequency signal amplified by amplifier circuit 22, and outputs the result to combiner 206. Combiner 205 combines the high-frequency signal amplified by amplifier circuit 23 and the high-frequency signal amplified by amplifier circuit 24, and outputs the result to combiner 206. Combiner 206 combines the combined high-frequency signal output from combiner 204 and the combined high-frequency signal output from combiner 205, and outputs the result.

[0015] With this configuration, the final stage amplifier section 20 amplifies the high frequency signal with a substantially high gain.

[0016] The power supply line 90 is connected to the amplifier circuits 21, 22, 23, and 24. The power supply line 90 is a power supply line common to the amplifier circuits 21, 22, 23, and 24. The power supply line 90 includes, for example, a main power supply line 91 and a plurality of branch power supply lines 92. The plurality of branch power supply lines 92 branch off from the main power supply line 91 and are connected to the amplifier circuits 21, 22, 23, and 24, respectively. With this configuration, the power supply line 90 supplies a drive voltage VDD to the amplifier circuits 21, 22, 23, and 24.

[0017] The amplifier circuits 21, 22, 23, and 24 have the same configuration. Supply control signals are input to the amplifier circuits 21, 22, 23, and 24. The amplifier circuits 21, 22, 23, and 24 control the application of the drive voltage VDD to the respective amplifier elements in response to the supply control signals.

[0018] With this configuration, the drive voltage VDD is applied to the amplifier circuits 21, 22, 23, and 24 during the output period of the high-frequency signal, and the drive voltage VDD is not applied during other periods. As described above, the output signals of the amplifier circuits 21, 22, 23, and 24 are combined, and the final-stage amplifier unit 20 outputs a pulsed high-frequency signal with high output intensity.

[0019] (Configuration of amplifier circuit 21) As described above, the amplifier circuits 21, 22, 23, and 24 have the same configuration, and therefore, the amplifier circuit 21 will be described below as a representative example.

[0020] 1, the amplifier circuit 21 includes a final stage amplifier 31, a fuse 32, a drain voltage control circuit 33, a switch 34, and a power line monitoring IC 351. The final stage amplifier 31 corresponds to the "amplifying section" of the present invention, the fuse 32 corresponds to the "protecting section" of the present invention, the drain voltage control circuit 33 corresponds to the "power supply control section" of the present invention, and the switch 34 corresponds to the "switching section" of the present invention.

[0021] The final stage amplifier 31 is composed of, for example, a FET. The gate of the FET is connected to an input section 211 of the amplifier circuit 21 for receiving a high frequency signal. The source of the FET is grounded. The drain of the FET is connected to an output section 212 of the amplifier circuit 21 for receiving a high frequency signal. The drain of the FET is also connected to a drain voltage control circuit 33.

[0022] The drain voltage control circuit 33 includes, for example, a FET and includes a first connection part 331, a second connection part 332, and a third connection part 333. The gate of the FET is connected to the first connection part 331, the drain of the FET is connected to the second connection part 332, and the source of the FET is connected to the third connection part 333. The second connection part 332 is connected to the fuse 32, and the third connection part 333 is connected to the drain of the FET that constitutes the final stage amplifier 31. Note that the number of FET stages that constitute the drain voltage control circuit 33 is not limited to one, and may be multiple stages.

[0023] The fuse 32 is connected between the second connection part 332 of the drain voltage control circuit 33 and the common power supply line 90. In other words, one terminal of the fuse 32 is connected to the second connection part 332 of the drain voltage control circuit 33, and the other terminal of the fuse 32 is connected to the power supply branch line 92. In other words, the fuse 32 is inserted in the middle of the power supply branch line 92.

[0024] The switch 34 includes a terminal 341, a terminal 342, and a terminal 343. The terminal 341 is selectively connected to the terminal 342 and the terminal 343. The terminal 341 is connected to the first connection section 331 of the drain voltage control circuit 33. The terminal 342 is connected to the input section 214 of the supply control signal in the final stage amplifier section 20. The terminal 343 is grounded.

[0025] The power supply line monitoring IC 351 is connected to one end of the fuse 32 and the second connection part 332 of the drain voltage control circuit 33. The power supply line monitoring IC 351 is also connected to the switch 34. The power supply line monitoring IC 351 generates a monitoring signal according to the voltage at one end of the fuse 32 and outputs it to the switch 34. For example, the monitoring signal has a signal strength proportional to the voltage value at one end of the fuse 32.

[0026] The high frequency signal is input to the final stage amplifier 31 via the input section 211. A drive voltage VDD is applied to the final stage amplifier 31 via a fuse 32 and a drain voltage control circuit 33.

[0027] More specifically, when terminals 341 and 342 of switch 34 are connected, if the supply control signal input from input unit 214 is in a high state (on state), conduction occurs between the drain and source of the third FET in drain voltage control circuit 33. This causes drive voltage VDD to be applied to final stage amplifier 31 via fuse 32 and drain voltage control circuit 33. On the other hand, when terminals 341 and 342 of switch 34 are connected, if the supply control signal input from input unit 214 is in a low state (off state), the drain and source of the third FET in drain voltage control circuit 33 is open. This prevents drive voltage VDD from being applied to final stage amplifier 31.

[0028] By switching the supply control signal between the on state and the off state, there are periods when the final stage amplifier 31 operates to amplify and output the high frequency signal, and periods when the final stage amplifier 31 is not operating and does not output the high frequency signal, causing the amplifier circuit 21 to output a pulsed high frequency signal with amplified signal strength.

[0029] (Fail-safe operation due to the configuration of the amplifier circuits 21-24) In such a configuration, if the final stage amplifier 31 fails and shorts out, the amplifier circuit 21 operates as follows.

[0030] If the final stage amplifier 31 fails and a drain-source short occurs, a large drive current for the final stage amplifier 31 flows from the power supply main line 91 through the power supply branch line 92, the fuse 32, and the drain voltage control circuit 33. This current blows the fuse 32, thereby cutting off the power supply branch line 92. In other words, the connection between the drain voltage control circuit 33 and the final stage amplifier 31 and the power supply main line 91 is cut off.

[0031] This makes it possible to suppress a voltage drop in the power supply main line 91 and to suppress a drop in the drive voltage of the other amplifier circuits 22, 23, and 24 connected to other power supply branch lines 92 branching from the power supply main line 91. Therefore, the operating states of the amplifier circuits 22, 23, and 24 are maintained. Similarly, even if any of the amplifier circuits 22, 23, and 24 fails, the operating states of the other amplifier circuits are maintained.

[0032] In this way, by configuring the amplifier circuits 21-24 as described above, it is possible to suppress adverse effects on other amplifier circuits due to a failure in the final stage amplifier.

[0033] The power supply line monitoring IC 351 detects the voltage on the drain voltage control circuit 33 side of the fuse 32 (the drive voltage for the final stage amplifier 31) and generates a monitoring signal with a signal strength corresponding to this voltage. The power supply line monitoring IC 351 outputs the monitoring signal to the switch 34.

[0034] 3A, in the normal state, when the switch 34 receives a supply control signal and operates the final stage amplifier 31, the switch 34 connects the terminals 341 and 342 electrically. The normal state is when the final stage amplifier 31 is not malfunctioning, the fuse 32 is not blown, and the drive voltage VDD is supplied from the power supply line 90 to the drain voltage control circuit 33 and the final stage amplifier 31. In this state, the terminals 341 and 343 are open.

[0035] When the voltage on the drain voltage control circuit 33 side of the fuse 32 drops due to the disconnection of the fuse 32, the signal strength of the supervisory signal also changes (decreases). Therefore, the signal strength of the supervisory signal applied to the switch 34 changes (decreases).

[0036] 3B, switch 34 switches the connection so that terminals 341 and 342 are opened and terminals 341 and 343 are connected. As a result, the gate of the first FET of drain voltage control circuit 33 is grounded, and the connection between control unit 40 (see FIG. 5 described later), which is the output source of the supply control signal, and drain voltage control circuit 33 is cut off. Therefore, it is possible to suppress the occurrence of malfunctions such as voltage drops and malfunctions of the power supply to control unit 40.

[0037] In this way, by configuring the amplifier circuits 21-24 as described above, it is possible to suppress adverse effects on other circuits (other circuits connected to the amplifier circuits) due to a failure in the final stage amplifier.

[0038] (Fail-safe processing method) The above-described amplifier circuits 21-24 perform the fail-safe processing, for example, in accordance with the flow shown in Fig. 4. Fig. 4 is a flowchart showing the fail-safe processing according to the embodiment of the present invention.

[0039] As shown in FIG. 4, the power supply line monitoring IC 351 detects the voltage on the drain voltage control circuit 33 side of the fuse 32 and generates a monitoring signal (S11).

[0040] When the signal strength of the supervisory signal falls below the supervisory threshold (S12: YES), the switch 34 cuts off the connection between the drain voltage control circuit 33 and the control unit 40 (S13). That is, when the final stage amplifier 31 fails and shorts, the fuse 32 is blown, and the voltage on the drain voltage control circuit 33 side of the fuse 32 drops, the signal strength of the supervisory signal drops accordingly. Then, when the signal strength of the supervisory signal falls below the supervisory threshold, the connection between the drain voltage control circuit 33 and the control unit 40 is cut off.

[0041] If the signal strength of the monitoring signal is not less than the monitoring threshold (S12: NO), the switch 34 maintains the connection between the drain voltage control circuit 33 and the control unit 40 (S14). In other words, if the final stage amplifier 31 is not faulty, the fuse 32 is not blown. Therefore, the voltage on the drain voltage control circuit 33 side of the fuse 32 is maintained at the drive voltage VDD, and accordingly, the signal strength of the monitoring signal is also maintained at a high level. In this case, the connection between the drain voltage control circuit 33 and the control unit 40 is maintained.

[0042] By performing such fail-safe processing, adverse effects on other amplifier circuits and other circuits when the final stage amplifier 31 fails can be suppressed.

[0043] (Configuration of transmitting device) The above-described final stage amplifier unit 20 is used in, for example, a transmission device as shown in Fig. 5. Fig. 5 is a functional block diagram showing the configuration of a transmission device according to an embodiment of the present invention.

[0044] As shown in FIG. 5, the transmitting device 10 includes a final stage amplifier 20, a transmission signal generator 41, a variable ATT (attenuator) 42, a main amplifier 43, a coupler 44, a controller 40, a power supply 50, a fault number detector 60, and an antenna 100.

[0045] The power supply 50 supplies power to parts that require power supply in the transmission device 10. As an example, the power supply 50 supplies power to the final stage amplifier unit 20, and this power supplies the drive voltage VDD.

[0046] The transmission signal generating unit 41 generates a high frequency signal of a predetermined frequency and outputs it to the variable ATT 42. An example of a specific configuration of the transmission signal generating unit 41 is known, and therefore a description thereof will be omitted.

[0047] The variable ATT 42 is formed of, for example, a variable resistor. The variable ATT 42 is set to obtain the attenuation amount given by the control unit 40. The variable ATT 42 attenuates the input high-frequency signal by the set attenuation amount and outputs the signal to the main amplification unit 43.

[0048] The main amplifier 43 is configured, for example, by semiconductor amplifier circuits connected in multiple stages and filters connected between these amplifier circuits. The main amplifier 43 amplifies the high-frequency signal from the variable ATT 42 and outputs it to the final-stage amplifier 20. The gain of the main amplifier 43 is set, for example, so that the waveform of the high-frequency signal is not distorted by amplification and so that a predetermined signal strength is obtained.

[0049] The final stage amplifier 20 has the above-described configuration and amplifies the high-frequency signal from the main amplifier 43 so that it reaches a target intensity during transmission. The final stage amplifier 20 also receives a supply control signal from the controller 40 and performs amplification processing in accordance with the supply control signal. This allows the generation of a pulsed high-frequency signal, as described above. The final stage amplifier 20 outputs the amplified and waveform-controlled high-frequency signal (transmission signal) to the antenna 100 via the coupler 44.

[0050] The antenna 100 transmits the input transmission signal. The coupler 44 distributes a part of the transmission signal as a reference signal and outputs it to the control unit 40.

[0051] The control unit 40 sets an APC target value. The APC target value is a target signal strength of the transmission signal input to the antenna 100. While monitoring the signal strength of the reference signal, the control unit 40 sets the attenuation amount of the variable ATT 42 so that the signal strength of the transmission signal becomes the APC target value. As described above, the set attenuation amount is provided to the variable ATT 42, and the variable ATT 42 sets a resistance value to achieve this attenuation amount.

[0052] With this configuration, the transmitting device 10 controls the transmission signal so that it has a target signal strength, and transmits the transmission signal with the controlled signal strength to the outside from the antenna 100. This allows the transmitting device 10 to transmit the transmission signal with a substantially stable signal strength.

[0053] Furthermore, by including the final stage amplifier unit 20 having the above-described configuration, the transmitting device 10 can implement a fail-safe in the event of a failure of the final stage amplifier 31 of the final stage amplifier unit 20, thereby suppressing the adverse effects of this failure on other circuits of the transmitting device 10.

[0054] (Transmission power control) The transmitter 10 can perform more effective transmission control by further including the following configuration: Fig. 6 is a circuit diagram showing another example of an amplifier circuit according to an embodiment of the present invention; Fig. 7 is a circuit diagram showing the configuration of a fault number detection unit;

[0055] The amplifier circuit 21' shown in Fig. 6 differs from the amplifier circuit 21 shown in Fig. 1 in that it further includes an output unit for a supervisory signal. Other configurations of the amplifier circuit 21' shown in Fig. 6 are similar to those of the amplifier circuit 21 shown in Fig. 1, and a description of similar parts will be omitted.

[0056] The amplifier circuit 21′ includes a supervisory signal output unit 215. The supervisory signal output unit 215 is connected to the power line monitoring IC 351. The power line monitoring IC 351 outputs a supervisory signal to the switch 34 and also to the supervisory signal output unit 215. The other amplifier circuits constituting the final stage amplifier unit 20 also include supervisory signal output terminals in a similar manner. The supervisory signals output from the respective amplifier circuits are input to the fault number detector 60.

[0057] The fault number detection unit 60 generally adds together the signal strength of the monitoring signal from the power supply line monitoring IC 351 of the amplifier circuit 21', the signal strength of the monitoring signal from the power supply line monitoring IC 352 of the amplifier circuit 22' (not shown), the signal strength of the monitoring signal from the power supply line monitoring IC 353 of the amplifier circuit 23' (not shown), and the signal strength of the monitoring signal from the power supply line monitoring IC 354 of the amplifier circuit 24' (not shown), and outputs the result as a fault number detection signal.

[0058] Specifically, for example, as shown in FIG. 7 , the fault number detection unit 60 includes an operational amplifier 61 and resistors 621-626. The resistor 621 is connected to the power line monitoring IC 351 via the output unit 215. The resistor 622 is connected to the power line monitoring IC 352 via the output unit 225 (not shown). The resistor 623 is connected to the power line monitoring IC 353 via the output unit 235 (not shown). The resistor 624 is connected to the power line monitoring IC 354 via the output unit 245 (not shown). The resistors 621, 622, 623, and 624 are connected to the non-inverting input terminal of the operational amplifier 61. The output terminal of the operational amplifier 61 is connected to the inverting input terminal of the operational amplifier 61 via the resistor 626. The connection point between the inverting input terminal and the resistor 626 is grounded via the resistor 625.

[0059] With this configuration, the signal strength of the fault number detection signal depends on the number of faults. For example, the signal strength of the monitoring signal when an abnormality (failure) is detected is set to Low level, and the signal strength of the monitoring signal when normal is set to Hi level. As a result, the signal strength of the fault number detection signal decreases as the number of faults increases. That is, the signal strength of the fault number detection signal is lower when one amplifier circuit is faulty and three amplifier circuits are normal than when four amplifier circuits are normal. The signal strength of the fault number detection signal is lower when two amplifier circuits are faulty and two amplifier circuits are normal than when one amplifier circuit is faulty and three amplifier circuits are normal. The signal strength of the fault number detection signal is lower when three amplifier circuits are faulty and one amplifier circuit is normal than when two amplifier circuits are faulty and two amplifier circuits are normal. The signal strength of the fault number detection signal is lower when four amplifier circuits are faulty and one amplifier circuit is normal (total faults) than when three amplifier circuits are faulty and one amplifier circuit is normal.

[0060] The fault number detection signal having such a signal strength is input to the control unit 40. The control unit 40 calculates the number of faults from the fault number detection signal.

[0061] The control unit 40 changes the APC target value depending on the number of failures. More specifically, the more the number of failures increases, the lower the APC target value is set. Then, the control unit 40 sets an attenuation amount (corresponding to the "parameter related to adjustment" of the present invention) according to the set APC target value and provides it to the variable ATT 42. The variable ATT 42 corresponds to the "adjustment unit" of the present invention, and the control unit 40 corresponds to the "parameter control unit" of the present invention.

[0062] With this configuration, the transmitting device 10 increases the signal strength of the high frequency signal input to the amplifier circuits that are not failing, and can prevent the final stage amplifier 31 from being saturated, for example.

[0063] More specifically, when a failure reduces the number of operational amplifier circuits, the signal strength of the transmitted signal decreases. In this case, without the configuration of the present invention, the attenuation of the variable ATT 42 would be set to a small value in an attempt to achieve the APC target value. As a result, the signal strength of the high-frequency signal input to the amplifier circuit increases, causing the final-stage amplifier 31 of the amplifier circuit to saturate.

[0064] However, by lowering the APC target value depending on the number of failures, it is not necessary to significantly change the attenuation of the variable ATT 42. This makes it possible to suppress the degree to which the signal strength of the high frequency signal input to the amplifier circuit increases, and to prevent the final stage amplifier 31 of the amplifier circuit from becoming saturated.

[0065] This allows the transmitting device 10 to suppress the occurrence of side lobes in the transmission signal. That is, if none of the final stage amplifiers in the final stage amplifying unit 20 has a failure, the transmitting device 10 can transmit the transmission signal while suppressing the occurrence of side lobes.

[0066] (Transmission control method 1) The transmitting device 10 performs the fail-safe processing and transmission control, for example, according to the flow shown in Fig. 8. Fig. 8 is a flowchart showing the fail-safe processing and first transmission control according to an embodiment of the present invention. Note that the fail-safe processing is the same as in Fig. 4, and the description of the same parts will be omitted as appropriate.

[0067] As shown in FIG. 8, the power supply line monitoring ICs 351-354 of the amplifier circuits in the final stage amplifier section 20 detect the voltage on the drain voltage control circuit 33 side of each fuse 32 and generate a monitoring signal (S11).

[0068] When the signal strength of the monitoring signal becomes less than the monitoring threshold (S12: YES), the switch 34 of each amplifier circuit in the final stage amplifier unit 20 cuts off the connection between the drain voltage control circuit 33 and the control unit 40 (S13).

[0069] The fault number detector 60 generates a fault number detection signal using the monitoring signal, and the controller 40 calculates the number of faults from the signal strength of the fault number detection signal (S21). The controller 40 sets an APC target value according to the number of faults (S22).

[0070] The control unit 40 sets the attenuation amount of the variable ATT 42 according to the APC target value (S23). More specifically, the control unit 40 sets the attenuation amount of the variable ATT 42 based on the difference between the signal strength of the reference signal of the transmission signal and the APC target value.

[0071] If the signal strength of the monitoring signal is not less than the monitoring threshold (S12: NO), the switch 34 of each amplifier circuit in the final stage amplifier unit 20 continues to connect the drain voltage control circuit 33 to the control unit 40 (S14).

[0072] Since there is no faulty amplifier circuit, the control unit 40 maintains the APC target value (S31). The control unit 40 sets the attenuation amount of the variable ATT 42 according to the APC target value (S23). More specifically, the control unit 40 sets the attenuation amount of the variable ATT 42 based on the difference between the signal strength of the reference signal of the transmission signal and the APC target value.

[0073] By performing such processing, it is possible to realize the above-mentioned fail-safe processing and transmission control that suppresses the occurrence of side lobes.

[0074] (Transmission control method 2) The transmitting device 10 performs the fail-safe processing and transmission control, for example, according to the flow shown in Fig. 9. Fig. 9 is a flowchart showing the fail-safe processing and second transmission control according to an embodiment of the present invention. Note that the fail-safe processing and part of the transmission control are the same as those in Fig. 8, and the description of the same parts will be omitted as appropriate.

[0075] If there is a fault, the process up to step S21 is the same as in Fig. 8, and therefore the description will be omitted. The control unit 40 compares the number of faults with a fault number threshold. If the number of faults is less than the fault number threshold (S41: NO), the control unit 40 sets an APC target value according to the number of faults (S22). The control unit 40 sets the attenuation amount of the variable ATT 42 according to the APC target value (S23). More specifically, the control unit 40 sets the attenuation amount of the variable ATT 42 from the difference between the signal strength of the reference signal of the transmission signal and the APC target value.

[0076] If the number of failures is equal to or greater than the failure number threshold (S41: YES), the control unit 40 detects whether or not there is a total failure. If there is a total failure (S42: YES), the control unit 40 stops transmission (S45). If there is not a total failure (S42: NO), the control unit 40 stops APC control (S43). In other words, in step S43, the control unit 40 stops setting the APC target value and stops control to match the signal strength of the reference signal to the APC target value. When the attenuation setting from the control unit 40 stops, the variable ATT 42 sets the attenuation to a fixed value (S44).

[0077] By performing this processing, it is possible to realize transmission control that suppresses the occurrence of side lobes in the same way as the first transmission control, unlike the first transmission control. Also, if the number of failures increases, it is possible that the setting of the variable ATT to match the APC target value cannot be stably controlled. In such cases, stable transmission control can be achieved by setting the attenuation amount of the variable ATT to a fixed value.

[0078] When performing such second transmission control, the control unit 40 can also perform control according to, for example, the control table shown in Fig. 10. Fig. 10 is a diagram showing an example of a control table for the second transmission control of the present invention. Note that Fig. 10 shows a case where the number of amplifier circuits is four, but the number is not limited to this, and a table can be set based on a similar concept according to each number.

[0079] The control unit 40 detects the number of faults. If the number of faults is 0-3, i.e., if all the amplifier circuits are not faulty, the control unit 40 transmits using the amplifier circuits that are operating. On the other hand, if the number of faults is 4, i.e., if all the amplifier circuits are faulty, the control unit 40 stops transmission.

[0080] If the number of faults is 0, the control unit 40 sets the APC target value to Pn0 and sets the attenuation of the variable ATT 42 to ATT0. The attenuation ATT0 is sequentially updated and set based on the difference between the APC target value Pn0 and the reference signal.

[0081] If the number of faults is one, the control unit 40 sets the APC target value to Pn1 and sets the attenuation of the variable ATT 42 to ATT1. The APC target value Pn1 is a value smaller than the APC target value Pn0. The attenuation ATT1 is set by successively updating it based on the difference between the APC target value Pn1 and the reference signal.

[0082] If the number of faults is two or three, the control unit 40 stops the APC control and sets the attenuation of the variable ATT 42 to ATTc, which is a fixed value.

[0083] (Another way to generate a monitoring signal) In the above explanation, a supervisory signal is generated at each predetermined sampling timing and used, but a supervisory signal for determination can also be generated from supervisory signals at multiple sampling timings and used for the above-mentioned fail-safe processing and transmission control. Fig. 11 is a flowchart showing an example of a process for generating a supervisory signal for determination.

[0084] At a predetermined sampling timing, the power supply line monitoring ICs 351-354 generate a monitoring signal corresponding to the drive voltage VDD, more precisely, the voltage on the drain voltage control circuit 33 side of the fuse 32 (S111). The power supply line monitoring ICs 351-354 detect the signal strength of the monitoring signal and temporarily store it (S112). The power supply line monitoring ICs 351-354 continue this process until a predetermined number of times have been performed (S113: NO).

[0085] When the generation of the monitoring signal and the detection of the signal strength reach a predetermined number of times (S113: YES), the power line monitoring ICs 351-354 calculate the signal strength of the monitoring signal for determination (S114). The power line monitoring ICs 351-354 output the monitoring signal for determination to the switch 34 or the fault number detection unit 60. The switch 34 or the fault number detection unit 60 uses the signal strength of the monitoring signal for determination to perform the above-mentioned processes and controls.

[0086] The signal strength of the supervisory signal for determination is calculated, for example, by averaging the signal strengths of the supervisory signal at multiple sampling times.Furthermore, the signal strength of the supervisory signal for determination is calculated by excluding the maximum and minimum values ​​of the signal strengths of the supervisory signal at multiple sampling times and then averaging the remaining signal strengths.

[0087] By performing such processing, the influence of noise contained in the drive voltage VDD can be suppressed, and therefore a monitor signal (monitor signal for determination) with a more stable signal strength can be obtained.

[0088] The transmitter having the above-described configuration is applied to, for example, a radar device, but the above-described configuration can be applied to any device that generates a high-frequency signal requiring high output using a semiconductor amplifier circuit.

[0089] In the above description, the power supply line monitoring ICs 351-354 perform fault detection based on voltage, but fault detection can also be performed based on current. [Explanation of symbols]

[0090] 10: Transmitting device 20: Final stage amplifier 21, 22, 23, 24: Amplification circuit 31: Final stage amplifier 32: Fuse 33: Drain voltage control circuit 34: Switch 40: Control unit 41: Transmission signal generator 42: Variable ATT 43: Main amplifier 44: Coupler 50: Power supply 60: Fault count detection unit 61: Operational amplifier 90: Power line 100: Antenna 201, 202, 203: Distributor 204, 205, 206: Synthesizer 211, 214: Input section 212, 215, 225, 235, 245: Output section 331: First connection part 332: Second connection part 333: Third connection part 341, 342, 343: Terminals 351, 352, 353, 354: Power line monitoring IC 621, 622, 623, 624, 625, 626: Resistor

Claims

1. a plurality of amplifiers for amplifying high frequency signals; a power supply main line common to the plurality of amplifier units; a plurality of power supply branch lines branching from the power supply main line; a protection unit that is disposed on the power supply branch line connected to the amplifier unit, and that is cut off when a drive current flowing from the power supply branch line to the amplifier unit becomes large, thereby interrupting the power supply branch line and thereby interrupting the connection between the power supply main line and the amplifier unit; a power supply control unit connected between the amplifier unit and the protection unit and controlling the supply of a drive voltage to the amplifier unit; a monitoring unit that generates a monitoring signal having a signal strength corresponding to a voltage on the amplifier side of the protection unit; a control unit that generates a supply control signal to be provided to the power supply control unit in order to control the supply of the drive voltage to the amplifier unit when the signal strength of the monitor signal decreases, and a switch that controls interruption of connection between the power supply control unit and the power supply control unit; An amplifier device comprising:

2. An amplification device according to claim 1, the power supply control unit is configured using a FET, a gate of the FET constituting the power supply control unit is connected to the switch; The switch grounds the gate of the FET to cut off the connection between the control unit and the power supply control unit. Amplification device.

3. An amplification device according to claim 1 or claim 2, a synthesis unit that synthesizes the high-frequency signals output from the plurality of amplification units, Amplification device.

4. An amplification device according to claim 3; an antenna connected to the combiner and transmitting the combined high-frequency signal; A radar device comprising:

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