Semiconductor Devices

Abstract

The objective of the present invention is to provide a semiconductor device comprising a plurality of semiconductor elements, wherein the degree of freedom of the layout can be improved, the temperature of the semiconductor elements can be detected while taking into consideration the distribution of heat generated within the semiconductor device, and the effective area of the semiconductor elements can be maximized. This semiconductor device comprises: a base plate; a plurality of semiconductor elements; and a plurality of wiring elements disposed on the base plate so as to be adjacent to the plurality of semiconductor elements on a one-to-one basis. A diode for detecting the temperature of the adjacent semiconductor element among the plurality of semiconductor elements is disposed inside each wiring element. A wire pad of each wiring element is disposed so as to oppose a wire pad of the adjacent semiconductor element. The diode of each wiring element is disposed on the side closer to the adjacent semiconductor element. The wire pad of each semiconductor element and the wire pad of each wiring element adjacent to each semiconductor element are connected by a wire.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In semiconductor devices mounted on power converters such as inverters, a configuration is adopted in which multiple semiconductor elements are connected in parallel to be driven in order to pass a large current. In a semiconductor device having multiple semiconductor elements, Patent Document 1, for example, discloses a configuration in which wiring elements are provided separately from the semiconductor elements as a means for maximizing the effective area of ​​the semiconductor elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 110170 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology described in Patent Document 1, a wiring element is placed in the center of a base plate, and multiple semiconductor elements are placed around the wiring element, thereby making the wire lengths of the semiconductor elements and the wiring elements uniform. This creates restrictions on the placement of the semiconductor elements and the wiring elements, and on the routing of the external electrodes, resulting in a problem of low layout freedom.

[0005] Furthermore, in order to monitor overheating and overcurrent conditions in a semiconductor device, it is necessary to provide temperature detection elements for detecting the temperatures of the semiconductor elements in multiple semiconductor elements, which makes it difficult to maximize the effective area of ​​all semiconductor elements.If a temperature detection element is provided in any of multiple semiconductor elements, it can only detect the temperature of the semiconductor element in which the temperature detection element is provided, so it is not possible to select the semiconductor element for temperature detection taking into account the heat generation distribution within the semiconductor device.

[0006] Therefore, the present disclosure aims to provide a technology that can improve layout freedom in a semiconductor device having multiple semiconductor elements, detect the temperature of the semiconductor elements taking into account the heat distribution within the semiconductor device, and maximize the effective area of ​​the semiconductor elements. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure comprises a base plate, a plurality of semiconductor elements mounted on the base plate, each having a wire pad, and a plurality of wiring elements arranged on the base plate adjacent to each of the semiconductor elements, each having a wire pad, wherein a temperature sensor is arranged within each of the wiring elements to detect the temperature of an adjacent semiconductor element among the plurality of semiconductor elements, the wire pad of each of the wiring elements is arranged to face the wire pad of the adjacent semiconductor element, the temperature sensor of each of the wiring elements is arranged on the side of the adjacent semiconductor element, and the wire pad of each of the semiconductor elements and the wire pad of each of the wiring elements adjacent to each of the semiconductor elements are connected via wires. [Effects of the Invention]

[0008] According to the present disclosure, multiple wiring elements are arranged adjacent to multiple semiconductor elements, and the wire pads of each wiring element are arranged facing the wire pads of the adjacent semiconductor elements, so that wires between the semiconductor elements and the wiring elements do not interfere with each other and wiring can be performed within a certain wire length. This eliminates the need to arrange the semiconductor elements so as to surround the wiring elements, and improves the layout flexibility of the semiconductor device compared to conventional methods.

[0009] Furthermore, since a temperature sensor corresponding to each semiconductor element is disposed within each wiring element, the semiconductor element for temperature detection can be selected taking into consideration the heat distribution within the semiconductor device.

[0010] In addition, because the temperature sensor of each wiring element is located on the side of the adjacent semiconductor element, thermal coupling with the semiconductor element is good, improving the temperature detection accuracy of the semiconductor element. This allows the number of temperature sensors to be reduced from the semiconductor element, maximizing the effective area of ​​the semiconductor element.

[0011] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a top view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a top view of a wiring element included in the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA in FIG. [Figure 5] FIG. 4 is a cross-sectional view taken along line BB in FIG. 3. [Figure 6] 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment. [Figure 7] FIG. 10 is a top view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a top view of a wiring element included in a semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is an equivalent circuit diagram of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a top view of a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a top view of a wiring element included in a semiconductor device according to a third embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line CC in FIG. [Figure 13] 10 is an equivalent circuit diagram of a semiconductor device and a control board when a high-voltage diode is provided on the control board. FIG. [Figure 14] 11 is an equivalent circuit diagram of a semiconductor device and a control board when a high-voltage diode is provided in the semiconductor device according to the third embodiment. FIG. [Figure 15] FIG. 10 is a top view of a wiring element included in a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 10 is an equivalent circuit diagram of a wiring element included in a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 10 is a top view of a semiconductor device according to a fifth embodiment. [Figure 18] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 19] FIG. 13 is a top view of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] <First Embodiment> <Overall structure of semiconductor device> The first embodiment will be described below with reference to the drawings. FIG. 1 is a top view of a semiconductor device 100 according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device 100 according to the first embodiment. FIG. 3 is a top view of a wiring element 10 included in the semiconductor device 100 according to the first embodiment. FIG. 4 is a cross-sectional view taken along line AA in FIG. 3. FIG. 5 is a cross-sectional view taken along line BB in FIG. 3. FIG. 6 is an equivalent circuit diagram of the semiconductor device 100 according to the first embodiment. In FIG. 2, the extending directions of the external electrodes 20 and the control terminals 22 have been changed to make it easier to see the connection relationship between the components.

[0014] As shown in Figures 1 and 2, the semiconductor device 100 includes a base plate 1, multiple (e.g., three) semiconductor elements 2, multiple (e.g., three) wiring elements 10, external electrodes 20, and four control terminals 22.

[0015] The base plate 1 is mainly made of metals such as Cu and Al. The base plate 1 is formed in a rectangular shape when viewed from above and functions as a drain terminal. Hereinafter, the base plate 1 will also be referred to as the drain terminal 1.

[0016] A plurality of semiconductor elements 2 are mounted on a base plate 1 by bonding their back surfaces via a conductive bonding material 5 such as solder, Ag paste, or Cu paste. Each semiconductor element 2 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The surface electrode of each semiconductor element 2 is divided into two areas: an area where main terminal electrodes 3 through which a main current flows are located, and an area where wire pads 4 are located for transmitting drive voltage, temperature, and overcurrent signals for each semiconductor element 2. The area where the wire pads 4 are located is on the right side (the wiring element 10 side) in FIG. 1, and the area where the main terminal electrodes 3 are located is on the left side in FIG. 1.

[0017] The main terminal electrode 3 is bonded to an external electrode 20 via a conductive bonding material 5, and the wire pad 4 is connected to a wire pad 12 of an adjacent wiring element 10 via a wire 21. Each semiconductor element 2 may be a semiconductor switching element other than a MOSFET, such as an IGBT (Insulated Gate Bipolar Transistor) or a reverse conducting IGBT.

[0018] The multiple wiring elements 10 are arranged on the base plate 1 so as to be adjacent to the multiple semiconductor elements 2, respectively. The multiple wiring elements 10 are arranged on the base plate 1 by bonding their back surfaces via a conductive bonding material 5. Within each wiring element 10 are arranged a resistor 14 that suppresses the oscillation action of an adjacent semiconductor element 2 among the multiple semiconductor elements 2, and a diode 13 that serves as a temperature sensor that detects the temperature of the adjacent semiconductor element 2. The diode 13 of each wiring element 10 is arranged on the side of the adjacent semiconductor element 2.

[0019] The external electrodes 20 are made of Cu and are arranged on the main terminal electrodes 3 of the multiple semiconductor elements 2 to connect the multiple semiconductor elements 2. The main terminal electrodes 3 function as source terminals, and the external electrodes 20 arranged on the main terminal electrodes 3 also function as source terminals. Hereinafter, the external electrodes 20 will also be referred to as source terminals 20.

[0020] As shown in FIGS. 1 and 6, the semiconductor elements 2 are connected in parallel, and the wiring elements 10 are connected to the semiconductor elements 2 in a state adjacent to each of the semiconductor elements 2.

[0021] The four control terminals 22 are terminals for inputting and outputting signals related to the control of each semiconductor element 2. The four control terminals 22 are a current sense terminal 22a, a Kelvin source terminal 22b, a gate terminal 22c, and a temperature sense anode terminal 22d, and are connected to each semiconductor element 2 via each wiring element 10. In the first embodiment, a current sensing method is adopted as a short circuit detection method for detecting a short circuit state of the semiconductor element 2.

[0022] <Structure of wiring element> Next, the structure of each wiring element 10 will be described. As shown in Figures 3, 4, and 5, each wiring element 10 has a Si substrate 11 as its base material, and a back electrode 15 made of Al, Ti, Ni, or Au is formed on the back surface of the Si substrate 11. The back surface of each wiring element 10 is bonded to the base plate 1 via a conductive bonding material 5, similar to the semiconductor element 2.

[0023] A thermal oxide film 16 is formed on the surface of the Si substrate 11, and passive elements such as a resistor 14 made of polycrystalline polysilicon (Poly-Si) 18 and a diode 13 made of polycrystalline polysilicon (P-type) 18a and polycrystalline polysilicon (N-type) 18b are formed on the thermal oxide film 16. In order to insulate the resistor 14 from each signal terminal of the diode 13 on the surface side of the Si substrate 11, an insulating interlayer film 17 is formed on the thermal oxide film 16 and the polycrystalline polysilicon 18, 18a, 18b. Furthermore, a wire pad 12 made of Al is formed on the insulating interlayer film 17 as a surface electrode.

[0024] A contact portion 17a is provided in a portion of the insulating interlayer film 17 for electrically connecting the resistor 14 and the diode 13 to the wire pad 12 serving as a surface electrode. As shown in FIG. 1, the wire pad 4 of the semiconductor element 2 is connected to the control terminal 22 via the wiring element 10, which has the function of relaying wiring. Therefore, as shown in FIGS. 1, 4, and 5, the surface of the wiring element 10 is provided with wire pads 12 for connecting the wire pad 4 of the semiconductor element 2 to the control terminal 22 with wires 21. The wire pads 12 of each wiring element 10 are arranged so as to face the wire pads 4 of the adjacent semiconductor element 2, and are also arranged in other locations. The wire pads 4 of each semiconductor element 2 are connected to the wire pads 12 of each wiring element 10 adjacent to each semiconductor element 2 via wires 21.

[0025] The inside of the semiconductor device 100 is sealed with a sealing material (not shown) made of epoxy resin or the like to ensure insulation.

[0026] <Effects> Next, the effects of the semiconductor device 100 according to the first embodiment will be described in comparison with the technology described in Patent Document 1 (WO 2020 / 110170).

[0027] In the technology described in Patent Document 1, a wiring element is placed in the center of a base plate, and multiple semiconductor elements are placed around the wiring element so that the wire lengths between the semiconductor element and the wiring element are uniform. As a result, restrictions are imposed on the placement of the semiconductor element and the wiring element, and on the routing of the external electrodes, resulting in a problem of low layout freedom.

[0028] In contrast, the semiconductor device 100 according to the first embodiment includes a base plate 1, a plurality of semiconductor elements 2 mounted on the base plate 1, each having a wire pad 4, and a plurality of wiring elements 10 arranged on the base plate 1 adjacent to the plurality of semiconductor elements 2, each having a wire pad 12. A diode 13 is arranged within each wiring element 10 as a temperature sensor for detecting the temperature of an adjacent semiconductor element 2 among the plurality of semiconductor elements 2. The wire pad 12 of each wiring element 10 is arranged so as to face the wire pad 4 of the adjacent semiconductor element 2. The diode 13 as a temperature sensor of each wiring element 10 is arranged on the side of the adjacent semiconductor element 2. The wire pad 4 of each semiconductor element 2 and the wire pad 12 of each wiring element 10 adjacent to each semiconductor element 2 are connected via wires 21.

[0029] Therefore, the multiple wiring elements 10 are arranged adjacent to the multiple semiconductor elements 2, respectively, and the wire pads 12 of each wiring element 10 are arranged facing the wire pads 4 of the adjacent semiconductor element 2, so that the wires 21 between the semiconductor elements 2 and the wiring elements 10 do not interfere with each other, and wiring can be performed at a fixed wire length or less. This eliminates the need to arrange the semiconductor elements 2 so as to surround the wiring elements 10, and improves the layout freedom of the semiconductor device 100 compared to conventional methods.

[0030] In addition, since a diode 13 is arranged within each wiring element 10 as a temperature sensor corresponding to each semiconductor element 2, the semiconductor element 2 for temperature detection can be selected taking into account the heat distribution within the semiconductor device 100.

[0031] Furthermore, the diode 13 serving as a temperature sensor in each wiring element 10 is arranged on the side of the adjacent semiconductor element 2, which provides good thermal coupling with the semiconductor element 2 and improves the accuracy of temperature detection for the semiconductor element 2. This allows the temperature sensor to be removed from the semiconductor element 2, thereby maximizing the effective area of ​​the semiconductor element 2.

[0032] Furthermore, when multiple semiconductor elements 2 are driven in parallel, variations in the characteristics of the semiconductor elements 2 and stray inductance of the main terminals and wires 21 within the semiconductor device 100 can cause transient surge voltages and currents to become biased, potentially resulting in malfunction and destruction of the semiconductor elements 2. Generally, to suppress gate oscillation of the semiconductor elements 2 due to transient surges at turn-off, a balancing resistor for the purpose of oscillation suppression is provided on the gate wiring of the semiconductor elements 2. In this embodiment, each wiring element 10 further includes a resistor 14 for suppressing oscillation of the adjacent semiconductor element 2. This eliminates the need to provide a balancing resistor in the semiconductor element 2, making it possible to inexpensively suppress malfunction and destruction of the semiconductor device 100.

[0033] <Embodiment 2> Next, a semiconductor device 100A according to a second embodiment will be described. Fig. 7 is a top view of the semiconductor device 100A according to the second embodiment. Fig. 8 is a top view of an interconnection element 10A included in the semiconductor device 100A according to the second embodiment. Fig. 9 is an equivalent circuit diagram of the semiconductor device 100A according to the second embodiment. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0034] As shown in FIGS. 7, 8, and 9, in the second embodiment, the short-circuit detection method for detecting a short-circuit state of the semiconductor element 2 is changed from a current sensing method to a desaturation voltage detection method. Therefore, instead of the current sense terminal 22a (see FIG. 1), a desaturation voltage detection output terminal 22e is provided as the control terminal 22 to output the desaturation voltage (drain voltage) of each semiconductor element 2 to the outside. The desaturation voltage detection output terminal 22e is connected to the drain terminal 1. By changing the short-circuit detection method from the current sensing method to the desaturation voltage detection method, the current sense element 4a formed in each semiconductor element 2 and the current sense path formed in the wiring element 10 are eliminated, as shown in FIG. 1. Here, the current sense path refers to the portion of the path from the current sense element 4a shown in FIG. 1 to the current sense terminal 22a via the wire 21 and the wire pad 12, which is formed in the wiring element 10.

[0035] As described above, the semiconductor device 100A according to the second embodiment further includes a control terminal 22 for inputting and outputting signals related to the control of each semiconductor element 2, and the control terminal 22 includes a non-saturation voltage detection output terminal 22e for extracting the drain voltage of each semiconductor element 2 to the outside.

[0036] Therefore, the current sensing elements 4a of the semiconductor elements 2 and the current sensing paths of the wiring elements 10 can be reduced, and the cost of the semiconductor device 100A can be reduced without impairing the protection function of the semiconductor elements 2.

[0037] <Third Embodiment> Next, a semiconductor device according to a third embodiment will be described. Fig. 10 is a top view of a semiconductor device 100B according to the third embodiment. Fig. 11 is a top view of an interconnection element 10B included in the semiconductor device 100B according to the third embodiment. Fig. 12 is a cross-sectional view taken along line CC in Fig. 11. Note that in the third embodiment, the same components as those described in the first and second embodiments are designated by the same reference numerals, and description thereof will be omitted.

[0038] 10, 11, and 12, in the third embodiment, a high-voltage diode 19 is disposed in each wiring element 10B to insulate the non-saturation voltage detection output terminal 22e for extracting the drain voltage of the adjacent semiconductor element 2 to the outside. - Layer 29, N + Layer 30, P - Layer 31, P + A layer 32 is formed.

[0039] Next, the effect of arranging a high-voltage diode 19 in each wiring element 10B will be described, comparing it with the case where the high-voltage diode 19 is arranged on a control board that controls the semiconductor device. Fig. 13 is an equivalent circuit diagram of the semiconductor device and the control board when the high-voltage diode 19 is provided on the control board. Fig. 14 is an equivalent circuit diagram of the semiconductor device 100B and the control board when the high-voltage diode 19 is provided in the semiconductor device 100B according to the third embodiment.

[0040] As shown in FIG. 13, the control board is provided with a high-voltage diode 19 in addition to a control IC 33, a resistor 34, and a capacitor 35, and it is necessary to provide high-voltage wiring at a location on the control board that is connected to the desaturation voltage detection output terminal 22e.

[0041] In contrast, as shown in FIG. 14, when a high-voltage diode 19 is arranged in each wiring element 10B, the desaturation voltage detection output terminal 22e is electrically insulated within the semiconductor device 100B, so there is no need to provide high-voltage wiring on the control board, which can lead to a reduction in the size of the control board and improved layout flexibility.

[0042] Also, the charging current I CHG , the value of resistor 34 R DESAT , the forward voltage V of the high-voltage diode 19 F , the saturation voltage V of the semiconductor element 2, which is a MOSFET DS Then, the overcurrent determination threshold V of the control IC33 DESAT is V DESAT =I CHG ×R DESAT +V F+V DS It is expressed as:

[0043] MOSFET saturation voltage V DS has a positive temperature characteristic where the absolute value increases as the temperature increases, so the higher the ambient temperature, the lower the overcurrent determination threshold V DESAT The control IC 33 determines the overcurrent threshold V DESAT However, since the monitoring range of the control IC 33 is limited, the overcurrent determination threshold V DESAT If this becomes too high, it will affect the operating temperature range of the overcurrent protection circuit.

[0044] 14, by arranging the high-voltage diode 19 in each wiring element 10B near the semiconductor element 2, which is a heat source, the temperature of the high-voltage diode 19 rises more than in the case of FIG. 13. The forward voltage V F has a negative temperature characteristic that decreases as the temperature increases, and acts to cancel the MOSFET saturation voltage temperature characteristic. DESAT The detection accuracy is improved.

[0045] <Fourth Embodiment> Next, a semiconductor device according to embodiment 4 will be described. Fig. 15 is a top view of the wiring element 10C included in the semiconductor device according to embodiment 4. Fig. 16 is an equivalent circuit diagram of the wiring element 10C included in the semiconductor device according to embodiment 4. Note that in embodiment 4, the same components as those described in embodiments 1 to 3 are designated by the same reference numerals and description thereof will be omitted.

[0046] In the fourth embodiment, a protection diode 24 is added to the first embodiment. Specifically, as shown in FIGS. 15 and 16, a protection diode 24 is disposed within each wiring element 10C to protect the adjacent semiconductor element 2 from electrostatic breakdown. Specifically, within each wiring element 10C, a protection diode 24 is disposed between the gate terminal G and the Kelvin source terminal KS, and between the current sense terminal CS and the Kelvin source terminal KS. Here, the gate terminal G, the Kelvin source terminal KS, the current sense terminal CS, and the temperature sense anode terminal A in FIGS. 15 and 16 are connected via wires 21 to the gate terminal 22c, the Kelvin source terminal 22b, the current sense terminal 22a, and the temperature sense anode terminal 22d in FIG. 1, respectively.

[0047] This makes it possible to suppress electrostatic breakdown of the semiconductor element 2, thereby improving the reliability and ease of assembly of the semiconductor device.

[0048] <Fifth Embodiment> Next, a semiconductor device 100D according to a fifth embodiment will be described. Fig. 17 is a top view of the semiconductor device 100D according to the fifth embodiment. Fig. 18 is a cross-sectional view of the semiconductor device 100D according to the fifth embodiment. Note that in the fifth embodiment, the same components as those described in the first to fourth embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0049] 17 and 18, in the fifth embodiment, the plurality of wiring elements 10 are arranged at positions on the external electrode 20 corresponding to each of the plurality of semiconductor elements 2 so as to be adjacent to and above each of the plurality of semiconductor elements 2 with the external electrode 20 in between. The plurality of wiring elements 10 are arranged on the external electrode 20 by bonding their back surfaces via a conductive bonding material 5.

[0050] Within each wiring element 10 are disposed a resistor 14 for suppressing the oscillation of the semiconductor element 2 adjacent thereto below, across the external electrode 20, among the multiple semiconductor elements 2, and a diode 13 as a temperature sensor for detecting the temperature of the semiconductor element 2 adjacent thereto below, across the external electrode 20. The wire pads 12 of each wiring element 10 are disposed so as to face the wire pads 4 of the semiconductor element 2 adjacent thereto below, across the external electrode 20, and are also disposed in other locations. The diodes 13 of each wiring element 10 are disposed on the side of the semiconductor element 2 adjacent thereto below, across the external electrode 20. The wire pads 4 of each semiconductor element 2 and the wire pads 12 of the wiring elements 10 adjacent thereto above each semiconductor element 2 are connected via wires 21.

[0051] As described above, in the semiconductor device 100D according to the fifth embodiment, similarly to the first embodiment, it is possible to improve the degree of freedom in layout, detect the temperature of the semiconductor element 2 taking into consideration the heat distribution within the semiconductor device 100D, and maximize the effective area of ​​the semiconductor element 2. Furthermore, it is not necessary to provide a balancing resistor in the semiconductor element 2, and malfunction and breakdown of the semiconductor device 100D can be suppressed at low cost.

[0052] Furthermore, since the multiple wiring elements 10 are arranged at positions on the external electrodes 20 corresponding to the multiple semiconductor elements 2 so as to be adjacent to and above each of the multiple semiconductor elements 2 with the external electrodes 20 interposed therebetween, the area of ​​the base plate 1 can be reduced compared to the case of embodiment 1. This allows the semiconductor device 100D to be miniaturized.

[0053] <Sixth Embodiment> Next, a semiconductor device 100E according to embodiment 6 will be described. Fig. 19 is a top view of the semiconductor device 100E according to embodiment 6. Note that in embodiment 6, the same components as those described in embodiments 1 to 5 are denoted by the same reference numerals, and description thereof will be omitted.

[0054] In the fifth embodiment, the plurality of wiring elements 10 are arranged on the upper surfaces of the external electrodes 20 that are arranged in the regions where the main terminal electrodes 3 of each semiconductor element 2 are arranged.

[0055] 19, in the sixth embodiment, the main terminal electrode 3, which is the surface electrode of each semiconductor element 2, is divided into two regions 3a and 3b. A plurality of wiring elements 10 are arranged in one region 3a, and external electrodes 20 are arranged in the other region 3b.

[0056] Specifically, the wiring elements 10 are bonded to one region 3a of each of the semiconductor elements 2 via a conductive bonding material (not shown) so as to be adjacent to and above each of the semiconductor elements 2. The external electrodes 20 are bonded to the other region 3b of each of the semiconductor elements 2 via a conductive bonding material (not shown).

[0057] Within each wiring element 10 are disposed a resistor 14 that suppresses the oscillation of the semiconductor element 2 adjacent below it among the multiple semiconductor elements 2, and a diode 13 that serves as a temperature sensor that detects the temperature of the semiconductor element 2 adjacent below. The wire pads 12 of each wiring element 10 are disposed so as to face the wire pads 4 of the semiconductor element 2 adjacent below, and are also disposed in other locations. The diodes 13 of each wiring element 10 are disposed on the side of the semiconductor element 2 adjacent below. The wire pads 4 of each semiconductor element 2 and the wire pads 12 of each wiring element 10 adjacent above each semiconductor element 2 are connected via wires 21.

[0058] As described above, in the semiconductor device 100E according to the sixth embodiment, similarly to the first embodiment, it is possible to improve the degree of freedom in layout, detect the temperature of the semiconductor element 2 taking into consideration the heat distribution within the semiconductor device 100E, and maximize the effective area of ​​the semiconductor element 2. Furthermore, it is not necessary to provide a balancing resistor in the semiconductor element 2, and malfunction and breakdown of the semiconductor device 100E can be suppressed at low cost.

[0059] Furthermore, since the main terminal electrode 3 of each semiconductor element 2 is divided into two regions 3a, 3b, with each wiring element 10 arranged in one region 3a and the external electrode 20 arranged in the other region 3b, the thermal coupling between the wiring element 10 and the semiconductor element 2 is improved compared to embodiment 5, and the temperature detection accuracy of the semiconductor element 2 is improved.

[0060] <Modifications of Embodiments 1 to 6> In the first to sixth embodiments, the number of the semiconductor elements 2 and the number of the wiring elements 10, 10A, 10B, 10C are each described as three, but this is not limited thereto, and it is sufficient that the number of both is two or more and is the same.

[0061] Furthermore, in embodiments 1 to 6, the same number of wiring elements 10, 10A, 10B, and 10C as the semiconductor elements 2 are arranged, but the number of wiring elements 10, 10A, 10B, and 10C does not have to be the same as the semiconductor elements 2, and two or more wiring elements 10, 10A, 10B, and 10C may be configured on one Si substrate 11.

[0062] In addition, in the first to sixth embodiments, a capacitor made of a silicon oxide film or an insulating interlayer film may be formed in each of the wiring elements 10, 10A, 10B, and 10C. By forming a low-pass filter with the resistor 14 in each of the wiring elements 10, 10A, 10B, and 10C, the resistance of the semiconductor element 2 to switching noise is improved.

[0063] Furthermore, in the first to sixth embodiments, the resistance value of the resistors 14 arranged in each of the wiring elements 10, 10A, 10B, and 10C may be adjustable by laser trimming. This makes it possible to suppress variations in the balance resistors connected between each of the semiconductor elements 2. When placing a balance resistor at the gate to prevent gate oscillation when turning off the parallel operation, a large difference in the values ​​of the balance resistors connected to each of the semiconductor elements 2 increases the risk of oscillation. However, since the variation in the resistance values ​​is reduced, the risk of oscillation is reduced and malfunction of the semiconductor elements 2 can be suppressed.

[0064] In addition, the protection diode 24 of the fourth embodiment can be adopted in the second and third embodiments, and the desaturation voltage detection output terminal 22e of the second embodiment, the high-voltage diode 19 of the third embodiment, and the protection diode 24 of the fourth embodiment can be adopted in the fifth and sixth embodiments.

[0065] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0066] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. [Explanation of symbols]

[0067] 1 base plate, 2 semiconductor element, 3 main terminal electrode, 3a, 3b regions, 4 wire pad, 10, 10A, 10B, 10C wiring elements, 12 wire pad, 13 diode, 14 resistor, 19 high voltage diode, 20 external electrode, 21 wire, 22 control terminal, 22e output terminal for detecting desaturation voltage, 24 protection diode.

Claims

1. A base plate and a plurality of semiconductor elements mounted on the base plate, each having a wire pad; a plurality of wiring elements disposed on the base plate adjacent to the plurality of semiconductor elements, each of the wiring elements having a wire pad; a temperature sensor for detecting the temperature of an adjacent semiconductor element among the plurality of semiconductor elements is disposed within each of the wiring elements; the wire pads of each of the wiring elements are arranged to face the wire pads of the adjacent semiconductor elements; the temperature sensor of each of the wiring elements is disposed on the side of the adjacent semiconductor element, The semiconductor device, wherein the wire pads of each of the semiconductor elements and the wire pads of each of the wiring elements adjacent to each of the semiconductor elements are connected via wires.

2. 2. The semiconductor device according to claim 1, wherein each of said wiring elements further includes a resistor for suppressing oscillation of said adjacent semiconductor element.

3. Further, a control terminal is provided for inputting and outputting signals related to the control of each of the semiconductor elements, 3. The semiconductor device according to claim 1, wherein said control terminal includes a terminal for extracting a drain voltage of each of said semiconductor elements to the outside.

4. 4. The semiconductor device according to claim 3, wherein a high-voltage diode is disposed within each of said wiring elements to insulate said terminal for extracting said drain voltage of said adjacent semiconductor element to the outside.

5. 2. The semiconductor device according to claim 1, wherein a protection diode is disposed in each of said wiring elements to protect said adjacent semiconductor elements from electrostatic breakdown.

6. A base plate and a plurality of semiconductor elements mounted on the base plate, each having a wire pad; external electrodes arranged on the plurality of semiconductor elements and connecting the plurality of semiconductor elements; a plurality of wiring elements each having a wire pad, the wiring elements being arranged on the external electrodes at positions corresponding to the semiconductor elements so as to be adjacent to and above the respective semiconductor elements with the external electrodes interposed therebetween; a temperature sensor is disposed within each of the wiring elements to detect the temperature of one of the plurality of semiconductor elements adjacent thereto below across the external electrode; the wire pads of each of the wiring elements are arranged to face the wire pads of the adjacent semiconductor element below, with the external electrodes interposed therebetween; the temperature sensor of each of the wiring elements is disposed on the side of the semiconductor element adjacent thereto below, with the external electrode interposed therebetween; The semiconductor device, wherein the wire pads of each of the semiconductor elements and the wire pads of each of the wiring elements adjacent to and above each of the semiconductor elements are connected via wires.

7. 7. The semiconductor device according to claim 6, wherein each of said wiring elements further includes a resistor for suppressing oscillation of said semiconductor element adjacent thereto below with said external electrode interposed therebetween.

8. A base plate and a plurality of semiconductor elements mounted on the base plate, each having a wire pad and a surface electrode divided into two regions; external electrodes arranged on the plurality of semiconductor elements and connecting the plurality of semiconductor elements; a plurality of wiring elements each having a wire pad, the wiring elements being arranged in one region of each of the plurality of semiconductor elements so as to be adjacent to and above the semiconductor elements; the external electrodes are connected to the other regions of the semiconductor elements; a temperature sensor for detecting the temperature of the semiconductor element adjacent below among the plurality of semiconductor elements is disposed within each of the wiring elements; the wire pads of each of the wiring elements are arranged to face the wire pads of the adjacent semiconductor element below; The temperature sensor of each of the wiring elements is disposed on the side of the semiconductor element adjacent thereto below, The semiconductor device, wherein the wire pads of each of the semiconductor elements and the wire pads of each of the wiring elements adjacent to and above each of the semiconductor elements are connected via wires.

9. 9. The semiconductor device according to claim 8, wherein each of said wiring elements further includes a resistor for suppressing oscillation of said semiconductor element adjacent thereto below.

10. 9. The semiconductor device according to claim 1, wherein a capacitor made of a silicon oxide film or an insulating interlayer film is formed in each of said wiring elements.

11. 10. The semiconductor device according to claim 2, wherein the resistance value of the resistor disposed in each of the wiring elements can be adjusted by laser trimming.

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