Bandpass Filter

Abstract

This bandpass filter comprises: an input terminal (1) that receives an RF signal as an input; a multi-phase distributor (3) that divides the RF signal input to the input terminal into n RF signals having phases differing by 360 deg / n, where n is a natural number greater than or equal to 1; n signal paths (17-20) that are connected to the multi-phase distributor and each have a sample-and-hold element with two switches, each of the n signal paths sampling and holding one of the n RF signals with phases differing by 360 deg / n from the multi-phase distributor and outputting the held signal; a multi-phase synthesizer (4) that is connected to the n signal paths and synthesizes n signals output from the n signal paths; an output terminal (2) that outputs a signal obtained by the synthesizing by the multi-phase synthesizer; and a clock signal source (21) that outputs a clock signal (S1) that drives all the switches.

Description

[Technical Field]

[0001] The present disclosure relates to bandpass filters. [Background technology]

[0002] In wireless communications, bandpass filters are used to remove interference or unwanted waves. Patent Document 1 discloses technology related to a bandpass filter circuit. More specifically, Patent Document 1 discloses a bandpass filter circuit including: a switch connected between an input and an output and switching an input signal voltage at a system clock frequency; a switched capacitor connected between the switch and ground potential; multiple sample-and-hold capacitors connected between the output and ground potential; and multiple sample-and-hold switches connected between the output and ground potential and connected in series to each of the sample-and-hold capacitors, wherein the sample-and-hold switches are sequentially turned on one by one at a sampling clock frequency to hold a signal voltage appearing at a sample time in the sample-and-hold capacitor and the sample-and-hold switches are sequentially switched cyclically. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-82875 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the configuration in which sample-hold switches are switched cyclically and sequentially as in Patent Document 1 has the problem that it is difficult to generate a clock signal that switches multiple sample-hold switches in a short signal cycle.

[0005] The present disclosure has been made to solve such problems, and aims to provide a bandpass filter that passes RF signals in a desired band without cyclically switching multiple switches sequentially. [Means for solving the problem]

[0006] One aspect of a bandpass filter according to an embodiment of the present disclosure includes: an input terminal that accepts an RF signal as an input, where n is a natural number greater than or equal to 1; a multi-phase divider that divides the RF signal input to the input terminal into n RF signals that differ in phase by 360 degrees / n; n signal paths connected to the multi-phase divider, each signal path having a sample-and-hold element including two switches, that accepts one of the n RF signals that differ in phase by 360 degrees / n from the multi-phase divider, samples and holds it, and outputs the held signal; a multi-phase combiner connected to the n signal paths and combines the n signals output from the n signal paths; an output terminal that outputs a signal combined by the multi-phase combiner; and a clock signal source that outputs a clock signal that drives all switches. [Effects of the Invention]

[0007] According to the bandpass filter according to the embodiment of the present disclosure, RF signals in a desired band can pass through without cyclically switching a plurality of switches sequentially. [Brief explanation of the drawings]

[0008] [Figure 1] Fig. 1A is a diagram showing a configuration of a band-pass filter according to Embodiment 1. Fig. 1B is a diagram showing an example of the waveform of a clock signal used by the band-pass filter of Fig. 1A. [Figure 2] FIG. 2 is a diagram illustrating a first modification of the band-pass filter according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating a second modification of the band-pass filter according to the first embodiment. [Figure 4]Fig. 4A is a diagram showing a configuration of a band-pass filter according to Embodiment 2. Fig. 4B is a diagram showing an example of a waveform of a clock signal used by the band-pass filter of Fig. 4A. [Figure 5] Fig. 5A is a diagram showing a configuration of a band-pass filter in the second embodiment when n = 2. Fig. 5B is a diagram showing an example of a waveform of a clock signal used by the band-pass filter of Fig. 5A. [Figure 6] Fig. 6A is a diagram showing an example of the waveform of an input RF signal when n = 2. Fig. 6B is a diagram showing an example of the waveform of an RF signal after signal processing in each signal path when n = 2. Fig. 6C is a diagram showing an example of the waveform of an RF signal output after synthesis processing when n = 2. [Figure 7] Fig. 7A is a diagram showing a configuration of a band-pass filter according to Embodiment 3. Fig. 7B is a diagram showing an example of a waveform of a clock signal used by the band-pass filter of Fig. 7A. [Figure 8] Fig. 8A is a diagram showing a configuration of a band-pass filter in the third embodiment when n = 2. Fig. 8B is a diagram showing an example of the waveform of a clock signal used by the band-pass filter of Fig. 8A. [Figure 9] Fig. 9A is a diagram showing a configuration of a band-pass filter according to Embodiment 4. Fig. 9B is a diagram showing an example of a waveform of a clock signal used by the band-pass filter of Fig. 9A. [Figure 10] Fig. 10A is a diagram showing a configuration of a band-pass filter in the fourth embodiment when n = 2. Fig. 10B is a diagram showing an example of a waveform of a clock signal used by the band-pass filter of Fig. 10A. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a current-controlled amplifier circuit included in the band-pass filter according to the fourth embodiment. [Figure 12] FIG. 12 is a diagram showing the frequency characteristics of the pass characteristics of the current-controlled amplifier circuit included in the band-pass filter according to the fourth embodiment. [Figure 13] FIG. 13 is a diagram illustrating the frequency characteristics of the bandpass filter according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Components with the same or similar reference numerals in the drawings have the same or similar configurations or functions, and redundant descriptions of such components will be omitted. Furthermore, in this disclosure, the term "or" is used to mean an inclusive logical OR unless otherwise specified.

[0010] Embodiment 1 <Configuration> A band-pass filter according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 3. Figure 1 is a circuit diagram illustrating a band-pass filter according to a first embodiment of the present disclosure. As shown in FIG. 1A, the bandpass filter according to the first embodiment includes: an input terminal 1 that receives an RF (Radio Frequency) signal as an input, where n is a natural number greater than or equal to 1; a multi-phase divider 3 that divides the RF signal input to input terminal 1 into n RF signals that differ in phase by 360 degrees / n; n signal paths 17-20 connected to multi-phase divider 3, each signal path including a sample-and-hold element including two switches, that receive one of the n RF signals that differ in phase by 360 degrees / n from multi-phase divider 3, sample and hold it, and output the held signal; a multi-phase combiner 4 connected to the n signal paths 17-20 and combines the n signals output from the n signal paths 17-20; an output terminal 2 that outputs the signal combined by the multi-phase combiner 4; and a clock signal source 21 that outputs a clock signal S1 that drives all the switches.

[0011] (clock signal source) A clock signal source 21 is used to drive all the switches, for example, with a period T LOThe band-pass filter outputs a square-wave clock signal S1 with a duty ratio of 50%. Note that as long as the band-pass filter operates as the desired filter, the duty ratio does not have to be 50%, and other periodic waveforms such as sine waves or sawtooth waves may be used.

[0012] (switch) The switches 5 to 12 are driven by a clock signal S1 output from a clock signal source 21. The switches 5 to 12 are turned ON when the clock signal S1 is HIGH. The switches 5 to 12 have the same characteristics.

[0013] (Multi-phase distributor) The multi-phase divider 3 divides an RF signal input to the input terminal 1 into n signals with phase differences of 360 degrees / n each. The multi-phase divider 3 has n output ports that output the n divided signals.

[0014] (Signal path) Each of the n signal paths includes a sample-and-hold element. As an example, as shown in FIG. 1A, each signal path includes two switches and one capacitor as sample-and-hold elements. FIG. 1A specifically illustrates signal paths 17 to 20 among the n signal paths. Note that the example of FIG. 1A does not intend to limit n to an integer equal to or greater than 4; as mentioned above, n may be a natural number equal to or greater than 1. Signal path 17 is connected to an output port of multi-phase divider 3 from which a 0° RF signal is output, and is composed of two switches 5 and 6 connected in series, and a capacitor 13 connected between the junction between switches 5 and 6 and ground. Signal path 18 is connected to an output port of multi-phase divider 3 from which a 360 / n×1 degree RF signal is output, and is composed of two switches 7 and 8 connected in series, and a capacitor 14 connected between the junction between switches 7 and 8 and ground. Signal path 19 is connected to an output port from which a 360 / nx2-degree RF signal is output from the multi-phase divider 3, and is composed of two switches 9 and 10 connected in series, and a capacitor 15 connected between the connection point between switches 9 and 10 and ground. Signal path 20 is connected to an output port from which a 360 / nx(n-1)-degree RF signal is output from the multi-phase divider 3, and is composed of two switches 11 and 12 connected in series, and a capacitor 16 connected between the connection point between switches 11 and 12 and ground. Capacitors 13 to 16 have the same characteristics.

[0015] (Multi-phase synthesizer) The multi-phase combiner 4 combines n signals, each with a phase difference of 360 degrees / n, output from the signal paths 17, 18, 19, . . . , 20. The signal combined by the multi-phase combiner 4 is output to the output terminal 2.

[0016] <Operation> An RF signal input from input terminal 1 is divided into RF signals of multiple phases, each differing in phase by 360 degrees / n, by multi-phase divider 3. For example, when n=3, the RF signal input from input terminal 1 is divided into three-phase RF signals, each differing in phase by 120 degrees.

[0017] The distributed 0° phase RF signal is down-converted to the clock frequency when clock signal S1 is HIGH (when switch 5 is ON). Then, a voltage is charged to capacitor 13 (low-pass filtered), and the charged signal is up-converted when clock signal S1 is HIGH (when switch 6 is ON). These operations are also performed for signal paths 18, 19, ..., 20.

[0018] The signals output from each signal path are added by a multi-phase combiner 4 to obtain an output signal.

[0019] This embodiment differs from the operational procedure described in Patent Document 1 in that a multi-phase input signal (RF signal) is down-converted or up-converted using a single-phase clock signal S1. That is, unlike Patent Document 1, this embodiment does not cyclically switch multiple switches sequentially; in other words, a single-phase input signal is not down-converted or up-converted using a multi-phase clock signal. The bandpass filter according to this embodiment can obtain narrow-band bandpass filter characteristics centered on the clock signal frequency. The phases of the clock signals during down-conversion and up-conversion do not need to match. However, the phase of the clock signal for down-conversion must match over the entire path, and the phase of the clock signal for up-conversion must match over the entire path. If the phases of the clock signals for down-conversion are not consistent over the entire path, the down-converted sections will be shifted, changing the voltage value charged to the capacitor and degrading the pass characteristics. Furthermore, if the phases of the clock signals for up-conversion are not consistent over the entire path, the sample and hold sections will be shifted, degrading the pass characteristics.

[0020] <Variation 1> Although FIG. 1A illustrates an example in which the sample-and-hold elements are configured using capacitors, the sample-and-hold elements may be configured using other electronic components or circuits. For example, as shown in FIG. 2, the sample-and-hold elements may be configured using first-order lag active circuits (13b-16b) instead of capacitors. The first-order lag active circuits 13b-16b are, for example, varactor diodes or amplifiers. Note that the active circuits used in each signal path have the same characteristics. FIG. 2 specifically illustrates signal paths 17b-20b among the n signal paths. Signal path 17b is connected to an output port of multi-phase divider 3 that outputs a 0° signal, and is composed of two switches 5 and 6 connected in series, and a first-order lag active circuit 13b connected between switches 5 and 6. Signal path 18b is connected to an output port of multi-phase divider 3 that outputs a 360 / n×1 degree signal, and is composed of two switches 7 and 8 connected in series, and a first-order lag active circuit 14b connected between switches 7 and 8. Signal path 19b is connected to an output port from which a 360 / nx2 degree signal is output from the multi-phase divider 3, and is composed of two switches 9 and 10 connected in series, and a first-order lag active circuit 15b connected between switches 9 and 10. Signal path 20b is connected to an output port from which a 360 / nx(n-1) degree signal is output from the multi-phase divider 3, and is composed of two switches 11 and 12 connected in series, and a first-order lag active circuit 16b connected between switches 11 and 12.

[0021] <Variation 2> As yet another example, as shown in FIG. 3, instead of capacitors, current-controlled amplifier circuits (13c to 16c) may be used to configure sample-and-hold elements. FIG. 3 specifically illustrates signal paths 17c to 20c among the n signal paths. As shown in FIG. 3, signal path 17c is connected to an output port of multi-phase divider 3 from which a 0° signal is output, and is configured with two switches 5 and 6 connected in series, and a current-controlled amplifier circuit 13c connected between switches 5 and 6. Signal path 18c is connected to an output port of multi-phase divider 3 from which a 360 / n×1 degree signal is output, and is configured with two switches 7 and 8 connected in series, and a current-controlled amplifier circuit 14c connected between switches 7 and 8. Signal path 19c is connected to an output port of multi-phase divider 3 from which a 360 / n×2 degree signal is output, and is configured with two switches 9 and 10 connected in series, and a current-controlled amplifier circuit 15c connected between switches 9 and 10. Signal path 20c is connected to an output port of multi-phase divider 3 that outputs a 360 / nx(n-1)-degree signal, and is composed of two switches 11 and 12 connected in series and a current-controlled amplifier circuit 16c connected between switches 11 and 12. The current-controlled amplifier circuits used in each signal path have the same characteristics. A circuit such as that shown in FIG. 11 may be used as each current-controlled amplifier circuit. An example configuration shown in FIG. 11 will be described later in conjunction with embodiment 4.

[0022] Embodiment 2 <Configuration> A band-pass filter according to a second embodiment of the present disclosure will be described with reference to Fig. 4 to Fig. 6. Fig. 4 is a circuit diagram illustrating a band-pass filter according to a second embodiment of the present disclosure. As shown in Fig. 4A, the band-pass filter according to the second embodiment has an input terminal 1 that receives an RF (Radio Frequency) signal as an input, and a filter that receives the RF signal input to the input terminal 1 in a 360° / 2 phase. n Two phases differing by two n and a multi-phase divider 3 that divides the RF signal into two nThe signal paths 17 to 20 each include a sample-and-hold element including two switches, and are 360° / 2 n Two phases differing by two n 2 receives one of the RF signals from the multi-phase divider 3, samples and holds it, and outputs the held signal. n Signal paths 17-20 and 2 n connected to signal paths 17 to 20, n 2 output from signal paths 17-20 n the signal combined by the multi-phase combiner 4; an output terminal 2 that outputs the signal combined by the multi-phase combiner 4; and a clock signal source 21 that outputs a clock signal S1 that drives all the switches in the equal-length signal paths.

[0023] (clock signal source) The clock signal source 21 is configured to drive all the switches, for example, with a period T LO The bandpass filter outputs a square-wave clock signal S1 with a duty ratio of 50%. Note that the duty ratio does not have to be 50%, and other periodic waveforms such as sine waves or sawtooth waves may be used as long as the bandpass filter operates as desired. The signal paths from the clock signal source 21 to the switches 5 to 12 are all equal in length.

[0024] (switch) The switches 5 to 12 are driven by a clock signal S1 output from a clock signal source 21. The switches 5 to 12 are turned ON when the clock signal S1 is HIGH. The switches 5 to 12 have the same characteristics.

[0025] (Multi-phase distributor) The multi-phase distributor 3 divides the RF signal input to the input terminal 1 into 360° / 2 n Two phases differing by two n The phase difference can be given by adjusting the length of the line in the multi-phase distributor 3. n 2 to output the signal n It has an output port.

[0026] (Signal path) 2 n Each signal path of the signal paths includes a sample-and-hold element. As an example, as shown in FIG. 4A, each signal path includes two switches and one capacitor as sample-and-hold elements. n The figure specifically illustrates signal paths 17 to 20 among the signal paths. Signal path 17 is connected to an output port of multi-phase divider 3 from which a 0° RF signal is output, and is composed of two switches 5 and 6 connected in series, and a capacitor 13 connected between the connection point between switches 5 and 6 and ground. Signal path 18 is connected to an output port of multi-phase divider 3 from which a 360 / 2 RF signal is output, and is composed of two switches 5 and 6 connected in series, and a capacitor 13 connected between the connection point between switches 5 and 6 and ground. n The signal path 19 is connected to an output port from which an x1-degree RF signal is output, and is composed of two switches 7 and 8 connected in series, and a capacitor 14 connected between the junction between the switches 7 and 8 and ground. n The signal path 20 is connected to an output port from which an x2-degree RF signal is output, and is composed of two switches 9 and 10 connected in series, and a capacitor 15 connected between the connection point between the switches 9 and 10 and ground. n x(2 n The amplifier is connected to an output port from which a -1) degree RF signal is output, and is composed of two switches 11 and 12 connected in series, and a capacitor 16 connected between the connection point between switches 11 and 12 and ground. Capacitors 13 to 16 have the same characteristics.

[0027] (Multi-phase synthesizer) The multi-phase combiner 4 combines the phases of the signals output from the signal paths 17, 18, 19, . . . , 20, each of which has a phase of 360 degrees / 2. n 2 different n The signal synthesized by the multi-phase synthesizer 4 is output to the output terminal 2.

[0028] As an example, a circuit diagram when n=2 in the second embodiment is shown in FIG. 5A. Since n=2, the number of signal paths is 4 (=2 2) The connection relationships other than the specific number of paths are the same as in FIG. 4A. FIG. 5B is a diagram showing an example of the waveform of a clock signal used by the band-pass filter of FIG. 5A.

[0029] <Operation> FIG. 6 is a diagram showing an example of waveforms at each stage when n=2 in the second embodiment. Fig. 6A is a diagram showing an example of the waveform of an input RF signal, Fig. 6B is a diagram showing an example of the waveform of an RF signal processed in each signal path, and Fig. 6C is a diagram showing an example of the waveform of an RF signal output after synthesis processing.

[0030] When n=2, the input signal is divided into four phases by the multi-phase divider 3a, and then the divided RF signal with a phase of 0° is down-converted at the clock frequency when the clock signal S1 is HIGH (when the switch 5 is ON). Then, a voltage is charged to the capacitor 13 (low-pass filtered), and the charged signal is up-converted when the clock signal S1 is HIGH (when the switch 6 is ON).

[0031] These operations are also performed on signal paths 18, 19, ..., 20. Figure 6B shows the waveforms of the signals on each signal path after down-conversion, low-pass filtering, and up-conversion. The signals output from each signal path are added by a multi-phase combiner 4a to obtain the output signal shown in Figure 6C.

[0032] This embodiment differs from the operational procedure described in Patent Document 1 in that a four-phase input signal (RF signal) is down-converted and up-converted using a single-phase clock signal S1. The bandpass filter according to this embodiment can obtain narrow-band bandpass filter characteristics with the clock signal frequency as the center frequency. The phases of the clock signals during down-conversion and up-conversion do not need to match. However, the phase of the clock signal for down-conversion must match over the entire path, and the phase of the clock signal for up-conversion must match over the entire path. If the phase of the clock signal for down-conversion does not match over the entire path, the down-converted section will shift, changing the voltage value charged to the capacitor and degrading the pass characteristics. Furthermore, if the phase of the clock signal for up-conversion does not match over the entire path, the sample section and hold section will shift, degrading the pass characteristics.

[0033] In this embodiment, the signal paths from the clock signal source to each switch are aligned, so a virtual short occurs at the end of the clock signal path through the parasitic capacitance of each down-conversion switch between signal paths with a 180° phase difference. This makes it possible to provide a bandpass filter that makes the loss due to the clock signal source invisible and improves the high-frequency pass characteristics of the input signal.

[0034] Embodiment 3 <Configuration> Next, a band-pass filter according to a third embodiment of the present disclosure will be described with reference to Fig. 7 and Fig. 8. Fig. 7A is a circuit diagram showing a band-pass filter according to the third embodiment of the present disclosure. As shown in Fig. 7A, the band-pass filter according to the third embodiment includes an input terminal 1, an output terminal 2, a multi-phase divider 3, and multi-phase combiners 4 and 2. n The signal paths 17b to 20b are each made up of switches 5 to 12 and first-order lag active circuits 13b to 16b.

[0035] (clock signal source) The clock signal source 21 has a period T LO The bandpass filter outputs a square-wave clock signal S1 with a duty ratio of 50%. Note that the duty ratio does not have to be 50%, and other periodic waveforms such as sine waves or sawtooth waves may be used as long as the bandpass filter operates as desired. The signal paths from the clock signal source 21 to the switches 5 to 12 are all equal in length.

[0036] (switch) The switches 5 to 12 are controlled by a clock signal S1 output from a clock signal source 21. The switches 5 to 12 are turned ON when the clock signal S1 is HIGH. The switches 5 to 12 have the same characteristics.

[0037] The active circuits 13b to 16b of the first-order delay system are, for example, varactor diodes or amplifiers. Note that the active circuits used in each signal path have the same characteristics.

[0038] (Multi-phase distributor) The multi-phase distributor 3 divides the RF signal input to the input terminal 1 into 360° / 2 n Two phases differing by two n The phase difference can be given by adjusting the length of the line in the multi-phase distributor 3. n 2 to output the signal n It has an output port.

[0039] (Signal path) 2 n Each signal path of the signal paths includes a sample-and-hold element. As an example, as shown in FIG. 7A, each signal path includes two switches and one active circuit of a first-order delay system. In FIG. 7A, n The signal paths 17b to 20b are specifically illustrated. The signal path 17b is connected to an output port from which a 0° signal is output from the multi-phase divider 3, and is composed of two switches 5 and 6 connected in series and a first-order delay active circuit 13b connected between the switches 5 and 6. The signal path 18b is connected to an output port from which a 360 / 2° signal is output from the multi-phase divider 3, and is composed of two switches 5 and 6 connected in series and a first-order delay active circuit 13b connected between the switches 5 and 6.n The signal path 19b is connected to an output port from which a signal of x1 degree is output, and is composed of two switches 7 and 8 connected in series, and a first-order delay active circuit 14b connected between the switches 7 and 8. The signal path 19b is connected to the ... of the multi-phase divider 3 from the 360 / 2 n The signal path 20b is connected to an output port from which a signal of x2 degrees is output, and is composed of two switches 9 and 10 connected in series, and a first-order delay active circuit 15b connected between the switches 9 and 10. The signal path 20b is connected to the ... of the multi-phase divider 3 from n x(2 n The circuit is connected to an output port from which a signal of −1) degree is output, and is composed of two switches 11 and 12 connected in series, and an active circuit 16b of a first-order delay system connected between the switches 11 and 12.

[0040] (Multi-phase synthesizer) The multi-phase combiner 4 combines the phases of the signals output from the signal paths 17b, 18b, 19b, . . . , 20b, each of which has a phase of 360 degrees / 2 n 2 different n The signal synthesized by the multi-phase synthesizer 4 is output to the output terminal 2.

[0041] As an example, a circuit diagram when n=2 in the third embodiment is shown in FIG. 8A. Since n=2, the number of signal paths is 4 (=2 2 ) The connection relationships other than the specific number of paths are the same as in FIG. 7A. FIG. 8B is a diagram showing an example of the waveform of a clock signal used by the band-pass filter of FIG. 8A.

[0042] <Operation> The general shapes of the input waveform, the waveforms processed by each signal path, and the output waveform are the same as those in Figure 6. Since the active circuit of the first-order lag system functions in the same way as a capacitor, the band-pass filter of embodiment 3 operates in the same way as in embodiment 2. The passband width is determined by a value equivalent to the capacitance of the active circuit of the first-order lag system.

[0043] When n=2, the input signal is divided into four phases by the multi-phase divider 3a, and then the divided RF signal of phase 0° is down-converted at the clock frequency when the clock signal S1 is HIGH (when the switch 5 is ON). After that, a voltage is charged (low-pass filtered) to the active circuit 13b of the first-order lag system, and the charged signal is up-converted when the clock signal S1 is HIGH (when the switch 6 is ON).

[0044] These operations are performed on signal paths 18b, 19b, ..., 20b. The waveform of each signal path after upconversion is as shown in Figure 6B, and the signals output from each signal path are added by multi-phase combiner 4a to obtain the output signal shown in Figure 6C.

[0045] While Patent Document 1 down-converts and up-converts a single-phase input signal using a four-phase clock signal, this embodiment down-converts and up-converts a four-phase input signal using a single-phase clock signal, which is a difference from the technology of Patent Document 1. The bandpass filter of this embodiment, like the filter of Patent Document 1, can achieve narrowband bandpass filter characteristics with the clock signal frequency as its center frequency. The phases of the clock signals during down-conversion and up-conversion do not need to match. However, the phase of the clock signal for down-conversion must match over the entire path, and the phase of the clock signal for up-conversion must match over the entire path. If the phase of the clock signal for down-conversion does not match over the entire path, the down-converted section will shift, changing the voltage value charged to the active circuit of the first-order lag system and degrading the pass characteristics. Furthermore, if the phase of the clock signal for up-conversion does not match over the entire path, the sample section and hold section will shift, degrading the pass characteristics.

[0046] In this embodiment, since the signal paths from the clock signal source to each switch are aligned, a virtual short occurs at the end of the clock signal path through the parasitic capacitance of each down-conversion switch between signal paths with a 180° phase difference. This makes it possible to provide a bandpass filter that makes the loss due to the clock signal source invisible and improves the high-frequency pass characteristics of the input signal. In addition, when a varactor diode is used as the active circuit of the first-order delay system, the capacitance value can be voltage-controlled, making it possible to achieve variability in the passband width. Replacing the varactor diode with an amplifier makes it possible to improve the pass characteristics.

[0047] Embodiment 4 <Configuration> Next, a band-pass filter according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 9 to 13. FIG. 9A is a circuit diagram showing a band-pass filter according to a fourth embodiment of the present disclosure. The circuit diagram of FIG. 9A differs from the circuit diagram of FIG. 7A in that the first-order delay active circuit of FIG. 7A is replaced with a current-controlled amplifier circuit. As shown in FIG. 9A, the band-pass filter according to the fourth embodiment has an input terminal 1, an output terminal 2, a multi-phase divider 3, a multi-phase combiner 4, a multi-phase combiner 2, and a multi-phase combiner 3. n The signal paths 17c to 20c are each composed of switches 5 to 12 and current-controlled amplifier circuits 13c to 16c. The current-controlled amplifier circuits 13c to 16c are first-order lag amplifier circuits that maintain a constant pass gain even when the passband width is varied by current control.

[0048] (clock signal source) The clock signal source 21 has a period T LO The bandpass filter outputs a square-wave clock signal S1 with a duty ratio of 50%. Note that the duty ratio does not have to be 50%, and other periodic waveforms such as sine waves or sawtooth waves may be used as long as the bandpass filter operates as desired. The signal paths from the clock signal source 21 to the switches 5 to 12 are all equal in length.

[0049] (switch) The switches 5 to 12 are controlled by a clock signal S1 output from a clock signal source 21. The switches 5 to 12 are turned ON when the clock signal S1 is HIGH. The switches 5 to 12 have the same characteristics.

[0050] (Multi-phase distributor) The multi-phase distributor 3 divides the signal input to the input terminal 1 into 360 degrees / 2 n Two phases differing by two n The phase difference can be given by adjusting the length of the line in the multi-phase distributor 3. n 2 to output the signal n It has an output port.

[0051] (Signal path) 2 n Each signal path of the signal path includes a sample-and-hold element. As an example, as shown in Figures 9A and 11, each signal path consists of two switches and one current-controlled amplifier circuit. In Figure 9A, n 9A, signal path 17c is connected to an output port from which a 0° signal is output from multi-phase divider 3, and is composed of two switches 5 and 6 connected in series, and a current-controlled amplifier circuit 13c connected between switches 5 and 6. Signal path 18c is connected to an output port from which a 360 / 2 ... n The signal path 19c is connected to an output port from which a signal of x1 degree is output, and is composed of two switches 7 and 8 connected in series, and a current-controlled amplifier circuit 14c connected between the switches 7 and 8. The signal path 19c is connected to the ... of the multi-phase divider 3, and is composed of a 360 / 2 n The signal path 20c is connected to an output port from which a signal of x2 degrees is output, and is composed of two switches 9 and 10 connected in series, and a current-controlled amplifier circuit 15c connected between the switches 9 and 10. The signal path 20c is connected to the output port from which a signal of x2 degrees is output from the multi-phase divider 3. n x(2 nThe amplifier is connected to an output port from which a signal of -1) degree is output, and is composed of two switches 11 and 12 connected in series, and a current-controlled amplifier circuit 16c connected between the switches 11 and 12. The current-controlled amplifier circuits used in each signal path have the same characteristics.

[0052] (Multi-phase synthesizer) The multi-phase combiner 4 combines the phases of the signals output from the signal paths 17c, 18c, 19c, . . . , 20c, each of which has a phase of 360 degrees / 2 n 2 different n The signal synthesized by the multi-phase synthesizer 4 is output to the output terminal 2.

[0053] As an example, a circuit diagram when n=2 in the fourth embodiment is shown in FIG. 10A. Since n=2, the number of signal paths is 4 (=2 2 ) The connection relationships other than the specific number of paths are the same as in FIG. 9A. FIG. 10B is a diagram showing an example of the waveform of a clock signal used by the band-pass filter of FIG. 10A.

[0054] 11 shows an example of a current-controlled amplifier circuit according to the fourth embodiment. An input voltage Vin input to an input terminal 31 (second input terminal) is connected to the gate terminal of an N-type transistor 36 (first N-type transistor). A resistor 35 is connected between a power supply terminal 33 and the drain terminal of the N-type transistor 36. A variable current source 37 (first current source) is connected between the source terminal of the N-type transistor 36 and ground. A gate terminal of an N-type transistor 39 (second N-type transistor) is connected to the drain terminal of the N-type transistor 36. A current source 40 (second current source) is connected between the source terminal of the N-type transistor 39 and ground. A source terminal of a P-type transistor 38 is connected to the power supply terminal 33, a gate terminal of the P-type transistor 38 is connected to a bias terminal 34, and a drain terminal of the P-type transistor 38 is connected to the drain terminal of the N-type transistor 39. An output terminal 32 (second output terminal) is connected to the drain terminals of the N-type transistor 39 and the P-type transistor 38.

[0055] 11 is expressed by the following equation (1) using the resistance value R of resistor 35, the transconductance gm of N-type transistors 36 and 39, the output resistance Ro of P-type transistor 38, the current I supplied by variable current sources 37 and 40, and the input voltage Vin. In equation (1), β is the gain coefficient of N-type transistors 36 and 39, and λ is the channel modulation effect coefficient of P-type transistor 38. TIFF0007738802000001.tif11166

[0056] The upper cutoff frequency fc is expressed by the following equation (2): Co is the parasitic capacitance between the drain and source of the P-type transistor 38. TIFF0007738802000002.tif12166

[0057] The passband variable range is expressed by the following equation (3): In equation (3), Imin and Imax are the minimum and maximum currents of the variable current source, respectively. TIFF0007738802000003.tif13166

[0058] As described above, the voltage gain is determined by the sizes and resistance value R of N-type transistors 36 and 39 and P-type transistor 38, and not by current control of variable current sources 37 and 40. Furthermore, the high cutoff frequency fc can be varied by current control of variable current sources 37 and 40. For example, if the current I of variable current sources 37 and 40 is given a 1000-fold dynamic range of about 1 μA to 1 mA, then the equation for the wide cutoff frequency shows that the amount of passband variation can also be varied over a wide band with a dynamic range of about 1000 times.

[0059] The voltage gain of this amplifier circuit and the pass characteristics of this bandpass filter are shown in Figures 12 and 13. The 3 dB bandwidth of the bandpass filter is twice the upper cutoff frequency fc of the amplifier circuit.

[0060] <Operation> The input waveform, the waveforms processed in each signal path, and the output waveform are generally the same as in FIG.

[0061] When n=2, the input signal is divided into four phases by the multi-phase divider 3a, and then the divided RF signal of phase 0° is down-converted at the clock frequency when the clock signal S1 is HIGH (when the switch 5 is ON). Then, a voltage is charged (low-pass filtered) to the current-controlled amplifier circuit 13c, and the charged signal is up-converted when the clock signal S1 is HIGH (when the switch 6 is ON).

[0062] These operations are performed on signal paths 18c, 19c, ..., 20c. The waveform of each signal path after upconversion is as shown in Figure 6B, and the signals output from each signal path are added by multi-phase combiner 4a to obtain the output signal shown in Figure 6C.

[0063] While Patent Document 1 down-converts and up-converts a single-phase input signal using a four-phase clock signal, this embodiment down-converts and up-converts a four-phase input signal using a single-phase clock signal, which is a difference between the technology of Patent Document 1. The bandpass filter of this embodiment, like the filter of Patent Document 1, can achieve narrow bandpass filter characteristics centered on the clock signal frequency. The phases of the clock signals during down-conversion and up-conversion do not need to match. However, the phase of the clock signal for down-conversion must match over the entire path, and the phase of the clock signal for up-conversion must match over the entire path. If they do not match, the down-converted section will shift, changing the voltage value charged to the current-controlled amplifier circuit and degrading the pass characteristics. Furthermore, if the phase of the clock signal for up-conversion does not match over the entire path, the sample and hold sections will shift, degrading the pass characteristics.

[0064] In this embodiment, the signal paths from the clock signal source to each switch are aligned, so a virtual short occurs at the end of the clock signal path through the parasitic capacitance of each down-conversion switch between signal paths with a 180° phase difference. This makes it possible to provide a bandpass filter that makes the loss due to the clock signal source invisible and improves the high-frequency pass characteristics of the input signal.

[0065] In the example of FIG. 11, a field effect transistor is used as the transistor, but any semiconductor element having a transconductance gm may be used, and a semiconductor element such as a bipolar transistor may also be used.

[0066] It is possible to combine the embodiments, and to modify or omit each embodiment as appropriate. [Industrial Applicability]

[0067] The bandpass filters of the present disclosure can be used in wireless communication devices. [Explanation of symbols]

[0068] 1 input terminal, 2 output terminal, 3 multi-phase divider, 3a multi-phase divider, 4 multi-phase combiner, 4a multi-phase combiner, 5-12 switch, 13 capacitor, 13b active circuit, 13c current-controlled amplifier circuit, 14 capacitor, 14b active circuit, 14c current-controlled amplifier circuit, 15 capacitor, 15b active circuit, 15c current-controlled amplifier circuit, 16 capacitor, 16b active circuit, 16c current-controlled amplifier circuit, 17(b, c)-20(b, c) signal path, 21 clock signal source, 31 input terminal, 32 output terminal, 33 power supply terminal, 34 bias terminal, 35 resistor, 36 N-type transistor, 37 variable current source, 38 P-type transistor, 39 N-type transistor, 40 variable current source.

Claims

1. Let n be a natural number greater than or equal to 1. an input terminal that accepts an RF signal as an input; a multi-phase divider that divides an RF signal input to the input terminal into n RF signals with phases that differ by 360 degrees / n; n signal paths connected to the multi-phase divider, each signal path including a sample-and-hold element including two switches, receiving one of the n RF signals having phases different by 360 degrees / n from the multi-phase divider, sampling and holding the signal, and outputting the held signal; a multi-phase combiner connected to the n signal paths and combining n signals output from the n signal paths; an output terminal for outputting a signal synthesized by the multi-phase synthesizer; a clock signal source that outputs a clock signal that drives all switches so that the phases of the clock signals are the same in all of the n signal paths; Equipped with Bandpass filter.

2. The multi-phase divider divides the RF signal input to the input terminal into n RF signals with phase differences of 360 degrees / n, instead of dividing the RF signal into n RF signals with phase differences of 360 degrees / n. ｎ Two phases differ by ｎ and dividing it into RF signals of The number of signal paths is two. ｎ Each signal path is 360 degrees / 2 ｎ Two phases differ by ｎ receiving one of the RF signals from the multi-phase divider, sampling and holding it, and outputting the held signal; The multi-phase combiner ｎ is connected to the signal path of the ｎ 2 output from the signal path ｎ The signals are combined, the signal paths between the clock signal source and all switches are equal in length; 2. The bandpass filter according to claim 1.

3. The sample and hold element includes two switches connected in series and a capacitor connected to a connection point between the two switches and ground.

2. The bandpass filter according to claim 1.

4. the sample-and-hold element comprises two switches connected in series, and a first-order lag active circuit disposed between the two switches and connected to the two switches; 2. The bandpass filter according to claim 1.

5. the sample and hold element comprises two switches connected in series and a current-controlled amplifier circuit disposed between the two switches and connected to the two switches; The current-controlled amplifier circuit is a first-order delay amplifier circuit, and has a constant pass gain even when the pass bandwidth is varied by current control.

2. The bandpass filter according to claim 1.

6. The current controlled amplifier circuit comprises: a second input terminal; and A power terminal and A bias terminal; a first N-type transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the first N-type transistor being connected to the second input terminal; a resistor connected between the power supply terminal and the drain terminal of the first N-type transistor; a first current source connected between the source terminal of the first N-type transistor and ground; a second N-type transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the second N-type transistor being connected to the drain terminal of the first N-type transistor; a second current source connected between the source terminal of the second N-type transistor and ground; a P-type transistor having a gate terminal, a drain terminal, and a source terminal, the source terminal of the P-type transistor being connected to the power supply terminal, the gate terminal of the P-type transistor being connected to the bias terminal, and the drain terminal of the P-type transistor being connected to the drain terminal of the second N-type transistor; a second output terminal connected to the drain terminal of the second N-type transistor and the drain terminal of the P-type transistor; Equipped with 6. A bandpass filter according to claim 5.

7. 7. The band-pass filter according to claim 1, wherein the clock signal has a duty cycle of 50%.

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