Spin quantum bit semiconductor device and its integrated circuit

Abstract

To provide a spin quantum bit type semiconductor element capable of making high-speed spin operation compatible with high integration, and an integrated circuit therefor.SOLUTION: A spin quantum bit type semiconductor element 1 comprises: a body 3 consisting of a semiconductor layer per se on which a quantum bot 2 is formed (and at least one of the semiconductor layer and a structure part disposed around the semiconductor layer); a gate electrode 5 disposed at a position opposed with the quantum dot 2 on the semiconductor layer; a fine magnet 6 which is embedded in the body 3 entirely or partially so as to satisfy respective position conditions of a first position condition of a nearby position of the quantum dot 2, a second position condition that a position of a lower end is a position lower than the gate electrode 5, and a position condition (third position condition) of a position having no rotation symmetry with the quantum dot 2 defined as a rotation center in a view from an upper side of the body 3; and a static magnetic field application unit capable of applying a static magnetic field to the quantum dot 2 and the fine magnet 6.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a spin qubit semiconductor device that performs spin manipulation on electrons in quantum dots using a gradient magnetic field applied from a micromagnet, and an integrated circuit thereof. [Background technology]

[0002] Quantum computers are attracting attention as computers that can achieve computing performance that exceeds that of current computers. Furthermore, among the basic elements that make up such quantum computers, spin qubits have attracted particular attention as quantum bits that can be put to practical use because they have a long coherence time (the time during which interference between two quantum superposed states continues), which is an indicator of the time that information can be retained, and can perform a large number of quantum operations. In addition, as semiconductor-type qubits, spin qubits have the advantage of being able to be highly integrated by miniaturization using conventional semiconductor integration technology, and can also operate at high temperatures.

[0003] While transistors used in current computers operate by turning current on and off, the spin qubit operates by using the up / down spin of electrons confined in quantum dots as an information carrier. In conventional spin quantum bits, the spin of electrons is manipulated by applying an alternating magnetic field such as microwaves to the quantum dot, which forms a quantum two-level system consisting of up-spin and down-spin energy levels by applying a static magnetic field. However, spin manipulation using an AC magnetic field must be performed on each element, which can easily lead to crosstalk between the individual integrated elements, making it necessary to manipulate the spins using electrical signals. When spin manipulation is performed using an electric signal, the electric signal must be converted into a magnetic signal that affects the electron spin. One possible conversion method is to use interactions inherent in materials, such as spin-orbit interaction or hyperfine interaction. However, these interactions are weak, resulting in slow manipulation speeds, making them unsuitable for the high-speed spin manipulation required to perform multiple quantum operations within a certain period of time.

[0004] For this reason, a spin manipulation method based on electron dipole spin resonance (EDSR) using a gradient magnetic field generated by a minute magnet has been proposed (see Non-Patent Document 1). It has now been experimentally demonstrated that spin manipulation using this method is feasible (see Non-Patent Document 2), and research has also been reported on the arrangement and size of the micromagnets used for spin manipulation (see Non-Patent Documents 3 and 4).

[0005] The basic device structure common to these conventional spin qubits that utilize electron dipole spin resonance is shown in Figure 1. As shown in FIG. 1, the spin quantum bit 100 comprises a body 103 having a semiconductor region in which a quantum dot (QD) 102 is formed, a gate electrode 105 arranged on the body 103 facing the quantum dot 102 via a gate insulating layer 104, a magnet 106 arranged above the quantum dot 102, and a static magnetic field application unit (not shown) that applies a static magnetic field B0 to the quantum dot 102.

[0006] In the spin qubit 100, when a static magnetic field B0 is applied, electrons in the quantum dot 102 form a quantum two-level system consisting of up-spin and down-spin energy levels. The magnet 106 is also magnetized by the static magnetic field B0, forming a magnetic field B. This magnetic field B is generated by a gradient magnetic field B, the magnetic field strength of which varies spatially at the position of the quantum dot 102. SL That is, B of magnetic field B X The component (the component in the right direction in FIG. 1) changes in intensity depending on the position in the height direction (the vertical direction in FIG. 1) of the body 103, and the gradient of the intensity change determines the gradient magnetic field BSL In this state, when an AC voltage is applied to the gate electrode 105, the center of gravity of the electron in the quantum dot 102 is shifted to the gradient magnetic field B SL The electrons oscillate within the gate electrode 105, and transition between the two levels in the quantum two-level system. That is, the electron spin can be manipulated by an electric signal transmitted through the gate electrode 105.

[0007] However, the spin qubit 100 has the following problems. The calculations in the quantum computer must be performed multiple times within a limited coherence time, and high speed spin manipulation is required. The transition speed between two levels in spin manipulation is determined by the gradient magnetic field B SL The gradient field strength of the magnet 106 depends on the magnetic field strength of the quantum dot 102. However, in the spin qubit 100, the magnet 106 is disposed at a distance of several hundred nanometers or more from the quantum dot 102 above the body 103 via the gate electrode 105 (electrode thickness of 100 nm or more), and therefore a gradient magnetic field strength sufficient for high-speed spin manipulation cannot be obtained. Furthermore, if the magnet 106 is made larger than several hundred nanometers on a side to apply a strong gradient magnetic field to the quantum dot 102 from a distance, the area required to form each spin qubit 100 would be large, hindering high integration in the integrated circuit. Furthermore, if the magnet 106 is made to be such a large size, the magnet 106 would interfere with the various wiring necessary for the operation of the spin qubit 100, requiring additional area for wiring, further hindering high integration in the integrated circuit. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Y. Tokura et al., Physical Review Letters 96, 047202 (2006). [Non-patent document 2] MP-Ladriere et al., Nature Physics 4, 776 (2008). [Non-patent document 3] J. Yoneda et al, Applied Physics Express 8, 084401 (2015). [Non-patent document 4] G. Simion, IEDM2020, 30.2, p.657 (2020). Summary of the Invention [Problem to be solved by the invention]

[0009] The present invention aims to solve the above-mentioned problems in the prior art and to achieve the following object: to provide a spin qubit semiconductor device and an integrated circuit thereof that can achieve both high-speed spin manipulation and high integration. [Means for solving the problem]

[0010] The means for solving the above problems are as follows: <1> a gate electrode disposed on the semiconductor layer opposite the quantum dot; a micromagnet wholly or partially embedded in the body so as to satisfy the following positional conditions: a first positional condition in which the quantum dot is located near the gate electrode; a second positional condition in which the lower end of the semiconductor layer is located below the gate electrode when viewed from above, with the surface of the semiconductor layer closest to the gate electrode as the upper surface and the surface opposite to the upper surface as the lower surface; and a third positional condition in which the quantum dot is located at a position that does not have rotational symmetry around the quantum dot as the center of rotation when viewed from above. A spin quantum bit semiconductor device comprising: a body configured of at least one of a semiconductor layer in which quantum dots are formed and a structural portion disposed around the semiconductor layer; <2> The upper end of the micro-magnet is positioned below the gate electrode. <1> The spin qubit semiconductor device according to claim 1. <3> At least the upper end portion of the micro magnet on the side close to the quantum dot has an L-shaped corner in the vertical cross section. <2> The spin qubit semiconductor device according to claim 1. <4> The corner is positioned 5 nm to 25 nm below the upper surface of the semiconductor layer. <3> The spin qubit semiconductor device according to claim 1. <5> The micro magnets are in the shape of a rectangular pillar that is vertically supported, and the maximum diameter of the upper surface is 10 μm or less, and the area of ​​the upper surface is 100 μm. 2 The following is the above <3> from <4> 1. The spin qubit semiconductor device according to claim 1 , <6> The semiconductor layer has a cross shape in which two linear layers cross in a direction perpendicular to each other when viewed from above the body, quantum dots are formed at the intersections of the cross shapes, and micro magnets are arranged at positions facing each other across one of the linear layers when viewed from above the body. <1> from <5> 1. The spin qubit semiconductor device according to claim 1 , <7> The material for forming the micro magnet contains at least one element of iron, cobalt, nickel, and manganese. <1> from <6> 1. The spin qubit semiconductor device according to claim 1 , <8> The aforementioned <1> from <7> 1. An integrated circuit integrating a plurality of spin qubit semiconductor elements according to any one of claims 1 to 8, wherein a plurality of quantum dots are formed in a single semiconductor layer formed in the same body, and an element structure of the spin qubit semiconductor element is formed for each quantum dot. [Effects of the Invention]

[0011] According to the present invention, it is possible to solve the above-mentioned problems in the prior art, and to provide a spin qubit semiconductor device and an integrated circuit thereof that are capable of achieving both high-speed spin manipulation and high integration. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is an explanatory diagram for explaining a basic element structure common to conventional spin qubits that utilize electron dipole spin resonance. [Figure 2] 1 is an explanatory diagram for explaining the basic device structure of a spin qubit semiconductor device according to the present invention.

[0023] FIG. [Figure 3(a)]FIG. 1 is an explanatory diagram (1) showing an example of a static magnetic field applying unit. [Figure 3(b)] FIG. 2 is an explanatory diagram (2) showing an example of a static magnetic field applying unit. [Figure 3(c)] FIG. 3 is an explanatory diagram showing an example of a static magnetic field applying unit. [Figure 3(d)] FIG. 4 is an explanatory diagram (4) showing an example of a static magnetic field applying unit. [Figure 3(e)] FIG. 5 is an explanatory diagram (5) showing an example of a static magnetic field applying unit. [Figure 3(f)] FIG. 6 is an explanatory diagram showing an example of a static magnetic field applying unit. [Figure 4] 10A and 10B are explanatory diagrams illustrating an example of a modification of the position of the micro magnets. [Figure 5(a)] FIG. 1 is a top view (1) illustrating an example of the positional relationship between quantum dots and micro-magnets arranged in a linear semiconductor layer. [Figure 5(b)] FIG. 2 is a top view (2) illustrating an example of the positional relationship between quantum dots and micro-magnets arranged on a linear semiconductor layer. [Figure 6(a)] FIG. 1 is a top view (1) illustrating an example of the positional relationship between quantum dots and micro-magnets arranged in a two-dimensional lattice-shaped semiconductor layer. [Figure 6(b)] FIG. 2 is a top view (2) illustrating an example of the positional relationship between quantum dots and micro-magnets arranged in a two-dimensional lattice-shaped semiconductor layer. [Figure 6(c)] FIG. 10 is a top view (3) illustrating an example of the positional relationship between quantum dots and micro-magnets arranged in a two-dimensional lattice-shaped semiconductor layer. [Figure 6(d)] FIG. 4 is a top view explanatory diagram (4) showing an example of the positional relationship between quantum dots and micro-magnets arranged in a two-dimensional lattice-shaped semiconductor layer. [Figure 7(a)] FIG. 10 is a top view (1) illustrating another example of the positional relationship between quantum dots and micro-magnets. [Figure 7(b)] FIG. 10 is a top view (2) illustrating another example of the positional relationship between quantum dots and micro-magnets. [Figure 8(a)] 1 is a perspective view showing an overview of a spin qubit semiconductor device according to a first embodiment. FIG. [Figure 8(b)] 1 is a cross-sectional view showing an overview of a spin qubit semiconductor device according to a first embodiment. [Figure 9] FIG. 1 is an explanatory diagram (1) for explaining the operation of the spin qubit semiconductor device according to the first embodiment. [Figure 10] 1 is a diagram illustrating the energy levels of electrons in a quantum dot before and after application of a static magnetic field. [Figure 11] FIG. 10 is an explanatory diagram (2) for explaining the operation of the spin qubit semiconductor device according to the first embodiment. [Figure 12(a)] FIG. 1 is an explanatory diagram showing the relationship between the energy positions of a quantum dot and a reservoir in an initial state. [Figure 12(b)] FIG. 10 is an explanatory diagram showing the relationship between the energy positions of the quantum dot and the reservoir after a voltage is applied to the reservoir electrode. [Figure 13] FIG. 10 is an explanatory diagram for explaining a method for reading out the state of a quantum bit by gate reflectometry. [Figure 14] 10A and 10B are explanatory diagrams for explaining changes in voltage over time during operation and during readout. [Figure 15(a)] FIG. 1 is a perspective view illustrating a method for reading out the state of a quantum bit by the Elsermann method. [Figure 15(b)] FIG. 15(b) is a cross-sectional view taken along the dotted line in FIG. 15(a). [Figure 16] FIG. 10 is an explanatory diagram for explaining the relationship between the energy position during operation and the energy position during readout. [Figure 17(a)] 1 is a cross-sectional view (1) showing the manufacturing process. [Figure 17(b)] FIG. 2 is a cross-sectional view (2) showing the manufacturing process. [Figure 17(c)] FIG. 3 is a cross-sectional view showing the manufacturing process. [Figure 17(d)] FIG. 4 is a cross-sectional view showing the manufacturing process. [Figure 17(e)] 5 is a cross-sectional view showing the manufacturing process. [Figure 17(f)] 6 is a cross-sectional view showing the manufacturing process. [Figure 17(g)] 7 is a cross-sectional view showing the manufacturing process. [Figure 17(h)] 8 is a cross-sectional view showing the manufacturing process. [Figure 17(i)] 9 is a cross-sectional view showing the manufacturing process. [Figure 17(j)] 10 is a cross-sectional view showing the manufacturing process. [Figure 17(k)] 11 is a cross-sectional view showing the manufacturing process. [Figure 17(l)] 12 is a cross-sectional view showing the manufacturing process. [Figure 17(m)] 13 is a cross-sectional view showing the manufacturing process. [Figure 18] FIG. 10 is a cross-sectional view showing an overview of a spin qubit semiconductor device according to a second embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing an overview of a spin qubit semiconductor device according to a third embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a modified example of the spin qubit semiconductor device according to the first embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing a modified example of the spin qubit semiconductor device according to the second embodiment. [Figure 22] FIG. 10 is a cross-sectional view showing a modified example of the spin qubit semiconductor device according to the third embodiment. [Figure 23] 1 is a top view illustrating an overview of an integrated circuit of a spin qubit semiconductor device according to the present invention. FIG. [Figure 24(a)] FIG. 1 is a top view illustrating an overview of a spin qubit semiconductor device related to a simulation test setup. [Figure 24(b)] FIG. 1 is a partial cross-sectional view showing an overview of a spin qubit semiconductor device in a simulation test setup. [Figure 25] FIG. 10 is a diagram showing the relationship between the arrangements A to E of the micro-magnets and the intensity of the gradient magnetic field. [Figure 26] FIG. 10 is a diagram showing the relationship between the arrangements A to E of the micro-magnets and the gradient magnetic field distribution. [Figure 27] 10 shows the calculation results of the gradient magnetic field distribution in the diagonal cross section of the arrangement E. [Figure 28]FIG. 10 is a diagram showing the results of a simulation in which the relationship between the distance from the top surface of the Si semiconductor layer to the top surface of the micro-magnet and the gradient magnetic field strength was tested while changing the size of the micro-magnet in a spin qubit semiconductor element relating to configuration E. [Figure 29] FIG. 10 is a diagram showing the results of a simulation in which the relationship between the distance from the top surface of the Si semiconductor layer to the bottom surface of the micro-magnet and the gradient magnetic field strength was tested while changing the size of the micro-magnet in a spin qubit semiconductor element relating to configuration E. DETAILED DESCRIPTION OF THE INVENTION

[0013] (Spin qubit semiconductor device) The spin qubit semiconductor device of the present invention will be described with reference to the drawings. First, the basic device structure of a spin qubit semiconductor device according to the present invention is shown in FIG. 2, the spin qubit semiconductor device 1 has a quantum dot 2, a body 3, a gate insulating layer 4, a gate electrode 5, and a micro magnet 6. It also has a static magnetic field applying unit (not shown).

[0014] In the illustrated example, the body 3 is composed of the semiconductor layer itself in which the quantum dots 2 are formed. The body 3 may also be composed of any structural part disposed around the semiconductor layer, as will be described in the following embodiments 1 to 3. The semiconductor layer and quantum dots 2 are not particularly limited and may be formed using known materials and methods, and a typical example is the device structure of a known single-electron transistor.

[0015] The gate electrode 5 is disposed on the body 3 (the semiconductor layer) at a position facing the quantum dot 2 via the gate insulating layer 4. The gate electrode 5 controls the movement of electrons to the quantum dot 2 by applying a voltage, and also oscillates the electrons in the quantum dot 2 in the gradient magnetic field formed by the micro magnet 6 by applying an AC voltage, thereby manipulating the spin of the electrons. There are no particular limitations on the gate insulating layer 4 and the gate electrode 5 either, and they may be formed using known materials and methods, and may have the same device structure as the single-electron transistor, for example.

[0016] In the illustrated example, the micromagnet 6 is entirely embedded in the body 3 and disposed in the vicinity of the quantum dot 2 (first position condition). The stronger the magnetic field strength of the gradient magnetic field formed by the micromagnet 6, the faster the spin manipulation of electrons in the quantum dot 2 can be, and the gradient magnetic field strength is stronger the closer the distance from the micromagnet 6. Therefore, the closer the position at which the micromagnet 6 is formed to the quantum dot 2, the more preferable it is; in this specification, "vicinity" means that the shortest distance between the quantum dot 2 and the micromagnet 6 is 100 nm or less. This proximity arrangement of the micromagnet 6 to the quantum dot 2 is made possible by embedding the micromagnet 6 in the body 3.

[0017] Furthermore, as a positioning of the micromagnet 6 that is embedded in the body 3 and is advantageous for the proximity positioning, when viewed from above with the surface of the body 3 (semiconductor layer) closer to the gate electrode 5 as the upper surface and the surface facing the upper surface as the lower surface, the position of the lower end of the micromagnet 6 is positioned below the gate electrode 5 (second positioning condition). Additionally, although not an essential condition of the present invention, as a preferred example, the position of the upper end of the micromagnet 6 is positioned below the gate electrode 5, and as an even more preferred example, the position of the upper end of the micromagnet 6 is positioned below the upper surface of the body 3 (semiconductor layer). The arrangement of these micro magnets 6 in the order described makes it easy to free the space above the gate electrode 5 or the body 3 (the semiconductor layer) from the micro magnets 6, and ultimately makes it possible to realize a structure that makes it easy to secure various wiring spaces such as the electrode wiring of the gate electrode 5.

[0018] The shape of the micro magnet 6 is not limited to the examples shown in the figure, and any shape such as a rectangular prism, a cylinder, an elliptical cylinder, a cone, a frustum, etc. can be adopted, and these shapes may be partial, or any shape combining multiple shapes can be adopted. A suitable shape for the micromagnet 6 is one having an L-shaped corner in the vertical cross section. Having such a corner allows a gradient magnetic field with a strong magnetic field strength to be formed in the vicinity of the corner. The corner may be formed at either the upper or lower end of the micromagnet 6, but in either case, it is important to position the micromagnet 6 so that the corner is close to the quantum dot 2 in order to utilize the gradient magnetic field near the corner. For example, in the illustrated example, two corners are formed at each of the upper (and lower) ends of the micro-magnet 6, but if there is only one corner formed at each of the upper (and lower) ends of the micro-magnet 6 and the rest are U-shaped, the upper (and lower) end portion closer to the quantum dot 2 will be considered to be the corner.

[0019] When the corner is formed in the micro magnet 6, the position of the corner is preferably 5 nm to 25 nm below the upper surface of the body 3 (the semiconductor layer). In other words, in the illustrated example, the shortest distance d top It is preferable that the distance between the micro magnets 6 and the corners is 5 nm to 25 nm. The gradient magnetic field formed at the corners has a stronger magnetic field strength at positions that are shifted several nm above and below the positions of the corners, and therefore, by arranging the micro magnets 6 in this way, it is possible to perform spin manipulation at higher speeds. Furthermore, when the corner is formed at the upper end of the micro magnet 6 and the position of the corner is 5 nm to 25 nm below the upper surface of the body 3 (the semiconductor layer), it is preferable to maintain a minimum thickness of 15 nm in the height direction (vertical direction) of the micro magnet 6, and position the lower end of the micro magnet 6 20 nm to 40 nm or more below the upper surface of the body 3 (the semiconductor layer). In other words, the shortest distance d between the lower end of the micro magnet 6 and the upper surface of the body 3 (the semiconductor layer) is bottom is preferably 20 nm to 40 nm or more. By setting the size of the micro-magnet 6 in the height direction (vertical direction) with the lower end at such a position, a gradient magnetic field with a strong magnetic field strength can be applied to the quantum dots 2. In addition, as the thickness of the micro-magnet 6 in the height direction increases, the strength of the gradient magnetic field acting on the quantum dot 2 tends to increase. However, even if the size of the micro-magnet 6 is set so that the position of the bottom end of the micro-magnet 6 is more than 100 nm below the top surface of the body 3 (the semiconductor layer), there is no significant difference in the strength of the gradient magnetic field acting on the quantum dot 2. Therefore, the position of the bottom end of the micro-magnet 6 (d bottom The maximum depth of the junction 10 is about 140 nm from the top surface of the body 3 (the semiconductor layer). The position of the micro magnet 6 is set based on the position of the corner relative to the top surface of the body 3 (the semiconductor layer) because the quantum dot 2 is formed at a very shallow position from the top surface of the body 3 (the semiconductor layer), that is, at a position on the gate electrode 5 side of the body 3 (the semiconductor layer).

[0020] Furthermore, when the corners of the micro-magnet 6 are formed, it is preferable that they be formed in the shape of a rectangular prism, a circular cylinder, or an elliptical cylinder that stands upright in the vertical direction, for ease of manufacturing by lithography processing, and among these, it is particularly preferable that they be formed in the shape of a square prism, as this shape makes it easy to achieve high integration.

[0021] Since the micro magnet 6 is embedded in the body 3 and can be placed in close proximity to the quantum dot 2, it can exert a gradient magnetic field of sufficient strength on the quantum dot 2 with a smaller size than conventional spin quantum bits 100 (see non-patent documents 1 to 4). From the viewpoint of high integration, it is preferable that the size of the micro magnet 6 is small, as long as a gradient magnetic field of sufficient strength is obtained to manipulate the spins of electrons in the quantum dots 2. In particular, the size of the semiconductor layer in the in-layer direction is of interest for high integration, and in this specification, "micro" means that the maximum diameter of the micro magnet 6 in the in-layer direction of the semiconductor layer is 10 μm or less. For example, when the micro magnet 6 is formed as a square pillar that stands upright in the vertical direction (thickness direction of the semiconductor layer), the maximum diameter of the top surface (and bottom surface) is set to 10 μm or less, and the area of ​​the top surface (and bottom surface) is set to 100 μm or less. 2 It is preferable that the following be true: The lower limit of the maximum diameter is about 3 nm from the viewpoint of forming a gradient magnetic field of sufficient strength, and the lower limit of the area is about 9 nm. 2 That's about it.

[0022] Examples of materials for forming the micro magnets 6 include known magnetic materials that are magnetized by the external magnetic field applied from the static magnetic field application unit, and among these, magnetic materials containing at least one of the elements iron, cobalt, nickel, and manganese are preferable. The method for forming the micro magnets 6 is not particularly limited, and examples thereof include known methods (CVD, ALD, CMP, etc.) using these materials.

[0023] The static magnetic field applying unit is a unit that can apply a static magnetic field B0 to the quantum dots 2 and the micro magnets 6. The static magnetic field B0 is made uniform over the entire element formation region and is applied in a direction perpendicular to the gradient magnetic field of the micro magnets 6. The static magnetic field applying unit is not particularly limited and can be appropriately selected from known members composed of magnets and coils.

[0024] The static magnetic field application unit does not need to be one for each element, but may be configured so that only one is arranged in the integrated circuit, or may be configured so that one is arranged for the same body (body 3) in the configuration exemplified in Figures 3(a) to (f). Note that Figure 3(a) shows an example of a configuration in which the body 3 is arranged outside the coil, Figure 3(b) shows an example of a configuration in which the body 3 is arranged inside the coil and suspended by a support rod, Figure 3(c) shows an example of a configuration in which the coil is wound around the body 3, Figure 3(d) shows an example of a configuration in which the coil is arranged on the body 3, Figure 3(e) shows an example of a configuration in which a bar magnet is arranged on the body 3, and Figure 3(f) shows an example of a configuration in which a cylindrical magnet is arranged on the body 3.

[0025] In the spin quantum bit semiconductor element 1 shown in Figure 2, the micro magnet 6 is configured so that its entirety is embedded within the body 3, but as in the modified example shown in Figure 4, only a portion of the micro magnet 6 may be configured so that it is embedded within the body 3. In this modified example, the micro magnet 6 can also be disposed in the vicinity of the quantum dot 2.

[0026] The micro magnets 6 are arranged in positions that do not have rotational symmetry around the quantum dots 2 as the center of rotation when viewed from above the body 3 (third positional condition). In this specification, "not having rotational symmetry" means that when the body 3 (semiconductor layer) is rotated at any angle less than 360° in a direction parallel to the in-layer direction, the positions at which the micro magnets 6 are formed do not overlap at any angle. An example of the configuration of the body 3 and the micro magnets 6 will be described using a top view.

[0027] First, FIGS. 5(a) and 5(b) show examples of the positional relationship between the quantum dots 2 and the micro magnets 6 arranged in the linear body 3 (the semiconductor layer). Each of the configurations shown in Figures 5(a) and (b) is an example of a one-dimensional configuration in which the body 3 is formed from one linear layer (e.g., a fin-type semiconductor layer), and one or two micro-magnets 6 are arranged side by side in the linear body 3 (the semiconductor layer), and when the micro-magnets 6 are arranged on both sides of the body 3, the top surface shapes of the micro-magnets 6 are configured to be different.

[0028] Next, an example of the positional relationship between the quantum dots 2 and the micro magnets 6 arranged in the two-dimensional lattice-shaped body 3 (the semiconductor layer) will be shown. 6(a) to 6(d) are examples of two-dimensional lattice configurations in which the body 3 is configured by crossing two of the linear layers, and one or more micromagnets 6 are arranged in a position sandwiched between the two linear layers. When two micromagnets 6 with the same top surface shape are arranged, the micromagnets 6 are arranged in a position straddling one of the linear layers. When micromagnets 6 are arranged in a position straddling one of the linear layers, the two micromagnets 6 may be arranged in opposing positions sandwiching one of the linear layers, or one micromagnet 6 may be arranged so that it is beneath one of the linear layers.

[0029] In each of the configurations shown in Figures 6(a) to (d), the linear layer is configured so that four arms extend from the position of the quantum dot 2, but the linear layer may also be configured so that three or six arms extend from the position of the quantum dot 2, as shown in Figures 7(a) and (b), in which case one or more micro-magnets 6 are arranged in a position sandwiched between two adjacent linear layers. When the micro-magnet 6 is arranged in a position that does not have rotational symmetry around the quantum dot 2 as the center of rotation when viewed from above the body 3, the magnetic field exerted on the quantum dot 2 from the micro-magnetic field 6 becomes inclined, and a gradient magnetic field is exerted on the quantum dot 2.

[0030] [First embodiment] The spin qubit semiconductor device of the present invention can take various forms based on the basic device structure shown in FIG. The spin qubit semiconductor device 10 according to the first embodiment will be described with reference to Figures 8(a) and 8(b). Figure 8(a) is a perspective view showing an overview of the spin qubit semiconductor device 10 according to the first embodiment, and Figure 8(b) is a cross-sectional view showing an overview of the spin qubit semiconductor device 10 according to the first embodiment.

[0031] The spin qubit semiconductor device 10 includes quantum dots 12, a substrate 13a, a fin-shaped semiconductor layer 13b, a gate insulating layer 14, a gate electrode 15, and a micromagnet 16. The device also includes the static magnetic field application unit (not shown). In these components, the quantum dots 12, gate insulating layer 14, gate electrode 15, micro magnet 16 and static magnetic field applying section are configured in the same manner as those described for the spin quantum bit semiconductor device 1. The spin quantum bit semiconductor device 10 is configured according to a FinFET device structure, and instead of the body 3 of the spin quantum bit semiconductor device 1, the body is configured as a structural part arranged around the fin-shaped semiconductor layer 13b, and is composed of a substrate 13a that supports the semiconductor layer 13b, and a micro magnet 16 is embedded in the substrate 13a.

[0032] There are no particular limitations on the substrate 13a, and any known substrate can be used, including, for example, various substrates used in semiconductor devices and the BOX layer (SiO2 layer) in an SOI substrate. The semiconductor layer 13b is configured as a linear layer formed on the substrate 13a and is made of a known semiconductor material, for example, various semiconductor materials used in semiconductor devices or a Si layer in an SOI substrate.

[0033] The following describes the operation of the spin qubit semiconductor device 10. Although the device structure of the spin qubit semiconductor device 10 can also include various device structures of semiconductor devices that use known quantum dots, the following description will be given assuming that the device structure is that of a typical single-electron transistor (SET) as a representative device structure. As shown in Figure 9, in the spin quantum bit semiconductor element 10, two barrier gate electrodes 19 are formed on the semiconductor layer 13a via the gate insulating layer 14 on both sides of the gate electrode 15 so as to sandwich the gate electrode 15 in the intra-layer direction of the semiconductor layer 13a. Furthermore, a source electrode 17 and a drain electrode 18 are disposed on the semiconductor layer 13a at positions sandwiching one barrier gate electrode 19 between the gate electrode 15 and the semiconductor layer 13a in the layer direction. The gate electrode 15 controls the movement of electrons to the quantum dots 12, and the barrier gate electrode 19 controls the tunnel coupling between the quantum dots 12 and the source on the source electrode 17 side and the drain on the drain electrode 18 side. That is, by manipulating the voltages of the gate electrode 15 and the barrier gate electrode 19, the tunneling of electrons into the quantum dot 12 can be controlled, and a quantum dot 12 in which only one electron is confined can be formed. FIG. 9 shows a cross section of the semiconductor layer 13b in the longitudinal direction (y direction) of FIG. 8(a).

[0034] When a static magnetic field B0 is applied from the static magnetic field application unit to the localized level of the electrons confined in the quantum dot 12, the energy level becomes gμ B B0(μ BZeeman splitting occurs, where the energy difference between the |0> and |1> states causes splitting, and a quantum two-level system represented by two quantum states, |0> and |1>, is generated in the quantum dot 12 (see Figure 10).

[0035] In addition, in the spin qubit semiconductor device 10, as shown in FIG. 11, the source electrode 17 and the drain electrode 18 are used as reservoir electrodes, and a reservoir 13c is formed in the semiconductor layer 13b by manipulating the voltage of the reservoir electrodes to store electrons. By manipulating the voltages of the gate electrode 15 and the barrier gate electrode 19, the Fermi level (E F When voltage is applied so that the reservoir 13c is aligned with the quantum two-level system, electrons tunnel from the reservoir 13c to the lower energy level of the quantum two-level system of the quantum dot 12, creating a state in which one electron exists in the |0> state (see FIGS. 12(a) and 12(b)). The initialization is completed by creating a state in which one electron exists in the |0> state.

[0036] 8(b), when an AC voltage is applied to gate electrode 15 after initialization is complete, the center of gravity of the electrons in quantum dot 12 oscillates in the gradient magnetic field formed by micromagnet 16, and the electrons transition between the two quantum levels. At this time, the gradient magnetic field formed by micromagnet 16 and the AC magnetic field created by gate electrode 15 to which AC voltage is applied resonate (Rabi resonance) with the electrons in quantum dot 12, causing the |0> state and the |1> state to overlap, and Rabi oscillations to occur in which the |0> state and the |1> state are repeated while taking intermediate states between them. Therefore, in spin qubit semiconductor device 10, the |0> state, |1> state, and their intermediate superposition state (hereinafter simply referred to as a "qubit") of the quantum two-level system can be controlled by controlling the electrical signal applied to gate electrode 15.

[0037] There are no particular limitations on the method for reading out the quantum bits in the quantum dots 12, and it can be appropriately selected from known methods. Here, two representative methods will be described: gate reflectometry and Elsermann's method.

[0038] An overview of spin qubit semiconductor device 10 including a readout configuration using the gate reflectometry method is shown in Figure 13. Note that Figure 13 shows a cross section of semiconductor layer 13b in the longitudinal direction (y direction) of Figure 8(a), and for simplicity of the drawing, only the configuration necessary for the readout operation is depicted. 13, in the readout configuration using the gate reflectometry method, a gate insulating layer 14' and a gate electrode 15' are formed in parallel with the element structure of the quantum dots 12 and the gate electrode 15, and a readout quantum bit is formed below them. In addition, the gate electrode 15' is connected to the high-frequency circuit HFC via a coil.

[0039] As a readout method, first, two quantum bits, the quantum bit and the readout quantum bit in the quantum dot 12, are coupled together. In other words, these two quantum bits are electrically connected so that electrons can tunnel between the quantum bit and the readout quantum bit. Then, the voltages (V C ,V R Next, a high frequency voltage is input from the high frequency circuit HFC to the gate electrode 15', and the reflected wave is measured by the high frequency circuit HFC for reading. At this time, the voltage (V C The phase or amplitude of the reflected wave changes in response to a quantum state change of the quantum bit on the quantum dot 12 side, which is exemplarily illustrated by a ) change (see FIG. 14). This allows the state of the quantum bit to be read out.

[0040] Next, Figures 15(a) and 15(b) show an overview of a spin qubit semiconductor device 10 with a readout configuration based on the Elsermann method. Note that Figure 15(b) shows a cross section of the position enclosed by the dotted line in Figure 15(a). To simplify the drawing, only the configuration necessary for the readout operation is shown. As shown in these figures, in the readout configuration using the Elsermann method, the single-electron transistor (SET) device structure consisting of the fin-shaped semiconductor layer 13b', gate electrode 15', source electrode 17, and drain electrode 18 is placed in parallel with the single-electron transistor (SET) device structure in which quantum dots 12 are formed, at a position not affected by the gradient magnetic field from the micro-magnet 16. These two SETs are coupled by capacitance as shown in Fig. 15(b). In the device structure of a single electron transistor (SET) in which quantum dots 12 are formed, the energy level of reservoir 13c is manipulated by reservoir electrode 18' (source electrode 17 and drain electrode 18 in FIG. 9).

[0041] As a reading method, first, the Fermi level (E F ) is set higher than the two levels of the quantum bit in the quantum dot 12. In this state, when a voltage is applied to the gate electrode 15 and the Fermi level of the reservoir electrode is set to be located between the two levels of the quantum bit, electron tunneling from the quantum dot 12 to the reservoir 13c is permitted only when the electrons of the quantum bit are in the |1> state (see FIG. 16). Furthermore, the drain current flowing between the source electrode 17 and the drain electrode 18 changes in response to the change in the number of electrons in the quantum dot 12 at this time. This allows the state of the quantum bit to be read out.

[0042] Next, an example of a method for manufacturing the spin qubit semiconductor device 10 will be described with reference to FIGS. 17(a) to 17(m).

[0043] First, a semiconductor substrate is prepared in which a semiconductor layer 13b is formed on a substrate 13a. Here, an SOI substrate is used as the semiconductor substrate, and the substrate 13a is formed of a BOX layer (SiO2), and the semiconductor layer 13b is formed of a Si layer. Next, a Si3N4 layer (insulating material layer) is formed on the semiconductor layer 13b by a known chemical vapor deposition method (CVD method) (see FIG. 17(a)). Next, an etching mask M is formed on the Si3N4 layer by a known lithography process (see FIG. 17(b)). Next, etching is performed using CF4 gas by a known reactive ion etching method (RIE method), and the portions of the Si3N4 layer that are not covered with the etching mask M are anisotropically etched (see FIG. 17(c)). Next, the etching mask M is removed by oxygen ashing (see FIG. 17(d)). Next, the semiconductor layer 13b is anisotropically etched using HBr gas by the reactive ion etching method to form fins (see FIG. 17(e)). Next, Si3N4 is deposited from above the fin by chemical vapor deposition or atomic layer deposition (ALD) to cover the top and side surfaces of the fin with Si3N4, thereby forming sidewalls (see FIG. 17(f)). Next, anisotropic etching is performed using CF4 plasma to remove the Si3N4 except for the sidewalls (see FIG. 17(g)). Next, an SiO2 layer is formed on the substrate 13a by the chemical vapor deposition method. After deposition, the top surface is planarized by a known chemical mechanical polishing method (CMP method) (see FIG. 17(h)). Next, an etching mask M is formed on the SiO2 layer by lithography (see FIG. 17(i)). Next, the SiO2 layer and the substrate 13a are anisotropically etched by the reactive ion etching method using CHF3 gas to form trenches for embedding the micro magnets 16 (see FIG. 17(j)). Next, the etching mask M is removed by the oxygen ashing process. After that, the material for forming the micro magnets 16 is deposited in the trenches by the chemical vapor deposition method or the atomic layer deposition method (see FIG. 17(k)). Next, molding is performed by the chemical mechanical polishing method, and the micro magnets 16 are placed at the desired positions (see FIG. 17(l)). Finally, the SiO2 layer is backfilled by the chemical vapor deposition method to obtain a configuration equivalent to the spin qubit semiconductor device 10 (FIG. 17(m)).

[0044] In the manufacturing method described above, the formation of each part is performed by a known manufacturing method, so that existing semiconductor manufacturing facilities can be used, and it can be said to be a practical manufacturing method. In particular, by using the SOI substrate, existing silicon device manufacturing facilities can be used, making it highly practical. Furthermore, by forming the trenches for embedding the micro magnets 16 based on the sidewall positions of the Si3N4, the micro magnets 16 can be formed near the quantum dots 12 without causing variations in the formation positions. The manufacturing method described above is merely an example, and any manufacturing method selected from known semiconductor device manufacturing methods can be applied.

[0045] [Second embodiment] Next, a spin bit type semiconductor device 20 according to the second embodiment will be described with reference to Fig. 18. In the illustrated example, two equivalent device structures are shown. The spin qubit semiconductor device 20 has quantum dots 22, a semiconductor layer 23, a gate insulating layer 24, a gate electrode 25, and a micro magnet 26. It also has the static magnetic field applying unit (not shown). In these components, the quantum dots 22, the gate insulating layer 24, the gate electrode 25, the micro magnet 26 and the static magnetic field applying section are configured in the same manner as those described for the spin quantum bit semiconductor device 10.

[0046] In spin quantum bit semiconductor device 20, instead of the body of spin quantum bit semiconductor device 10 which is made up of substrate 13a, a body is used which is made up of semiconductor layer 23 having the fin-like shape on its upper surface and gate insulating layer 24 as the structural part arranged around semiconductor layer 23, and quantum dots 22 are formed in the fin-like shape part. In this example, the micro magnets 26 are embedded in the semiconductor layer 23 and the gate insulating layer 24 so as to straddle the interface between these members, but as a modified example, the micro magnets 26 may be configured to be embedded only in the semiconductor layer 23 or only in the gate insulating layer 24. In other words, the body may be configured from the semiconductor layer 23, the gate insulating layer 24, and these members. In spin qubit semiconductor device 20 to which such a configuration is applied, the same operation as that of spin qubit semiconductor device 10 can be obtained according to the basic structure described with reference to FIG. Moreover, it can be practically manufactured in accordance with the manufacturing method described for the spin qubit semiconductor device 10.

[0047] [Third embodiment] Next, a spin bit semiconductor device 30 according to a third embodiment will be described with reference to Fig. 19. In the illustrated example, two equivalent device structures are shown. In the figure, reference numeral 32 denotes a quantum dot, and reference numeral 35 denotes a gate electrode. In spin qubit semiconductor device 30, instead of the body of spin qubit semiconductor device 20 which is composed of semiconductor layer 23 and gate insulating layer 24, a body composed of semiconductor layer 33b and gate insulating layer 34 is applied. In this body, semiconductor layer 33b, which corresponds to semiconductor layer 23, is supported on substrate 33a. In this example, the micro magnet 36 is embedded in the semiconductor layer 33b and the gate insulating layer 34 so as to straddle the interface between these members, but as a modified example, the micro magnet 36 may be configured to be embedded only in the semiconductor layer 33b or only in the gate insulating layer 34. Alternatively, the size of the micro magnet 36 may be changed so that it hangs down toward the substrate 33a, and the micro magnet 36 may be configured to be embedded so as to straddle the respective members of the substrate 33a, the semiconductor layer 33b, and the gate insulating layer 34. The body may be composed of the semiconductor layer 33b, the gate insulating layer 34, the substrate 33a, and these members. In spin qubit semiconductor device 30 to which such a configuration is applied, the same operation as that of spin qubit semiconductor device 10 can be obtained according to the basic structure described with reference to FIG. Furthermore, it can be practically manufactured in accordance with the manufacturing method described for the spin qubit semiconductor device 10.

[0048] Next, modified examples of the spin qubit semiconductor devices 10, 20, and 30 will be described with reference to FIGS. 20, spin qubit semiconductor device 10 and equivalent spin qubit semiconductor device 10' are formed on both the top and bottom surfaces of substrate 13a. Such a double-sided structure may be formed on a single substrate 13a, or may be formed by bonding two separately formed device structures together on substrates 13a. 21, spin qubit semiconductor element 20 and equivalent spin qubit semiconductor element 20' are formed on both the top and bottom surfaces of semiconductor layer 23. Such a double-sided structure may be formed on a single semiconductor layer 23, or may be formed by bonding two separately formed element structures together. 22, spin qubit semiconductor element 30 and equivalent spin qubit semiconductor element 30' are formed on both the top and bottom surfaces of substrate 33a. Such a double-sided structure may be formed on a single substrate 33a, or may be formed by bonding two separately formed element structures together. In these modified examples, when two separately formed element structures are bonded together, an optional intermediate substrate may be sandwiched between the two element structures, and the two element structures may be bonded to both sides of this intermediate substrate. Furthermore, when viewing one quantum dot (12, 22, 32) in these modified examples, one gate electrode (15, 25, 35) is disposed above and below it. In this case, the surface of the semiconductor layer (13b, 23, 33b) on which the gate electrode (15, 25, 35) closest to the quantum dot (12, 22, 32) is disposed is defined as the upper surface, and the above-described explanation regarding the up-down relationship applies. In other words, the up-down relationship in this specification is determined regardless of the up-down relationship determined by the action of gravity.

[0049] (integrated circuits) The integrated circuit of the present invention is characterized in that it is configured by arranging a plurality of the spin quantum bit semiconductor elements of the present invention, a plurality of quantum dots are formed in a single semiconductor layer formed in the same body, and an element structure of the spin quantum dot semiconductor element is formed for each quantum dot. A specific configuration of the integrated circuit is, as exemplified in Figure 23, a configuration in which multiple spin quantum dot semiconductor elements 1 (see Figure 2) are formed via barrier gates in a body 3 configured in a two-dimensional lattice pattern. [Example]

[0050] In order to examine the effectiveness and preferable conditions of the present invention, a simulation test was carried out regarding the strength of the gradient magnetic field applied from the micro magnet to the quantum dot.

[0051] The simulation test was based on the spin qubit semiconductor device shown in Figures 24(a) and (b). Figure 24(a) is a top view illustrating an overview of the spin qubit semiconductor device used in the simulation test, and Figure 24(b) is a partial cross-sectional view illustrating an overview of the spin qubit semiconductor device used in the simulation test. Note that the reference numerals in these figures correspond to those in Figure 2.

[0052] Specifically, we assumed a cross-shaped semiconductor layer in which two fin-shaped Si semiconductor layers, each having a line width of 10 nm, cross each other in an orthogonal direction, and the quantum dots 2 are formed at the intersections of the cross shapes (see FIG. 24(a)). The body 3 is composed of the semiconductor layer and an SiO2 region covering the semiconductor layer (see FIG. 24(b)). The micromagnet 6 is a cobalt magnet in the shape of a square prism with a depth of 30 nm, a width of 30 nm, and a height of 105 nm. The sidewall thickness is 6 nm, and the micromagnet 6 is embedded in a SiO2 region that hangs down from the outermost side of the Si3N4 sidewall covering the side of the body 3, with the side of the micromagnet 6 facing the quantum dot 2 aligned along the SiO2 region (see Figures 24(a) and 24(b)). The micromagnet 6 is also configured so that its upper end is 15 nm lower than the upper end of the semiconductor layer (see Figure 24(b)). The micromagnet 6 is magnetized by an external magnetic field (a static magnetic field applied from the static magnetic field application unit), and the direction of the external magnetic field is the z-direction, which is the height direction of the micromagnet 6. The direction of the gradient magnetic field is the x-direction, which is perpendicular to the external magnetic field.

[0053] With this configuration as the basic configuration, the micromagnet arrangements A to E shown in FIG. 25 are assumed, and the gradient magnetic field strength (B SL ) and calculate the three-dimensional distribution of the gradient magnetic field strength (B SL0 ) was calculated. Note that Fig. 25 is a diagram showing the relationship between the arrangements A to E of the micro magnets and the gradient magnetic field strength. The calculations were performed by numerically solving Maxwell's equations under the Coulomb gauge condition, using the numerical calculation software Impulse TCAD (developed by the National Institute of Advanced Industrial Science and Technology) with a function for solving the Maxwell's equations implemented.

[0054] The five arrangements of the micro-magnets 6 shown in Figure 25 are intended to verify the effect of the arrangement of the micro-magnets 6 relative to the quantum dots 2 when the spin quantum bit semiconductor element is viewed from above, and all arrangements of the micro-magnets 6 relative to the four corners of the quantum dots 2 are considered, including those that result in the same arrangement when rotated an integer multiple of 90 degrees as equivalent arrangements. Fig. 26 shows the relationship between the arrangements A to E of the micro-magnets 6 obtained by calculation and the gradient magnetic field distribution. In Fig. 26, the horizontal axis indicates the displacement position in the x direction, with the origin being the center position of the quantum dot 2 in the x direction (see Fig. 24(b) and Fig. 25), and the vertical axis indicates the gradient magnetic field strength, with the gradient magnetic field strength applied in the positive direction of the x axis in Fig. 24(a) being a positive value and the gradient magnetic field strength applied in the negative direction of the x axis in Fig. 24(a) being a negative value. The arrangement with the largest absolute value provides the quantum dot 2 with the strongest gradient magnetic field strength.

[0055] As can be seen from Figure 26, in arrangements A and B, the gradient magnetic field strength at the position of the quantum dot 2 is 0 due to symmetry. Furthermore, of the three magnets included in arrangement D, the two micro-magnets 6 arranged diagonally correspond to arrangement B and do not generate a gradient magnetic field at the position of the quantum dot 2, so arrangement D has the same gradient magnetic field strength as arrangement C when one micro-magnet 6 is arranged. The gradient magnetic field strength formed by arrangement E at the position of the quantum dot 2 is equivalent to twice the gradient magnetic field strength formed by one micro-magnet 6, and arrangement E is the condition for obtaining the largest gradient magnetic field strength of all arrangements. As shown in Table 1 below, the spin quantum bit semiconductor element of the present invention can generate a gradient magnetic field strength that is 5 to 10 times stronger than that of the conventional technology (Non-Patent Documents 3 and 4) while using a magnet that is smaller than that of the conventional technology (Non-Patent Documents 3 and 4) (see Configuration E). In other words, this result shows that it is possible to obtain a gradient magnetic field strength that is not possible with conventional technology, while solving the problem of the magnet size (area) becoming enormous compared to the unit area (approximately tens of nm x tens of nm) required to form the device structure of one quantum dot 2, which hinders high integration.

[0056] [Table 1]

[0057] Next, Fig. 27 shows the calculation results of the gradient magnetic field distribution in the diagonal cross section of the arrangement E. In Fig. 27, the horizontal axis indicates the displacement (r) position in the diagonal direction with the origin being the center position of the diagonal direction of the quantum dot 2 (QD) (see the upper left of Fig. 27), and the vertical axis indicates the displacement (z) position in the height direction with the origin being the center position of the height direction of the quantum dot 2 (QD) (z direction in Fig. 24(b)). Also, the 50 to -50 (B SL The scale indicated by (mT / nm) indicates the gradient magnetic field strength by the shade of color, and the darker the color, the stronger the gradient magnetic field strength.

[0058] 27, the gradient magnetic field strength is strong near the corner of the L-shaped cross section of the micromagnet 6 (BNM), and is maximum at a point slightly shifted in the z direction from the corner. Therefore, when spinning electrons in the quantum dots 2 using the gradient magnetic field formed near the corner on the upper end side of the micromagnet 6, it is preferable to set the position of the corner of the micromagnet 6 slightly above or below the quantum dots 2, that is, the upper surface of the Si semiconductor layer.

[0059] Next, for arrangement E, we verified how far below the top surface of the Si semiconductor layer (quantum dots 2) the position of the corner of the micro-magnet 6 should be set, and also verified how large the micro-magnet 6 should be. 28 shows the results of a simulation conducted to test the relationship between the distance from the top surface of the Si semiconductor layer to the top surface of the micro magnet 6 and the gradient magnetic field strength in the spin qubit semiconductor device according to the configuration E, while changing the size of the micro magnet 6. In FIG. top ) indicates the distance from the top surface of the Si semiconductor layer to the top surface of the micro magnet 6, and B SL0 is the gradient magnetic field strength (B SL0 ), L represents the length of one side of the top surface (bottom surface) of the micro magnet 6, and L 2The area of ​​the top surface (bottom surface) is expressed as (depth x width). Note that the height of the micro magnet 6 in this simulation test (see FIG. 24(b)) remains at 105 nm.

[0060] As can be seen from Figure 28, the area (L 2 ), a significant increase in the gradient magnetic field strength is observed when the position of the corner is 5 nm to 25 nm below the top surface of the Si semiconductor layer (quantum dots 2), and it is found that the optimum condition is when the position of the corner is 10 nm to 20 nm below the top surface of the Si semiconductor layer (quantum dots 2). Furthermore, under these conditions, when the area of ​​the top surface (bottom surface) of the micro magnet 6 is smallest (L 2 = 10 × 10 (nm 2 )), a gradient magnetic field strength that surpasses that of the conventional technology (Table 1) can be obtained.

[0061] Next, Fig. 29 shows the results of a simulation conducted to test the relationship between the distance from the top surface of the Si semiconductor layer to the bottom surface of the micro magnet 6 and the gradient magnetic field strength in the spin qubit semiconductor device according to Arrangement E, while changing the size of the micro magnet 6. In Fig. 29, Bottom Depth (d bottom ) indicates the distance from the top surface of the Si semiconductor layer to the bottom surface of the micro magnet 6, and B SL0 and L are the same as those explained in Fig. 28. In this simulation test, the size of the micro magnet 6 in the height direction is of interest. In addition, L 2 = 10 × 10 (nm 2 ) simulation is top (See Figure 28) is set to 10 nm, and L 2 = 20 × 20 (nm 2 ) and L 2 = 30 × 30 (nm 2 ) each simulation in d top (See FIG. 28) is set to 15 nm.

[0062] As can be seen from Figure 29, the area (L 2) micro magnet 6, Bottom Depth (d bottom ) in the depth range of 100 nm or more, there is no significant change in the gradient magnetic field strength, and it can be seen that if the height direction of the micro-magnet 6 is such that the position of the bottom surface of the micro-magnet 6 is 100 nm or more below the top surface of the Si semiconductor layer, almost the maximum gradient magnetic field strength can be obtained. [Explanation of symbols]

[0063] 1,10,10',20,20',30,30' Spin quantum dot semiconductor device 2,12,22,32,102 quantum dots 3,103 body 4,14,14',24,34,104 Gate insulating layer 5,15,15',25,35,105 Gate electrode 6,16,26,36 Micro magnet 13a,33a board 13b, 13b', 23, 33b Semiconductor layer 13c reservoir 17 Source electrode 18 Drain electrode 18' reservoir electrode 19 Barrier electrode 100 spin qubits 106 Magnet

Claims

1. a body formed of at least one of a semiconductor layer in which quantum dots are formed and a structural portion disposed around the semiconductor layer; a gate electrode disposed on the semiconductor layer at a position facing the quantum dots; a micromagnet that is wholly or partially embedded in the body so as to satisfy the following positional conditions: a first positional condition that the micromagnet is located near the quantum dot; a second positional condition that the lower end of the micromagnet is located below the gate electrode when viewed from above, with the surface of the semiconductor layer closer to the gate electrode as the upper surface and the surface opposite to the upper surface as the lower surface; and a third positional condition that the micromagnet is located at a position that does not have rotational symmetry with the quantum dot as the center of rotation when viewed from above the body. a static magnetic field applying unit capable of applying a static magnetic field to the quantum dots and the micro magnets; A spin qubit semiconductor device comprising:

2. 2. The spin quantum bit semiconductor device according to claim 1, wherein the upper end of the micro-magnet is positioned below the gate electrode.

3. 3. The spin quantum bit semiconductor device according to claim 2, wherein at least the upper end portion of the micro-magnet, which is closer to the quantum dot, has an L-shaped corner in a vertical cross section.

4. 4. The spin qubit semiconductor device according to claim 3, wherein the corners are positioned 5 nm to 25 nm below the top surface of the semiconductor layer.

5. The micro magnets are in the shape of a rectangular pillar that stands upright in the vertical direction, and the maximum diameter of the top surface is 10 μm or less, and the area of ​​the top surface is 100 μm. ２ 5. A spin qubit semiconductor device according to claim 3, wherein:

6. the semiconductor layer has a cross shape in which two linear layers cross in directions perpendicular to each other when viewed from above the body, and quantum dots are formed at the intersections of the cross shapes; 6. The spin quantum bit semiconductor device according to claim 1, wherein the micro magnets are arranged at positions facing each other across one of the linear layers when viewed from above the body.

7. 7. The spin quantum bit semiconductor device according to claim 1, wherein the material forming the micro magnet contains at least one element selected from the group consisting of iron, cobalt, nickel, and manganese.

8. An integrated circuit in which a plurality of spin qubit semiconductor devices according to any one of claims 1 to 7 are integrated, 1. An integrated circuit comprising: a semiconductor layer formed in the same body; a plurality of quantum dots formed in the semiconductor layer; and a spin qubit semiconductor element structure formed for each quantum dot.

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