Fabricating submicron contacts to buried well devices

Abstract

To provide a semiconductor structure and a method for forming a semiconductor structure.SOLUTION: In a semiconductor structure 2900, two isolation structures 2908 are formed within a semiconductor (2902). A cavity 2918 is etched into the semiconductor 2902 between two isolation structures 2908 in the semiconductor 2902. Dopants are injected underneath the cavity 2918 to form a doped region within the semiconductor 2902 below the cavity 2918 between the two isolation structures 2908. A contact is formed in the cavity 2918. The contact is on the doped region and are in direct contact with the doped region.SELECTED DRAWING: Figure 29

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductors, and more particularly to methods for fabricating semiconductor structures, and more particularly to methods for fabricating contacts to active areas within cavities in semiconductor structures. [Background technology]

[0002] In manufacturing integrated circuits, reducing the size of features for semi-circuits, such as transistors, can allow for increased transistor density. By reducing the size of transistors and other semiconductor devices, smaller chips, increased power efficiency, and other improvements can be realized. For example, increased power efficiency can result in smaller transistors that can perform more calculations while generating less heat compared to larger transistors. Furthermore, smaller die sizes can reduce manufacturing costs and increase chip density.

[0003] Technologies for various sizes of features in semiconductor manufacturing are referred to as "process nodes" or "technology nodes." As technology node sizes decrease, smaller feature sizes exist with those technologies, making it possible to fabricate smaller transistors that are smaller and more power efficient.

[0004] As chip sizes decrease, fabricating semiconductor devices with smaller features becomes a challenge. For example, as feature sizes decrease, lithography processes become more difficult. As another example, increasing transistor density increases crosstalk and capacitive loading as the frequency of operation increases. Another challenge includes dissipating heat from the operation of higher density transistors. Furthermore, as feature sizes decrease, tighter tolerances are required to fabricate transistors and other semiconductor structures.

[0005] Therefore, it would be desirable to have a method and apparatus that takes into account at least some of the above-mentioned problems, as well as possible other problems. For example, it would be desirable to have a method and apparatus that overcomes the technological problems of producing semiconductors with smaller features. Summary of the Invention

[0006] One embodiment of the present disclosure provides a method for fabricating a semiconductor structure. A first silicon germanium layer on a silicon layer positioned on a second silicon germanium layer on a substrate is etched to form a shallow trench isolation cavity extending through the first silicon germanium layer and the silicon layer into the second silicon germanium layer. A dielectric is deposited in the shallow trench isolation cavity to form an isolation structure. The first silicon germanium layer on the silicon layer positioned on the second silicon germanium layer in an area positioned between two of the isolation structures is etched to form a cavity. A dopant is implanted into the cavity to form an n-well. The dopant is implanted at an energy level that reduces lateral straggle of the dopant to a desired level. Metal is deposited so that the metal in the cavity contacts the n-well.

[0007] In another embodiment of the present disclosure, a method forms a semiconductor structure. Two isolation structures are formed in the semiconductor. A cavity is etched in the semiconductor between the two isolation structures. A dopant is implanted into the underside of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. A contact is formed in the cavity. The contact is on and in direct contact with the doped region.

[0008] In yet another embodiment of the present disclosure, a semiconductor structure includes a semiconductor. Two shallow trench isolation structures are located within the semiconductor. A cavity is located between the two shallow trench isolation structures. An active area is located within the semiconductor below the cavity. A metal contact is located within the cavity. The metal contact directly contacts the active area.

[0009] These features and functions may be realized alone in various embodiments of the present disclosure or may be combined in yet further embodiments, further details of which can be seen with reference to the following description and drawings.

[0010] The novel features believed characteristic of the illustrative embodiments are set forth in the appended claims, however, the illustrative embodiments and preferred modes of use, further objects and features thereof will best be understood by reading the following detailed description of illustrative embodiments of the present disclosure when read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view of a semiconductor according to an illustrative embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor according to an illustrative embodiment. [Figure 3] FIG. 1 is a top view of a hard mask on a semiconductor structure, according to an illustrative embodiment. [Figure 4] 1 is a cross-sectional view of a semiconductor having a shallow trench isolation cavity and a hard mask according to an example embodiment. [Figure 5] FIG. 1 is a top view of a semiconductor having an isolation structure according to an illustrative embodiment. [Figure 6] 1 is a cross-sectional view of a semiconductor having an isolation structure according to an illustrative embodiment. [Figure 7] FIG. 1 illustrates a top view of a semiconductor having a dual layer hard mask according to an example embodiment. [Figure 8]1 is a cross-sectional view of a semiconductor having a dual layer hard mask according to an illustrative embodiment. [Figure 9] FIG. 1 illustrates a top view of a semiconductor having patterned photoresist on a dual layer hard mask according to an illustrative embodiment. [Figure 10] 1 is a cross-sectional view of a semiconductor having an organic photoresist patterned to expose an opening, according to an illustrative embodiment. [Figure 11] 1 is a top view of a semiconductor having a cavity formed therein, according to an illustrative embodiment; [Figure 12] 1 is a cross-sectional view of a semiconductor cavity according to an example embodiment. [Figure 13] FIG. 2 is a top view of a semiconductor having a liner according to an illustrative embodiment. [Figure 14] 1 is a cross-sectional view of a semiconductor having a cavity according to an illustrative embodiment. [Figure 15] 1 is a top view of a semiconductor having an active area according to an illustrative embodiment. [Figure 16] 1 is a cross-sectional view of a semiconductor device having an active area according to an illustrative embodiment. [Figure 17] FIG. 1 is a top view of a semiconductor with an ohmic metal according to an example embodiment. [Figure 18] 1 is a cross-sectional view of a semiconductor device having an active area according to an illustrative embodiment. [Figure 19] FIG. 1 is a top view of a semiconductor having contacts according to an illustrative embodiment. [Figure 20] 1 is a cross-sectional view of a semiconductor device having an active area according to an illustrative embodiment. [Figure 21] 1 is a flowchart of a process for fabricating a semiconductor structure, in accordance with an illustrative embodiment. [Figure 22] 10 is a flowchart of a further operation in a process for manufacturing a semiconductor structure, in accordance with an illustrative embodiment. [Figure 23]10 is a flowchart of a further operation in a process for manufacturing a semiconductor structure, in accordance with an illustrative embodiment. [Figure 24] 10 is a flowchart of a further operation in a process for manufacturing a semiconductor structure, in accordance with an illustrative embodiment. [Figure 25] 1 is a flowchart for forming an isolation structure in a semiconductor structure, in accordance with an illustrative embodiment. [Figure 26] 10 is a flowchart illustrating forming contacts in accordance with an illustrative embodiment. [Figure 27] 1 is a flowchart of a process for fabricating a semiconductor structure, in accordance with an illustrative embodiment. [Figure 28] 1 is a flowchart of a process for fabricating a contact to a buried channel layer, according to an illustrative embodiment. [Figure 29] 1 is a block diagram of a semiconductor structure according to an illustrative embodiment. [Figure 30] FIG. 1 is a block diagram of a product management system in accordance with an illustrative embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0012] Exemplary embodiments recognize and take into account one or more different considerations. For example, exemplary embodiments recognize and take into account that it is beneficial to reduce the active area of ​​n-well transistors from several microns to sub-micron levels. Exemplary embodiments recognize and take into account that this reduction in feature size allows contact locations to be closer to the device core area, thus resulting in shorter signal lines and smaller charge storage areas. Exemplary embodiments recognize and take into account that reducing the size of the n-well area allows for a reduction in the device footprint.

[0013] The exemplary embodiments recognize and take into account that in reducing the size of an active area, such as an n-well, the access resistance between the contact and the active area becomes more important. Furthermore, the exemplary embodiments recognize and take into account that implant spread also becomes more of an issue as the size of the active area becomes smaller. For example, as the width of the active area becomes smaller, the spread tolerance decreases. Spread is the standard deviation of the Gaussian distribution of implanted ions in a direction perpendicular to the ion motion.

[0014] The illustrative embodiments recognize and take into account that one way in which access resistance and implant spreading can be reduced includes using a recess etch in conjunction with an isolation structure before implanting dopants at an energy level that reduces the lateral spreading of the dopants to a desired level.

[0015] Thus, exemplary embodiments provide methods and apparatus for fabricating contacts to structures such as buried wells. For example, exemplary embodiments may provide methods for fabricating submicron contacts to buried wells in silicon / silicon germanium (Si / SiGe) field effect devices. The process in exemplary embodiments allows for improved alignment of contacts to recessed active areas such as buried wells. In exemplary embodiments, the contacts are self-aligned, where implants for the recessed active areas and deposition of the contacts are performed using a single lithography step. In other words, the same mask and pattern used to etch the cavity for the buried well or other buried active area are also used to form the contacts.

[0016] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it will be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. Furthermore, each example given in connection with various embodiments is intended to be illustrative, not limiting.

[0017] Further, the drawings are not necessarily to scale, and some features may be exaggerated to show details of particular components. Thus, the specific structures and functions disclosed herein are not intended to be limiting, but merely as a representative basis for teaching those skilled in the art how to variously employ the methods and structures of the present disclosure.

[0018] For purposes of explanation, hereinafter the terms "upper," "lower," "right," "left," "vertical," "horizontal," "above," "below," and their derivatives, refer to the embodiments of the present disclosure as oriented in the drawings. The term "disposed over" means that a first element, such as a first structure, is above a second element, such as a second structure. In this case, an intervening element, such as an interface structure (e.g., an interface layer), may be present between the first and second elements.

[0019] In this disclosure, when an element, such as a layer, region, or substrate, is referred to as being "on" or "on" another element, the element may be directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on," "directly above," or "on and directly in contact with" another element, there are no intervening elements present, and the element is in contact with the other element.

[0020] The processes, steps, and structures described below do not create a complete process flow for manufacturing integrated circuits. The present disclosure can be practiced in conjunction with integrated circuit manufacturing techniques currently used in the art, and some commonly performed process steps are included only as necessary for an understanding of various embodiments of the present disclosure. Drawings depicting cross-sectional views of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn to illustrate various exemplary features of the present disclosure.

[0021] 1-20, cross-sectional views of a process for forming a semiconductor structure are depicted, according to one illustrative embodiment. First, referring to FIG. 1, a plan view of a semiconductor is depicted, according to one illustrative embodiment. In this illustrative example, a semiconductor 100 may be processed to fabricate a field effect transistor or other suitable device.

[0022] Referring to Figure 2, a cross-sectional view of a semiconductor device is depicted in accordance with one exemplary embodiment. In exemplary embodiments, the same reference numbers may be used in multiple figures. Repeated use of reference numbers in different figures represents the same element in the different figures.

[0023] In this illustrative embodiment, semiconductor device 100 is shown in cross-section taken along line 2-2 in Figure 1. As depicted, semiconductor device 100 is a set of semiconductor layers, which in this embodiment are comprised of a first silicon germanium layer 200, a silicon layer 202, and a second silicon germanium layer 204.

[0024] As used herein, a "set of," when used in reference to items, means one or more items. For example, a "set of semiconductor layers" is one or more semiconductor layers.

[0025] In this illustrative example, a first silicon germanium layer 200 is in direct contact with a silicon layer 202. The silicon layer 202 is in direct contact with a second silicon germanium layer 204. These layers can be processed to fabricate a semiconductor structure, such as a silicon / silicon germanium (Si / SiGe) field effect transistor (FET), or a structure that may be some other suitable device or part of a device. These layers are positioned on a substrate (not shown) in this drawing.

[0026] 3, a top view of a hard mask on a semiconductor structure is depicted, according to one illustrative embodiment. As depicted, hard mask 300 has been patterned with openings for etching semiconductor 100 to form trench isolation cavities. The trench isolation cavities include shallow trench isolation cavity 302 and shallow trench isolation cavity 304.

[0027] As depicted, hard mask 300 is comprised of an inorganic material, as opposed to a polymer or other organic soft resist material. In this exemplary embodiment, hard mask 300 may provide good profile and sidewall control when performing etching operations such as recess etching and etching including plasma etching. In this exemplary embodiment, hard mask 300 is comprised of a SiN X In other exemplary embodiments, hard mask 300 may be composed of other inorganic materials, such as metal oxides, silicon oxides, or other suitable materials. In this embodiment, hard mask 300 may also be referred to as an etch mask.

[0028] 4 depicts a cross-sectional view of a semiconductor device and hard mask having shallow trench isolation cavities according to one example embodiment. In this depicted example, a view of semiconductor device 100 is shown as a cross-section taken along line 4-4 of FIG. 3. As depicted in this figure, shallow trench isolation cavities 302 and shallow trench isolation cavities 304 extend through first silicon germanium layer 200 and silicon layer 202 into second silicon germanium layer 204.

[0029] Referring now to FIG. 5, a top view of a semiconductor device having isolation structures is depicted according to an exemplary embodiment. In this figure, a dielectric material, such as silicon oxide (SiO), is deposited in shallow trench isolation cavities, i.e., shallow trench isolation cavities 302 and 304, to form isolation structures. These isolation structures include isolation structure 500 and isolation structure 502. These isolation structures are formed from depositing a dielectric material, such as silicon oxide, in the shallow trench isolation cavities. In this example, hard mask 300 is removed after forming isolation structures 500 and 502.

[0030] Referring to Figure 6, a cross-sectional view of a semiconductor having isolation structures is depicted, according to one illustrative embodiment. In this depicted example, a view of semiconductor 100 is shown as a cross-section taken along line 6-6 of Figure 5. As can be seen in this cross-sectional view, isolation structure 500 and isolation structure 502 are formed from a dielectric filling shallow trench isolation cavity 302 and shallow trench isolation cavity 304, respectively.

[0031] 7, a top view of a semiconductor having a dual layer hard mask is depicted, in accordance with one illustrative embodiment. In this figure, a dual layer hard mask 700 is shown on a semiconductor 100.

[0032] 8 depicts a cross-sectional view of a semiconductor having a dual layer hard mask according to one example embodiment. In this depicted example, semiconductor 100 is shown in cross-section taken along line 8-8 of FIG.

[0033] In this illustrative example, the dual-layer hard mask 700 is comprised of a first hard mask layer 800 and a second hard mask layer 802. These hard mask layers are comprised of different types of materials. In other words, the first hard mask layer 800 is comprised of a different type of material than the second hard mask layer 802. In this illustrative example, the first hard mask layer 800 may be comprised of a dielectric material such as silicon oxide. The second hard mask layer 802 may be comprised of a metal alloy, silicon nitride, or other suitable material other than silicon oxide.

[0034] 9, a top view of a semiconductor having patterned photoresist on a bilayer hard mask is depicted, according to one illustrative embodiment. In this figure, photoresist 900 is composed of an organic material and is patterned with openings, such as opening 902, opening 904, and opening 906. In this illustrative example, these openings are created to expose bilayer hard mask 700 in areas where an etching process is to be performed to form cavities.

[0035] 10, a cross-sectional view of a semiconductor having organic photoresist patterned to expose openings is depicted, according to one illustrative embodiment. In this depicted example, semiconductor 100 is shown in a cross-sectional view taken along line 10-10 in FIG. 9. In FIG. 9, opening 902, opening 904, and opening 906 are present in photoresist 900. As depicted, these openings in photoresist 900 are positioned to etch cavities positioned between and on either side of isolation structure 500 and isolation structure 502.

[0036] 11 , a top view of a semiconductor device having cavities formed therein is shown, according to one illustrative embodiment. As depicted in this figure, cavities including cavity 1100, cavity 1102, and cavity 1104 are formed in semiconductor 100 through openings 902, 904, and 906 in photoresist 900 using an etching process. As shown in this figure, photoresist 900 has been removed to expose bilayer hard mask 700. The openings in photoresist 900 allow for etching of the cavities. In this example, no etching occurred where photoresist 900 was present.

[0037] 12 depicts a cross-sectional view of a semiconductor cavity according to one example embodiment. In this depicted example, semiconductor 100 is shown in cross-section taken along line 12-12 in FIG.

[0038] In this illustration, cavity 1100, cavity 1102, and cavity 1104 extend through first silicon germanium layer 200 but not through silicon layer 202 or second silicon germanium layer 204 in semiconductor 100. In this illustrative example, the cavities are recessed cavities that extend into first silicon germanium layer 200 in semiconductor 100. Cavity 1100, cavity 1102, and cavity 1104 may each have a width of from about 50 nm to about 200 nm. Each of these cavities may have a depth of from about 50 nm to about 200 nm. In this illustrative example, the depth of the cavities may be measured from the surface of semiconductor 100.

[0039] In an exemplary embodiment, cavity 1100, cavity 1102, and cavity 1104 may each have a depth of about 20 nm above silicon layer 202. When this number is used, the depth for these cavities may be based on the thickness of first silicon germanium layer 200 above silicon layer 202.

[0040] 13, a top view of a semiconductor having a liner is depicted, according to one illustrative embodiment. In this illustrative example, a liner 1300 is deposited on the semiconductor 100. The liner 1300 is an atomic layer deposition (ALD) liner. This type of liner can be formed using thin film deposition techniques. This type of technique can be based on the sequential use of gas phase chemical processes.

[0041] 14, a cross-sectional view of a semiconductor device having a cavity is depicted, according to one illustrative embodiment. In this illustrative example, semiconductor device 100 is shown in cross-section taken along line 14-14 of FIG. 13.

[0042] In this exemplary embodiment, liner 1300 is made of silicon oxide (SiO2), silicon nitride (SiN X ), aluminum oxide (Al2O3), or some other dielectric layer. In this exemplary embodiment, liner 1300 may have a thickness of from about 30 angstroms to about 100 angstroms.

[0043] As used herein, the phrase "at least one of" used in conjunction with enumerated items means that various combinations of one or more of the enumerated items may be used, and that only one of each enumerated item may be required. In other words, "at least one of" means that any combination of items, and that some items from the list may be used, but not all of the enumerated items are required. An item may be a specific object, thing, or category.

[0044] For example, without limitation, "at least one of item A, item B, and item C" can include item A, item A and item B, or item B. This example can also include item A, item B, and item C, or item B and item C. Of course, any combination of these items can be present. In certain exemplary embodiments, "at least one of" can be, by way of example and not limitation, "two items A, one item B, and ten items C," "four items B, and seven items C," or any other suitable combination.

[0045] Referring now to FIG. 15, a top view of a semiconductor having an active area is depicted according to one exemplary embodiment. In this figure, an implantation process has been performed prior to removing liner 1300 of FIGS. 13-14. In the exemplary embodiment, liner 1300 acts as a screening layer to reduce damage to semiconductor 100. As depicted in this example, liner 1300 is removed after implanting dopants to form the active area. In this example, the active area in semiconductor 100 takes the form of n-well 1600, n-well 1602, and n-well 1604.

[0046] 16, a cross-sectional view of a semiconductor having an active area is depicted, according to one illustrative embodiment. In this depicted example, a semiconductor 100 is shown in cross-section taken along line 16-16 in FIG. 15.

[0047] In this cross-sectional view, n-well 1600, n-well 1602, and n-well 1604 are formed using energy levels for implanting dopants selected to minimize lateral spread as much as possible while still providing the desired doping level in the n-wells. For example, a low energy level implant can be performed as opposed to a high energy implant. In other words, energy levels can be selected such that lateral spread of dopants from the direction of implant can be reduced as much as possible, or to some desired level, while still obtaining the desired doping level in the active area, such as in the n-wells.

[0048] In this exemplary embodiment, low energy implants of dopants can be performed using implant energies of less than about 20 keV. For example, implant energies of from about 5 keV to about 20 keV can achieve lateral spreads of less than about 15 nm. These implant energies are in contrast to the higher implant energies used in semiconductor manufacturing, which can range from about 40 keV to over 200 keV.

[0049] In this manner, energy levels can be selected to provide lateral spreading of the dopant that occurs at a desired level, or in other words, to reduce lateral spreading while still producing the desired doping in an active area, such as an n-well.

[0050] As can be seen in this cross-sectional view, n-well 1600, n-well 1602, and n-well 1604 extend below cavity 1100, cavity 1102, and cavity 1104. These n-wells extend through first silicon germanium layer 200, through silicon layer 202, and into second silicon germanium layer 204. In this embodiment, these n-wells may have a width corresponding to the cavities. In an exemplary embodiment, the depth of the n-wells may be approximately 40 nm.

[0051] 17, a top view of a semiconductor with ohmic metal is depicted, according to one illustrative embodiment. Ohmic metal 1700 is deposited and chemical-mechanical polished (CMP) such that ohmic metal 1700 is positioned within cavity 1100, cavity 1102, and cavity 1104.

[0052] 18, a cross-sectional view of a semiconductor having an active area is depicted, according to one illustrative embodiment. In this depicted example, semiconductor 100 is shown in cross-section taken along line 18-18 of FIG. 17.

[0053] As depicted, ohmic metal 1700 in cavity 1100 is in direct contact with n-well 1600, ohmic metal 1700 in cavity 1102 is in direct contact with n-well 1602, and ohmic metal 1700 in cavity 1104 is in direct contact with n-well 1604. In this illustrative example, ohmic metal 1700 may be any metal that can be used to make an ohmic contact to an active area.

[0054] 19, a top view of a semiconductor having contacts is depicted according to one illustrative embodiment. In this illustrative example, semiconductor 100 has been processed to form metal contact 1900, metal contact 1902, and metal contact 1904 from ohmic metal 1700 of FIGS. 17-18.

[0055] 20 depicts a cross-sectional view of a semiconductor having an active area according to one example embodiment. In this depicted example, semiconductor 100 is shown in cross-section taken along line 20-20 of FIG. 19. As seen in this figure, a hard mask was applied in a pattern such that an etching process would form metal contact 1900, metal contact 1902, and metal contact 1904. However, this pattern of dual layer hard mask 700 has also been removed from semiconductor 100 by etching.

[0056] 1-20 are provided to illustrate steps that may be used to fabricate contacts to recessed active areas in a semiconductor. In other words, the active areas are below the surface of the semiconductor. In this illustrative example, n-well 1600, n-well 1602, and n-well 1604 are examples of recessed active areas located below cavity 1100, cavity 1102, and cavity 1104, respectively.

[0057] In an exemplary embodiment, this process can be used to fabricate submicron contacts to buried well Si / SiGe field effect devices. The process flow in Figures 1-20 allows for a more planar semiconductor surface. In an exemplary embodiment, this allows for the formation of next level structures such as gates, contacts, back-end-of-line (BEOL) structures, or other structures.

[0058] Furthermore, the implant plane is closer to the Si well (channel) with a recessed active area. Therefore, a lower energy implant can achieve the desired active area. Using a lower energy implant, the spread of the implant is controlled to define an implant boundary with at least one of sharper corners, a desired width, or other desired shape or dimension for the semiconductor structure.

[0059] The illustration of steps in Figures 1-20 is not meant to limit the aspects of other exemplary embodiments that may be used to fabricate contacts to active areas in semiconductors. For example, in other exemplary embodiments, a single layer mask may be used instead of the dual layer hard mask 700. While three cavities are shown as being installed, other embodiments may include etching only a single cavity. Additionally, other steps may be performed but are not shown so as not to obscure aspects of the invention. For example, photoresist deposition and patterning steps may be used to overlay various materials, such as hard masks or other layers.

[0060] In some embodiments, the bilayer hardmask 700 does not necessarily need to be removed as shown in FIGS. 19 and 20 . Other processing can be performed to fabricate a structure with the bilayer hardmask 700 still in place. In other words, the bilayer hardmask 700 can be subsequently removed after other processing to form the semiconductor structure has been performed. In yet other embodiments, the bilayer hardmask 700 can remain in place as a component within the semiconductor structure. For example, the bilayer hardmask 700 can be used as a gate oxide.

[0061] Thus, one or more exemplary embodiments may overcome technical challenges in fabricating semiconductors with smaller features. One or more exemplary embodiments provide technical solutions for fabricating contacts to active areas in semiconductors. The semiconductor may be a semiconductor substrate or a semiconductor structure composed of one or more different layers of semiconductor.

[0062] An exemplary embodiment provides a method for fabricating a semiconductor structure. In one exemplary embodiment, isolation structures are formed in a semiconductor. A cavity is etched in the semiconductor between two of the isolation structures. A dopant is implanted into the underside of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. A contact is formed in the cavity. The contact is on and in direct contact with the doped region.

[0063] Accordingly, illustrative embodiments provide methods and semiconductor structures for contacts to active areas. The illustrative embodiments can be implemented to form submicron contacts to active areas in semiconductor structures. In that case, the illustrative embodiments can use one or more operations to reduce the footprint of the device. For example, when dopants are implanted using operations in the illustrative embodiments, the n-well area can be reduced in size with less dopant spreading. Furthermore, the active area can be formed closer to the core area of ​​the device. The core area can be a channel area where charge in the n-well reservoir is transported and manipulated for logic operations.

[0064] In one or more embodiments, a recess etch and implant are performed. Contacts are formed in the cavities formed from the recess etch. In a single lithography operation, alignment issues of the contacts to the active area are reduced compared to other currently used techniques.

[0065] In an exemplary embodiment, the fabrication of Si / SiGe nanoelectronics is enabled using this process to create contacts to buried active areas. The process in the exemplary embodiment can also be used to fabricate semiconductor structures for quantum processing devices. For example, contacts can be made to active areas in devices selected from at least one of optical waveguides using point defects in silicon carbide device layers, slot waveguides, ridge waveguides, rib waveguides, buried optical waveguides, suspended waveguides, optical resonators, photon emission quantum memories, or other suitable structures used in quantum processing devices.

[0066] 21, a flowchart of a process for fabricating a semiconductor structure is depicted, according to one illustrative embodiment. The process begins by forming two isolation structures in a semiconductor (operation 2100). In operation 2100, the semiconductor can take several different forms. For example, the semiconductor can be selected from a set of semiconductor layers and / or a substrate.

[0067] In this exemplary embodiment, two isolation structures formed from a dielectric material fill the two cavities. In this embodiment, these isolation structures are shallow trench isolation (STI) structures. The semiconductor may be composed of a material selected from at least one of silicon, silicon germanium, indium phosphate, silicon carbide, gallium arsenide, gallium nitride, or any other suitable material. For example, a suitable material may be a material used with a buried well high electron mobility transistor (HEMT) structure. A HEMT is a field effect transistor that incorporates a junction between two materials with different bandgaps (i.e., a heterojunction) as a channel instead of a doped region.

[0068] The process etches a cavity in a semiconductor between two isolation structures in the semiconductor (operation 2102). The process implants a dopant below the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures (operation 2104). In operation 2104, the implantation of the dopant forms a recessed active area in the semiconductor. The dopant is one of an n-type dopant and a p-type dopant. In this illustrative example, the active area may be an n-well, a p-well, an n+ region, a p+ region, or any other suitable type of active area. Further, in operation 2104, the dopant is implanted at an energy level that reduces lateral spreading of the dopant to a desired level.

[0069] The process forms a contact in the cavity, where the contact is on and in direct contact with the doped region (operation 2106), after which the process terminates.

[0070] 22, a flowchart of further operations in a process for fabricating a semiconductor structure is depicted, illustrating examples of further operations that may be performed in the process of FIG.

[0071] The process deposits a liner before implanting dopants into the cavity to form a doped region in the semiconductor below the cavity (operation 2200). This operation may be performed before operation 2104 of Figure 21 .

[0072] The process removes the liner before depositing metal into the cavity, whereby the metal forms an ohmic contact to the doped region (operation 2104). This operation may be performed before operation 2106 of Figure 21. The process then terminates.

[0073] 23, a flowchart of further operations in a process for fabricating a semiconductor structure is depicted, illustrating examples of further operations that may be performed in the process of FIG.

[0074] The process deposits and patterns a hard mask having openings on the surface of the semiconductor before etching the semiconductor to form two shallow trench isolation cavities (operation 2300), after which the process terminates.

[0075] 24, a flowchart of further operations in a process for fabricating a semiconductor structure is depicted, illustrating examples of further operations that may be performed in the process of FIG.

[0076] The process forms openings in the hard mask before etching the semiconductor to form two shallow trench isolation cavities (operation 2400). The process then terminates. The openings define areas for etching the two shallow trench isolation cavities.

[0077] 25, an example flowchart for forming an isolation structure in a semiconductor structure is depicted, according to an illustrative embodiment. The flowchart illustrates one example of one way in which operation 2100 of FIG. 21 may be performed.

[0078] The process begins by etching a semiconductor to form two shallow trench isolation cavities in the semiconductor (operation 2500). The process then deposits a dielectric within the two shallow trench isolation cavities to form two isolation structures (operation 2502). The process then terminates.

[0079] 26, a flowchart for forming contacts is depicted in accordance with an illustrative embodiment. The flowchart depicts one example of one way in which operation 2106 of FIG. 21 may be performed.

[0080] The process deposits metal on the semiconductor, where the metal fills the cavity (operation 2600). The process removes the metal from areas outside the cavity, where the metal remaining in the cavity forms a contact to the doped region (operation 2602). The process then terminates.

[0081] 27, a flowchart of a process for fabricating a semiconductor structure is depicted, according to one illustrative embodiment. In this example, the semiconductor structure is formed in a semiconductor comprised of a first silicon germanium layer, a silicon layer, and a second silicon germanium layer. These layers may be positioned on a substrate. The substrate may be a silicon germanium substrate, a silicon substrate, or any other suitable type of substrate.

[0082] The process begins by etching a first silicon germanium layer on a silicon layer positioned on a second silicon germanium layer to form a shallow trench isolation cavity that extends through the first silicon germanium layer and the silicon layer into the second silicon germanium layer (operation 2700). The process deposits a dielectric in the shallow trench isolation cavity to form an isolation structure (operation 2702).

[0083] The process etches the first silicon germanium layer on the silicon layer located on the second silicon germanium layer in an area located between two of the isolation structures to form a cavity (operation 2704). The process performs a low-energy implant into the cavity to form an n-well (operation 2706). In an exemplary embodiment, the low-energy implant may be a dopant implant performed using an implant energy of about 5 keV to about 20 keV. The energy level in operation 2706 may be any energy level that reduces lateral spread of the dopant to a desired level. The energy level may be selected to minimize lateral spread as much as possible while still providing a desired doping level in the n-well.

[0084] The process deposits metal in the cavity so that it contacts the n-well (operation 2708). The process then terminates. In operation 2708, the contact is a direct contact of the metal in the cavity to the n-well. In this example, the metal may be any metal that makes an ohmic contact to a semiconductor, such as a Si / SiGe structure.

[0085] Referring to FIG. 28, a flowchart of a process for fabricating a contact to a buried channel layer is depicted, according to one exemplary embodiment. In this example, the buried channel layer is a buried active area, such as an n-well. In this example, the fabrication may be for submicron contacts to buried well Si / SiGe devices. This process can be used to fabricate semiconductor structures such as those shown in the processes depicted in FIGS. 1-20.

[0086] The process begins by depositing a hard mask on a semiconductor including a first silicon germanium layer in direct contact with a silicon layer. The silicon layer is in direct contact with a second silicon germanium layer (operation 2800). The process patterns the hard mask to form openings (operation 2802). The process etches the semiconductor structure, thereby forming trenches where the openings exist in the hard mask (operation 2804). This etch may be part of a shallow trench isolation technique. Operation 2804 may be a shallow trench isolation (STI) etch that forms tapered sidewalls with rounded bottoms to reduce or prevent any stress or electric field concentrations. In this example, the shallow trench isolation etch may use a primary etch gas such as HBr, Cl, or CF with an additional gas such as O to passivate the Si or SiGe sidewalls during the etch operation.

[0087] The process deposits a dielectric material to form a shallow trench isolation structure in the trench (operation 2806). In operation 2806, the dielectric material may be silicon oxide or some other suitable material. Furthermore, more than one type of dielectric material may be used in operation 2806.

[0088] The process performs chemical mechanical polishing to remove the hard mask used to etch the trenches (operation 2808). The process then deposits a bilayer hard mask over the semiconductor structure (operation 2810). The process then deposits photoresist over the bilayer hard mask (operation 2812). The process then pattern the photoresist to form openings for etching cavities between the isolation structures (operation 2814).

[0089] The process etches the semiconductor structure, thereby removing the dual layer hard mask where the openings in the photoresist are located (operation 2816).

[0090] The process strips the photoresist from the semiconductor structure (operation 2818). The process then performs an etching process, whereby the silicon germanium is removed where the bilayer hard mask is no longer present, forming cavities between the isolation structures (operation 2820). In operation 2820, an etching process is performed into the first silicon germanium layer, and in this illustrative example, not into or through the silicon layer. In this operation, the etching may be an active recess etch that provides a flat bottom profile with vertical sidewall profiles and square bottom corners. This profile results in uniform implantation when forming n-wells or other active areas. This etch may be performed using a very thin primary etch gas, such as CF4 or Cl2, without any passivation chemistry. In this depicted example, the etching process may be performed to form multiple cavities, each having a width of about 50 nm to about 200 nm. Furthermore, in this example, the cavities may have a depth of about 50 nm to about 200 nm from the surface of the semiconductor structure.

[0091] The process deposits an atomic layer deposition liner over the semiconductor structure (operation 2822). This liner may reduce damage to the semiconductor structure when ion implantation is performed. For atomic layer deposition liners, the liner may be silicon oxide (SiO), silicon nitride (SiN), or other suitable materials.X The liner may be comprised of a material selected from at least one of silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), or some other dielectric layer. In this exemplary embodiment, the atomic layer deposition liner may have a thickness of from about 30 angstroms to about 100 angstroms. The particular thickness is selected to allow a desired amount of ions to be implanted while reducing damage to materials underlying the semiconductor structure located below the liner.

[0092] The process then performs a low energy implant to form an active area in the form of an n-well in the semiconductor structure below the cavity between the shallow trench isolation structures (operation 2824). In operation 2824, the energy level used for the implant may be, for example, from about 5 keV to about 20 keV.

[0093] In this exemplary embodiment, the ion implantation energy level may be selected to reduce or maintain lateral spread of the dopants implanted into the semiconductor structure at a desired level. In this exemplary embodiment, the lateral spread is the distance that the implanted dopants may spread laterally from the axis along which the ion implantation is performed. By reducing this type of spread of the dopants during implantation, features such as the size of the active area may be made smaller compared to current techniques that use high energy ion implantation.

[0094] The process removes the atomic layer deposition liner from the semiconductor structure (operation 2826). The process deposits metal such that it fills the cavity (operation 2828). In operation 2828, the metal directly contacts the n-well. The metal is an ohmic metal, a metal or metal alloy that can be used to make an ohmic contact to the semiconductor structure. The process performs chemical mechanical polishing (operation 2830). The process performs a wet etching process to remove the bilayer hard mask and form contacts for the semiconductor structure (operation 2832). The process then terminates. In example embodiments, operation 2832 is an optional operation. In some example embodiments, the hard mask can preserve and form structures such as gate oxides.

[0095] 21-28 can be implemented to fabricate contacts to recessed active areas in semiconductors. For example, this process can be used to fabricate submicron contacts to buried well Si / SiGe devices.

[0096] The flowcharts and block diagrams in the various illustrated embodiments illustrate the structure, functionality, and operation of some possible implementations of apparatuses and methods in an example embodiment. In this regard, each block in a flowchart or block diagram may represent at least one of a module, a segment, a function, or a portion of an operation or step. For example, one or more of the blocks may be implemented as program code, hardware, or a combination of program code and hardware to control processing equipment for manufacturing semiconductor structures. When implemented in hardware, the hardware may take the form of, for example, an integrated circuit manufactured or configured to perform one or more operations in the flowcharts or block diagrams. When implemented as a combination of program code and hardware, the implementation may take the form of firmware. Each block in a flowchart or block diagram may be implemented using a dedicated hardware system or a combination of dedicated hardware and a program executed by the dedicated hardware to perform various operations to operate processing equipment for manufacturing semiconductor structures.

[0097] In some alternative implementations of an exemplary embodiment, one or more functions described in a block may occur out of the order described in the figures. For example, in some cases, two blocks shown in succession may be performed substantially simultaneously, or the blocks may sometimes be performed in reverse order depending on the functionality involved. Also, other blocks may be added in addition to the blocks shown in a flowchart or block diagram.

[0098] 29, a block diagram of a semiconductor structure is depicted in accordance with an illustrative embodiment. In this illustrative example, semiconductor structure 2900 is an example of a semiconductor structure that may be formed as depicted in the steps and structures shown in FIGS. 1-20 and within the flowcharts of FIGS. 21-28.

[0099] In this depicted embodiment, semiconductor structure 2900 is comprised of a semiconductor 2902. Semiconductor 2902 is comprised of a material selected from at least one of silicon, silicon germanium, indium phosphate, silicon carbide, gallium arsenide, gallium nitride, or any other suitable material.

[0100] Semiconductor 2902 may be at least one of a set of semiconductor layers 2904 or a substrate 2906. As depicted, isolation structure 2908 is positioned within semiconductor 2902. Isolation structure 2908 includes trench 2910 having dielectric 2912. In this example, isolation structure 2908 is two shallow trench isolation structures 2914. As depicted, dielectric 2912 may take several different forms. For example, dielectric 2912 may be one of silicon dioxide, fluorine doped silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, and other suitable materials.

[0101] A cavity 2918 is positioned between two of the isolation structures 2908. The cavity 2918 may have a depth of about 50 nm to about 200 nm from the surface of the semiconductor 2902. Additionally, in one embodiment, the cavity 2918 has a width of about 20 nm to about 200 nm.

[0102] An active area 2916 is positioned in the semiconductor 2902 below the cavity 2918. The active area 2916 may be one of an n-well, a p-well, an n+ region, and a p+ region. The dopant in the active area 2916 may be one of an n-type dopant or a p-type dopant.

[0103] In an exemplary embodiment, a metal contact 2920 is within cavity 2918. Metal contact 2920 is in direct contact with active area 2916. In this embodiment, metal contact 2920 is an ohmic contact 2922.

[0104] With reference now to Figure 30, a block diagram of a product management system is depicted in accordance with an illustrative embodiment. Product management system 3000 is a physical hardware system. In this illustrative example, product management system 3000 includes at least one of a manufacturing system 3002 or a maintenance system 3004.

[0105] The manufacturing system 3002 is configured to manufacture products. As depicted, the manufacturing system 3002 includes a manufacturing facility 3006. The manufacturing facility 3006 includes at least one of a processing facility 3008 or an assembly facility 3010.

[0106] Processing equipment 3008 is equipment used to process components for parts used to form products. Processing equipment 3008 may be used to process at least one of metal parts, composite parts, semiconductors, circuits, fasteners, ribs, skin panels, spars, antennas, or other suitable types of parts.

[0107] For example, processing equipment 3008 may include machines and tools, which may be at least one of a drill, a hydraulic press, a furnace, a mold, a composite tape layer, a vacuum system, a lathe, or other suitable types of equipment.

[0108] With respect to processing semiconductor components, processing equipment 3008 may include at least one of an epitaxial reactor, an oxidation system, a diffusion system, an etching machine, a cleaning machine, a bonding machine, a dicing machine, a wafer saw, an ion implanter, a physical vapor deposition system, a chemical vapor deposition system, a photolithography system, an electron beam lithography system, a plasma etcher, a die attachment machine, a wire bonder, a die overcoat system, a molding machine, a hermetic sealer, an electrical tester, a burn-in oven, a retention bake oven, a UV eraser, or any other suitable type of equipment that may be used to fabricate semiconductor structures.

[0109] Assembly facility 3010 is a facility used to assemble parts to form a product, such as a chip, an integrated circuit, a computer, an aircraft, or some other product. Assembly facility 3010 may also include machines and tools. Such machines and tools may be at least one of a robotic arm, a crawler, a fastener installation system, a rail-based drilling system, or a robot.

[0110] In this illustrative example, maintenance system 3004 includes maintenance facility 3012. Maintenance facility 3012 may include any equipment necessary to perform maintenance on a product. Maintenance facility 3012 may include tools for performing various operations on parts of the product. These operations may include at least one of disassembling the part, refurbishing the part, inspecting the part, reworking the part, manufacturing a replacement part, or other operations for performing maintenance on the product. Such operations may be routine maintenance, inspection, updates, refurbishing, or other types of maintenance operations.

[0111] In this illustrative example, maintenance facility 3012 may include ultrasound inspection equipment, x-ray imaging systems, vision systems, drills, crawlers, and other suitable devices. In some cases, maintenance facility 3012 may include fabrication facility 3008, assembly facility 3010, or both, for manufacturing and assembling parts needed for maintenance.

[0112] The product management system 3000 also includes a control system 3014. The control system 3014 is a hardware system and may also include software or other types of components. The control system 3014 is configured to control the operation of at least one of the manufacturing system 3002 or the maintenance system 3004. Specifically, the control system 3014 may control the operation of at least one of the processing equipment 3008, the assembly equipment 3010, or the maintenance equipment 3012.

[0113] The hardware in control system 3014 may be implemented using hardware that may include computers, circuits, networks, and other types of equipment. Control may take the form of direct control of manufacturing equipment 3006. For example, robots, computer-controlled machines, and other equipment may be controlled by control system 3014. In other illustrative examples, control system 3014 may manage actions performed by personnel 3016 in the manufacture or maintenance of a product. For example, control system 3014 may assign tasks, provide instructions, display models, or perform other actions to manage the actions performed by personnel 3016. In these illustrative examples, the various steps described and illustrated for fabricating contacts to recessed active areas in semiconductor devices may be performed using control system 3014.

[0114] In various illustrative examples, workers 3016 may operate or interact with at least one of manufacturing facility 3006, maintenance facility 3012, or control system 3014. This interaction may occur to manufacture semiconductor structures and other components for products, such as semiconductor devices or components used in products such as aircraft, spacecraft, communications systems, microelectromechanical systems, optical elements, or superconducting single photon detectors.

[0115] Thus, exemplary embodiments provide methods and semiconductor structures for contacts to active areas. Exemplary embodiments provide methods for fabricating semiconductor structures. In one exemplary embodiment, isolation structures are formed in a semiconductor. A cavity is etched in the semiconductor between two of the isolation structures. Dopants are implanted into the underside of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. In an exemplary embodiment, the doped region is a recessed active area. A contact is formed in the cavity. The contact is on the doped region and in direct contact with the doped region.

[0116] Exemplary embodiments can be implemented to form submicron contacts to active areas in semiconductor structures. In such cases, exemplary embodiments can use one or more operations to reduce the footprint of the device. For example, when dopants are implanted using operations in exemplary embodiments, the n-well area can be reduced in size with less spreading of the dopants. Additionally, the active area can be formed closer to the core area of ​​the device.

[0117] In one or more embodiments, a recess etch and an implant are performed. Contacts are formed in the cavities formed from the recess etch. In a single lithography operation, alignment issues of the contacts with the active area are reduced.

[0118] The description of various exemplary embodiments is presented for purposes of illustration and description and is not intended to be exhaustive or limited to the disclosed forms of embodiments. Components that perform operations or tasks are described by various examples. In an exemplary embodiment, a component may be configured to perform the described operations or tasks. For example, the component may have a structural configuration or design that provides the component with the ability to perform the operations or tasks described as being performed by the component in the exemplary example. Furthermore, when terms such as "includes," "including," "has," and "contains" are used herein, these terms are intended to be inclusive in a manner similar to the open transitional term "comprises," without excluding additional or other elements.

[0119] The present invention further includes embodiments according to the following clauses: Article 1. A method for manufacturing a semiconductor structure (2900), comprising: etching the first silicon germanium layer (200) over the silicon layer (202) positioned on the second silicon germanium layer (204) on a substrate (2906) to form a shallow trench isolation cavity (302, 304) extending through the first silicon germanium layer (200) and the silicon layer (202) into the second silicon germanium layer (204); depositing a dielectric (2912) within the shallow trench isolation cavity (302, 304) to form an isolation structure (500, 502, 2908); Etching the first silicon germanium layer (200) on the silicon layer (202) located on the second silicon germanium layer (204) in an area located between two of the isolation structures (500, 502, 2908) to form a cavity (1100, 1102, 1104, 2918); implanting dopants into the cavity (1100, 1102, 1104, 2918) to form an n-well, the dopants being implanted at an energy level that reduces lateral spread of the dopants to a desired level; and depositing a metal in the cavity (1100, 1102, 1104, 2918) such that the metal contacts the n-well. Article 2. 2. The method of claim 1, further comprising depositing a hard mask (300) on a surface of the first silicon germanium layer (200) before etching the first silicon germanium layer (200) on the silicon layer (202) positioned on the second silicon germanium layer (204) on the substrate (2906) to form the shallow trench isolation cavity (302, 304) extending through the first silicon germanium layer (200) and the silicon layer (202) into the second silicon germanium layer (204). Article 3. 3. The method of claim 2, further comprising forming openings (902, 904, 906) in the hard mask (300) before etching the first silicon germanium layer (200) on the silicon layer (202) positioned on the second silicon germanium layer (204) on the substrate (2906) to form the shallow trench isolation cavities (302, 304) extending through the first silicon germanium layer (200) and the silicon layer (202) into the second silicon germanium layer (204), the openings (902, 904, 906) defining areas for etching the shallow trench isolation cavities (302, 304). Article 4. depositing a liner (1300) before performing the implantation into the cavity (1100, 1102, 1104, 2918) to form the n-well below the cavity (1100, 1102, 1104, 2918); and A method according to any one of clauses 1 to 3, further comprising removing the liner (1300) before depositing the metal in the cavity (1100, 1102, 1104, 2918) so that the metal forms an ohmic contact (2922) to the n-well. Article 5. 5. The method of clause 4, wherein the liner (1300) is an atomic layer deposition liner. Article 6. The liner (1300) is made of SiO2, SiN X 5. The method of claim 4, wherein the material is selected from one of: Article 7. 7. The method of any one of clauses 1 to 6, further comprising performing chemical mechanical polishing on the deposited metal, wherein the metal outside the area of ​​the cavity (1100, 1102, 1104, 2918) is removed and the metal within the cavity (1100, 1102, 1104, 2918) forms an ohmic contact (2922) to the n-well. Article 8. 8. The method of any one of clauses 1 to 7, wherein the dielectric (2912) is one of silicon dioxide, fluorine-doped silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide. Article 9. 9. The method of any one of clauses 1 to 8, wherein the energy level is from about 5 keV to about 20 keV. Article 10. 10. The method of any one of clauses 1 to 9, wherein the cavities (1100, 1102, 1104, 2918) have a depth of from about 50 nm to about 200 nm. Article 11. 11. The method of any one of clauses 1 to 10, wherein the cavity (1100, 1102, 1104, 2918) has a width of from about 20 nm to about 200 nm. Article 12. 12. The method of any one of clauses 1 to 11, wherein the cavity (1100, 1102, 1104, 2918) has a depth of about 20 nm above the silicon layer (202). Article 13. A method for manufacturing a semiconductor structure (2900), comprising: forming two isolation structures (500, 502, 2908) in a semiconductor (100, 2902); Etching a cavity (1100, 1102, 1104, 2918) in the semiconductor (100, 2902) between the two isolation structures (500, 502, 2908) in the semiconductor (100); implanting dopants below the cavity (1100, 1102, 1104, 2918) to form a doped region in the semiconductor (100, 2902) below the cavity (1100, 1102, 1104, 2918) between the two isolation structures (500, 502, 2908); and forming a contact in the cavity (1100, 1102, 1104, 2918), the contact overlying and in direct contact with the doped region. Article 14. depositing a liner (1300) before injecting dopants into the cavity (1100, 1102, 1104, 2918) to form the doped region in the semiconductor (100, 2902) below the cavity (1100, 1102, 1104, 2918); and 14. The method of claim 13, further comprising removing the liner (1300) before depositing the metal in the cavity (1100, 1102, 1104, 2918) so that the metal forms the contact in the form of an ohmic contact (2922) to the doped region. Article 15. 15. The method of clause 14, wherein the liner (1300) is an atomic layer deposition liner. Article 16. The liner (1300) is made of SiO2, SiN X 15. The method of claim 14, wherein the material is selected from one of: Article 17. forming two isolation structures (500, 502, 2908) in the semiconductor (100, 2902), Etching a semiconductor (100, 2902) to form two shallow trench isolation cavities (302, 304) in the semiconductor (100, 2902); and 17. The method of any one of clauses 13 to 16, comprising depositing a dielectric (2912) in the two shallow trench isolation cavities (302, 304) to form the two isolation structures (500, 502, 2908). Article 18. 18. The method of claim 17, wherein the dielectric (2912) is one of silicon dioxide, fluorine-doped silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide. Article 19. 18. The method of claim 17, further comprising depositing and patterning a hard mask (300) having openings (902, 904, 906) on a surface of the semiconductor (100, 2902) before etching the semiconductor (100, 2902) to form the two shallow trench isolation cavities (302, 304). Article 20. 20. The method of claim 19, further comprising forming openings (902, 904, 906) in the hard mask (300) before etching the semiconductor (100, 2902) to form the two shallow trench isolation cavities (302, 304), the openings (902, 904, 906) defining areas for etching the two shallow trench isolation cavities (302, 304). Article 21. forming the contact in the cavity (1100, 1102, 1104, 2918), the contact being on and in direct contact with the doped region; 15. The method of claim 14, comprising depositing a metal on the semiconductor (100), the metal filling the cavity (1100, 1102, 1104, 2918). Article 22. forming the contact in the cavity (1100, 1102, 1104, 2918), the contact being on and in direct contact with the doped region; 22. The method of claim 21, further comprising removing the metal from areas outside the cavity (1100, 1102, 1104, 2918), wherein the metal remaining within the cavity (1100, 1102, 1104, 2918) forms the contact to the doped region. Article 23. 23. The method of any one of clauses 13 to 22, wherein the dopant is implanted at an energy level of from about 5 keV to about 20 keV. Article 24. 14. The method of claim 13, wherein the doped region has a depth of about 50 nm to about 200 nm from a surface of the semiconductor (100, 2902). Article 25. 25. The method of any one of clauses 13 to 24, wherein the cavity (1100, 1102, 1104, 2918) has a width of from about 20 nm to about 200 nm. Article 26. 26. The method of any one of clauses 13 to 25, wherein the semiconductor (100, 2902) is composed of a material selected from at least one of silicon, silicon germanium, indium phosphate, silicon carbide, gallium arsenide, or gallium nitride. Article 27. 27. The method of any one of clauses 13 to 26, wherein the semiconductor (100, 2902) is selected from at least one of a set of semiconductor layers (2904) and a substrate (2906). Article 28. 28. The method of any one of clauses 13 to 27, wherein the dopant is one of an n-type dopant and a p-type dopant. Article 29. Semiconductors (100, 2902), two shallow trench isolation structures (2914) in the semiconductor (100, 2902); a cavity (1100, 1102, 1104, 2918) between the two shallow trench isolation structures (2914); an active area (2916) within the semiconductor (100) below the cavity (1100, 1102, 1104, 2918); and A semiconductor structure (2900) comprising metal contacts (1902, 1904, 2920) within the cavity (1100, 1102, 1104, 2918), the metal contacts (1902, 1904, 2920) in direct contact with the active area (2916). Article 30. 30. The semiconductor structure (2900) of clause 29, wherein the cavity (1100, 1102, 1104, 2918) has a depth of from about 50 nm to about 200 nm. Article 31. 31. The semiconductor structure (2900) of clause 29 or 30, wherein the cavity (1100, 1102, 1104, 2918) has a width of from about 20 nm to about 200 nm. Article 32. A semiconductor structure (2900) according to any one of clauses 29 to 31, wherein the semiconductor (100, 2902) is composed of a material selected from at least one of silicon, silicon germanium, indium phosphate, silicon carbide, gallium arsenide, or gallium nitride. Article 33. 33. The semiconductor structure (2900) of any one of clauses 29 to 32, wherein the semiconductor (100, 2902) is selected from at least one of a set of semiconductor layers (2904) or a substrate (2906). Article 34. 34. The semiconductor structure (2900) of any one of clauses 29 to 33, wherein the active area (2916) is one of an n-well, a p-well, an n+ region, and a p+ region. Article 35. 35. The semiconductor structure (2900) of any one of clauses 29 to 34, wherein the dopant in the active area (2916) is one of an n-type dopant and a p-type dopant.

[0120] Numerous modifications and variations will be apparent to those skilled in the art. Furthermore, various exemplary embodiments may provide different features as compared to other preferred embodiments. The selected embodiment(s) have been chosen and described in order to best explain the principles and practical applications of the embodiments and to facilitate others skilled in the art in understanding the disclosure of the various embodiments and various modifications suitable for the particular applications contemplated.

Claims

1. A method for manufacturing a semiconductor structure (2900), comprising: etching the first silicon germanium layer (200) over the silicon layer (202) positioned on the second silicon germanium layer (204) on a substrate (2906) to form a shallow trench isolation cavity (302, 304) extending through the first silicon germanium layer (200) and the silicon layer (202) into the second silicon germanium layer (204); depositing a dielectric (2912) within the shallow trench isolation cavity (302, 304) to form an isolation structure (500, 502, 2908); Etching the first silicon germanium layer (200) on the silicon layer (202) located on the second silicon germanium layer (204) in an area located between two of the isolation structures (500, 502, 2908) to form a cavity (1100, 1102, 1104, 2918); Injecting dopants into the cavity (1100, 1102, 1104, 2918) to form an n-well, wherein the dopants are implanted at an energy level of 5 keV to 20 keV, reducing lateral extent of the dopants to less than 15 nm; depositing a liner (1300) before performing an implantation into the cavity (1100, 1102, 1104, 2918) to form the n-well below the cavity (1100, 1102, 1104, 2918); depositing a metal in the cavity (1100, 1102, 1104, 2918) such that the metal contacts the n-well, wherein the metal fills the cavity; removing the liner (1300) before depositing the metal into the cavity (1100, 1102, 1104, 2918) so that the metal forms an ohmic contact (2922) to the n-well; removing the metal from areas outside the cavities (1100, 1102, 1104, 2918), wherein the metal remaining in the cavities (1100, 1102, 1104, 2918) forms contacts to doped regions; A method comprising:

2. 2. The method of claim 1, further comprising depositing a hard mask (300) on a surface of the first silicon germanium layer (200) before etching the first silicon germanium layer (200) on the silicon layer (202) positioned on the second silicon germanium layer (204) on the substrate (2906) to form the shallow trench isolation cavity (302, 304) through the first silicon germanium layer (200) and the silicon layer (202) and into the second silicon germanium layer (204).

3. 3. The method of claim 2, further comprising forming openings in a photoresist prior to etching the first silicon germanium layer on the silicon layer positioned on the second silicon germanium layer on the substrate to form the shallow trench isolation cavities extending through the first silicon germanium layer and the silicon layer into the second silicon germanium layer, the openings defining areas for etching the shallow trench isolation cavities.

4. The method of any one of claims 1 to 3, wherein the liner (1300) is an atomic layer deposition liner.

5. The liner (1300) is made of SiO ２ , SiN Ｘ , and Al ２ O ３ The method according to any one of claims 1 to 4, wherein the material is selected from one of the following:

6. 6. The method of claim 1, further comprising performing chemical mechanical polishing on the deposited metal, wherein the metal outside the area of ​​the cavity (1100, 1102, 1104, 2918) is removed and the metal within the cavity (1100, 1102, 1104, 2918) forms an ohmic contact (2922) to the n-well.

7. 7. The method of claim 1, wherein the dielectric (2912) is one of silicon dioxide, fluorine-doped silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide.

8. 8. The method of claim 1, wherein the cavity (1100, 1102, 1104, 2918) has a depth of about 50 nm to about 200 nm.

9. 9. The method of claim 1, wherein the cavity (1100, 1102, 1104, 2918) has a width of from about 20 nm to about 200 nm.

10. 10. The method of claim 1, wherein the cavity (1100, 1102, 1104, 2918) has a depth of about 20 nm above the silicon layer (202).

11. A semiconductor structure (2900) obtained by the method of any one of claims 1 to 10, wherein the semiconductor structure (2900) comprises: Semiconductors (100, 2902), two shallow trench isolation structures (2914) in said semiconductor (100, 2902); a cavity (1100, 1102, 1104, 2918) between the two shallow trench isolation structures (2914); an active area (2916) in the semiconductor (100) below the cavity (1100, 1102, 1104, 2918); and 1. A method for manufacturing a semiconductor structure (2900) comprising metal contacts (1902, 1904, 2920) in the cavities (1100, 1102, 1104, 2918), the metal contacts (1902, 1904, 2920) directly contacting the active area (2916) and filling the cavities (1100, 1102, 1104, 2918).

12. 12. The method for manufacturing a semiconductor structure (2900) of claim 11, wherein the cavity (1100, 1102, 1104, 2918) has a depth of from about 50 nm to about 200 nm.

13. 13. The method for manufacturing a semiconductor structure (2900) of claim 11 or 12, wherein the cavity (1100, 1102, 1104, 2918) has a width of from about 20 nm to about 200 nm.

14. 14. A method for manufacturing a semiconductor structure (2900) according to any one of claims 11 to 13, wherein the semiconductor (100, 2902) is composed of a material selected from at least one of silicon, silicon germanium, indium phosphate, silicon carbide, gallium arsenide, or gallium nitride.

15. 15. The method for manufacturing a semiconductor structure (2900) according to any one of claims 11 to 14, wherein the active area (2916) is one of an n-well, a p-well, an n+ region, and a p+ region.

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