Memory drive device, information processing device, and control method

Abstract

A memory drive device, an information processing device, and a control method are provided that reduce data corruption due to retention characteristics and improve reliability. [Solution] An SSD (Solid State Drive) provided in an information processing device 100 includes a data storage unit including a data storage area and a test storage area, and a control unit. The data storage area is composed of rewritable nonvolatile memory and stores data used for information processing. The test storage area is composed of nonvolatile memory and stores predetermined test data. The control unit determines that a predetermined data retention period has been reached if date and time information acquired from the information processing device is accurate and if the power outage period based on the date and time information exceeds a threshold period. If the date and time information is inaccurate, the control unit determines that the predetermined data retention period has been reached based on an index value related to storage defects in the test storage area, and rewrites data already stored in the data storage area.

Description

[Technical Field]

[0001] The present invention relates to a memory drive device, an information processing device, and a control method. [Background technology]

[0002] In recent years, memory drive devices such as SSDs (Solid State Drives) have become known (see, for example, Patent Document 1). Such memory drive devices use nonvolatile memories such as NAND (Negative AND) flash memories. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-17262 Summary of the Invention [Problem to be solved by the invention]

[0004] In rewritable nonvolatile memories such as NAND flash memories, data may become corrupted over time. The characteristic that causes data corruption over time is called the retention characteristic, and the period during which data is retained is called the retention period. In the conventional memory drive devices described above, it is difficult to determine how much time has passed since the data was written, so data may become corrupted if the retention period is exceeded, for example.

[0005] The present invention has been made to solve the above problems, and its purpose is to provide a memory drive device, an information processing device, and a control method that can reduce data corruption due to retention characteristics and improve reliability. [Means for solving the problem]

[0006] In order to solve the above problem, one aspect of the present invention is a memory drive device having a rewritable non-volatile memory, comprising: a data storage area composed of the non-volatile memory and capable of storing data used for information processing; a test storage area composed of the non-volatile memory and storing predetermined test data; and a control unit that rewrites data already stored in the data storage area when a predetermined data retention period has been reached, wherein the control unit calculates a power-off period of the upper device based on date and time information acquired from the upper device to which the memory drive device is connected, and determines that the predetermined data retention period has been reached if the acquired date and time information is accurate and the power-off period exceeds a threshold period, and if the date and time information is not accurate, determines that the predetermined data retention period has been reached based on an index value regarding memory defects for the test storage area in which the predetermined test data has been pre-stored.

[0007] In addition, one aspect of the present invention is that in the above-mentioned memory drive device, the power-off period is calculated based on first date and time information, which is the date and time information obtained when starting up the upper device from the BIOS (Basic Input Output System) of the upper device, and second date and time information, which is the date and time information when the memory drive device is powered off, and it is determined whether the obtained date and time information is accurate based on the time relationship between the first date and time information and the second date and time information.

[0008] Furthermore, one aspect of the present invention is that in the above-mentioned memory drive device, the index value includes a bit error rate when reading the test data from the test memory area, and when the date and time information is not accurate, the control unit may determine that the specified data retention period has been reached based on the bit error rate as the index value.

[0009] Furthermore, in one aspect of the present invention, in the above-mentioned memory drive device, when the date and time information is accurate, the control unit adopts the longer of a first power-off period calculated based on the first date and time information and the second date and time information, or a second power-off period estimated based on the bit error rate, as the power-off period; when the date and time information is inaccurate, the control unit adopts the second power-off period as the power-off period; and when the power-off period exceeds the threshold period, the control unit determines that the specified data retention period has been reached, and rewrites the data already stored in the data storage area.

[0010] In addition, one aspect of the present invention is that the above-mentioned memory drive device may be provided with a warning processing unit that, when the acquired date and time information is accurate, estimates the average ambient temperature of the higher-level device based on the difference between the first power-off period and the second power-off period, and, when the average ambient temperature is equal to or higher than a threshold temperature, outputs information indicating a warning to the higher-level device.

[0011] In addition, one aspect of the present invention is that in the above-mentioned memory drive device, the control unit may be provided with an estimation correction unit that estimates the second power supply stop period using an estimation model that estimates the power supply stop period from the bit error rate, and corrects the estimation model so that the first power supply stop period and the second power supply stop period coincide when the difference between the first power supply stop period and the second power supply stop period is equal to or greater than a certain period.

[0012] Furthermore, one aspect of the present invention is that in the above-mentioned memory drive device, the control unit may rewrite data already stored in the data storage area when the date and time information is not accurate and when the bit error rate reaches a predetermined threshold indicating that the predetermined data retention period has been reached.

[0013] Furthermore, one aspect of the present invention is that in the above-mentioned memory drive device, the control unit may rewrite data already stored in the data storage area when the date and time information is not accurate and when the change in the bit error rate reaches a predetermined threshold indicating that the predetermined data retention period has been reached.

[0014] Another aspect of the present invention is an information processing device that is the host device and includes the memory drive device described above, and that executes information processing using data stored in the memory drive device.

[0015] Another aspect of the present invention is a control method for a memory drive device having a rewritable non-volatile memory, a data storage area composed of the non-volatile memory and capable of storing data used for information processing, and a test storage area composed of the non-volatile memory and storing predetermined test data, in which a control unit calculates a power-off period of the upper device based on date and time information acquired from the upper device to which the memory drive device is connected, and determines that a predetermined data retention period has been reached if the acquired date and time information is accurate and the power-off period exceeds a threshold period, and determines that the predetermined data retention period has been reached based on an index value regarding memory defects for the test storage area in which the predetermined test data has been pre-stored if the predetermined data retention period has been reached, and rewrites data already stored in the data storage area when the predetermined data retention period has been reached. [Effects of the Invention]

[0016] According to the above aspect of the present invention, data corruption due to retention characteristics can be reduced, thereby improving reliability. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a diagram illustrating an example of a main hardware configuration of an information processing device and an SSD according to a first embodiment. [Figure 2]1 is a block diagram illustrating an example of a functional configuration of an SSD according to a first embodiment. [Figure 3] 4 is a flowchart showing an example of an operation of the SSD according to the first embodiment. [Figure 4] 10 is a flowchart illustrating an example of a correction process for an estimation model of an SSD according to the first embodiment. [Figure 5] 10 is a flowchart illustrating an example of a warning process of an SSD according to the first embodiment. [Figure 6] FIG. 10 is a block diagram illustrating an example of a functional configuration of an SSD according to a second embodiment. [Figure 7] 10 is a flowchart showing an example of an operation of an SSD according to the second embodiment. [Figure 8] FIG. 11 is a block diagram showing an example of a functional configuration of an SSD according to a third embodiment. [Figure 9] 10 is a flowchart showing an example of an operation of an SSD according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] A memory drive device, an information processing device, and a control method according to an embodiment of the present invention will be described below with reference to the drawings.

[0019] [First embodiment] FIG. 1 is a diagram illustrating an example of the main hardware configuration of an information processing device 100 and an SSD 40 according to the first embodiment. As shown in FIG. 1, the information processing device 100 is, for example, a notebook personal computer, and includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40.

[0020] A CPU (Central Processing Unit) 11 executes various arithmetic processes under program control, and controls the information processing device 100 as a whole.

[0021] The main memory 12 is a writable memory used as a read area for the execution program of the CPU 11 or as a work area for writing processing data for the execution program. The main memory 12 is composed of, for example, multiple DRAM (Dynamic Random Access Memory) chips. The execution program includes an OS (operating system), various drivers for operating peripheral devices, various services / utilities, application programs, etc.

[0022] Video subsystem 13 is a subsystem for realizing functions related to image display, and includes a video controller. This video controller processes drawing commands from CPU 11, writes the processed drawing information to a video memory, and also reads the drawing information from the video memory and outputs it to display unit 14 as drawing data (display data).

[0023] The display unit 14 is, for example, a liquid crystal display, and displays a display screen based on the drawing data (display data) output from the video subsystem 13.

[0024] The chipset 21 includes controllers for a Universal Serial Bus (USB), a Serial ATA (AT Attachment), a Serial Peripheral Interface (SPI) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express bus, and a Low Pin Count (LPC) bus, and is connected to a plurality of devices. In FIG. 1, a BIOS memory 22 and an SSD 40 are connected to the chipset 21 as examples of devices. The CPU 11 and the chipset 21 correspond to the main control unit 10 .

[0025] The BIOS (Basic Input Output System) memory 22 is configured with an electrically rewritable nonvolatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM (flash memory). The BIOS memory 22 stores the BIOS and system firmware for controlling the embedded controller 31, etc.

[0026] The SSD (Solid State Drive) 40 (an example of a memory drive device) is a memory drive device having a rewritable nonvolatile memory, and stores an OS, various drivers, various services / utilities, application programs, and various data. The information processing device 100 executes various information processes using the data stored in the SSD 40. The SSD 40 is connected to the chipset 21 via, for example, a serial ATA or a PCI-Express bus. The SSD 40 may also be connected to the CPU 11. In this embodiment, the SSD 40 is connected to the chipset 21 via an NVMe connection using a PCI-Express bus. The SSD 40 also includes a plurality of flash memories 41 and a memory controller 42 .

[0027] The flash memory 41 is, for example, a NAND flash memory, which is an example of a rewritable nonvolatile memory. The flash memory 41 writes data (“0”) to a memory cell or erases data (“1”) from a memory cell by injecting or extracting electrons into the floating gate of the memory cell. In the flash memory 41, data stored in the memory cell may become corrupted over time as electrons in the floating gate move. In the flash memory 41, the characteristic that causes data corruption over time is called the retention characteristic, and the period during which this data is retained is called the retention period. Furthermore, the higher the temperature, the shorter this retention period tends to be.

[0028] The memory controller 42 is a processor including, for example, a CPU, a ROM, a RAM, etc. (not shown), and performs overall control of the SSD 40. The memory controller 42 performs processes such as control processing of a host interface (host I / F) with the chipset 21, control processing of a memory interface (memory I / F) with the flash memory 41, and data management processing of the flash memory 41.

[0029] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing device 100. The embedded controller 31 also has a power management function that controls the power supply circuit 33. The embedded controller 31 is composed of a CPU, ROM, RAM, etc. (not shown), and also has A / D input terminals for multiple channels, D / A output terminals, a timer, and digital input / output terminals. The embedded controller 31 is connected to, for example, an input unit 32 and a power supply circuit 33 via these input / output terminals, and the embedded controller 31 controls the operations of these devices.

[0030] The input unit 32 is an input device such as a keyboard, a pointing device, or a touchpad.

[0031] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, an AC / DC adapter, and the like, and converts a DC voltage supplied from an external power supply or a battery into a plurality of voltages required to operate the information processing device 100. The power supply circuit 33 also supplies power to each unit of the information processing device 100 based on control from the embedded controller 31.

[0032] Next, the functional configuration of the SSD 40 according to this embodiment will be described with reference to FIG. FIG. 2 is a block diagram showing an example of the functional configuration of the SSD 40 according to this embodiment.

[0033] As shown in FIG. 2, the SSD 40 includes a data storage unit 50 and a control unit 60. The SSD 40 is connected to the main control unit 10 of the higher-level device (information processing device 100) via an NVMe connection.

[0034] The main control unit 10 is a functional unit realized by the CPU 11 and chipset 21 executing programs stored in the main memory 12, and executes various processes based on the OS. The main control unit 10 executes information processing, for example, using data stored in the SSD 40. The main control unit 10 also starts up the OS (for example, Windows (registered trademark)) by executing a BIOS program, for example. The main control unit 10 includes, for example, a BIOS processing unit 101.

[0035] The BIOS processing unit 101 is a functional unit realized by causing the CPU 11 to execute a BIOS program, and executes various BIOS processes. The BIOS processing unit 101 executes, for example, a process to start up the OS. Furthermore, when starting up the information processing device 100, the BIOS processing unit 101 transmits a timestamp (date and time information) to the SSD 40 using the NVMe Timestamp function.

[0036] The data storage unit 50 is a storage unit configured, for example, with the above-mentioned plurality of flash memories 41, and includes, for example, a data storage area 51, an ECC (Error Correction Code) storage area 52, a test storage area 53, a timestamp storage area 54, and an estimation model storage unit 55.

[0037] The data storage area 51 is configured by the flash memory 41 and is a storage area capable of storing data used for information processing. The data storage area 51 stores, for example, an OS, various drivers, various services / utilities, application programs, and various data.

[0038] The ECC storage area 52 is configured in the flash memory 41 and is a storage area that stores an error correction code (ECC) that corrects errors in the data stored in the data storage area 51 and the test storage area 53. For example, when data is stored (written) in the data storage area 51 or the test storage area 53, the ECC storage area 52 stores an error correction code (ECC) corresponding to the data.

[0039] The test storage area 53 is configured from the flash memory 41 and stores predetermined test data. The test storage area 53 stores test data for determining whether a predetermined data retention period indicating a predetermined period from data writing has been reached. For example, the test data is stored in the test storage area 53 when the information processing device 100 is shipped. Furthermore, the test data may be re-stored (rewritten) in the test storage area 53 when the OS is reinstalled after the information processing device 100 is shipped.

[0040] The timestamp storage area 54 is configured by the flash memory 41, and stores a BIOS timestamp (start-up timestamp) obtained from the BIOS, a timestamp (power-off timestamp) at shutdown, etc. The timestamp storage area 54 may also store a history of past BIOS timestamps and power-off timestamps.

[0041] The estimation model storage unit 55 is configured by the flash memory 41, and stores an estimation model for estimating a power-off lead time from a bit error rate (hereinafter referred to as BER (Bit Error Rate)) when reading test data from the test storage area 53. The power-off lead time indicates a period during which the information processing device 100 is powered off.

[0042] The estimation model estimates the power-off lead time from the BER using, for example, the following formula (1) which indicates the estimable data retention period (AF) or past actual values ​​of the BER and the power-off lead time.

[0043]

number

[0044] In equation (1), k represents the Boltzmann constant, H represents the activation energy, T1 represents the test temperature (43°C = 316.15K (Kelvin)), and T2 represents the actual temperature.

[0045] The control unit 60 is a functional unit realized by the memory controller 42 described above, and executes various processes for the SSD 40. The control unit 60 includes a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65, a count processing unit 66, a correction processing unit 67, and a warning processing unit 68.

[0046] The host I / F processing unit 61 controls the interface between the chipset 21 and the SSD 40. The host I / F processing unit 61 controls, for example, the interface of a PCI-Express bus (NVMe) and receives commands such as data write and read from the chipset 21. The host I / F processing unit 61 also outputs output information such as data read from the data storage unit 50 to the chipset 21 via the interface of the PCI-Express bus (NVMe). The host I / F processing unit 61 may also control the interface between the CPU 11 and the SSD 40.

[0047] The memory I / F processing unit 62 controls the interface between the control unit 60 (memory controller 42) and the data storage unit 50 (plurality of flash memories 41). The memory I / F processing unit 62 outputs, for example, erase, write, and read commands to the flash memory 41, and controls the flash memory 41.

[0048] The data management unit 63 manages the correspondence between the logical addresses of the SSD 40 used for control by the information processing device 100 and the physical addresses of the data storage unit 50 (flash memory 41), and also manages the data stored in the data storage unit 50. The data management unit 63 executes various processes based on various commands received by the host I / F processing unit 61 from the chipset 21.

[0049] The ECC processing unit 64 (an example of a correction processing unit) corrects errors in data read from the data storage unit 50 based on an ECC (error correction code). The ECC processing unit 64 determines whether or not garbled data (bit corruption) has occurred based on, for example, the read data and the ECC corresponding to the read data, and if garbled data (bit corruption) has occurred, executes error correction processing using the ECC to correct the garbled data.

[0050] When the SSD 40 reaches a predetermined data retention period, the test processing unit 65 rewrites data already stored in at least the data storage area 51. The test processing unit 65 determines whether the predetermined data retention period has been reached by switching between, for example, a power-off lead time A (first power-off period) based on a timestamp (BIOS timestamp) acquired from the main control unit 10 (host device) and a power-off lead time B (second power-off period) based on the BER of the test storage area 53.

[0051] The test processing unit 65 calculates the power-off lead time (power-off period) of the upper device based on the BIOS timestamp (date and time information) acquired from the upper device (main control unit 10 of the information processing device 100) to which the SSD 40 is connected. The test processing unit 65 calculates the power-off lead time A, for example, from the difference between the acquired BIOS timestamp (first date and time information) and a timestamp (a past timestamp such as the power-off timestamp (second power-off period)) stored in the timestamp storage area 54.

[0052] The test processing unit 65 also estimates the power-off lead time B based on an index value related to storage failure for the test storage area 53 in which predetermined test data is pre-stored. The index value related to storage failure includes, for example, a bit error rate (BER) when reading out the test data from the test storage area 53. The test processing unit 65 calculates the BER from the test storage area 53, and estimates the power-off lead time B from the calculated BE using, for example, an estimation model stored in the estimation model storage unit 55.

[0053] The test processing unit 65 also determines whether the acquired BIOS timestamp is accurate. For example, the test processing unit 65 determines whether the acquired BIOS timestamp is accurate based on whether there is a discrepancy between the acquired BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65 determines whether the acquired BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp.

[0054] The BIOS timestamp may be inaccurate if, for example, the RTC (Real Time Clock) of the chipset 21 of the information processing device 100 is reset, or if the battery (backup power supply) for the RTC runs out of power.

[0055] If the acquired BIOS timestamp is accurate, the test processing unit 65 uses the longer of power-off lead time A and power-off lead time B as the power-off lead time. If the acquired BIOS timestamp is not accurate, the test processing unit 65 uses power-off lead time B as the power-off lead time.

[0056] Furthermore, if the power-off lead time exceeds the threshold period, the test processing unit 65 determines that the predetermined data retention period has been reached, and rewrites the data already stored in the data storage area 51. That is, if the acquired BIOS timestamp is accurate and the power-off lead time exceeds the threshold period, the test processing unit 65 determines that the predetermined data retention period has been reached, and rewrites the data already stored in the data storage area 51.

[0057] The test processing unit 65 backs up the data already stored in the data storage area 51 to a buffer storage unit composed of RAM (not shown) via the memory I / F processing unit 62, and rewrites (restores) the data.

[0058] In addition, if the acquired BIOS timestamp is inaccurate, the test processing unit 65 uses the power-off lead time B as the power-off lead time, and therefore, if the timestamp is inaccurate, determines that the specified data retention period has been reached based on an index value (e.g., BER) related to memory defects for the test memory area 53.

[0059] In addition, when the test processing unit 65 rewrites data already stored in the data memory area 51, it may also rewrite data in other areas (such as the test memory area 53, the timestamp memory area 54, and the estimation model memory unit 55) as well.

[0060] The count processing unit 66 stores the acquired BIOS timestamp in the timestamp storage area 54, and also counts the date and time from the BIOS timestamp using the internal clock of the SSD 40.

[0061] If the difference between power-off lead time A and power-off lead time B is equal to or greater than a certain period, correction processing unit 67 corrects the estimation model so that power-off lead time A and power-off lead time B match. Correction processing unit 67 corrects the estimation model by, for example, adjusting activation energy H in equation (1) above so that power-off lead time A and power-off lead time B match. Correction processing unit 67 stores the corrected estimation model in estimation model storage unit 55.

[0062] If the acquired BIOS timestamp is accurate, the warning processing unit 68 estimates the average ambient temperature of the information processing device 100 (host device) based on the difference between the power-off lead time A and the power-off lead time B. The warning processing unit 68 estimates the average ambient temperature of the information processing device 100 (host device), for example, using the above-mentioned formula (1). If the average ambient temperature is equal to or higher than a threshold temperature, the warning processing unit 68 outputs information indicating a warning (for example, a message indicating a warning) to the host device (the main control unit 10 of the information processing device 100). Here, the threshold temperature is, for example, a predetermined temperature that exceeds the upper limit of the guaranteed storage temperature of the SSD 40, and the warning processing unit 68 transmits a message indicating a warning that data has been stored above the upper limit of the guaranteed storage temperature to the main control unit 10, and causes the main control unit 10 to output the warning message to the information processing device 100.

[0063] Next, the operation of the SSD 40 according to this embodiment will be described with reference to the drawings. 3 is a flowchart showing an example of the operation of the SSD 40 according to this embodiment. Here, a process performed by the SSD 40 to prevent data corruption due to retention will be described.

[0064] 3, the control unit 60 of the SSD 40 first acquires a timestamp from the BIOS of the information processing device 100 (step S101). The test processing unit 65 of the control unit 60 acquires the timestamp sent by the BIOS processing unit 101 of the main control unit 10 using the NVMe Timestamp function as a BIOS timestamp (first date and time information). The count processing unit 66 of the control unit 60 stores the acquired BIOS timestamp in the timestamp storage area 54, and counts the date and time from the BIOS timestamp using the internal clock of the SSD 40.

[0065] Next, the test processing unit 65 calculates the power-off lead time A based on the acquired timestamp and the timestamp of the previous power-off (step S102). The test processing unit 65 calculates the power-off lead time A, for example, from the difference between the acquired BIOS timestamp and the power-off timestamp stored in the timestamp storage area 54.

[0066] Next, the test processing unit 65 calculates the BER of the test storage area 53 (step S103). The test processing unit 65 reads the test data from the test storage area 53 via the memory I / F processing unit 62, and calculates the BER.

[0067] Next, the test processing unit 65 estimates the power-off lead time B from the BER (step S104). The test processing unit 65 estimates the power-off lead time B from the BER using the estimation model stored in the estimation model storage unit 55.

[0068] Next, the test processing unit 65 determines whether the timestamp acquired from the BIOS is accurate (step S105). The test processing unit 65 determines whether the acquired BIOS timestamp is accurate, for example, depending on whether there is a discrepancy between the acquired BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65 determines whether the acquired BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp. If the BIOS timestamp is accurate (step S105: YES), the test processing unit 65 proceeds to step S106. If the BIOS timestamp is not accurate (step S105: NO), the test processing unit 65 proceeds to step S107.

[0069] In step S106, the test processing unit 65 adopts the longer of the power-off lead time A and the power-off lead time B. After the process of step S106, the test processing unit 65 advances the process to step S108.

[0070] In step S107, the test processing unit 65 uses the power-off lead time B. After the process of step S107, the test processing unit 65 advances the process to step S108.

[0071] Next, in step S108, the test processing unit 65 determines whether the power-off lead time has exceeded the threshold period. If the power-off lead time has exceeded the threshold period (step S108: YES), the test processing unit 65 determines that the predetermined data retention period has been reached, and proceeds to step S109. If the power-off lead time has not exceeded the threshold period (is equal to or less than the threshold period) (step S108: NO), the test processing unit 65 determines that the predetermined data retention period has not been reached, and proceeds to step S110.

[0072] In step S109, the test processing unit 65 executes a data refresh process. The test processing unit 65 saves data already stored in the data storage area 51 to a buffer storage unit configured by a RAM (not shown) via the memory I / F processing unit 62, for example, and rewrites (restores) the data.

[0073] Next, in step S110, the test processing unit 65 determines whether or not a shutdown request has been received from the BIOS. The test processing unit 65 determines whether or not a shutdown request command has been received from the BIOS via the host I / F processing unit 61. If the test processing unit 65 has received a shutdown request from the BIOS (step S110: YES), the test processing unit 65 proceeds to step S111. If the test processing unit 65 has not received a shutdown request from the BIOS (step S110: NO), the test processing unit 65 returns the process to step S110.

[0074] In step S111, the test processing unit 65 stores a timestamp before shutdown in the timestamp storage area 54. The test processing unit 65 stores a power-off timestamp (second date and time information) counted by the count processing unit 66 using the internal clock of the SSD 40 in the timestamp storage area 54. After processing in step S111, the test processing unit 65 executes shutdown processing of the SSD 40 and ends the processing.

[0075] Next, the correction process for the estimation model of the SSD 40 will be described with reference to FIG. FIG. 4 is a flowchart showing an example of a correction process for the estimation model of the SSD 40 according to this embodiment.

[0076] 4, the correction processing unit 67 of the control unit 60 determines whether the timestamp acquired from the BIOS is accurate (step S201). If the timestamp acquired from the BIOS (BIOS timestamp) is accurate (step S201: YES), the correction processing unit 67 proceeds to step S202. If the timestamp acquired from the BIOS (BIOS timestamp) is not accurate (step S201: NO), the correction processing unit 67 returns the process to step S201.

[0077] In step S202, the correction processing unit 67 determines whether the difference between the power-off lead time A and the power-off lead time B is equal to or greater than a certain period. If the difference between the power-off lead time A and the power-off lead time B is equal to or greater than the certain period (step S202: YES), the correction processing unit 67 proceeds to step S203. If the difference between the power-off lead time A and the power-off lead time B is less than the certain period (step S202: NO), the correction processing unit 67 returns the process to step S201.

[0078] In step S203, the correction processing unit 67 performs recalibration of the test storage area 53 to correct the estimation model. The correction processing unit 67 corrects the estimation model so that the power-off lead time A and the power-off lead time B match. For example, the correction processing unit 67 adjusts the activation energy H in the above-mentioned equation (1) to correct the estimation model so that the power-off lead time A and the power-off lead time B match. The correction processing unit 67 stores the corrected estimation model in the estimation model storage unit 55. After processing in step S203, the correction processing unit 67 returns the processing to step S201.

[0079] Next, the warning process of the SSD 40 will be described with reference to FIG. FIG. 5 is a flowchart showing an example of a warning process of the SSD 40 according to this embodiment.

[0080] 5, the warning processing unit 68 of the control unit 60 determines whether the timestamp acquired from the BIOS is accurate (step S301). If the timestamp acquired from the BIOS (BIOS timestamp) is accurate (step S301: YES), the warning processing unit 68 proceeds to step S302. If the timestamp acquired from the BIOS (BIOS timestamp) is not accurate (step S301: NO), the warning processing unit 68 returns the process to step S301.

[0081] In step S302, the warning processing unit 68 estimates the average ambient temperature from the difference between the power-off lead time A and the power-off lead time B. The warning processing unit 68 estimates the average ambient temperature of the information processing device 100 (host device) using, for example, the above-mentioned formula (1).

[0082] Next, the warning processing unit 68 determines whether the average ambient temperature is equal to or greater than the threshold temperature (step S303). If the average ambient temperature is equal to or greater than the threshold temperature (step S303: YES), the warning processing unit 68 proceeds to step S303. If the average ambient temperature is less than the threshold temperature (step S303: NO), the warning processing unit 68 returns the process to step S301.

[0083] In step S304, the warning processing unit 68 transmits a warning message to the information processing device 100. For example, the warning processing unit 68 transmits a warning message to the main control unit 10 to warn that the data has been stored at a temperature exceeding the upper limit of the guaranteed storage temperature, and causes the main control unit 100 to output the warning message. After the processing of step S203, the warning processing unit 68 returns the processing to step S201.

[0084] As described above, the SSD 40 (memory drive device) according to this embodiment is a memory drive device having a rewritable flash memory 41 (non-volatile memory) and includes a data storage area 51, a test storage area 53, and a control unit 60. The data storage area 51 is configured with the flash memory 41 and is an area capable of storing data used for information processing. The test storage area 53 is configured with the flash memory 41 and stores predetermined test data. The control unit 60 rewrites data already stored in the data storage area 51 when a predetermined data retention period has been reached. The control unit 60 calculates the power-off lead time (power-off period) of the host device (information processing device 100) to which the SSD 40 is connected based on a BIOS timestamp (date and time information) acquired from the host device. If the acquired BIOS timestamp is accurate and the power-off lead time exceeds a threshold period, the control unit 60 determines that the predetermined data retention period has been reached. If the timestamp is inaccurate, the control unit 60 determines that the predetermined data retention period has been reached based on an index value (e.g., BER) related to storage defects for the test storage area 53, in which predetermined test data has been previously stored.

[0085] As a result, the SSD 40 (memory drive device) according to this embodiment switches between determining whether a predetermined data retention period has been reached based on a power-off lead time (power-off period) based on a BIOS timestamp (date and time information) acquired from a higher-level device (information processing device 100), and determining whether a predetermined data retention period has been reached based on an index value (for example, BER). Therefore, the SSD 40 (memory drive device) according to this embodiment can appropriately and reliably determine whether a predetermined data retention period has been reached, and can appropriately rewrite data to the data storage area 51 before data corruption occurs, thereby reducing data corruption due to retention characteristics and improving reliability.

[0086] Furthermore, in this embodiment, the control unit 60 calculates the power-off lead time based on a BIOS timestamp (first date and time information) that is a timestamp acquired from the BIOS of the host device when the host device is started, and a power-off timestamp (second date and time information) that is a timestamp when the power is turned off to the SSD 40. Furthermore, the control unit 60 determines whether the acquired BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp.

[0087] As a result, the SSD 40 according to this embodiment can easily calculate the power-off lead time using the BIOS timestamp (first date and time information) and the power-off timestamp (second date and time information). Furthermore, the SSD 40 according to this embodiment can appropriately determine whether the BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp. Therefore, the SSD 40 according to this embodiment can appropriately use the power-off lead time calculated from the BIOS timestamp to reduce data corruption due to retention characteristics and improve reliability.

[0088] In this embodiment, the index value also includes a bit error rate (BER) when reading the test data from the test storage area 53. When the BIOS timestamp is not accurate, the control unit 60 determines whether the predetermined data retention period has been reached based on the bit error rate (BER) as the index value.

[0089] As a result, the SSD 40 according to this embodiment can accurately determine the possibility of data corruption due to retention by using the bit error rate (BER) even when, for example, it is not possible to determine whether the information processing device 100 is off or whether a temperature change has occurred. Therefore, the SSD 40 according to this embodiment can more appropriately reduce data corruption due to the retention characteristics of the flash memory 41.

[0090] Furthermore, in this embodiment, when the BIOS timestamp is accurate, the control unit 60 uses the longer of power-off lead time A (first power-off period) calculated based on the BIOS timestamp and the power-off timestamp, or power-off lead time B (second power-off period) estimated based on the bit error rate (BER), as the power-off lead time. Furthermore, when the BIOS timestamp is inaccurate, the control unit 60 uses power-off lead time B as the power-off lead time. When the power-off lead time exceeds a threshold period, the control unit 60 determines that the predetermined data retention period has been reached, and rewrites the data already stored in the data storage area 51.

[0091] As a result, the SSD 40 according to this embodiment can appropriately and accurately determine that the specified data retention period has been reached by using the more appropriate power-off lead time between the power-off lead time A (first power-off period) and the power-off lead time B (second power-off period), and can more appropriately reduce data corruption due to the retention characteristics of the flash memory 41.

[0092] The SSD 40 according to this embodiment also includes a warning processor 68. If the acquired BIOS timestamp is accurate, the warning processor 68 estimates the average ambient temperature of the host device based on the difference between power-off lead time A and power-off lead time B, and if the average ambient temperature is equal to or greater than a threshold temperature, outputs information indicating a warning to the host device. Here, the threshold temperature is, for example, a predetermined temperature that exceeds the upper limit of the guaranteed storage temperature of the SSD 40.

[0093] As a result, the SSD 40 according to this embodiment can output a warning to the user when, for example, the SSD 40 is stored in a high-temperature environment, such as when the temperature exceeds the upper limit of the SSD 40's guaranteed storage temperature.

[0094] Furthermore, in this embodiment, the control unit 60 estimates the power-off lead time B using an estimation model that estimates the power-off lead time from the bit error rate. The SSD 40 according to this embodiment includes a correction processing unit 67. When the difference between the power-off lead time A and the power-off lead time B is equal to or greater than a certain period of time, the correction processing unit 67 corrects the estimation model so that the power-off lead time A and the power-off lead time B match.

[0095] As a result, the SSD40 of this embodiment can appropriately correct the estimation model when the difference between the power-off lead time A based on the BIOS timestamp and the power-off lead time B based on the BER becomes large, thereby improving the estimation accuracy of the power-off lead time.

[0096] The information processing device 100 according to this embodiment is a host device that includes the SSD 40 described above and executes information processing using data stored in the SSD 40. As a result, the information processing device 100 according to this embodiment can achieve the same effects as the SSD 40 according to this embodiment described above, reducing data corruption due to retention characteristics and improving reliability.

[0097] Furthermore, a control method according to this embodiment is a control method for an SSD 40 having a rewritable flash memory 41, a data storage area 51 configured by the flash memory 41 and capable of storing data used for information processing, and a test storage area 53 configured by the flash memory 41 and storing predetermined test data, and includes a first processing step, a second processing step, and a third processing step. In the first processing step, the control unit 60 calculates the power-off lead time of the host device (information processing device 100) to which the SSD 40 is connected based on a BIOS timestamp acquired from the host device. If the acquired BIOS timestamp is accurate and the power-off lead time exceeds a threshold period, the control unit 60 determines that the predetermined data retention period has been reached based on an index value (e.g., BER) related to storage defects for the test storage area 53, in which predetermined test data has been previously stored. In the third processing step, the control unit 60 rewrites the data already stored in the data storage area 51 when the predetermined data retention period has been reached.

[0098] As a result, the control method according to this embodiment has the same effect as the SSD 40 according to this embodiment described above, and can reduce data corruption due to retention characteristics and improve reliability.

[0099] [Second embodiment] Next, an SSD 40a according to a second embodiment will be described with reference to the drawings. In the second embodiment, a modified example will be described in which the determination of whether a predetermined data retention period has been reached based on the BER is made without using the power-off lead time.

[0100] FIG. 6 is a block diagram showing an example of the functional configuration of the SSD 40a according to this embodiment. As shown in FIG. 6, an SSD 40a (an example of a memory drive device) includes a data storage unit 50a and a control unit 60a.

[0101] In this figure, the same components as those in Figure 2 are denoted by the same reference numerals, and their description will be omitted. Also, the hardware configuration of the SSD 40a and the information processing device 100 according to this embodiment is the same as that of the first embodiment shown in Figure 1, and therefore the description thereof will be omitted here.

[0102] The data storage unit 50a is a storage unit configured by the above-mentioned plurality of flash memories 41, and includes, for example, a data storage area 51, an ECC storage area 52, a test storage area 53, and a timestamp storage area . In this embodiment, the data storage unit 50a is different from the data storage unit 50 of the first embodiment in that it does not include the estimation model storage unit 55.

[0103] The control unit 60a is a functional unit realized by the memory controller 42 described above, and executes various processes for the SSD 40a. The control unit 60a includes a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65a, and a count processing unit 66.

[0104] In this embodiment, the control unit 60a differs from the control unit 60 of the first embodiment in that it does not include the correction processing unit 67 and the warning processing unit 68, and in that the processing by the test processing unit 65a is different.

[0105] If the BIOS timestamp is accurate, the test processing unit 65a calculates the power-off lead time based on the BIOS timestamp. If the BIOS timestamp is accurate and the power-off lead time exceeds a threshold period, the test processing unit 65a determines that the predetermined data retention period has been reached and rewrites the data already stored in the data storage area 51.

[0106] In addition, the test processing unit 65a calculates the BER for the test memory area 53, and if the BIOS timestamp is not accurate and the BER reaches a predetermined threshold indicating that the predetermined data retention period has been reached, it determines that the predetermined data retention period has been reached and rewrites the data already stored in the data memory area 51.

[0107] The details of the calculation process of the power-off lead time and the calculation process of the BER by the test processing unit 65a are the same as those of the test processing unit 65 of the first embodiment described above, and therefore will not be described here.

[0108] Next, the operation of the SSD 40a according to this embodiment will be described with reference to FIG. 7 is a flowchart showing an example of the operation of the SSD 40a according to this embodiment. Here, a process in which the SSD 40a prevents data corruption due to retention will be described.

[0109] 7, the processes from step S401 to step S403 are the same as the processes from step S101 to step S103 shown in Fig. 3 described above, and therefore description thereof will be omitted here. Note that in this embodiment, in step S402, the test processing unit 65a calculates the power-off lead time A as the power-off lead time.

[0110] Next, in step S404, the test processing unit 65a determines whether the timestamp acquired from the BIOS is accurate. The test processing unit 65a determines whether the acquired BIOS timestamp is accurate, for example, depending on whether there is a discrepancy between the acquired BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65a determines whether the acquired BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp. If the BIOS timestamp is accurate (step S404: YES), the test processing unit 65a proceeds to step S405. If the BIOS timestamp is not accurate (step S404: NO), the test processing unit 65a proceeds to step S406.

[0111] In step S405, the test processing unit 65a determines whether the power-off lead time exceeds the threshold period. If the power-off lead time exceeds the threshold period (step S405: YES), the test processing unit 65a determines that the predetermined data retention period has been reached, and proceeds to step S407. If the power-off lead time does not exceed the threshold period (is equal to or less than the threshold period) (step S405: NO), the test processing unit 65a determines that the predetermined data retention period has not been reached, and proceeds to step S408.

[0112] Furthermore, in step S406, the test processing unit 65a determines whether the BER is equal to or greater than a predetermined threshold. Here, the predetermined threshold is a value indicating that a predetermined data retention period has been reached. That is, the test processing unit 65a determines whether the predetermined data retention period has been reached based on the BER. If the BER is equal to or greater than the predetermined threshold (step S406: YES), the test processing unit 65a proceeds to step S407. If the BER is less than the predetermined threshold (step S406: NO), the test processing unit 65a proceeds to step S408.

[0113] In step S407, the test processing unit 65a executes a data refresh process. The test processing unit 65a saves data already stored in the data storage area 51 to a buffer storage unit configured by a RAM (not shown) via the memory I / F processing unit 62, and rewrites (restores) the data.

[0114] The subsequent processes of steps S408 and S409 are similar to the processes of steps S110 and S111 shown in FIG. 3 described above, and therefore will not be described here.

[0115] As described above, the SSD 40a according to this embodiment includes a data storage area 51, a test storage area 53, and a control unit 60a. The control unit 60a calculates the power-off lead time (power-off period) of the host device to which the SSD 40 is connected based on a BIOS timestamp (date and time information) acquired from the host device. If the acquired BIOS timestamp is accurate and the power-off lead time exceeds a threshold period, the control unit 60a determines that the predetermined data retention period has been reached. If the timestamp is inaccurate, the control unit 60a determines that the predetermined data retention period has been reached based on an index value (e.g., BER) related to storage defects for the test storage area 53, in which predetermined test data is pre-stored. If the predetermined data retention period has been reached, the control unit 60a rewrites the data already stored in the data storage area 51.

[0116] As a result, the SSD 40a of this embodiment, like the SSD 40 of the first embodiment described above, can properly rewrite data to the data storage area 51 before data corruption occurs, thereby reducing data corruption due to retention characteristics and improving reliability.

[0117] In addition, in this embodiment, the control unit 60a rewrites data already stored in the data storage area 51 if the BIOS timestamp is not accurate and if the bit error rate (BER) reaches a predetermined threshold indicating that the predetermined data retention period has been reached.

[0118] As a result, the SSD 40a according to this embodiment has the same effects as the SSD 40 according to the first embodiment described above, and can reduce data corruption due to retention characteristics and improve reliability.

[0119] [Third embodiment] Next, an SSD 40b according to a third embodiment will be described with reference to the drawings. In the third embodiment, a modification of the second embodiment will be described in which the reaching of a predetermined data retention period is determined based on the amount of change in the index value (BER).

[0120] FIG. 8 is a block diagram showing an example of the functional configuration of the SSD 40b according to this embodiment. As shown in FIG. 8, an SSD 40b (an example of a memory drive device) includes a data storage unit 50b and a control unit 60b.

[0121] In this figure, the same components as those in Figure 6 are denoted by the same reference numerals, and the description thereof will be omitted. Also, the hardware configuration of the SSD 40b and the information processing device 100 according to this embodiment is the same as that of the first embodiment shown in Figure 1, and therefore the description thereof will be omitted here.

[0122] The data storage unit 50b is a storage unit configured with the above-mentioned multiple flash memories 41, and includes, for example, a data storage area 51, an ECC storage area 52, a test storage area 53, a timestamp storage area 54, and a BER storage area 56.

[0123] The BER storage area 56 is configured by the flash memory 41, and stores the initial value of the BER of the test storage area 53. The initial value of the BER is updated when the test processing unit 65b rewrites data to the data storage area 51.

[0124] The control unit 60b is a functional unit realized by the memory controller 42 described above, and executes various processes for the SSD 40b. The control unit 60b includes a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65b, and a count processing unit 66.

[0125] If the BIOS timestamp is accurate, the test processing unit 65b calculates the power-off lead time based on the BIOS timestamp. If the BIOS timestamp is accurate and the power-off lead time exceeds a threshold period, the test processing unit 65b determines that the predetermined data retention period has been reached and rewrites the data already stored in the data storage area 51.

[0126] In addition, the test processing unit 65a calculates the BER for the test memory area 53, and if the BIOS timestamp is not accurate and the change in the BER reaches a predetermined threshold indicating that the predetermined data retention period has been reached, it determines that the predetermined data retention period has been reached and rewrites the data already stored in the data memory area 51.

[0127] For example, the test processing unit 65b calculates the BER of the test storage area 53 and acquires the initial value of the BER stored in the BER storage area 56. The test processing unit 65b determines that a predetermined data retention period has been reached when the amount of change in the calculated BER from the initial BER value is equal to or greater than a predetermined threshold ΔR1. Here, the predetermined threshold ΔR1 is set as the amount of change in BER corresponding to the period within which errors can be corrected in the data of the test storage area 53 by the error correction process by the ECC processing unit 64, based on, for example, the retention characteristics of the flash memory 41 (characteristics relating to the passage of time and data corruption).

[0128] In addition, when the change in BER becomes equal to or greater than a predetermined threshold ΔR1, the test processing unit 65b rewrites the data already stored in the data memory area 51 and updates the initial value of the BER stored in the BER memory area 56 to the calculated current BER value.

[0129] The processing of the test processing unit 65b in this embodiment differs in that it is changed to a process of determining whether a predetermined data retention period has been reached based on the amount of change in the index value (BER) described above. The other processes are the same as those of the test processing unit 65a in the second embodiment.

[0130] Next, the operation of the SSD 40b according to this embodiment will be described with reference to FIG. 9 is a flowchart showing an example of the operation of the SSD 40b according to this embodiment. Here, a process by the SSD 40b to prevent data corruption due to retention will be described.

[0131] In FIG. 9, the processes from step S501 to step S505 are the same as the processes from step S401 to step S405 shown in FIG. 7 described above, and therefore a description thereof will be omitted here.

[0132] In step S506, the test processing unit 65b acquires the initial value of the BER (past BER value) from the BER storage area 56. The test processing unit 65b acquires the initial value of the BER stored in the BER storage area 56 via the memory I / F processing unit 62.

[0133] Next, the test processing unit 65b determines whether the amount of change in BER is equal to or greater than a predetermined threshold ΔR1 (step S507). Here, the predetermined threshold ΔR1 is a value indicating that a predetermined data retention period has been reached. The test processing unit 65b calculates the amount of change in BER by the difference between the calculated BER and the initial value of BER, and determines whether the amount of change in BER is equal to or greater than the predetermined threshold ΔR1. If the amount of change in BER is equal to or greater than the predetermined threshold ΔR1 (step S507: YES), the test processing unit 65b proceeds to step S508. If the amount of change in BER is less than the predetermined threshold ΔR1 (step S507: NO), the test processing unit 65b proceeds to step S510.

[0134] In step S508, the test processing unit 65b rewrites the data in the data storage area 51. The test processing unit 65b executes the same process as step S109 in FIG.

[0135] Next, the test processing unit 65b stores the BER in the BER storage area 56 (step S509). That is, the test processing unit 65b updates the initial value of the BER stored in the BER storage area 56 to the calculated current BER value. After processing in step S509, the test processing unit 65b proceeds to the process in step S510.

[0136] The subsequent processes of steps S510 and S511 are similar to the processes of steps S408 and S409 shown in FIG. 7, and therefore description thereof will be omitted here.

[0137] The test processing unit 65b may rewrite the data already stored in the data storage area 51 and the test storage area 53 when a predetermined data retention period has elapsed.

[0138] As described above, in this embodiment, the control unit 60b rewrites data already stored in the data storage area 51 when the BIOS timestamp is not accurate and when the change in the bit error rate (BER) reaches a predetermined threshold ΔR1, which indicates that a predetermined data retention period has been reached.

[0139] As a result, the SSD 40b (memory drive device) and information processing device 100 according to this embodiment achieve the same effects as those of the first and second embodiments described above, reducing data corruption due to the retention characteristics of the flash memory 41 and improving reliability.

[0140] The present invention is not limited to the above-described embodiments, and can be modified within the scope of the present invention. For example, in each of the above embodiments, the information processing device 100 is described as being a notebook personal computer, but this is not limited to this and may be another information processing device, such as a desktop personal computer or a tablet terminal device.

[0141] In addition, in each of the above embodiments, an example has been described in which the BER is used as an index value indicating the proportion of memory defects in the test memory area 53, but this is not limited to this, and other index values ​​may be used, such as the cell applied voltage, which is an applied voltage value corresponding to a change in the cell VT voltage. In each of the above embodiments, for example, the BER and the cell applied voltage may be used in combination as an index value.

[0142] Furthermore, in each of the above embodiments, an example has been described in which the processing by the control unit 60 (60a, 60b) (test processing unit 65 (65a, 65b)) is executed as internal processing of the SSD 40 (40a, 40b), but this is not limited to this, and part of the processing of the test processing unit 65 (65a, 65b) may be executed by the information processing device 100.

[0143] In addition, in each of the above embodiments, an example has been described in which the test processing unit 65 (65a, 65b) successively executes the process of determining whether a predetermined data retention period has been reached and the rewrite process of rewriting data to the data storage area 51, but this is not limiting, and the determination process and the rewrite process may be executed separately. The test processing unit 65 (65a, 65b) may execute the rewrite process, for example, triggered by a background media scan of the SSD 40 (40a, 40b).

[0144] Furthermore, the test processing unit 65 (65a, 65b) may perform the rewrite process on a block (or page) of the flash memory 41 to which data is written in the data storage area 51. Furthermore, the test processing unit 65 (65a, 65b) may perform the rewrite process on, for example, a block (or page) in the data storage area 51 that has a high BER and that has been rescued by the ECC function, and perform the rewrite process on the detected block (or page) with a high BER.

[0145] Furthermore, in each of the above embodiments, an example has been described in which the SSD 40 (40a, 40b) is provided with an ECC processing unit 64 as a functional unit realized by the memory controller 42, but this is not limited to this, and for example, the flash memory 41 may be provided with the ECC processing unit 64.

[0146] Each of the components of the SSD 40 (40a, 40b) and the information processing device 100 described above has an internal computer system. A program for implementing the functions of each of the components of the SSD 40 (40a, 40b) and the information processing device 100 described above may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into a computer system and executed to perform processing in each of the components of the SSD 40 (40a, 40b) and the information processing device 100 described above. Here, "reading a program recorded on a recording medium into a computer system and executing it" includes installing the program into a computer system. The term "computer system" here includes hardware such as an OS and peripheral devices. Furthermore, a "computer system" may include multiple computer devices connected via a network, including communication lines such as the Internet, WAN, LAN, and dedicated lines. Furthermore, a "computer-readable recording medium" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into a computer system. Thus, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

[0147] The recording medium also includes internal or external recording media accessible from a distribution server for distributing the program. The program may be divided into multiple parts, downloaded at different times, and then combined into SSD 40 (40a, 40b) and various components of information processing device 100, or each divided program may be distributed by a different distribution server. Furthermore, the term "computer-readable recording medium" also includes a storage medium that stores a program for a certain period of time, such as volatile memory (RAM) within a computer system that serves as a server or client when a program is transmitted over a network. The program may also be a storage medium for implementing some of the above-described functions. Furthermore, the program may be a so-called differential file (differential program) that can realize the above-described functions in combination with a program already stored in the computer system.

[0148] Furthermore, some or all of the above-described functions may be realized as an integrated circuit such as an LSI (Large Scale Integration). Each of the above-described functions may be individually implemented as a processor, or some or all of the functions may be integrated into a processor. Furthermore, the integrated circuit implementation method is not limited to LSI, and may be implemented using a dedicated circuit or a general-purpose processor. Furthermore, if an integrated circuit implementation technology that can replace LSI emerges due to advances in semiconductor technology, an integrated circuit based on that technology may be used. [Explanation of symbols]

[0149] 10 Main control unit 11 CPU 12. Main memory 13 Video Subsystem 14 Display section 21 Chipset 22 BIOS memory 31 Embedded Controller (EC) 32 Input section 33 Power supply circuit 40, 40a, 40b SSD 41 Flash memory 42 Memory Controller 50, 50a, 50b Data storage unit 51 Data Storage 52 ECC storage area 53 Test Storage Area 54 Timestamp storage area 55 Estimation model memory unit 56 BER storage area 60, 60a, 60b Control section 61 Host I / F processing section 62 Memory I / F processing unit 63 Data Management Department 64 ECC processing section 65, 65a, 65b Test processing section 67 Correction processing section 68 Warning processing section 100 Information processing device

Claims

1. A memory drive device having a rewritable nonvolatile memory, a data storage area configured by the nonvolatile memory and capable of storing data used in information processing; a test storage area configured by the nonvolatile memory and storing predetermined test data; a control unit that rewrites data already stored in the data storage area when a predetermined data retention period has elapsed; Equipped with The control unit calculates a power-off period of the host device based on date and time information acquired from the host device to which the memory drive device is connected, and determines that the predetermined data retention period has been reached if the acquired date and time information is correct and if the power-off period exceeds a threshold period; If the date and time information is not accurate, it is determined that the predetermined data retention period has been reached based on an index value relating to a storage defect for the test storage area in which the predetermined test data has been stored in advance. Memory drive device.

2. The control unit calculating the power-off period based on first date and time information, which is the date and time information acquired when the host device is started from a BIOS (Basic Input Output System) of the host device, and second date and time information, which is the date and time information when the memory drive device is powered off; determining whether the acquired date and time information is accurate based on a time relationship between the first date and time information and the second date and time information; 2. The memory drive device according to claim 1.

3. the index value includes a bit error rate when reading the test data from the test storage area; The control unit If the date and time information is not accurate, it is determined that the predetermined data retention period has been reached based on the bit error rate as the index value.

3. The memory drive device according to claim 2.

4. The control unit When the date and time information is accurate, adopting as the power outage period the longer of a first power outage period calculated based on the first date and time information and the second date and time information and a second power outage period estimated based on the bit error rate; If the date and time information is not accurate, the second power supply stop period is adopted as the power supply stop period; When the power supply stop period exceeds the threshold period, it is determined that the predetermined data retention period has been reached, and data already stored in the data storage area is rewritten.

4. The memory drive device according to claim 3.

5. and a warning processing unit that, when the acquired date and time information is correct, estimates an average ambient temperature of the host device based on a difference between the first power supply stop period and the second power supply stop period, and, when the average ambient temperature is equal to or higher than a threshold temperature, outputs information indicating a warning to the host device.

5. The memory drive device according to claim 4.

6. the control unit estimates the second power outage period using an estimation model that estimates the power outage period from the bit error rate; a correction processing unit that corrects the estimation model when a difference between the first power supply stop period and the second power supply stop period is equal to or greater than a certain period, so that the first power supply stop period and the second power supply stop period coincide with each other.

5. The memory drive device according to claim 4.

7. The control unit If the date and time information is not accurate and the bit error rate reaches a predetermined threshold indicating that the predetermined data retention period has been reached, rewriting the data already stored in the data storage area.

4. The memory drive device according to claim 3.

8. The control unit If the date and time information is not accurate and if the amount of change in the bit error rate reaches a predetermined threshold value indicating that the predetermined data retention period has been reached, rewriting of the data already stored in the data storage area is performed.

4. The memory drive device according to claim 3.

9. A memory drive device according to any one of claims 1 to 8, The host device executes information processing using data stored in the memory drive device. Information processing device.

10. A control method for a memory drive device having a rewritable nonvolatile memory, the memory drive device including a data storage area configured by the nonvolatile memory and capable of storing data used in information processing, and a test storage area configured by the nonvolatile memory and storing predetermined test data, comprising: The control unit calculates a power-off period of the host device based on date and time information acquired from the host device to which the memory drive device is connected, and determines that a predetermined data retention period has been reached if the acquired date and time information is correct and if the power-off period exceeds a threshold period; If the date and time information is not accurate, it is determined that the predetermined data retention period has been reached based on an index value relating to a storage defect for the test storage area in which the predetermined test data has been stored in advance; When the predetermined data retention period is reached, the data already stored in the data storage area is rewritten. Control method.

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