Semiconductor device and method for manufacturing the same

Abstract

To preferably improve embedding properties and flatness of a metal electrode in manufacture of a semiconductor device.SOLUTION: A method for manufacturing a semiconductor device including a semiconductor substrate comprises an interlayer insulation film forming step, a contact hole forming step, and an electrode forming step. The interlayer insulation film forming step forms an interlayer insulation film above the semiconductor substrate. The contact hole forming step forms a contact hole for exposing a part of an upper surface of the semiconductor substrate in the interlayer insulation film. The electrode forming step forms a metal electrode containing aluminum element by DC sputtering above the interlayer insulation film and in the contact hole. In at least a part of a step of forming the metal electrode in the electrode forming step, a heating temperature, which is a temperature at which the semiconductor substrate is heated, is higher than or equal to 400°C, and a DC sputtering power is less than or equal to 5 kW.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] BACKGROUND ART Conventionally, in the manufacturing method of semiconductor devices, a technique for "controlling the heating temperature of a semiconductor substrate and controlling the grain size (particle size) of a metal electrode" has been known (see, for example, Patent Document 1). Patent Document 1: JP 2019-145667 A Summary of the Invention [Problem to be solved by the invention]

[0003] In the manufacture of semiconductor devices, it is preferable to improve the embedding property and flatness of metal electrodes. [Means for solving the problem]

[0004] In order to solve the above-mentioned problems, one aspect of the present invention provides a method for manufacturing a semiconductor device including a semiconductor substrate. The method for manufacturing a semiconductor device may include an interlayer insulating film forming step. In the interlayer insulating film forming step, an interlayer insulating film may be formed above the semiconductor substrate. The method for manufacturing a semiconductor device may include a contact hole forming step. In the contact hole forming step, a contact hole that exposes a portion of the upper surface of the semiconductor substrate may be formed in the interlayer insulating film. The method for manufacturing a semiconductor device may include an electrode forming step. In the electrode forming step, a metal electrode containing aluminum element may be formed above the interlayer insulating film and in the contact hole by DC sputtering. In at least a portion of the process of forming the metal electrode in the electrode forming step, the heating temperature at which the semiconductor substrate is heated may be 400°C or higher. In at least a portion of the process of forming the metal electrode in the electrode forming step, the DC sputtering power may be 5 kW or less.

[0005] The heating temperature may be equal to or lower than 500° C. The DC sputtering power may be equal to or higher than 0.5 kW.

[0006] The electrode formation step may include a first sputtering step. The first sputtering step may include DC sputtering to form a first electrode layer containing aluminum element and being a part of the metal electrode. The electrode formation step may include a second sputtering step after the first sputtering step. In the second sputtering step, a second electrode layer containing aluminum element and being a part of the metal electrode may be formed by DC sputtering. In at least one of the first sputtering step and the second sputtering step, the heating temperature may be 400°C or higher. In at least one of the first sputtering step and the second sputtering step, the DC sputtering power may be 5kW or less.

[0007] In the second sputtering stage, the heating temperature may be 400° C. or higher. In the second sputtering stage, the DC sputtering power may be 5 kW or lower.

[0008] In the first sputtering step, the DC sputtering power may be 5 kW or more. In the first sputtering step, the first electrode layer may be formed up to the upper end of the interlayer insulating film. The thickness of the first electrode layer may be half or more of the thickness of the metal electrode. In the first sputtering step, the heating temperature may be 400°C or more.

[0009] The ratio of the thickness of the first electrode layer to the thickness of the second electrode layer may be changed based on the heating temperature, and the higher the heating temperature, the smaller the ratio of the thickness of the second electrode layer to the thickness of the first electrode layer may be.

[0010] In the first sputtering stage, the heating temperature may be 400°C or higher. In the first sputtering stage, the DC sputtering power may be 5 kW or lower. In the second sputtering stage, the heating temperature may be 400°C or higher. In the second sputtering stage, the DC sputtering power may be 5 kW or higher. The higher the heating temperature, the greater the ratio of the thickness of the second electrode layer to the first electrode layer may be.

[0011] A second aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include an interlayer insulating film. The interlayer insulating film may have a contact hole exposing a portion of the top surface of the semiconductor substrate. The interlayer insulating film may be provided above the semiconductor substrate. The semiconductor device may include a metal electrode. The metal electrode may be provided above the interlayer insulating film and in the contact hole. The unevenness of the top surface of the metal electrode may be half or less of the thickness of the interlayer insulating film. The thickness of the metal electrode may be 7.0 μm or less. The width of the contact hole may be 1.5 μm or less.

[0012] The unevenness of the upper surface of the metal electrode may be 0.5 μm or less. The thickness of the interlayer insulating film may be 0.5 μm or more. The metal electrode may be formed by laminating a first electrode layer and a second electrode layer.

[0013] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram illustrating an example of a flowchart of a method for manufacturing a semiconductor device 100. [Figure 2] 1A to 1C are diagrams illustrating an embodiment of a method for manufacturing a semiconductor device 100. [Figure 3] FIG. 10 is a diagram illustrating the electrode formation step S104. [Figure 4]1A and 1B are diagrams illustrating an example of a semiconductor device 100 according to an embodiment. [Figure 5] 1A and 1B are diagrams illustrating an example of a semiconductor device 100 in a comparative example. [Figure 6] 10A and 10B are diagrams illustrating another example of the semiconductor device 100 in the comparative example. [Figure 7] 10A and 10B are diagrams illustrating another example of the semiconductor device 100 in the comparative example. [Figure 8] 10A and 10B are diagrams illustrating another example of the semiconductor device 100 in the comparative example. [Figure 9] 10A and 10B are diagrams illustrating another example of the semiconductor device 100 in the comparative example. [Figure 10] FIG. 10 is a diagram illustrating another example of a flowchart of the method for manufacturing the semiconductor device 100. [Figure 11] 10A and 10B are diagrams illustrating an example of a first sputtering step S205 and a second sputtering step S206. [Figure 12] 10A and 10B are diagrams illustrating another example of the first sputtering step S205 and the second sputtering step S206. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0016] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0017] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0018] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0019] 1 is a diagram illustrating an example of a flowchart of a method for manufacturing a semiconductor device 100 (see FIG. 2). The method for manufacturing the semiconductor device 100 includes a preparation step S101, an interlayer insulating film formation step S102, a contact hole formation step S103, and an electrode formation step S104.

[0020] 2 is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. The semiconductor device 100 functions as a power conversion device such as an inverter, for example. The semiconductor device 100 may include an insulated gate bipolar transistor (IGBT), a diode such as an FWD (Free Wheel Diode), a combination of these such as an RC (Reverse Conducting)-IGBT, or a MOS transistor. The semiconductor device 100 is not limited to these examples.

[0021] First, in preparation step S101, a semiconductor substrate 10 is prepared. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may be a wafer including a plurality of semiconductor devices 100, or may be a substrate cut out from the wafer. The material of the semiconductor substrate 10 may be silicon (Si) or silicon carbide (SiC). A plurality of semiconductor devices 100 may be manufactured by dicing a wafer-like semiconductor substrate 10. The semiconductor substrate 10 has an upper surface 21.

[0022] The upper surface 21 of the semiconductor substrate 10 may be a surface on which a gate structure such as an IGBT or a MOS transistor is formed. The gate structure includes at least one of a gate electrode, a gate insulating film, a source region, an emitter region, and a channel region. The upper surface 21 of the semiconductor substrate 10 may be a so-called device surface.

[0023] Before the preparation step S101, a predetermined pattern may be formed on the upper surface 21 of the semiconductor substrate 10. For example, before the preparation step S101, a gate structure may be formed on the upper surface 21 of the semiconductor substrate 10. Before the preparation step S101, a step of implanting impurities into a predetermined region of the semiconductor substrate 10 and a step of annealing the semiconductor substrate 10 may be performed. Note that in FIG. 2, configurations such as the gate structure provided on the upper surface 21 of the semiconductor substrate 10 are omitted.

[0024] Next, in interlayer insulating film forming step S102, the interlayer insulating film 38 is formed. In interlayer insulating film forming step S102, the interlayer insulating film 38 is formed above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10. In interlayer insulating film forming step S102, the interlayer insulating film 38 may be formed over the entire upper surface 21 of the semiconductor substrate 10.

[0025] The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is, for example, a boron phosphorus silicate glass (BPSG) film. The interlayer insulating film 38 is formed, for example, by atmospheric pressure chemical vapor deposition (CVD). The interlayer insulating film 38 may also be formed by other known methods.

[0026] Next, in contact hole formation step S103, contact holes 54 are formed in the interlayer insulating film 38. In this example, the contact holes 54 expose a portion of the upper surface 21 of the semiconductor substrate 10. The contact holes 54 do not have to expose the entire upper surface 21 of the semiconductor substrate 10. By forming the contact holes 54, the interlayer insulating film 38 is provided on a portion of the upper surface 21 of the semiconductor substrate 10. As an example, the interlayer insulating film 38 is provided so as to cover the upper part of the gate electrode.

[0027] The contact holes 54 may be formed by etching. The etching may be dry etching, wet etching, or the like. The etching may be performed by a known method. In the contact hole formation step S103, the etching may be performed with a resist pattern provided. In the contact hole formation step S103, a reflow process may be performed on the interlayer insulating film 38 after the etching process. As an example, the reflow process on the interlayer insulating film 38 is performed in a nitrogen atmosphere at a temperature of about 1000°C for about 25 minutes.

[0028] After contact hole formation step S103 and before electrode formation step S104, a barrier metal may be formed above the interlayer insulating film 38. The barrier metal is omitted in FIG. 2. The barrier metal may contain Ti. The barrier metal may contain TiN. The barrier metal may be a laminate of Ti and TiN. When the barrier metal is a laminate of Ti and TiN, the thickness of Ti may be about 50 nm, and the thickness of TiN may be about 100 nm. In this specification, thickness refers to the difference in height between the upper surface and the lower surface in the Z-axis direction. The barrier metal may be formed using a DC magnetron sputtering device.

[0029] In the electrode formation step S104, a metal electrode 52 is formed. The metal electrode 52 may be a so-called main electrode of the semiconductor device 100. The main electrode may be the electrode that has the largest area in a top view among the electrodes arranged above the top surface 21 of the semiconductor substrate 10. The main electrode may be electrically connected to, for example, the emitter region or source region of the transistor section, or may be electrically connected to the anode region of the diode section.

[0030] The metal electrode 52 may be provided above the interlayer insulating film 38. In this example, the metal electrode 52 is provided so as to cover the interlayer insulating film 38. The metal electrode 52 may also be provided in a contact hole 54. In this example, the contact hole 54 is filled with the metal electrode 52.

[0031] 3 is a diagram illustrating the electrode formation step S104. The electrode formation step S104 is performed by an apparatus 200. FIG. 3 schematically illustrates the apparatus 200. The apparatus 200 may be a sputtering apparatus. In this example, the apparatus 200 is a DC sputtering apparatus such as a DC magnetron sputtering apparatus. In the electrode formation step S104, the metal electrode 52 may be formed by DC sputtering.

[0032] The apparatus 200 includes a support table 30, a target 40, and a power supply 50. In the electrode formation step S104, the semiconductor device 100 may be placed above the support table 30. In this example, the semiconductor device 100 is placed in contact with the upper surface of the support table 30. Furthermore, since the apparatus 200 is a DC magnetron sputtering apparatus, the apparatus 200 may include a magnet (not shown) that generates a magnetic force.

[0033] The target 40 is the material of the metal electrode 52. In this example, the target 40 contains aluminum elements. That is, the metal electrode 52 contains aluminum elements. The target 40 may be AlSi. The aluminum content of the target 40 may be 90 wt % or more.

[0034] The power supply 50 applies power. In this example, the power is applied by connecting the anode to ground and the cathode to the target 40. The support table 30 may be at a floating potential. The power applied by the power supply 50 is referred to as DC sputtering power W1.

[0035] In the electrode formation step S104, when forming the metal electrode 52, first, the inside of the apparatus 200 is evacuated. The inside of the apparatus 200 is evacuated using a vacuum pump or the like. After the inside of the apparatus 200 is evacuated, a small amount of gas is introduced into the apparatus 200. In this example, the gas is argon gas. After the gas is introduced, the gas pressure inside the apparatus 200 is, for example, 0.3 Pa. The gas pressure inside the apparatus 200 may be approximately 0.3 Pa.

[0036] When the power supply 50 applies power, argon elements discharge and become positive ions (argon ions 60), generating plasma. The argon ions 60 are then attracted to the target 40, which is the cathode, and collide with the target 40. As a result, AlSi molecules (molecules 62) are emitted from the target 40. The emitted molecules 62 attach to the opposing semiconductor device 100, and form metal electrodes 52 on the semiconductor device 100.

[0037] In the electrode formation step S104, the semiconductor substrate 10 is heated. The temperature to which the semiconductor substrate 10 is heated is set to a heating temperature T1. In this example, the semiconductor substrate 10 is heated via the support table 30. That is, the semiconductor substrate 10 may be heated by setting the temperature of the upper surface of the support table 30 to the heating temperature T1.

[0038] In this example, the heating temperature T1 is set to 400°C or higher. By setting the heating temperature T1 to 400°C or higher, grain growth during film formation is promoted, improving the embeddability. The heating temperature T1 in this example is 430°C. Furthermore, if the heating temperature is set too high, the load on the device 200 increases, and the characteristics of the device 200 may deteriorate. It is preferable that the heating temperature T1 be set to 500°C or lower.

[0039] In this example, the DC sputtering power W1 is set to 5 kW or less in the electrode formation step S104. By lowering the DC sputtering power W1, the film formation rate can be lowered. This increases the film formation time, and the reflow effect can improve the flatness of the metal electrode 52. When the DC sputtering power W1 is 5 kW or less, the DC sputtering film formation rate may be 8 nm / sec or less. In this example, the DC sputtering power W1 is 3 kW. The growth rate at this time was 5 nm / sec. In addition, to ensure a minimum film formation rate, it is preferable that the DC sputtering power be 0.5 kW or more.

[0040] In at least a part of the process of forming the metal electrode 52 in the electrode formation step S104, the heating temperature T1 may be 400°C or higher, and the DC sputtering power W1 may be 5 kW or lower. In this example, in all the processes of forming the metal electrode 52 in the electrode formation step S104, the heating temperature T1 is 400°C or higher, and the DC sputtering power W1 is 5 kW or lower.

[0041] 4 is a diagram illustrating an example of a semiconductor device 100 according to an embodiment. FIG. 4 shows the semiconductor device 100 after the electrode formation step S104. The conditions in this embodiment are a DC sputtering power W1 of 3 kW, a temperature T1 of 430°C, and a gas pressure of 0.3 Pa. The metal electrode 52 is formed to a thickness (thickness H3 in FIG. 4) of 5.0 μm.

[0042] The unevenness H1 of the upper surface 53 of the metal electrode 52 may be equal to or less than half the thickness H2 of the interlayer insulating film 38. The unevenness H1 of the upper surface 53 of the metal electrode 52 may be the difference in height between the portion of the upper surface 53 of the metal electrode 52 having the maximum height and the portion of the upper surface 53 of the metal electrode 52 having the minimum height. The thickness H2 of the interlayer insulating film 38 may be the difference in height between the portion of the upper surface of the interlayer insulating film 38 having the maximum height and the portion of the lower surface of the interlayer insulating film 38 having the minimum height. By setting the DC sputtering power W1 to 5 kW or less, the unevenness H1 of the upper surface 53 of the metal electrode 52 can be equal to or less than half the thickness H2 of the interlayer insulating film 38, thereby improving the flatness of the metal electrode 52.

[0043] As another condition, the thickness H3 of the metal electrode 52 may be 7.0 μm or less. The thickness H3 of the metal electrode 52 may be the average thickness of the metal electrode 52 (indicated by the dashed line). As an example, the metal electrode 52 is formed so that the thickness H3 is 5.0 μm. The width D1 of the contact hole may be 1.5 μm or less. Furthermore, the center-to-center distance D2 (cell pitch) of adjacent interlayer insulating films 38 may be 3.5 μm or less. Under these conditions, the flatness of the metal electrode 52 can be improved.

[0044] The unevenness H1 of the upper surface 53 of the metal electrode 52 may be 0.5 μm or less. The unevenness H1 of the upper surface 53 of the metal electrode 52 may be 0.25 μm or less. To improve the flatness of the metal electrode 52, it is preferable that the unevenness H1 of the upper surface 53 of the metal electrode 52 is as small as possible. In FIG. 4, the unevenness H1 of the upper surface 53 of the metal electrode 52 is 0.3 μm. Furthermore, the thickness H2 of the interlayer insulating film 38 may be 0.5 μm or more. The thickness H2 of the interlayer insulating film 38 may be 1.0 μm or more.

[0045] Fig. 5 is a diagram illustrating an example of a semiconductor device 100 in a comparative example. Like Fig. 4, Fig. 5 shows the semiconductor device 100 after the electrode formation step S104. The conditions in Fig. 5 are a DC sputtering power W1 of 12 kW and a temperature T1 of 240°C. Other conditions in Fig. 5 may be the same as those in Fig. 4.

[0046] 5, unevenness H4 on the upper surface 53 of the metal electrode 52 is 0.8 μm. Therefore, the flatness is poorer than that of the semiconductor device 100 in FIG. 4. Furthermore, because voids 55 have occurred, the contact holes 54 have not been filled, and the filling ability is poorer than that of the semiconductor device 100 in FIG. 4. The voids 55 are gaps that have occurred in the metal electrode 52.

[0047] Fig. 6 is a diagram illustrating another example of a semiconductor device 100 in a comparative example. Like Fig. 4, Fig. 6 shows the semiconductor device 100 after the electrode formation step S104. The conditions in Fig. 6 are a DC sputtering power W1 of 12 kW and a temperature T1 of 340°C. The other conditions in Fig. 6 may be the same as the conditions in Fig. 4.

[0048] 6, unevenness H5 on top surface 53 of metal electrode 52 is 1.0 μm. Therefore, the flatness is poorer than that of semiconductor device 100 in FIG. 4. Furthermore, voids 55 are generated, so contact hole 54 is not filled, and the filling ability is poorer than that of semiconductor device 100 in FIG. 4.

[0049] Fig. 7 is a diagram illustrating another example of a semiconductor device 100 in a comparative example. Like Fig. 4, Fig. 7 shows the semiconductor device 100 after the electrode formation step S104. The conditions in Fig. 7 are a DC sputtering power W1 of 12 kW and a temperature T1 of 430°C. Other conditions in Fig. 7 may be the same as those in Fig. 4.

[0050] The unevenness H6 of the upper surface 53 of the metal electrode 52 in Fig. 7 is 1.3 µm. Therefore, the flatness is poorer than that of the semiconductor device 100 in Fig. 4. Furthermore, in this example, no voids are generated and the contact hole 54 is filled.

[0051] Fig. 8 is a diagram illustrating another example of a semiconductor device 100 in a comparative example. Like Fig. 4, Fig. 8 shows the semiconductor device 100 after the electrode formation step S104. The conditions in Fig. 8 are a DC sputtering power W1 of 3 kW and a temperature T1 of 240°C. Other conditions in Fig. 8 may be the same as those in Fig. 4.

[0052] The unevenness H7 of the upper surface 53 of the metal electrode 52 in Fig. 8 is 0.8 µm. Therefore, the flatness is poorer than that of the semiconductor device 100 in Fig. 4. Furthermore, because voids 55 have occurred, the contact holes 54 are not filled, and the filling ability is poorer than that of the semiconductor device 100 in Fig. 4.

[0053] 9 is a diagram illustrating another example of a semiconductor device 100 in a comparative example. Similar to FIG. 4, FIG. 9 shows the semiconductor device 100 after the electrode formation step S104. The conditions in FIG. 9 are a DC sputtering power W1 of 3 kW and a temperature T1 of 340° C. The other conditions in FIG. 9 may be the same as those in FIG. 4.

[0054] 9, unevenness H8 on top surface 53 of metal electrode 52 is 1.0 μm. Therefore, the flatness is poorer than that of semiconductor device 100 in FIG. 4. Furthermore, voids 55 have occurred, so contact hole 54 is not filled, and the filling ability is poorer than that of semiconductor device 100 in FIG. 4.

[0055] 4 to 9, by setting the heating temperature T1 to 400° C. or higher and the DC sputtering power W1 to 5 kW or lower, it is possible to improve the embedding property of the metal electrode 52 and improve the flatness of the metal electrode 52. This reduces defects caused by the metal electrode 52 and reduces the causes of failures in the semiconductor device 100.

[0056] 10 is a diagram illustrating another example of a flowchart of a method for manufacturing a semiconductor device 100. The method for manufacturing a semiconductor device 100 includes a preparation step S201, an interlayer insulating film forming step S202, a contact hole forming step S203, and an electrode forming step S204. The preparation step S201, the interlayer insulating film forming step S202, and the contact hole forming step S203 of FIG. 1 may be the same as the preparation step S101, the interlayer insulating film forming step S102, and the contact hole forming step S103 of FIG.

[0057] In this example, the electrode formation step S204 includes a first sputtering step S205 and a second sputtering step S206. That is, in the electrode formation step S204, the metal electrode 52 is formed in two steps under different conditions. Specifically, the heating temperature or DC sputtering power is changed in the first sputtering step S205 and the second sputtering step S206. The heating temperature in the first sputtering step S205 is T2, and the DC sputtering power in the first sputtering step S205 is W2. The heating temperature in the second sputtering step S206 is T3, and the DC sputtering power in the second sputtering step S206 is W3.

[0058] FIG. 11 is a diagram illustrating an example of the first sputtering step S205 and the second sputtering step S206. In the first sputtering step S205, a first electrode layer 56 is formed. The first electrode layer 56 is a part of the metal electrode 52. That is, the first electrode layer 56 contains aluminum elements. In addition, in the second sputtering step S206, a second electrode layer 58 is formed. The second electrode layer 58 is a part of the metal electrode 52. That is, the second electrode layer 58 contains aluminum elements. In this example, the metal electrode 52 is formed by stacking the first electrode layer 56 and the second electrode layer 58.

[0059] In this example, in at least one of the first sputtering step S205 and the second sputtering step S206, the heating temperature is 400°C or higher, and the DC sputtering power is 5kW or lower. In Fig. 11, in the second sputtering step S206, the heating temperature T3 is 400°C or higher, and the DC sputtering power W3 is 5kW or lower. By setting the conditions for the second sputtering step S206 in this manner, the embedding property of the metal electrode 52 can be improved, and the flatness of the metal electrode 52 can be improved.

[0060] Furthermore, in the first sputtering step S205, the DC sputtering power W2 may be 5 kW or more. By setting the DC sputtering power W2 to 5 kW or more, the film formation rate can be increased, thereby improving throughput. In this case, the unevenness of the upper surface 57 of the first electrode layer 56 becomes greater than the unevenness of the upper surface 59 of the second electrode layer 58. Furthermore, in order to improve embeddability, the heating temperature T2 is preferably set to 400°C or more in the first sputtering step S205 as well. The heating temperatures T2 and T3 may be the same temperature.

[0061] In the first sputtering step S205, the first electrode layer 56 may be formed up to the upper end of the interlayer insulating film 38. In this example, the thickness H9 of the first electrode layer is at least half the thickness H11 of the metal electrode 52. The thickness H9 of the first electrode layer may be at least two-thirds of the thickness H11 of the metal electrode 52. The thickness H9 of the first electrode layer may be at least 2.5 μm. The thickness H10 of the second electrode layer may be at most 2.5 μm. The thickness H11 of the metal electrode 52 is, for example, 5.0 μm. The thickness H9 of the first electrode layer, the thickness H10 of the second electrode layer, and the thickness H11 of the metal electrode 52 may be average thicknesses. The thickness H9 of the first electrode layer, the thickness H10 of the second electrode layer, and the thickness H11 of the metal electrode 52 may be thicknesses at the locations where the contact holes 54 are provided in the Z-axis direction.

[0062] Furthermore, the ratio of the thickness H9 of the first electrode layer 56 to the thickness H10 of the second electrode layer 58 can be changed based on the heating temperature. For example, the higher the heating temperatures T2 and T3, the smaller the ratio of the thickness H10 of the second electrode layer 58 to the thickness H9 of the first electrode layer 56 can be. The higher the heating temperatures T2 and T3, the better the embedding and flatness. Therefore, by increasing the heating temperatures T2 and T3, it is possible to improve flatness even if the deposition amount in the second sputtering step S206 is reduced. A higher heating temperature allows for faster flatness in the second sputtering step S206, so the deposition amount in the first sputtering step S205, which has a higher deposition rate, can be increased.

[0063] 12 is a diagram illustrating another example of the first sputtering step S205 and the second sputtering step S206. In the first sputtering step S205, a first electrode layer 56 is formed. In the second sputtering step S206, a second electrode layer 58 is formed. In FIG. 12, the film formation conditions in the first sputtering step S205 and the second sputtering step S206 are changed from those in FIG. 11.

[0064] In this example, in at least one of the first sputtering step S205 and the second sputtering step S206, the heating temperature is 400°C or higher, and the DC sputtering power is 5kW or lower. In FIG. 12, in the first sputtering step S205, the heating temperature T2 is 400°C or higher, and the DC sputtering power W2 is 5kW or lower. By setting the conditions for the first sputtering step S205 in this manner, the embeddability of the metal electrode 52 can be improved, and the flatness of the metal electrode 52 can be improved. To improve the embeddability of the metal electrode 52 after the second sputtering step S206, the heating temperature T3 in the second sputtering step S206 is preferably 400°C or higher, and the DC sputtering power W3 is preferably 5kW or higher. Setting the DC sputtering power W3 to 5kW or higher can increase the film formation rate and improve throughput.

[0065] Furthermore, the ratio of the thickness H9 of the first electrode layer 56 to the thickness H10 of the second electrode layer 58 can be changed based on the heating temperature. For example, the higher the heating temperatures T2 and T3, the larger the ratio of the thickness H10 of the second electrode layer 58 to the thickness H9 of the first electrode layer 56 can be. The higher the heating temperatures T2 and T3, the better the embedding and flatness. Therefore, by increasing the heating temperatures T2 and T3, it is possible to improve flatness even if the deposition amount in the first sputtering step S205 is reduced. A higher heating temperature allows for faster flatness in the first sputtering step S205, so the deposition amount in the second sputtering step S206, which has a higher deposition rate, can be increased.

[0066] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0067] 10··Semiconductor substrate, 21··Top surface, 38··Interlayer insulating film, 30··Support base, 40··Target, 50··Power supply, 52··Metal electrode, 53··Top surface, 54··Contact hole, 55··Vacancy, 56··First electrode layer, 57··Top surface, 58··Second electrode layer, 59··Top surface, 60··Argon ions, 62··Molecules, 100··Semiconductor device, 200··Apparatus

Claims

1. A method for manufacturing a semiconductor device comprising a semiconductor substrate, comprising: forming an interlayer insulating film above the semiconductor substrate; forming a contact hole in the interlayer insulating film to expose a portion of an upper surface of the semiconductor substrate; an electrode forming step of forming a metal electrode containing aluminum elements on the interlayer insulating film and in the contact hole by DC sputtering; Equipped with The electrode forming step includes: a first sputtering step of forming a first electrode layer containing aluminum element by DC sputtering, the first electrode layer being a part of the metal electrode; a second sputtering step of forming a second electrode layer containing aluminum elements by DC sputtering after the first sputtering step, the second electrode layer being a part of the metal electrode; and In at least one of the first sputtering step and the second sputtering step, the heating temperature to which the semiconductor substrate is heated is 400° C. or higher, and the DC sputtering power is 5 kW or lower. A method for manufacturing semiconductor devices.

2. In the second sputtering step, the heating temperature is 400° C. or more, and the DC sputtering power is 5 kW or less. The method for manufacturing a semiconductor device according to claim 1 .

3. In the first sputtering step, the heating temperature is 400° C. or higher, and the DC sputtering power is greater than 5 kW. The method for manufacturing a semiconductor device according to claim 2 .

4. In the first sputtering step, the first electrode layer is formed up to an upper end of the interlayer insulating film. The method for manufacturing a semiconductor device according to claim 2 or 3.

5. The thickness of the first electrode layer is equal to or greater than half the thickness of the metal electrode. The method for manufacturing a semiconductor device according to any one of claims 2 to 4.

6. The ratio of the thickness of the first electrode layer to the thickness of the second electrode layer is changed based on the heating temperature. The method for manufacturing a semiconductor device according to any one of claims 3 to 5.

7. The higher the heating temperature, the smaller the ratio of the thickness of the second electrode layer to the thickness of the first electrode layer. The method for manufacturing a semiconductor device according to claim 6 .

8. In the first sputtering step, the heating temperature is 400° C. or more, and the DC sputtering power is 5 kW or less. The method for manufacturing a semiconductor device according to claim 1 .

9. In the second sputtering step, the heating temperature is 400° C. or higher, and the DC sputtering power is greater than 5 kW. The method for manufacturing a semiconductor device according to claim 8 .

10. The ratio of the thickness of the first electrode layer to the thickness of the second electrode layer is changed based on the heating temperature. The method for manufacturing a semiconductor device according to claim 8 or 9.

11. The higher the heating temperature, the larger the ratio of the thickness of the second electrode layer to the thickness of the first electrode layer. The method for manufacturing a semiconductor device according to claim 10.

12. The heating temperature is 500° C. or less. A method for manufacturing a semiconductor device according to any one of claims 1 to 11.

13. The DC sputtering power is 0.5 kW or more. A method for manufacturing a semiconductor device according to any one of claims 1 to 12.

14. The unevenness of the upper surface of the metal electrode is equal to or less than half the thickness of the interlayer insulating film, The thickness of the metal electrode is 7.0 μm or less, The width of the contact hole is 1.5 μm or less. A method for manufacturing a semiconductor device according to any one of claims 1 to 13.

15. The unevenness of the upper surface of the metal electrode is 0.5 μm or less. The method for manufacturing a semiconductor device according to claim 14.

16. The thickness of the interlayer insulating film is 0.5 μm or more. The method for manufacturing a semiconductor device according to claim 14 or 15.

17. The metal electrode is a laminate of a first electrode layer and a second electrode layer. A method for manufacturing a semiconductor device according to any one of claims 14 to 16.

18. In the first sputtering step, the first electrode layer is formed at a position contacting at least the upper surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to any one of claims 1 to 17.

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