Signal processing device and program

Abstract

To provide a signal processor which determines an abnormality of an AD converter while reducing the total channel number.SOLUTION: A signal processor 301 AD-converts a sensor signal input from current sensors 71, 72, and 73 provided in three-phase current paths 81, 82, and 83, respectively connected to a connection point P of a closed circuit and outputs the converted sensor signal as a conversion signal. Two AD converters 31 and 32 separately provided from each other have at least one channel in which a sensor signal is input. An abnormality determination unit 40 calculates a total current value as the sum of three conversion signals for a current which travels into the connection point P or travels out of the connection point P for the conversion signals output from the AD converters 31 and 32, and determines that a channel in one of the AD converters is abnormal when the absolute value of the total current value is larger than a determination threshold value. The sum of the number of channels in which a sensor signal is input in the two AD converters 31 and 32 is 3 in the range of at least 3 and not larger than 5(=2×3-1).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a signal processing device and a program. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there is known a technique for detecting a failure in an AD converter in a signal processing device that performs AD conversion on an input signal.

[0003] For example, Patent Document 1 discloses a fault detection method in which the same analog signal is input redundantly to two independent AD converters, and if the digital data output by each AD converter is equal to each other, it is determined to be normal, and if it is not equal, it is determined to be abnormal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-151405 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, if the conventional technology of Patent Document 1 is applied to a signal processing device to which signals from current sensors provided in the current paths of each phase of a three-phase motor are input, a total of six channels are required because three-phase sensor signals are input to each of two AD converters. Generally, for N types of input signals, the conventional technology of Patent Document 1 requires a total of 2N channels, which increases the number of parts and wiring work.

[0006] The present invention was created in consideration of these points, and its purpose is to provide a signal processing device and a program that perform AD conversion on a sensor signal of a current flowing in and out of a connection point of a closed circuit, and that can determine abnormalities in the AD converter while reducing the total number of channels. [Means for solving the problem]

[0007] Original Clearly The signal processing device performs analog-to-digital conversion on a plurality of sensor signals input from current sensors (71, 72, 73) provided on N current paths (81, 82, 83) (N is an integer equal to or greater than 3) connected to a connection point (P) of the closed circuit, and outputs the converted signals. For example, phase current sensor signals are input to the signal processing device from current sensors provided on U-phase, V-phase, and W-phase current paths connected to the neutral point of a Y-connected three-phase motor.

[0008] This signal processing device is composed of two or more independent N AD converters (31, 32 、33 ) and an abnormality determination unit (40). Providing two or more AD converters that are independent of each other is a minimum prerequisite for ensuring reliability equal to or greater than that of the prior art of Patent Document 1. Each AD converter has at least one channel to which a sensor signal is input.

[0009] The abnormality determination unit calculates a total current value, which is the sum of N converted signals corresponding to the currents flowing in and out of the connection point, for the converted signals output by each AD converter, and when the absolute value of the total current value is greater than a determination threshold, determines that one of the channels of one of the AD converters is abnormal.

[0010] 2 or more N For AD converters with less than 1000, the total number of channels to which sensor signals are input is (N+1) or more (2N-1) or less At least one of the N types of sensor signals output from each current sensor is input to each AD converter. At least one type of sensor signal is input in common to two or more AD converters. do. The abnormality determination unit compares a plurality of current sum values ​​calculated from a plurality of combinations of the converted signals, and estimates the channel of the AD converter that is abnormal.

[0011] According to Kirchhoff's law, the sum of the currents flowing in and out of the connection point of a closed circuit is 0. Therefore, when the total current value, which is the sum of N converted signals, is greater than the judgment threshold, it can be determined that the converted signal of one of the channels of one of the AD converters is abnormal. The judgment threshold is set to the upper limit of the absolute value of the range that is considered to be substantially 0, taking into account variations in current detection and conversion. Bright is less than 2N in the prior art (N+1) or more (2N-1) or less It is possible to detect abnormalities in the AD converter using the total number of channels. This reduces the number of components and wiring work.

[0012] reference In an aspect, The present invention Two or more units that are independent of each other (N-1) AD converters (31, 3 2) The total number of channels to which sensor signals are input is N At least one type of sensor signal out of the N types of sensor signals output from the current sensors is input to each AD converter. The N types of sensor signals are input to two or more AD converters without overlapping.

[0013] The present invention also provides a signal processing device. Specific behavior to This provides the same effects as the signal processing device. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a configuration diagram of a motor drive system to which a signal processing device according to a first embodiment is applied. [Figure 2] FIG. 1 is a block diagram of a signal processing device according to a first embodiment. [Figure 3] 4 is a time chart showing a phase current sum value in a normal state; [Figure 4] 10 is a time chart (1) showing the sum of phase currents when an abnormality occurs in the Iw channel of the second AD converter. [Figure 5] 10 is a time chart (2) showing the sum of phase currents when an abnormality occurs in the Iw channel of the second AD converter. [Figure 6]4 is a flowchart of an AD converter abnormality determination process according to the first embodiment. [Figure 7] FIG. 10 is a block diagram of a signal processing device according to a second embodiment. [Figure 8] 10 is a flowchart of an AD converter abnormality determination process according to the second embodiment. [Figure 9] FIG. 10 is a block diagram of a signal processing device according to a third embodiment. [Figure 10] 10 is a flowchart of an AD converter abnormality determination process according to the third embodiment. [Figure 11] 11 is a sub-flowchart 1 of the discrimination process in FIG. 10 . [Figure 12] 11 is a sub-flowchart 2 of the discrimination process in FIG. 10 . [Figure 13] FIG. 10 is a block diagram of a signal processing device according to a fourth embodiment. [Figure 14] FIG. 10 is a block diagram of a signal processing device according to a fifth embodiment. [Figure 15] FIG. 13 is a block diagram of a signal processing device according to a sixth embodiment. [Figure 16] FIG. 10 is a block diagram of a signal processing device of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0015] A signal processing device and a program according to an embodiment of the present invention will be described with reference to the drawings. The following first to sixth embodiments will be collectively referred to as "the present embodiment." 1、 The fourth embodiment corresponds to a reference embodiment. The signal processing device of this embodiment is applied to a drive system for a three-phase motor. The signal processing device performs analog-to-digital conversion (hereinafter referred to as "AD conversion") on three types of sensor signals input from three current sensors provided in the current paths of each phase, and outputs the converted signals.

[0016] [System Configuration] First, with reference to Fig. 1, the overall configuration of a motor drive system 90 to which the signal processing device of each embodiment is applied will be described. Fig. 1 shows the configuration of a signal processing device 301 of the first embodiment as a representative example. For example, the motor drive system 90 is a system that drives a permanent magnet synchronous three-phase AC motor 80 used as the main motor of a hybrid vehicle. The motor drive system 90 converts DC power from a high-voltage battery 16 into three-phase AC power using an inverter 60, and drives the motor 80 by passing the three-phase AC current from the inverter 60 to the motor 80.

[0017] Inverter 60 has six upper and lower arm switching elements 61-66 bridge-connected. Specifically, switching elements 61, 62, and 63 are upper arm switching elements for U-phase, V-phase, and W-phase, respectively, and switching elements 64, 65, and 66 are lower arm switching elements for U-phase, V-phase, and W-phase, respectively. Switching elements 61-66 are formed, for example, by IGBTs, and freewheeling diodes that allow current to flow from the low potential side to the high potential side are connected in parallel.

[0018] Inverter 60 converts DC power into three-phase AC power by operating switching elements 61-66 in accordance with switching signals ("SW signals" in the figure) generated by inverter control device 50 of ECU 200, and passes the three-phase AC current through each of phase windings 81, 82, 83. A capacitor 16 is provided on the battery 16 side of inverter 60 to smooth the input voltage.

[0019] Current sensors 71, 72, and 73 are provided on current paths 81, 82, and 83 connected to windings of each phase of motor 80, respectively, and detect phase currents flowing through windings 81, 82, and 83. Current sensor 71 detects U-phase current Iu, current sensor 72 detects V-phase current Iv, and current sensor 73 detects W-phase current Iw. Each of current sensors 71, 72, and 73 outputs the detected current as sensor signals Iu, Iv, and Iw to signal processing device 301 of ECU 200. In this embodiment, it is assumed that current sensors 71, 72, and 73 are normal.

[0020] For example, in a Y-connected three-phase motor 80, current paths 81, 82, and 83 of each phase are connected to a neutral point P, which is a connection point of the closed circuit. According to Kirchhoff's law, the sum of the currents flowing in and out of the connection point P of the closed circuit is zero. In other words, the relationship "Iu+Iv+Iw=0" holds for the sensor signals Iu, Iv, and Iw of the three current sensors 71, 72, and 73 provided respectively on the three current paths 81, 82, and 83 connected to the connection point P of the closed circuit.

[0021] The ECU 200 includes a signal processing device 301 and an inverter control device 50, and operates on power supplied from an ECU power supply 12 of approximately 12 V. For example, the signal processing device 301 of the first embodiment includes two AD converters 31 and 32 and an abnormality determination unit 40. The abnormality determination unit 40 and the inverter control device 50 of the signal processing device 301 are configured with a microcomputer or the like, and internally include a CPU, ROM, RAM, I / O, and bus lines connecting these components (not shown). The microcomputer executes software processing by running a pre-stored program in the CPU, and performs control through hardware processing using a dedicated electronic circuit.

[0022] In the first embodiment, the two AD converters 31 and 32 are provided independently of each other and have at least one channel to which the sensor signals Iu, Iv, and Iw are input. In the drawings, the first AD converter 31 is referred to as "ADC1" and the second AD converter 32 is referred to as "ADC2." The AD converters 31 and 32 convert the sensor signals Iu, Iv, and Iw input from the current sensors 71, 72, and 73 into AD signals, and output the converted signals CIu1, CIv1, and CIw2.

[0023] In the fourth to sixth embodiments, the number of mutually independent AD converters is 3. Furthermore, the number of channels to which the sensor signals Iu, Iv, and Iw are input in each AD converter, i.e., the number of converted signals output from each channel, differs depending on the embodiment.

[0024] The abnormality determination unit 40 determines whether there is an abnormality in the AD converters 31, 32. The determination method will be described later. If the abnormality determination unit 40 determines that there is an abnormality in either of the AD converters 31, 32, it sends an abnormality signal to the inverter control device 50.

[0025] The inverter control device 50 acquires the phase current conversion signals CIu1, CIv1, and CIw2 from the signal processing device 301. The inverter control device 50 also receives the rotation angle θ of the motor 80 from a rotation angle sensor (not shown), and receives a torque command Trq from a higher-level vehicle control circuit. * are input. Based on this information, the inverter control device 50 controls the operation of the inverter 60, for example, by current feedback control. Furthermore, when an abnormality signal is sent from the abnormality determination unit 40, the inverter control device 50 takes measures to deal with the abnormality depending on the situation.

[0026] Regarding abnormality detection for AD converters, for example, Patent Document 1 (Japanese Patent Laid-Open Publication No. 2000-151405) discloses a method of redundantly inputting the same analog signal to two independent AD converters and comparing the digital data output by each AD converter to detect abnormalities. Fig. 16 shows, as a comparative example, a configuration in which this conventional technology is applied to a signal processing device to which three-phase current sensor signals Iu, Iv, and Iw are input.

[0027] In the signal processing device 309 of the comparative example, three-phase sensor signals Iu, Iv, and Iw are input to two three-channel AD converters 31 and 32. The first AD converter 31 outputs converted signals CIu1, CIv1, and CIw1, and the second AD converter 32 outputs converted signals CIu2, CIv2, and CIw2.

[0028] The abnormality determination unit 49 of the comparative example compares the converted signals of the two AD converters 31, 32 for each sensor signal, and determines that an abnormality has occurred if the difference between the converted signals is greater than the determination threshold Dth. That is, when |CIu1-CIu2|>Dth, or |CIv1-CIv2|>Dth, or |CIw1-CIw2|>Dth, it determines that one of the two AD converters 31, 32 is abnormal. Note that the determination threshold Dth is set to a value that is regarded as substantially zero, taking into account variations in current detection and conversion.

[0029] In the signal processing device 309 of the comparative example, a total of six channels are required for the two AD converters 31 and 32. Generally, for N types of input signals, a total of 2N channels are required in the signal processing device 309 of the comparative example, which increases the number of components and the amount of wiring work.

[0030] Therefore, the signal processing device of this embodiment aims to determine abnormalities in the AD converters while reducing the total number of channels of two or three AD converters. In this embodiment, the main failure mode of the AD converter is assumed to be a failure in which the conversion signal becomes fixed on one channel of one AD converter during normal operation. For example, an abnormality in which the power supply of the AD converter is not turned on and the conversion signals of all channels become 0 is assumed to have been detected at the initial check stage, etc. Each embodiment will be explained below.

[0031] (First embodiment) Fig. 2 simply shows only the configuration related to abnormality determination of AD converters 31 and 32 in signal processing device 301 of the first embodiment. Compared to Fig. 1, the output of converted signals CIu1, CIv1, and CIw2 from each AD converter 31 and 32 to inverter control device 50 is omitted. Block diagrams of each signal processing device of the second to sixth embodiments are shown in accordance with Fig. 2.

[0032] Generally speaking, in a signal processing device, N types of sensor signals from N current sensors (N is an integer of 3 or greater) are input to a total of N to (2N-1) channels of 2 to N AD converters. At least one type of sensor signal out of the N types of sensor signals output from each current sensor is input to each AD converter. In other words, there is no AD converter to which a sensor signal is not input.

[0033] In the first embodiment, sensor signals from N current sensors are input to a total of N channels of two AD converters. When N=3, sensor signals from three current sensors 71, 72, and 73 are input to a total of three channels of two AD converters 31 and 32.

[0034] 2, the first AD converter 31 has two channels through which sensor signals are input, and the second AD converter 32 has one channel through which a sensor signal is input. The total number of channels through which sensor signals are input in the two AD converters 31 and 32 is 3, i.e., N.

[0035] The first AD converter 31 receives the U-phase sensor signal Iu and the V-phase sensor signal Iv and outputs converted signals CIu1 and CIv1. The second AD converter 32 receives the W-phase sensor signal Iw and outputs a converted signal CIw2. The three types of sensor signals Iu, Iv, and Iw are input separately to the two AD converters 31 and 32 without overlapping.

[0036] The abnormality determination unit 40 calculates a "sum current value" which is the sum of three converted signals CIu1, CIv1, CIw2 corresponding to the currents flowing in and out of the connection point P for the converted signals output by the AD converters 31, 32. In particular, in this embodiment, the currents detected by the current sensors 71, 72, 73 are called "sum phase current values" because they are phase currents of a three-phase motor. The abnormality determination unit 40 determines whether the AD converters 31, 32 are abnormal based on the sum phase current values ​​using logic described below. The sum phase current values ​​themselves are voltage signals.

[0037] The time charts in Figures 3 to 5 show the time-dependent changes in the conversion signals CIu1, CIv1, and CIw2 and the phase current sum value S. In the normal state shown in Figure 3, after AD conversion is completed, conversion signals CIu1, CIv1, and CIw2 with sinusoidal waveforms that are 120 degrees out of phase with each other are output. Strictly speaking, the conversion signals are discrete values, but they are illustrated as continuous sinusoidal waveforms, assuming that the conversion period is sufficiently short compared to one electrical period.

[0038] A judgment threshold value Sth close to 0 is set for the phase current sum value S. The range of ±Sth corresponds to a range that is regarded as substantially 0, taking into account detection variations of the current sensors 71, 72, 73 and conversion variations of the AD converters 31, 32. According to Kirchhoff's law, the absolute value |CIu1+CIv1+CIw2| of the phase current sum value S in a normal state is equal to or less than the judgment threshold value Sth, i.e., substantially 0. When the absolute value |CIu1+CIv1+CIw2| of the phase current sum value S is greater than the judgment threshold value Sth, the abnormality judgment unit 40 judges that one of the two AD converters 31, 32 is abnormal.

[0039] Figure 4 shows a case where an abnormality occurs in the converted signal CIw2 due to a failure of the second AD converter 32. The thin dotted line represents the converted signal CIw2 under normal conditions. After the abnormality occurs, the converted signal CIw2 remains constant at the value C(α) of α at the time of the abnormality, as shown by the thick dashed line. The sum of the phase currents S is the sum of the two normal converted signals CIu1 and CIv1 plus C(α). Since the sum of the two normal converted signals CIu1 and CIv1 is equal to "-CIw2," which is the inverse of the normal converted signal CIw2, the sum of the phase currents S after the abnormality occurs is an offset sine wave with an opposite phase to the normal converted signal CIw2. If an abnormality occurs at timing α near the peak of the converted signal CIv2, the absolute value |CIu1 + CIv1 + CIw2| of the sum of the phase currents S after the abnormality occurs is always greater than the determination threshold Sth, clearly indicating an abnormality.

[0040] FIG. 5 illustrates a case in which an abnormality occurs in the converted signal CIw2 due to a failure of the second AD converter 32 at a different timing than that shown in FIG. 4 . If the abnormality occurs at timing β near the zero crossing of the converted signal CIv2, i.e., if the value C(β) of the converted signal CIv2 at time β is close to 0, the sum of the phase currents S after the abnormality occurs fluctuates across zero. As a result, even after the abnormality occurs, a period ε occurs during one electrical cycle during which the absolute value |CIu1+CIv1+CIw2| of the sum of the phase currents S is equal to or less than the determination threshold value Sth. Therefore, the abnormality determination unit 40 calculates the sum of the phase currents S multiple times during one electrical cycle after the absolute value |CIu1+CIv1+CIw2| of the sum of the phase currents S exceeds the determination threshold value Sth. The abnormality determination unit 40 then determines the abnormality based on the determination logic described below.

[0041] The flowchart in Figure 6 shows the AD converter abnormality determination process according to the first embodiment. The conversion signal acquisition period, number of times, and determination logic are examples, and other determination logic may be used. The symbol "S" in the flowchart indicates a step. The flowchart in Figure 6 also shows a program that causes the abnormality determination unit 40 to operate so as to execute predetermined steps in the signal processing device 301. The flowcharts of the second and third embodiments can be interpreted in the same way.

[0042] In S11, the abnormality determination unit 40 acquires the converted signals CIu1 and CIv1 from the first AD converter 31, and acquires the converted signal CIw2 from the second AD converter 32. Each converted signal is acquired a predetermined number of times or more during one electrical cycle, over a period of one electrical cycle or more. In S12, the abnormality determination unit 40 calculates the phase current sum value S each time the converted signals CIu1, CIv1, and CIw2 are acquired.

[0043] In S13, it is determined whether the absolute value |CIu1+CIv1+CIw2| of the phase current sum S is equal to or less than the determination threshold value Sth. As described above, the determination threshold value Sth is set to the upper limit of the range of absolute values ​​that are regarded as substantially 0, taking into account variations in current detection and conversion.

[0044] 5, even if the conversion signal CIw2 is abnormal, there will be a period in which the absolute value |CIu1+CIv1+CIw2| of the phase current sum S is equal to or less than the determination threshold value Sth, depending on the timing of the abnormality occurrence. Therefore, a determination logic is required to prevent erroneous determination. For example, the abnormality determination unit 40 determines whether the number of times that the absolute value |CIu1+CIv1+CIw2| of the phase current sum S is equal to or less than the determination threshold value Sth is equal to or greater than a predetermined ratio during one electrical cycle.

[0045] Alternatively, the sensor signals Iu, Iv, and Iw may be filtered to remove noise, and then the absolute value of the phase current sum S may be evaluated after confirming that the maximum and minimum values ​​of each conversion signal within one electrical cycle exceed a threshold, i.e., that a sinusoidal fluctuation is occurring. Alternatively, a sinusoidal fluctuation may be confirmed based on the time change rate of each conversion signal. Depending on the determination logic, it may be possible to determine that an abnormality has occurred before one electrical cycle has elapsed since the occurrence of the abnormality. The step of comparing the absolute value of the phase current sum S with the determination threshold Sth in the flowcharts of the second and third embodiments is executed based on such a determination logic.

[0046] If the answer is YES in S13, it is determined in S14 that the Iu channel and Iv channel of the first AD converter 31 and the Iw channel of the second AD converter 32 are normal. In S14, "ADC1_UV: normal" means that both the Iu channel and the Iv channel of the first AD converter 31 are normal. In other words, if multiple channels are normal, the "and" in "UandV" is omitted.

[0047] If the result in S13 is NO, then in S15 it is determined that either the Iu channel or the Iv channel of the first AD converter 31 or the Iw channel of the second AD converter 32 is abnormal. In S15, "ADC1_UorV: abnormal" means that either the Iu channel or the Iv channel of the first AD converter 31 is abnormal. In other words, if any one of multiple channels is abnormal, "or" is indicated. The normal / abnormal notation in S14 and S15 is applied mutatis mutandis to the flowcharts of the second and third embodiments.

[0048] As described above, the signal processing device 301 of the first embodiment utilizes the fact that Kirchhoff's law holds true for the three-phase current conversion signals CIu1, CIv1, and CIv2, and can determine abnormalities in the AD converters 31 and 32 using a total of three channels. In other words, it is possible to determine abnormalities in the AD converters 31 and 32 using a total of fewer channels than the signal processing device 309 of the comparative example, thereby reducing the number of components and wiring man-hours.

[0049] Incidentally, Japanese Patent Laid-Open Publication No. 6-253585 (hereinafter referred to as the "Reference Document") discloses an abnormality detection device for detecting an abnormality based on the sum of the output values ​​of a three-phase current sensor that detects the current of a three-phase motor winding. However, the abnormality detection device in the Reference Document detects an abnormality in the current sensor, and makes no mention of an AD converter.

[0050] In contrast, the signal processing device of this embodiment is equipped with two or three AD converters that are installed independently of each other, from the viewpoint of ensuring the reliability of the AD converters, and determines whether an abnormality in the AD converters occurs on the assumption that the current sensors are normal. If the technology of the reference document is simply applied to determining an abnormality in an AD converter, one AD converter is sufficient, and there is no need to install two or three AD converters independently of each other. The signal processing device of this embodiment is characterized by its ability to determine an abnormality in an AD converter while reducing the total number of channels in a configuration equipped with multiple AD converters.

[0051] (Second embodiment) Next, a signal processing device 302 according to a second embodiment will be described with reference to Fig. 7 and Fig. 8. In the second embodiment, sensor signals from N current sensors are input to a total of (N+1) channels of two AD converters. When N=3, sensor signals from three current sensors 71, 72, and 73 are input to a total of four channels of two AD converters 31 and 32.

[0052] 7, the first AD converter 31 has three channels through which sensor signals are input, and the second AD converter 32 has one channel through which a sensor signal is input. In the two AD converters 31 and 32, the total number of channels through which sensor signals are input is four, i.e., (N+1).

[0053] The first AD converter 31 receives the U-phase sensor signal Iu, the V-phase sensor signal Iv, and the W-phase sensor signal Iw, and outputs converted signals CIu1, CIv1, and CIw1. The second AD converter 32 receives the W-phase sensor signal Iw, and outputs a converted signal CIw2. In other words, the W-phase sensor signal Iw is input to both AD converters as a single type of sensor signal.

[0054] 8 shows the AD converter abnormality determination process according to the second embodiment. In S21, the abnormality determination unit 40 obtains the converted signals CIu1, CIv1, and CIw1 from the first AD converter 31, and obtains the converted signal CIw2 from the second AD converter 32. In S22, the abnormality determination unit 40 uses the converted signals CIu1 and CIv1 of the U-phase and V-phase sensor signals Iu and Iv in common, and swaps only the converted signals CIw1 and CIw2 of the W-phase sensor signal Iw, to calculate two phase current sum values ​​S.

[0055] In S23, it is determined whether the absolute value |CIu1+CIv1+CIw1| of the phase current sum S is equal to or less than the determination threshold value Sth. If the answer is YES in S23, it is determined in S24, and if the answer is NO in S23, it is determined in S25, whether the absolute value |CIu1+CIv1+CIw2| of the phase current sum S is equal to or less than the determination threshold value Sth.

[0056] If S24 is YES, then in S26 it is determined that all channels of the first AD converter 31 and the second AD converter 32 are normal. If S24 is NO, then in S27 it is determined that all channels of the first AD converter 31 are normal, and that the Iw channel of the second AD converter 32 is abnormal. If S25 is YES, then in S28 it is determined that the Iw channel of the first AD converter 31 is abnormal, and that the Iw channel of the second AD converter 32 is normal. Note that the fact that the Iu channel and Iv channel of the first AD converter 31 are normal, other than the abnormal Iw channel, is omitted from the description.

[0057] If the answer is NO in S25, consider the following. Assuming that simultaneous failures of the two AD converters 31 and 32 are possible, it is also possible that the converted signals CIu1 and CIv1 commonly included in the phase current sum S are normal, while the converted signals CIw1 and CIw2 added together are both abnormal. However, in reality, the probability of the two AD converters 31 and 32 failing simultaneously is extremely low, almost zero. Therefore, this abnormality determination process is based on the premise that "an abnormality occurs in only one channel." This leads to the conclusion that either the converted signals CIu1 or CIv1 commonly included in the phase current sum S is abnormal.

[0058] Therefore, if the answer is NO in S25, it is determined in S29 that either the Iu channel or the Iv channel of the first AD converter 31 is abnormal and that the Iw channel of the second AD converter 32 is normal. It is not possible to determine whether the Iu channel or the Iv channel of the first AD converter 31 is abnormal.

[0059] That is, when an abnormality occurs in the channel of the W-phase sensor signal Iw input in common to two AD converters, it is possible to identify that the Iw channel of the first AD converter 31 or the second AD converter 32 is abnormal. When an abnormality occurs in the channel to which the non-common sensor signals Iu and Iv are input, it is possible to identify that the abnormality is at least in the first AD converter 31.

[0060] The abnormality determination unit 40 narrowing down the range of abnormal channels to some extent is expressed as "estimating the channel of the AD converter that is abnormal." In the AD converter abnormality determination process according to the second embodiment, the channel of the AD converter that is abnormal can be estimated by comparing multiple phase current sum values ​​S calculated from multiple combinations of conversion signals.

[0061] (Third embodiment) Next, a signal processing device 303 according to a third embodiment will be described with reference to Figures 9 to 12. In the third embodiment, sensor signals from N current sensors are input to a total of (2N-1) channels of two AD converters. When N=3, sensor signals from three current sensors 71, 72, and 73 are input to a total of five channels of two AD converters 31 and 32.

[0062] 9, the first AD converter 31 has three channels to which sensor signals are input, and the second AD converter 32 has two channels to which sensor signals are input. In the two AD converters 31 and 32, the total number of channels to which sensor signals are input is five, that is, (2N-1).

[0063] The first AD converter 31 receives the U-phase sensor signal Iu, the V-phase sensor signal Iv, and the W-phase sensor signal Iw, and outputs converted signals CIu1, CIv1, and CIw1. The second AD converter 32 receives the V-phase sensor signal Iv and the W-phase sensor signal Iw, and outputs converted signals CIv2 and CIw2. In other words, the two types of sensor signals, the V-phase sensor signal Iv and the W-phase sensor signal Iw, are input in common to two AD converters.

[0064] 10 shows the AD converter abnormality determination process according to the third embodiment. In S31, the abnormality determination unit 40 obtains converted signals CIu1, CIv1, and CIw1 from the first AD converter 31, and obtains converted signals CIu2 and CIw2 from the second AD converter 32. In S32, the abnormality determination unit 40 uses the converted signal CIu1 of the U-phase sensor signal Iu in common, and interchanges the converted signals CIv1 and CIv2 of the V-phase sensor signal Iv and the converted signals CIw1 and CIw2 of the W-phase sensor signal Iw to calculate two phase current sum values ​​S.

[0065] In S33, it is determined whether the absolute value |CIu1+CIv1+CIw1| of the phase current sum S is equal to or less than the determination threshold value Sth. If the answer is YES in S33, it is determined in S34, and if the answer is NO in S33, it is determined in S35, whether the absolute value |CIu1+CIv2+CIw2| of the phase current sum S is equal to or less than the determination threshold value Sth.

[0066] If the answer is YES in S34, it is determined in S36 that all channels of the first AD converter 31 and the second AD converter 32 are normal. If the answer is NO in S34, it is determined in S37 that all channels of the first AD converter 31 are normal, and that the Iv channel or Iw channel of the second AD converter 32 is abnormal. Then, the process proceeds to the determination process of S37A.

[0067] If the answer is YES in S35, it is determined in S38 that the Iv channel or the Iw channel of the first AD converter 31 is abnormal, and that the Iv channel and the Iw channel of the second AD converter 32 are normal. Then, the process proceeds to the determination process in S38A. If the answer is NO in S35, the abnormality determination is made on the premise that "an abnormality occurs in only one channel." Therefore, if the answer is NO in S35, it is determined in S39 that the Iu channel of the first AD converter 31 is abnormal, and that the Iv channel and the Iw channel of the AD converter 31 and the second AD converter 32 are normal.

[0068] A sub-flowchart of S37A is shown in Figure 11. In S371, the results of YES in S33 and NO in S34 are recorded for confirmation. In S372, the converted signals Cw1 and Cw2 in the two phase current sum values ​​S in S371 are swapped, and two more phase current sum values ​​S are calculated.

[0069] In S373, it is determined whether the absolute value |CIu1+CIv1+CIw2| of the phase current sum S is equal to or less than the determination threshold Sth and whether |CIu1+CIv2+CIw1| is greater than the determination threshold Sth. If the answer is NO in S373, conversely, in S374 it is determined whether the absolute value |CIu1+CIv1+CIw2| of the phase current sum S is greater than the determination threshold Sth and whether |CIu1+CIv2+CIw1| is equal to or less than the determination threshold Sth. Logically, either S373 or S374 should be YES and the other should be NO.

[0070] If the answer is YES in S373, it is considered that the converted signal CIv2 enclosed by the two-dot chain line is abnormal. In other words, it is determined that the Iv channel of the second AD converter 32 is abnormal and the Iw channel is normal. If the answer is YES in S374, it is considered that the converted signal CIw2 enclosed by the two-dot chain line is abnormal. In other words, it is determined that the Iv channel of the second AD converter 32 is normal and the Iw channel is abnormal. In this way, the abnormal channel of the second AD converter 32 is identified in the determination process of S37A. Note that instead of executing the main flow of FIG. 10 and the determination process of FIG. 11 in two stages, a logic may be used in which four different phase current sum values ​​S are calculated from the beginning and then a determination is made.

[0071] Fig. 12 shows a sub-flowchart of the determination process of S38A. S381 to S386 are similar to S371 to S376 in Fig. 11, and therefore description thereof will be omitted. In the determination process of S38A, an abnormal channel is identified from the Iv channel or the Iw channel of the first AD converter 31.

[0072] In the AD converter abnormality determination process according to the third embodiment, by comparing multiple phase current sum values ​​S calculated from multiple combinations of conversion signals, it is possible to estimate the abnormal AD converter channel and identify abnormalities in all five channels.

[0073] (Fourth, fifth, and sixth embodiments) Next, with reference to Figures 13 to 15, fourth to sixth embodiments will be described in which the signal processing device includes three AD converters 31, 32, and 33, the same number as the current sensors 71, 72, and 73. In the figures, the third AD converter 33 is referred to as "ADC3." In the fourth to sixth embodiments, sensor signals from N current sensors are input to a total of N to (2N-1) channels of the N AD converters. When N=3, sensor signals from the three current sensors 71, 72, and 73 are input to a total of 3 to 5 channels of the three AD converters 31, 32, and 33.

[0074] In the fourth to sixth embodiments, a total of N sensor signals, each of which is one of N types, are divided and input to N AD converters. When N=3, a total of three sensor signals Iu, Iv, and Iw, each of which is one of three types, are divided and input to three AD converters 31, 32, and 33.

[0075] 13, the first AD converter 31, the second AD converter 32, and the third AD converter 33 each have one channel to which a sensor signal is input. In the three AD converters 31, 32, and 33, the total number of channels to which sensor signals are input is 3, i.e., N.

[0076] The first AD converter 31 receives the U-phase sensor signal Iu and outputs a converted signal CIu1. The second AD converter 32 receives the V-phase sensor signal Iv and outputs a converted signal CIv2. The third AD converter 33 receives the W-phase sensor signal Iw and outputs a converted signal CIw3. The three types of sensor signals Iu, Iv, and Iw are input separately to the three AD converters 31, 32, and 33 without overlapping.

[0077] When the absolute value |CIu1+CIv2+CIw3| of the phase current sum value S is greater than the determination threshold value Sth, the abnormality determination unit 40 determines that one of the three AD converters 31, 32, 33 is abnormal. It is not possible to identify which AD converter is abnormal.

[0078] In the signal processing device 301 of the first embodiment, the first AD converter 31 sequentially AD-converts the input U-phase sensor signal Iu and V-phase sensor signal Iv. Because simultaneous AD conversion is not possible, a sample-and-hold circuit and a multiplexer circuit are required within the AD converter. In contrast, in the signal processing device 304 of the fourth embodiment, the three-phase sensor signals Iu, Iv, and Iw can be AD-converted simultaneously by three AD converters 31, 32, and 33, which simplifies the configuration within the AD converter and shortens the time required to detect an abnormality.

[0079] 14 is a combination of the fourth and second embodiments. The first AD converter 31 has two channels to which sensor signals are input, and the second AD converter 32 and the third AD converter 33 each have one channel to which sensor signals are input. The total number of channels to which sensor signals are input in the three AD converters 31, 32, and 33 is four, that is, (N+1).

[0080] The first AD converter 31 receives the U-phase sensor signal Iu and the W-phase sensor signal Iw and outputs conversion signals CIu1 and CIw1. The second AD converter 32 receives the V-phase sensor signal Iv and outputs a conversion signal CIv2. The third AD converter 33 receives the W-phase sensor signal Iw and outputs a conversion signal CIw3. In other words, the W-phase sensor signal Iw is input in common to two AD converters. Since the same type of sensor signal is not input to the same AD converter, the second W-phase sensor signal Iw is input to one of the two AD converters other than the AD converter to which the first W-phase sensor signal Iw was input.

[0081] The abnormality determination unit 40 determines whether or not an abnormality exists based on the absolute values ​​|CIu1+CIv2+CIw3| and |CIu1+CIv2+CIw1| of the two phase current summation values ​​S. When the absolute value of one or both of the phase current summation values ​​S is greater than the determination threshold value Sth, the abnormality determination unit 40 classifies the channel of each AD converter as normal or abnormal by the same process as in Fig. 8. Therefore, in the fifth embodiment, in addition to shortening the abnormality detection time, it is possible to estimate the AD converter channel that is abnormal.

[0082] 15 is a combination of the fourth and third embodiments. The first AD converter 31 and the second AD converter 32 each have two channels to which sensor signals are input, and the third AD converter 33 has one channel to which a sensor signal is input. In the three AD converters 31, 32, and 33, the total number of channels to which sensor signals are input is five, or (2N-1).

[0083] The first AD converter 31 receives the U-phase sensor signal Iu and the V-phase sensor signal Iv and outputs converted signals CIu1 and CIv1. The second AD converter 32 receives the V-phase sensor signal Iv and the W-phase sensor signal Iw and outputs converted signals CIv2 and CIw2. The third AD converter 33 receives the W-phase sensor signal Iw and outputs converted signal CIw3. That is, the V-phase sensor signal Iv and the W-phase sensor signal Iw are each input to two AD converters in common.

[0084] The abnormality determination unit 40 determines whether or not an abnormality exists based on, for example, the absolute values ​​|CIu1+CIv2+CIw3| and |CIu1+CIv1+CIw2| of two different phase current sum values ​​S. When the absolute value of one or both of the phase current sum values ​​S is greater than the determination threshold value Sth, the abnormality determination unit 40 classifies the channel of each AD converter as normal or abnormal by the same processing as in FIGS. 10 to 12. Therefore, in the sixth embodiment, in addition to shortening the abnormality detection time, it is possible to identify the AD converter channel that is abnormal.

[0085] (Other embodiments) (a) When a current sensor is provided in a phase current path of a polyphase motor, it is not limited to a three-phase motor, and may be provided in a phase current path of a motor with four or more phases. In the case of an N-phase motor (N is an integer equal to or greater than 3), N current paths are connected to the connection points of the closed circuit. For example, when N=4, the total number of channels to which sensor signals are input is 4, 5, 6, or 7. Furthermore, the signal processing device of the present invention is not limited to motor drive systems, but can be applied to any system having connection points of a closed circuit to which Kirchhoff's law can be applied.

[0086] (b) For the configurations illustrated in the drawings of each embodiment, by changing the order of the three phases of the sensor signal and the two or three AD converters, multiple equivalent configurations can be obtained. For example, in the first embodiment, one of the two AD converters 31, 32 is a single channel, and one of the three-phase sensor signals Iu, Iv, or Iw is input to that single channel, so there are six possible configurations. The second and third embodiments also have six possible configurations.

[0087] In the fourth embodiment, there are 3P3 = 6 combinations due to the permutation of the three phases. In the fifth embodiment, one phase of the sensor signal is input in duplicate for each pattern in the fourth embodiment. Since cases where the same type of sensor signal is input to the same AD converter are excluded, the second duplicate sensor signal is input to one of the two AD converters other than the AD converter to which the first sensor signal was input. Therefore, there are 6 × 3 × 2 = 36 combinations. In the sixth embodiment, two types of sensor signals are input to two of the three AD converters 31, 32, and 33, and one type of sensor signal is input to one AD converter. Although the calculation method is omitted, there are 72 combinations.

[0088] As described above, the present invention is not limited to the above-described embodiment, and can be implemented in various forms without departing from the spirit of the present invention.

[0089] The abnormality determination unit and method described herein may be implemented by a special-purpose computer configured by configuring a processor and memory programmed to execute one or more functions embodied in a computer program. Alternatively, the abnormality determination unit and method described herein may be implemented by a special-purpose computer configured by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the abnormality determination unit and method described herein may be implemented by one or more special-purpose computers configured by combining a processor and memory programmed to execute one or more functions with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory tangible storage medium. [Explanation of symbols]

[0090] 301-306 ···Signal processing device, 31, 32, 33 AD converter, 40...Abnormality determination unit, 71, 72, 73... Current sensor, 81, 82, 83... (phase) current paths.

Claims

1. A signal processing device that performs analog-to-digital conversion on a plurality of sensor signals input from current sensors (71, 72, 73) provided on N current paths (81, 82, 83) (N is an integer of 3 or more) connected to a connection point (P) of a closed circuit, and outputs the converted signals, Two or more and N or less AD converters (31, 32, 33) provided independently of each other and having at least one channel to which the sensor signal is input; an abnormality determination unit (40) that calculates a total current value, which is the sum of N of the converted signals corresponding to the currents flowing in and out of the connection point, for the converted signals output from each of the AD converters, and determines that any channel of any of the AD converters is abnormal when the absolute value of the total current value is greater than a determination threshold value; Equipped with In the two or more and N or less AD converters, the total number of channels to which the sensor signals are input is (N+1) or more and (2N-1) or less, At least one type of sensor signal among the N types of sensor signals output from each of the current sensors is input to each of the AD converters, and at least one type of sensor signal is input in common to two or more of the AD converters; The abnormality determination unit is a signal processing device that compares a plurality of the current sum values ​​calculated from a plurality of combinations of the converted signals and estimates which channel of the AD converter is abnormal.

2. The present invention is applied to a motor drive system (90) that drives a motor (80) by passing a polyphase AC current from an inverter (60) to the motor, The signal processing device according to claim 1 , wherein the current sensor detects a phase current flowing through a current path connected to each phase winding of the motor.

3. A program for a signal processing device that performs analog-to-digital conversion on a plurality of sensor signals input from current sensors (71, 72, 73) provided on N current paths (81, 82, 83) (N is an integer of 3 or more) connected to a connection point (P) in a closed circuit, and outputs the converted signals, The signal processing device includes: Two or more and N or less AD converters (31, 32, 33) are provided independently of each other, each having at least one channel to which the sensor signal is input, In the two or more and N or less AD converters, the total number of channels to which the sensor signals are input is (N+1) or more and (2N-1) or less, At least one type of sensor signal among the N types of sensor signals output from each of the current sensors is input to each of the AD converters, and at least one type of sensor signal is input in common to two or more of the AD converters, The signal processing device includes: A program that calculates a total current value, which is the sum of N conversion signals corresponding to the currents flowing in and out of the connection point, for the conversion signals output by each of the AD converters, and determines that one of the AD converters is abnormal when the absolute value of the total current value is greater than a judgment threshold, compares multiple total current values ​​calculated from multiple combinations of the conversion signals, and estimates the channel of the AD converter that is abnormal.

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