Wiring board and method for manufacturing the same

Abstract

To provide a wiring board and a manufacturing method thereof that can improve the reliability by improving the adhesion during heating, and secure the electrical characteristics and line insulation reliability of fine wiring in a manufacturing method of forming a fine wiring layer on a support board and mounting the wiring layer on an FC-BGA board.SOLUTION: There is provided a wiring board including at least a via layer on which vias are formed and a trench layer formed of lands and wiring on the via layer, in which taper angles of at least one set of forming patterns of vias, lands, and wirings are different, or provided a multi-layer wiring board in which at least one layer is composed of the wiring board.SELECTED DRAWING: Figure 28

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] In recent years, with the advancement of high speed and high integration of semiconductor devices, there is a demand for narrower pitches for connection terminals to semiconductor elements and finer board wiring for FC-BGA (Flip Chip-Ball Grid Array) wiring boards. On the other hand, there is a demand for connection between FC-BGA wiring boards and motherboards using connection terminals with almost the same pitch as before. To narrow the pitch of the connection terminals with the semiconductor elements and to miniaturize the board wiring, a method is known in which wiring is formed on silicon to serve as a substrate (silicon interposer) for connecting the semiconductor elements to an FC-BGA wiring board.

[0003] Silicon interposers are manufactured using silicon wafers with equipment for semiconductor front-end processing. Silicon wafers have limitations on their shape and size, and the number of interposers that can be manufactured from a single wafer is limited. In addition, the manufacturing equipment is expensive, so the interposers are also expensive. In addition, because silicon wafers are semiconductors, there is the problem of degradation of transmission characteristics.

[0004] Furthermore, Patent Document 1 discloses a method in which the surface of an FC-BGA wiring substrate is planarized by CMP (Chemical Mechanical Polishing) or the like, and then fine wiring is formed.

[0005] However, in the method of flattening the surface of the FC-BGA wiring substrate using CMP or other methods and then forming a fine wiring layer on top of that, although the degradation of transmission characteristics seen in silicon interposers is small, there are problems with reduced yield within the same substrate due to manufacturing defects in the FC-BGA wiring substrate combined with defects during the highly difficult fine wiring formation, and there are cases where delamination (peeling) occurs at the interface between the resin in the trench layer and the resin in the via layer due to thermal warping during mounting. Furthermore, it is necessary to ensure the electrical characteristics and inter-wire insulation reliability of the fine wiring layer.

[0006] Patent Document 2 discloses a method of forming a fine wiring layer on a support substrate, mounting it on an FC-BGA wiring substrate, and then peeling off the support substrate to form a narrow-pitch wiring substrate.

[0007] However, this technique has the problem that the adhesion of the interlayer connections in the fine wiring layers mounted on the FC-BGA wiring board is poor, and the electrical characteristics and inter-wire insulation reliability are insufficient. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-225671 [Patent Document 2] International Publication No. 2018 / 047861 Summary of the Invention [Problem to be solved by the invention]

[0009] The present invention has been made in consideration of the above problems, Multilayer with support that can precisely form microstructures An object of the present invention is to provide a wiring board. Another object of the present invention is to provide a multilayer wiring board with a support that can prevent short circuits between electrodes for bonding to an FC-BGA substrate and at the same time prevent delamination between the lands and the insulating resin that fills the surrounding area. [Means for solving the problem]

[0010] As a means for solving the above problem, the invention described in claim 1 of the present invention provides: A multilayer wiring board with a support body, having a structure in which a multilayer wiring board is laminated on at least one main surface of a plate-shaped support body, The multilayer wiring board is a via layer in which a plurality of vias are formed in an insulating resin; At least one or more trench layers each having a plurality of lands and a plurality of wirings formed in an insulating resin are alternately formed on the via layer; The vias in the via layer contact the lands in the trench layer, thereby forming an electrical interlayer connection between the trench layers. Characterized by With support It is a multilayer wiring board.

[0011] The invention described in claim 2 is as follows: 2. The multilayer wiring board with a support body according to claim 1, The multilayer wiring board is The multilayer wiring board has electrodes for bonding to an FC-BGA substrate formed on the via layers and the trench layers that are alternately formed, The taper angle of the side surface of the electrode for bonding to the FC-BGA substrate is larger than the taper angle of the land of the trench layer. Characterized by With support It is a multilayer wiring board. [Effects of the Invention]

[0015] According to the wiring board of the present invention, Multilayer with support that can precisely form microstructures by processing on a strong support A wiring board can be provided. Furthermore, by raising the sides of the electrodes for bonding to the FC-BGA substrate, it is possible to prevent short circuits between the electrodes for bonding, and at the same time, by laying the sides of the lands flat to increase the contact area between the lands and the insulating resin that fills the surrounding area, it is possible to provide a multilayer wiring board with a support that can prevent delamination between the lands and the insulating resin that fills the surrounding area. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 2 is a cross-sectional view showing a state in which a release layer is formed on a support. [Figure 2] FIG. 3 is a cross-sectional view showing a state in which a photosensitive resin layer has been formed. [Figure 3] FIG. 10 is a cross-sectional view showing a state in which a seed adhesion layer has been formed. [Figure 4] FIG. 10 is a cross-sectional view showing a state in which a seed layer has been formed. [Figure 5] FIG. 10 is a cross-sectional view showing a state in which a conductor layer has been formed. [Figure 6] FIG. 10 is a cross-sectional view showing a state in which the conductor layer and the seed layer have been polished and removed by surface polishing. [Figure 7] 10 is a cross-sectional view showing a state in which an electrode for bonding to a semiconductor element is formed by polishing and removing the surface layer of the seed adhesion layer and the photosensitive resin layer by surface polishing. FIG. [Figure 8] FIG. 10 is a cross-sectional view showing a state in which a photosensitive resin layer is formed in a via portion. [Figure 9]FIG. 10 is a cross-sectional view showing a state in which a photosensitive resin layer is formed on the land portion and the wiring portion. [Figure 10] FIG. 10 is a cross-sectional view showing a state in which a seed adhesion layer has been formed. [Figure 11] FIG. 10 is a cross-sectional view showing a state in which a seed layer has been formed. [Figure 12] FIG. 10 is a cross-sectional view showing a state in which a conductor layer has been formed. [Figure 13] FIG. 10 is a cross-sectional view showing a state in which a via portion and a wiring portion have been formed by surface polishing. [Figure 14] FIG. 14 is a cross-sectional view showing a state in which a multilayer wiring is formed by repeating the steps shown in FIGS. [Figure 15] FIG. 3 is a cross-sectional view showing a state in which a photosensitive resin layer has been formed. [Figure 16] FIG. 10 is a cross-sectional view showing a state in which a seed adhesion layer has been formed. [Figure 17] FIG. 10 is a cross-sectional view showing a state in which a seed layer has been formed. [Figure 18] FIG. 2 is a cross-sectional view showing a state in which a resist pattern is formed. [Figure 19] FIG. 10 is a cross-sectional view showing a state in which a conductor layer has been formed. [Figure 20] FIG. 10 is a cross-sectional view showing a state after the resist pattern has been removed. [Figure 21] FIG. 10 is a cross-sectional view showing a state in which an unnecessary seed adhesion layer and seed layer have been removed by etching. [Figure 22] FIG. 10 is a cross-sectional view showing a state in which a solder resist layer has been formed. [Figure 23] 10 is a cross-sectional view showing a state in which a surface treatment layer and a solder joint portion are formed and a wiring board on a support body is completed. FIG. [Figure 24] FIG. 10 is a cross-sectional view showing a state in which a wiring board on a support body and an FC-BGA substrate are joined and sealed with an underfill layer. [Figure 25] FIG. 10 is a cross-sectional view showing a state in which a peeling layer is irradiated with laser light. [Figure 26] FIG. 10 is a cross-sectional view showing a state in which the support has been removed. [Figure 27] FIG. 2 is a cross-sectional view showing a state in which a semiconductor element is mounted. [Figure 28] FIG. 10 is an enlarged detailed cross-sectional view of the wiring portion and via / land portion of the AA′ surrounding portion in the embodiment. [Figure 29] FIG. 10 is an enlarged detailed cross-sectional view of the wiring portion and via / land portion of the AA′ surrounding portion in the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0018] Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical concept of the present invention can be modified in various ways within the technical scope defined by the claims. In the present disclosure, the "taper angle" refers to the angle between the main surface of the insulating resin and the side surface of the electrode or the like.

[0019] An example of a manufacturing process for a wiring board using a support according to one embodiment of the present invention will be described with reference to FIGS.

[0020] (Support) 1 is preferably transparent, since light may be irradiated onto the release layer 2 through the support 1, and glass, for example, may be used. Glass has excellent flatness and high rigidity, making it suitable for forming a fine pattern on the wiring substrate 11 on the support. Furthermore, glass has a small coefficient of thermal expansion (CTE) and is resistant to distortion, making it excellent for ensuring pattern placement accuracy and flatness. When glass is used as the support 1, the glass is preferably thicker in order to prevent warping during the manufacturing process, and is, for example, 0.7 mm or thicker, preferably 1.1 mm or thicker. Also, the CTE of glass is 3(10 -6 / K) or more 15(10 -6 / K) or less, and from the viewpoint of the CTE of the FC-BGA wiring board 12 and the semiconductor element 15, it is preferable that the -6 / K) is more preferable. The type of glass that can be used includes, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, and the like. Furthermore, if the support 1 does not need to be light-transmitting when peeling it off, such as when the peel-off layer 2 is made of a resin that foams when heated, the support 1 can be made of a material with little distortion, such as metal or ceramics. In one embodiment of the present invention, a resin that absorbs UV light and becomes peelable is used as the peel layer 2, and glass is used as the support 1.

[0021] (Formation of peeling layer) First, as shown in FIG. 1, a release layer 2 necessary for peeling off the support 1 in a later step is formed on one surface of the support 1.

[0022] For example, a resin that becomes peelable by absorbing light such as IR or UV light and generating heat or changing properties, or a resin that becomes peelable by foaming due to heat, can be suitably used for the release layer 2. When a resin that becomes peelable by irradiation with light such as UV light, for example, laser light, is used, it becomes possible to remove the support 1 from the bonded assembly (see FIG. 24) of the wiring board 11 on the support and the FC-BGA substrate 12 (see FIG. 26) by irradiating the support 1 with light from the side opposite to the side where the release layer 2 is provided (see FIG. 25).

[0023] The material for the release layer 2 can be, for example, epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, or acrylic resin to which a material (e.g., 3M Wafer Support System) has been added that absorbs light such as IR and UV light, changes over time to become exothermic and peelable.

[0024] The release layer 2 may also contain additives such as a photodecomposition accelerator, a light absorber, a sensitizer, and a filler.

[0025] Alternatively, the layer can be selected from inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers.

[0026] In addition, the release layer 2 may be composed of multiple layers. For example, in order to protect the multilayer wiring layer formed on the support 1, a protective layer may be further provided on the release layer 2, or a layer that improves adhesion to the support 1 may be provided below the release layer 2.

[0027] Furthermore, a laser light reflecting layer or a metal layer may be provided between the peeling layer 2 and the multilayer wiring layer, and the configuration is not limited to this embodiment.

[0028] (Formation of photosensitive resin layer) Next, a photosensitive resin layer 3 is formed as shown in FIG. 2. In one embodiment of the present invention, the photosensitive resin layer 3 is formed, for example, by spin coating using a photosensitive epoxy resin. Photosensitive epoxy resins can be cured at relatively low temperatures and experience little shrinkage due to curing after formation, making them excellent for subsequent fine pattern formation. When a liquid photosensitive resin is used, the photosensitive resin layer 3 can be formed by a method selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like photosensitive resin is used, lamination, vacuum lamination, vacuum pressing, and the like can be applied.

[0029] As the photosensitive resin layer 3, in addition to a photosensitive epoxy resin, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified product thereof can be used as an insulating resin. Next, openings are formed in the photosensitive resin layer 3 by photolithography. The openings may be subjected to plasma treatment to remove any residues left behind during development. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the openings, and in one embodiment of the present invention, a thickness of 7 μm is formed, for example. The shape of the openings in plan view is set according to the pitch and shape of the bonding electrodes of the semiconductor element, and in one embodiment of the present invention, the openings have a diameter of 25 μm and are formed at a pitch of 55 μm, for example.

[0030] (Formation of seed adhesion layer and seed layer) Next, as shown in FIGS. 3 and 4, a seed adhesion layer 4 and a seed layer 5 are formed using a vacuum film formation method.

[0031] The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3 and prevents peeling of the seed layer 5. The seed adhesion layer 4 may be any layer that has high adhesion to the photosensitive resin layer 3 and also to the seed layer 5, and has high conductivity comparable to that of a metal. The seed adhesion layer 4 is formed by, for example, a sputtering method or a vapor deposition method, and may be made of, for example, Ti, Ni, Cr, Mo, W, Ta, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, a Cu alloy, or a combination of two or more of these.

[0032] The seed layer 5 is a layer that acts as a power supply layer for electrolytic plating in forming wiring.

[0033] The seed layer 5 is formed by, for example, sputtering or vapor deposition, and may be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, a Cu alloy, or a combination of two or more of these.

[0034] In one embodiment of the present invention, taking into consideration electrical properties, ease of manufacturing, and cost, a titanium layer is formed on the seed adhesion layer 4, and then, without breaking the vacuum, a copper layer is formed by sputtering in the same vacuum deposition apparatus as the seed layer 5. The total thickness of the titanium layer and copper layer is preferably 1 μm or less as a power supply layer for electroplating. In one embodiment of the present invention, Ti: 50 nm, Cu: 300 nm are formed.

[0035] (Formation of a conductor layer that serves as an electrode for bonding to a semiconductor element) Next, as shown in FIG. 5, a conductor layer 6 is formed by electrolytic plating. The conductor layer 6 serves as an electrode for bonding to a semiconductor element. Examples of plating methods for forming the conductor layer 6 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. However, electrolytic copper plating is preferred because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating, which serves as an electrode for bonding to a semiconductor element, is preferably 1 μm or more from the viewpoint of solder bonding and 30 μm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 9 μm is formed in the openings of the photosensitive resin layer 3, and Cu: 2 μm is formed on the upper part of the photosensitive resin layer 3.

[0036] (Removal of conductor layer and seed layer) 6, the copper plating layer is polished by chemical mechanical polishing (CMP) or the like to remove the conductor layer 6 and seed layer 5, thereby polishing the seed adhesion layer 4 and conductor layer 6 to expose the surface. In one embodiment of the present invention, 2 μm of Cu from the conductor layer 6 and 300 nm of Cu from the seed layer 5 on the photosensitive resin layer 3 are removed.

[0037] (Removal of seed adhesion layer and photosensitive resin layer) Next, as shown in FIG. 7, polishing such as CMP is performed again to remove the surface layer of the seed adhesion layer 4 and the photosensitive resin layer 3. Because the seed adhesion layer 4 and the photosensitive resin layer 3 are different materials, chemical polishing is less effective, and physical polishing using an abrasive is dominant. To simplify the process, the same polishing method as described above (FIG. 6) may be used, or to improve polishing efficiency, the polishing method may be changed depending on the material type of the seed adhesion layer 4 and the photosensitive resin layer 3. The conductor layer 6 remaining after polishing becomes an electrode for bonding to the semiconductor element.

[0038] (Formation of photosensitive resin layer for via formation) Next, as shown in FIG. 8, similarly to FIG. 2, a photosensitive resin layer 3 is formed on the upper surfaces of the conductor layer 6 and the photosensitive resin layer 3. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the opening, and in one embodiment of the present invention, a thickness of 2 μm is formed, for example. The shape of the opening in plan view is set from the perspective of connection with the conductor layer 6, and in one embodiment of the present invention, an opening with a diameter of 10 μm is formed, for example. This opening is a via portion 20 that connects the upper and lower layers of the multilayer wiring. The photosensitive resin layer 3 provided with the via portion 20 will be referred to as a via layer 18.

[0039] (Formation of photosensitive resin layer for forming land and wiring parts) Furthermore, as shown in Fig. 9, a photosensitive resin layer 3 is formed on the upper surface of the via layer 18 in Fig. 8. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the opening, and in one embodiment of the present invention, it is formed to be, for example, 2 µm. The shape of the opening in plan view is set from the perspective of connectivity of the laminate consisting of the upper and lower photosensitive resin layers 3, and an opening larger than the via portion 20 is formed in the upper photosensitive resin layer 3 outside the opening (via portion 20) in the lower photosensitive resin layer 3 (via layer 18).

[0040] In one embodiment of the present invention, an opening having a diameter of, for example, 25 μm is formed. This opening has the shape of a wiring portion 22 of the multilayer wiring and a part of a land portion 21 connecting the upper and lower layers. The photosensitive resin layer 3 forming the land portion 21 and wiring portion 22 is referred to as a trench layer 19. When forming the trench layer 19, the taper angle of the land portion 21 of the trench layer 19 (the angle between the slope of the opening of the photosensitive resin layer 3 formed on the underlayer and the underlayer) is formed to be smaller than that of the via portion 20 of the via layer 18, and also smaller than the taper angle of the wiring portion 22 of the trench layer 19.

[0041] When forming the trench layer 19, one method for making the taper angle of the land portion 21 of the trench layer 19 smaller (closer to horizontal) than the taper angle of the via portion 20 of the via layer 18 is to make the trench layer 19 thicker than the via layer 18 when using a positive resist as the photosensitive resin layer 3. By doing so, it becomes difficult for light to reach in the thickness direction, and the taper angle tends to become smaller (closer to horizontal). Another method is to use different photosensitive resins for the trench layer 19 and the via layer 18.

[0042] Another method for forming the wiring portion 22 of the trench layer 19 so that the taper angle is larger (closer to vertical) than the land portion 21 of the trench layer 19 is to vary the exposure dose between the land portion 21 and the wiring portion 22. When a positive resist is used as the photosensitive resin layer 3, increasing the exposure dose in the land portion 21 increases the difference in exposure dose between the upper and lower portions, and the taper angle of the land portion 21 becomes smaller (closer to horizontal). Furthermore, by decreasing the exposure dose in the wiring portion 22 compared to the land portion 21, the taper angle of the wiring portion 22 of the trench layer 19 can be made larger (closer to vertical) than the land portion 21 of the trench layer 19.

[0043] (Formation of seed adhesion layer and seed layer) 10 and 11, a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum film-forming apparatus similar to that shown in FIGS. 3 and 4. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed.

[0044] (Formation of conductor layer) Next, as shown in FIG. 12 , a conductor layer 6 is formed by electrolytic plating. The conductor layer 6 becomes the via / land portion 23 and the wiring portion 22. Examples of electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. However, electrolytic copper plating is preferable because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating is preferably 0.5 μm or more from the viewpoint of electrical resistance of the wiring portion and 30 μm or less from the viewpoint of productivity. In one embodiment of the present invention, of the double openings in the photosensitive resin layer 3, Cu: 6 μm is formed in the deepest inner opening, Cu: 4 μm is formed in the opening outside the deepest inner opening, and Cu: 2 μm is formed on the upper part of the photosensitive resin layer 3.

[0045] (Removal of the conductor layer and seed layer, and removal of the seed adhesion layer and photosensitive resin layer) 13, the conductive layer 6 and the seed layer 5 are removed by polishing using a CMP (chemical mechanical polishing) process or the like. Subsequently, polishing is performed again using a CMP (chemical mechanical polishing) process or the like to remove the seed adhesion layer 4 and the surface layer of the photosensitive resin layer 3. The conductive layer 6 remaining after the CMP process or the like becomes the via / land 23 portion and the wiring portion 22. In one embodiment of the present invention, 2 μm of Cu of the conductive layer 6 on top of the photosensitive resin layer 3 and 300 nm of Cu of the seed layer 5 are removed by polishing.

[0046] (Formation of conductor layer) Next, as shown in Fig. 14, a multi-layer wiring layer is formed by repeating the steps described with reference to Fig. 8 to Fig. 13. In one embodiment of the present invention, two wiring layers are formed.

[0047] Next, a description will be given of the process of forming electrodes for bonding to the FC-BGA substrate 12. As shown in Fig. 15, similarly to Fig. 2, a photosensitive resin layer 3 is formed on the upper surface of the multilayer wiring layer of Fig. 14.

[0048] Next, a seed adhesion layer 4 is formed as shown in Fig. 16. Furthermore, a seed layer 5 is formed as shown in Fig. 17. These are formed using a vacuum film-forming apparatus without breaking the vacuum, as described with reference to Figs. 3 and 4.

[0049] Next, as shown in FIG. 18, a resist pattern 7 is formed so as to have openings at positions including vias formed at positions connectable to the via / land portions 23 formed in FIG.

[0050] Thereafter, as shown in Fig. 19, a conductor layer 6 is formed by pattern plating using electrolytic copper plating. This conductor layer 6 serves as an electrode for bonding to the FC-BGA substrate 12. The thickness of the electrolytic copper plating is desirably 1 µm or more from the viewpoint of solder bonding, and 30 µm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 9 µm is formed in the openings of the photosensitive resin layer 3, and Cu: 7 µm is formed on the upper part of the photosensitive resin layer 3.

[0051] Thereafter, as shown in FIG. 20, the resist pattern 7 is removed.

[0052] 21, unnecessary seed layer 5 and seed adhesive layer 4 are removed by etching. In this state, conductive layer 6 remaining on the surface becomes an electrode for bonding with FC-BGA substrate 12.

[0053] Next, as shown in FIG. 22, the solder resist layer 8 is formed. The solder resist layer 8 is exposed to light and developed so as to cover the photosensitive resin layer 3, and is formed with openings that expose the conductor layer 6. Note that the material for the solder resist layer 8 can be, for example, an insulating resin with high heat resistance, such as an epoxy resin, an acrylic resin, or other insulating resin. In an embodiment of the present invention, the solder resist layer 8 is formed using a photosensitive solder resist material containing a filler.

[0054] Next, as shown in FIG. 23, a surface treatment layer 9 is provided to prevent oxidation of the surface of the conductor layer 6 and to improve the wettability of the solder bumps. In one embodiment of the present invention, electroless Ni / Pd / Au plating is formed as the surface treatment layer 9. Note that the surface treatment layer 9 is formed by using OSP (Organic Plating Plate). Alternatively, a film of a water-soluble preservative (water-soluble preflux) may be formed. Alternatively, electroless tin plating, electroless Ni / Au plating, etc. may be selected depending on the application. Next, a pattern made of a solder paste material such as cream solder made by kneading fine solder powder with flux is formed on the surface treatment layer 9 on the conductor layer 6 by screen printing or the like, and the solder paste is melted once and then cooled to adhere to the conductor layer 6 or to the surface treatment layer 9 on the conductor layer 6, thereby obtaining a joint of solder 10. This completes the wiring board 11 on the support body formed on the support body 1.

[0055] Next, as shown in FIG. 24, the wiring board 11 on the support and the FC-BGA substrate 12 are joined via solder joints 10, and the gap formed between the wiring board 11 on the support and the FC-BGA substrate 12 is sealed with an underfill layer 24 filled with an underfill material. Commercially available underfill materials can be used as the material for the underfill layer 24. For example, the underfill layer 24 may be made of one or a mixture of two or more of the following resins: epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, with fillers such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide added. The underfill layer 24 is formed by filling the gap with a liquid underfill material.

[0056] 25, in order to peel off the support 1, laser light 13 is irradiated from the back side of the support 1 to make the release layer 2 in a peelable state. That is, laser light 13 is irradiated from the surface of the support 1 opposite the FC-BGA substrate 12 to the release layer 2 formed at the interface with the support 1, making it in a peelable state, and the support 1 can be removed.

[0057] Next, as shown in FIG. 26, after the support 1 is peeled off, the seed adhesion layer 4 and the seed layer 5 remaining on the surface of the substrate are removed, thereby obtaining a wiring substrate 14.

[0058] 27, a semiconductor element 15 is mounted to complete a semiconductor device 16. At this time, prior to mounting the semiconductor element 15, the conductor layer 6 exposed on the surface may be subjected to a surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, or electroless Ni / Au plating to prevent oxidation and improve the wettability of the solder bumps. In this way, the semiconductor device 16 is completed. [Example]

[0059] Next, the effects of using the configuration of wiring board 14 and the manufacturing method thereof as described above will be described with reference to FIG. 28 showing an example and FIG. 29 showing a comparative example.

[0060] In this embodiment, the wiring portion 22, via / land portion 23, and electrode pad portion for bonding with the semiconductor element of the wiring substrate 11 on the support are formed by patterning the conductor layer 6 by polishing such as chemical mechanical polishing (CMP) (a so-called damascene process). Therefore, as shown in FIG. 28, a seed adhesion layer 4 can be disposed between the conductor layer 6 and the photosensitive resin 3 on the side surfaces of the wiring portion 22, via / land portion 23, and pad portion 25, which is an electrode for bonding with the semiconductor element. Also, as shown in FIGS. 24 to 27, the wiring substrate 11 on the support is inverted upside down, and the surface on which the solder 10 is formed is bonded to the FC-BGA substrate 12. The support 1 is then removed to obtain the wiring substrate 14. Therefore, the seed adhesion layer 4 can be disposed on the top and side surfaces of the wiring portion 22 and via / land portion 23, and the seed adhesion layer 4 can be disposed on the side surfaces of the pad portion 25, which is an electrode for bonding with the semiconductor element.

[0061] As described above, the conductor layer 6 of the wiring portion 22 and the via / land portion 23 can have a seed adhesion layer 4 arranged on the top surface and side surfaces, and the conductor layer 6 of the pad portion 25, which is the bonding electrode with the semiconductor element, has a seed adhesion layer 4 arranged on the side surfaces, thereby improving adhesion with the photosensitive resin layer 3 and preventing peeling.

[0062] Furthermore, in this substrate configuration, the relationship between the taper angles of the via portion 20 of the via layer 18 and the land portion 21 and wiring portion 22 of the trench layer 19 is formed as follows: land portion 21 of trench layer 19 < via portion 20 of the via layer < wiring portion 22 of trench layer 19 (the larger the taper angle, the closer to vertical it is).

[0063] By making the taper angle of the land portion 21 of the trench layer 19 smaller (closer to horizontal) than that of the via portion 20 of the via layer 18, it is possible to reduce stress on the interface between the resin of the trench layer 19 and the resin of the via layer 18. This is because the contact area can be increased.

[0064] Furthermore, by making the taper angle of the wiring portion 22 of the trench layer 19 larger (closer to perpendicular) than that of the land portion 21 of the trench layer 19 and making the wiring shape of the trench layer 19 rectangular or nearly rectangular, the widths of the top and bottom of the wiring are made uniform, making it easier to control the electrical characteristics by changing the line width. Furthermore, by making it rectangular, the resin width between the tops of the wiring does not become too narrow compared to the width between the bottoms, making it possible to ensure the reliability of inter-wire insulation.

[0065] When forming the trench layer 19, the taper angle of the land portion 21 of the trench layer 19 is made smaller (closer to horizontal) than that of the via portion 20 of the via layer 18. This is achieved by using the same positive photosensitive resist for the via layer 18 and the trench layer 19 and making the trench layer 19 1.5 μm thicker than the via layer 18. Also, the taper angle of the wiring portion 22 of the trench layer 19 is made larger (closer to vertical) than that of the land portion 21 of the trench layer 19. This is achieved by making the exposure dose of the wiring portion 22 smaller than that of the land portion 21. Specifically, the exposure dose of the wiring portion 22 is 250 mJ / cm 2 The exposure dose of the land portion 21 is 400 mJ / cm 2 It was decided.

[0066] The taper angle is defined as follows: The larger the taper angle is in the range of 0° to 90°, the closer it is to perpendicular. Taper angle of wiring portion 22 of trench layer 19: 80° or more and 90° or less Taper angle of via portion 20 of via layer: greater than 70° and smaller than 80° Taper angle of land portion 21 of trench layer 19: 70° or less

[0067] In the above configuration, the inter-wire insulation reliability and via connection reliability were evaluated. The inter-wire insulation reliability was tested in the wiring part 22 with a line / space of 2 / 2 μm, and the via connection reliability was tested in the via part 20 with a diameter of 10 μm and the land part 21 with a diameter of 20 μm.

[0068] The inter-wire insulation reliability test is carried out under the following conditions, and the resistance value is 10 6The standard for passing was Ω or more. Standard: JESD22-A110 Temperature: 130℃ Humidity: 85%RH Voltage: 3.3V Time: 192 hours

[0069] Via connection reliability was measured under the following conditions, and the pass criteria were a resistance change rate of within ±3% and no cracks or delamination. Standard: JESD22-A106B(Condition D) Temperature: -65℃ / 5min ⇒ Room temperature / 1min ⇒ 150℃ / 5min Cycles: 500 cycles Comparative example

[0070] In the comparative example, in contrast to the example, the relationship between the taper angles of the via portion 20 of the via layer 18, the land portion 21 of the trench layer 19, and the wiring portion 22 was formed so that they were all approximately the same, i.e., the land portion 21 of the trench layer 19 ≒ the via portion 20 of the via layer 18 ≒ the wiring portion 22 of the trench layer 19. Specifically, this was achieved by making the trench layer 19 and the via layer 18 have the same thickness (3 μm). This was achieved by making the exposure dose of the wiring portion 22 and the exposure dose of the land portion 21 the same. Specifically, this was achieved by making the exposure dose of the wiring portion 22 and the exposure dose of the land portion 21 400 mJ / cm 2 It was decided.

[0071] The taper angle is defined as follows: The larger the taper angle is in the range of 0° to 90°, the closer it is to perpendicular. Wiring portion 22 of trench layer 19: 70 to 80° Via layer via section 20: 70~80° Land portion 21 of trench layer 19: 70 to 80°

[0072] <Confirmation of action and effect> Table 1 shows the results of the inter-wire insulation reliability and via connection reliability tests for the above-mentioned Examples and Comparative Examples. It has been confirmed that by specifying the relationship between the via portion 20 of the via layer 18 according to the present invention, the land portion 21 of the trench layer 19, and the taper angle of the wiring portion 22, it is possible to reduce stress at the resin interface of the trench layer / resin of the via layer and ensure the reliability of inter-wire insulation.

[0073] [Table 1]

[0074] The above-described embodiment is merely an example, and other specific details such as structure can be modified as appropriate.

[0075] The present invention can be used in a semiconductor device having a wiring substrate with an interposer or the like interposed between a main substrate and an IC chip. [Explanation of symbols]

[0076] 1 Support 2. Peel layer 3 Photosensitive resin layer 4 Seed adhesion layer 5 Seed layer 6 Conductor Layer 7 Resist pattern 8 Solder resist layer 9 Surface treatment layer 10 Solder 11 Wiring board on support 12 FC-BGA board 13 Laser light 14 Wiring board 15 Semiconductor elements 16 Semiconductor Devices 17 Insulating layer 18 via layer 19 Trench layer 20 Via section 21 Land Department 22 Wiring section 23 Via / Land Section 24 Underfill layer 25 Pad section

Claims

1. A multilayer wiring board with a support body, which has a structure in which a multilayer wiring board is laminated on at least one main surface of a plate-shaped peelable support body, The multilayer wiring board is a via layer in which a plurality of vias are formed in an insulating resin; At least one or more trench layers each having a plurality of lands and a plurality of wirings formed in an insulating resin are alternately formed on the via layer; the vias of the via layer and the lands of the trench layer are in contact with each other, thereby electrically connecting the trench layers to each other; The multilayer wiring board has electrodes for bonding to an FC-BGA substrate formed on the via layers and the trench layers that are alternately formed, a taper angle of a side surface of the electrode for bonding to the FC-BGA substrate being larger than a taper angle of a land of the trench layer; Multilayer wiring board with support.

2. The support-attached multilayer wiring board according to claim 1, a taper angle of the land of the trench layer is smaller than that of the via of the via layer; Multilayer wiring board with support.

3. 3. The multilayer wiring board with a support body according to claim 1, The taper angle of the wiring in the trench layer is larger than that of the land in the trench layer. Multilayer wiring board with support.

4. 4. The multilayer wiring board with a support body according to claim 1, The taper angle of the wiring in the trench layer is larger than that of the via in the via layer. Multilayer wiring board with support.

5. The multilayer wiring board includes the multilayer wiring board with a support body according to any one of claims 1 to 4, from which the support body has been removed, A structure in which a semiconductor element is bonded to an electrode for bonding with a semiconductor element of the multilayer wiring board, Semiconductor device.

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