Semiconductor device, monolithic microwave integrated circuit, semiconductor package, and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device, a monolithic microwave integrated circuit, a semiconductor package, and a method for manufacturing a semiconductor device which can increase resistance to moisture.SOLUTION: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate; a first insulation film covering the semiconductor element; a second insulation film on the first insulation film; and a third insulation film on the second insulation film. It is more difficult for water to penetrate the first insulation film or the third insulation film than the second insulation film. A dielectric constant of the second insulation film is lower than that of the first insulation film or the third insulation film. The first insulation film has a first part in contact with a first region of an upper surface of the semiconductor substrate. The third insulation film has a second part in contact with an upper surface and a side surface of the first part and with a second region more distant from the semiconductor element than the first region of the upper surface of the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a monolithic microwave integrated circuit, a semiconductor package, and a method for manufacturing a semiconductor device. [Background technology]

[0002] There is a semiconductor device in which an interlayer insulating film is provided on a semiconductor substrate, and in this semiconductor device, an organic interlayer insulating film and an inorganic film are stacked to improve moisture resistance (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-47575 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, as semiconductor substrates have become thinner, they are more susceptible to warping. When warping occurs, inorganic films are more likely to peel off from the semiconductor substrate. This peeling of the inorganic film reduces the moisture resistance of the semiconductor device.

[0005] An object of the present disclosure is to provide a semiconductor device, a monolithic microwave integrated circuit, a semiconductor package, and a method for manufacturing a semiconductor device that can improve moisture resistance. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, a first insulating film covering the semiconductor element, a second insulating film formed on the first insulating film, and a third insulating film formed on the second insulating film, wherein the first insulating film and the third insulating film are less permeable to moisture than the second insulating film, the second insulating film has a lower dielectric constant than the first insulating film and the third insulating film, the first insulating film has a first portion in contact with a first region on an upper surface of the semiconductor substrate, and the third insulating film has a second portion in contact with an upper surface and a side surface of the first portion and a second region on the upper surface of the semiconductor substrate that is farther from the semiconductor element than the first region. [Effects of the Invention]

[0007] According to the present disclosure, moisture resistance can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is an enlarged view of the semiconductor substrate according to the first embodiment. [Figure 3] FIG. 3 is a diagram (part 1) showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a diagram (part 2) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a diagram (part 3) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a diagram (part 4) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a diagram (part 5) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a diagram (part 6) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a diagram (part 7) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a diagram (part 1) showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a diagram (part 2) showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 14] FIG. 14 is a diagram (part 1) showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 15] FIG. 15 is a diagram (part 2) showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a diagram (part 3) showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 18] FIG. 18 is an enlarged view of a semiconductor substrate according to the fourth embodiment. [Figure 19] FIG. 19 is a diagram (part 1) showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a diagram (part 2) showing the manufacturing process of the semiconductor device according to the third embodiment. [Figure 21] FIG. 21 is a diagram (part 3) showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 22] FIG. 22 is a diagram (part 4) showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 23] FIG. 23 is a diagram (part 5) showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing a semiconductor package according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, a first insulating film covering the semiconductor element, a second insulating film formed on the first insulating film, and a third insulating film formed on the second insulating film, wherein the first insulating film and the third insulating film are less permeable to moisture than the second insulating film, the second insulating film has a lower dielectric constant than the first insulating film and the third insulating film, the first insulating film has a first portion in contact with a first region on an upper surface of the semiconductor substrate, and the third insulating film has a second portion in contact with an upper surface and a side surface of the first portion and with a second region on the upper surface of the semiconductor substrate that is farther from the semiconductor element than the first region.

[0011] The first insulating film contacts the upper surface and side surfaces of the second portion of the third insulating film and the second region of the semiconductor substrate. This improves adhesion between the first insulating film and the third insulating film and the semiconductor substrate. As a result, even if the semiconductor substrate warps, the first insulating film and the third insulating film are less likely to peel off from the semiconductor substrate. This improves the moisture resistance of the semiconductor device and improves its reliability. Furthermore, since the second insulating film has a lower dielectric constant than the first insulating film and the third insulating film, providing wiring layers sandwiching the second insulating film therebetween can suppress an increase in parasitic capacitance between the wiring layers.

[0012] [2] In [1], the first insulating film and the third insulating film may contain silicon nitride or silicon oxide, and the second insulating film may contain polyimide. In this case, silicon nitride and silicon oxide provide excellent moisture resistance, while polyimide makes it easy to achieve a low dielectric constant.

[0013] [3] In [1] or [2], the semiconductor device may include a plurality of inorganic films of at least one type selected from the group consisting of silicon nitride films and silicon oxide films, and the third insulating film may be the inorganic film farthest from the semiconductor element among the plurality of inorganic films. In this case, the inorganic film farthest from the semiconductor element contacts the upper surface and side surfaces of the first portion of the first insulating film and the second region of the semiconductor substrate. By making the inorganic film farther from the semiconductor element less likely to peel off from the semiconductor substrate, it is possible to suppress moisture penetration into the semiconductor device from the outside.

[0014] [4] In any one of [1] to [3], the semiconductor substrate may have a first plane formed in the first region and a second plane formed in the second region, and the second plane may be closer to the bottom surface of the semiconductor substrate than the first plane. In this case, a step is formed between the first plane and the second plane, increasing the area where the third insulating film contacts the semiconductor substrate. This increase in area improves adhesion between the semiconductor substrate and the third insulating film. As a result, the third insulating film is less likely to peel off from the semiconductor substrate, improving the moisture resistance of the semiconductor device.

[0015] [5] In [4], the semiconductor substrate may have a substrate and a semiconductor layer formed on the substrate, and the second plane may be formed on the semiconductor layer. In this case, adhesion between the third insulating film and the semiconductor layer is improved, and moisture resistance of the semiconductor device is improved.

[0016] [6] In any one of [1] to [5], a wiring layer may be formed on the second insulating film and covered with the third insulating film. In this case, it is possible to reduce parasitic capacitance between the wiring layer formed on the second insulating film and a wiring layer formed closer to the semiconductor substrate than the wiring layer.

[0017] [7] In any one of [1] to [6], the semiconductor device may further include a fourth insulating film formed between the first insulating film and the semiconductor element, and a fifth insulating film formed between the fourth insulating film and the semiconductor element, the fifth insulating film being less permeable to moisture than the second insulating film and the fourth insulating film, the fourth insulating film having a lower dielectric constant than the first insulating film, the third insulating film, and the fifth insulating film, the fifth insulating film having a third portion in contact with a third region on the upper surface of the semiconductor substrate that is closer to the semiconductor element than the first region, and the first insulating film being in contact with the upper surface and side surfaces of the third portion. The first insulating film being in contact with the upper surface and side surfaces of the third portion of the fifth insulating film improves adhesion between the first insulating film and the fifth insulating film and the semiconductor substrate. The improved adhesion makes the first insulating film and the fifth insulating film less likely to peel from the semiconductor substrate, improving moisture resistance.

[0018] [8] In [7], the fourth insulating film may contain polyimide, and the fifth insulating film may contain silicon nitride or silicon oxide. In this case, the silicon nitride and silicon oxide provide excellent moisture resistance, while the polyimide makes it easy to achieve a low dielectric constant.

[0019] [9] In any one of [1] to [8], the semiconductor element may include a high electron mobility transistor. In this case, the moisture resistance of the semiconductor device including the high electron mobility transistor can be improved.

[0020]

[10] A monolithic microwave integrated circuit according to another aspect of the present disclosure includes the semiconductor device according to any one of [1] to [9]. In this case, the moisture resistance of the monolithic microwave integrated circuit can be improved.

[0021]

[11] A semiconductor package according to another aspect of the present disclosure includes the semiconductor device according to any one of [1] to [9] and a resin that seals at least the top and side surfaces of the semiconductor device. In this case, the moisture resistance of the resin-sealed semiconductor package can be improved.

[0022]

[12] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of: forming a semiconductor element on a semiconductor substrate; forming a first insulating film covering the semiconductor element and having a first portion in contact with a first region on an upper surface of the semiconductor substrate; forming a second insulating film on the first insulating film; and forming a third insulating film on the second insulating film, wherein the first insulating film and the third insulating film are less permeable to moisture than the second insulating film, the second insulating film has a lower dielectric constant than the first insulating film and the third insulating film, and the third insulating film is formed to have a second portion in contact with an upper surface and a side surface of the first portion and a second region on the upper surface of the semiconductor substrate that is farther from the semiconductor element than the first region.

[0023] Because the first insulating film contacts the upper surface and side surfaces of the second portion of the third insulating film and the second region of the semiconductor substrate, adhesion between the first insulating film and the third insulating film and the semiconductor substrate is improved. As a result, even if the semiconductor substrate warps, the first insulating film and the third insulating film are less likely to peel off from the semiconductor substrate. This improves the moisture resistance of the semiconductor device and improves its reliability. Furthermore, because the second insulating film has a lower dielectric constant than the first insulating film and the third insulating film, providing wiring layers sandwiching the second insulating film therebetween can suppress an increase in parasitic capacitance between the wiring layers.

[0024] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0025] (First embodiment) 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure.

[0026] The semiconductor device 100 according to the first embodiment is, for example, a monolithic microwave integrated circuit (MMIC). The semiconductor device 100 includes a semiconductor substrate 10 and semiconductor elements formed thereon, such as a HEMT 110 and a capacitor 120. The semiconductor elements may be resistors and inductors.

[0027] The semiconductor substrate 10 comprises a substrate 102 and a semiconductor layer 101 formed thereon. The substrate 102 is a substrate for growing a gallium nitride (GaN)-based semiconductor. The substrate 102 is, for example, a silicon carbide (SiC) substrate. The thickness of the substrate 102 is, for example, within a range of 75 μm to 150 μm, and is, for example, 100 μm. The semiconductor layer 101 includes a GaN-based nitride semiconductor layer. The thickness of the nitride semiconductor layer is, for example, within a range of 0.5 μm to 3.0 μm, and is, for example, 1.0 μm. Note that a gallium arsenide (GaAs)-based semiconductor layer may also be used as the semiconductor layer 101.

[0028] Here, an enlarged view of the semiconductor substrate 10 in the semiconductor device according to the first embodiment will be described with reference to FIG.

[0029] 2, the semiconductor substrate 10 includes a substrate 102 and a GaN-based semiconductor layer 101. The GaN-based semiconductor layer 101 is epitaxially grown on the substrate 102 by, for example, metal organic chemical vapor deposition (MOCVD). The semiconductor layer 101 includes a buffer layer 161, a channel layer 162, and an electron supply layer 163.

[0030] The buffer layer 161 is a GaN layer epitaxially grown on the substrate 102. The thickness of the buffer layer 161 is, for example, in the range of 300 nm to 1000 nm, and is 500 nm in one example.

[0031] The channel layer 162 is a GaN layer epitaxially grown on the buffer layer 161. The thickness of the channel layer 162 is in the range of 5 nm to 15 nm, and is 10 nm in one example.

[0032] The electron supply layer 163 is an aluminum gallium nitride (AlGaN) layer epitaxially grown on the channel layer 162. The thickness of the electron supply layer 163 is in the range of 20 nm to 40 nm, and is 30 nm in one example.

[0033] The HEMT 110 has a source electrode 111, a drain electrode 112, and a gate electrode 113 formed on the semiconductor layer 101. In the HEMT 110, a plurality of openings are formed in an insulating film 114, and the source electrode 111, the gate electrode 113, and the drain electrode 112 are formed inside each opening. The insulating film 114 may be, for example, a silicon nitride (SiN) film. The insulating film 114 has a thickness of, for example, 100 nm. The HEMT 110 further has an insulating film 121 that covers the source electrode 111, the gate electrode 113, the drain electrode 112, and the insulating film 114. As an example, a SiN film may be used as the insulating film 121. The insulating film 121 has a thickness of, for example, 100 nm.

[0034] The source electrode 111 and the drain electrode 112 are each made of an ohmic metal layer. The ohmic metal layer is formed by alloying a laminated structure of, for example, a titanium (Ti) layer or a tantalum (Ta) layer and an aluminum (Al) layer through heat treatment. The thickness of the Ti layer or the Ta layer is, for example, in the range of 50 nm to 20 nm, and is, for example, 10 nm. The thickness of the Al layer is, for example, in the range of 50 nm to 1000 nm, and is, for example, 500 nm.

[0035] The gate electrode 113 is provided on the semiconductor layer 101. The gate electrode 113 is disposed between the source electrode 111 and the drain electrode 112. The gate electrode 113 has a laminated structure of, for example, a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer. The Ni layer has a thickness of, for example, 100 nm, the Pd layer has a thickness of, for example, 50 nm, and the Au layer has a thickness of, for example, 500 nm. The Ni layer forms a Schottky junction with the semiconductor layer 101.

[0036] The capacitor 120 has a lower electrode 122, a dielectric film 123, and an upper electrode 124 formed in this order on an insulating film 121. The lower electrode 122 and the upper electrode 124 are each made of a metal layer, for example, a laminate of a Ti layer and an Au layer. The width of the lower electrode 122 is, for example, 160 μm, and the width of the upper electrode 124 is, for example, 150 μm. The thickness of the Ti layer is in the range of 10 nm to 300 nm, for example, 100 nm. The thickness of the Au layer is in the range of 100 nm to 2000 nm, for example, 1000 nm. The dielectric film 123 is made of, for example, a SiN film or a silicon oxide (SiO) film. The thickness of the dielectric film 123 is in the range of 100 nm to 400 nm, for example, 200 nm.

[0037] The semiconductor device 100 includes a first wiring layer 131 and a second wiring layer 132. The second wiring layer 132 is electrically connected to the source electrode 111 and the upper electrode 124 via the first wiring layer 131. Although not shown, the source electrode 111 and the gate electrode 113 are also connected to the first wiring layer 131 and the second wiring layer 132, respectively. The semiconductor device 100 also includes a third wiring layer 133, a fourth wiring layer 134, and an opening 109. The first wiring layer 131, the second wiring layer 132, the third wiring layer 133, and the fourth wiring layer 134 are each made of a titanium tungsten (TiW) layer and an Au layer. The TiW layer has a thickness of, for example, 100 nm, and the Au layer has a thickness of 2.0 μm.

[0038] The semiconductor device 100 has a sixth insulating film 151, a seventh insulating film 141, an eighth insulating film 152, a fifth insulating film 142, a fourth insulating film 153, a first insulating film 143, a second insulating film 154, a third insulating film 144, and a ninth insulating film 155.

[0039] The seventh insulating film 141 covers the first wiring layer 131 and the upper surface and side surfaces of the sixth insulating film 151. The eighth insulating film 152 covers the upper surface and side surfaces of the seventh insulating film 141. The fifth insulating film 142 covers the second wiring layer 132 and the upper surface and side surfaces of the eighth insulating film 152. The fourth insulating film 153 covers the upper surface and side surfaces of the fifth insulating film 142.

[0040] The first insulating film 143 covers the third wiring layer 133 and the upper surface and side surfaces of the fourth insulating film 153. The second insulating film 154 covers the upper surface and side surfaces of the first insulating film 143. The third insulating film 144 covers the fourth wiring layer 134 and the upper surface and side surfaces of the second insulating film 154. The ninth insulating film 155 covers the upper surface and side surfaces of the third insulating film 144.

[0041] The seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 protect the first wiring layer 131, the second wiring layer 132, the third wiring layer 133, and the fourth wiring layer 134, respectively, from the intrusion of moisture.

[0042] In this manner, the sixth insulating film 151, the eighth insulating film 152, the fourth insulating film 153, the second insulating film 154, and the ninth insulating film 155, and the seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 are stacked. Furthermore, the sixth insulating film 151, the eighth insulating film 152, the fourth insulating film 153, the second insulating film 154, and the ninth insulating film 155, and the seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 cover the top and side surfaces of the HEMT 110 and the capacitor 120. The semiconductor device 100 also has an end portion 150. The end portion 150 is a portion that surrounds all semiconductor elements, such as the HEMT 110 and the capacitor 120, in a plan view perpendicular to the top surface of the semiconductor substrate 10. The end portion 150 is located, for example, within a certain distance from the outer edge of the semiconductor substrate 10 toward the center of the semiconductor substrate 10.

[0043] The sixth insulating film 151, the eighth insulating film 152, the fourth insulating film 153, the second insulating film 154, and the ninth insulating film 155 are each, for example, a polyimide film. The polyimide film is used as an interlayer insulating film between each of the wiring layers from the first wiring layer 131 to the fourth wiring layer 134. Because the dielectric constant of a polyimide film is relatively low, an increase in parasitic capacitance between the wiring layers can be suppressed. For example, by using the eighth insulating film 152 formed from polyimide, the parasitic capacitance between the first wiring layer 131 and the second wiring layer 132 can be suppressed low. By using the fourth insulating film 153 formed from polyimide, the parasitic capacitance between the second wiring layer 132 and the third wiring layer 133 can be suppressed low. Furthermore, by using the second insulating film 154 formed from polyimide, the parasitic capacitance between the third wiring layer 133 and the fourth wiring layer 134 can be suppressed low. The sixth insulating film 151, the eighth insulating film 152, the fourth insulating film 153, the second insulating film 154, and the ninth insulating film 155 each have a thickness in the range of 1.0 μm to 5.0 μm, and is 2.0 μm in one example.

[0044] The seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 are, for example, silicon nitride (SiN) films. The thickness of each of the seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 is in the range of 50 nm to 400 nm, and is 200 nm, for example. Note that the seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 may also be silicon oxide (SiO) films.

[0045] The first insulating film 143, the third insulating film 144, the fifth insulating film 142, and the seventh insulating film 141 are less permeable to moisture than the sixth insulating film 151, the eighth insulating film 152, the fourth insulating film 153, the second insulating film 154, and the ninth insulating film 155. The sixth insulating film 151, the eighth insulating film 152, the fourth insulating film 153, the second insulating film 154, and the ninth insulating film 155 have lower dielectric constants than the first insulating film 143, the third insulating film 144, the fifth insulating film 142, and the seventh insulating film 141.

[0046] The seventh insulating film 141 has a portion in contact with the side surface of the sixth insulating film 151 and a fourth portion 181 in contact with the semiconductor layer 101 in the fourth region 171 at the end portion 150. The eighth insulating film 152 is in contact with the upper surface of the fourth portion 181 of the seventh insulating film 141 and the side surface of the seventh insulating film 141 at the end portion 150. The eighth insulating film 152 is not in contact with the semiconductor layer 101 at the end portion 150.

[0047] The fifth insulating film 142 has a portion in contact with the side surface of the eighth insulating film 152 and a third portion 182 in contact with the semiconductor layer 101 in the third region 172 at the end portion 150. The fourth insulating film 153 is in contact with the upper surface of the third portion 182 of the fifth insulating film 142 and the side surface of the fifth insulating film 142 at the end portion 150. The fourth insulating film 153 is not in contact with the semiconductor layer 101 at the end portion 150.

[0048] At the end 150, the first insulating film 143 has a portion that contacts the side surface of the fourth insulating film 153 and a first portion 183 that contacts the semiconductor layer 101 in the first region 173. At the end 150, the second insulating film 154 contacts the upper surface of the first portion 183 of the first insulating film 143 and the side surface of the first insulating film 143. Furthermore, the first portion 183 protrudes outward from the side surface of the second insulating film 154. Here, "outward" means the side closer to the outer edge of the semiconductor substrate 10 when viewed from the HEMT 110 and the capacitor 120. At the end 150, the second insulating film 154 does not contact the semiconductor layer 101.

[0049] At the end portion 150, the third insulating film 144 has a portion in contact with the side surface of the second insulating film 154, a portion in contact with the first portion 183 of the first insulating film 143, and a second portion 184 in contact with the second region 174 of the semiconductor layer 101. At the end portion 150, the ninth insulating film 155 is in contact with the upper surface of the second portion 184 of the third insulating film 144 and the side surface of the third insulating film 144. At the end portion 150, the ninth insulating film 155 is not in contact with the semiconductor layer 101.

[0050] Here, a method for manufacturing the semiconductor device 100 according to the embodiment will be described. Figures 3 to 8 are cross-sectional views showing a method for manufacturing the semiconductor device 100 according to the embodiment.

[0051] First, as shown in FIG. 3, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 has a substrate 102 and a semiconductor layer 101. The semiconductor layer 101 has a buffer layer 161, a channel layer 162 that functions as an electron transit layer, and an electron supply layer 163. Distortion occurs between the channel layer 162 and the electron supply layer 163 due to a difference in lattice constant. This distortion generates a two-dimensional electron gas (2DEG) at the interface between the channel layer 162 and the electron supply layer 163 on the channel layer 162 side, forming a channel region. A scribe region 103 is defined in the semiconductor substrate 10.

[0052] Next, an insulating film 114 is formed on the semiconductor layer 101 on which the HEMT 110 is to be formed. The insulating film 114 is formed by, for example, chemical vapor deposition (CVD).

[0053] Next, the insulating film 114 is etched using a mask at locations corresponding to the source electrode 111 and the drain electrode 112, forming openings therein. This etching exposes the semiconductor layer 101 in the respective openings. An ohmic metal layer is formed on the exposed semiconductor layer 101. The step of forming the ohmic metal layer includes, for example, a step of forming a Ti layer and an Al layer on the exposed semiconductor layer 101 and alloying them by heat treatment. The Ti layer and the Al layer are formed by, for example, vacuum deposition. The formed ohmic metal layers become the source electrode 111 and the drain electrode 112, respectively.

[0054] Next, the insulating film 114 between the source electrode 111 and the drain electrode 112 is partially etched to form an opening. This etching exposes the semiconductor layer 101 at the bottom of the opening. A gate electrode 113 is formed on this exposed semiconductor layer 101. The gate electrode 113 is made of, for example, a Ni layer formed on the semiconductor layer 101 and an Au layer formed on this Ni layer.

[0055] Next, in order to form the capacitor 120, an insulating film 121 is formed on the entire surface by a CVD method. The insulating film 121 covers the source electrode 111, the drain electrode 112, the gate electrode 113, the insulating film 114, and the entire surface of the semiconductor layer 101. The insulating film 121 is, for example, a SiN film.

[0056] Next, a metal layer made of a Ti layer and an Au layer is formed on the entire surface of the insulating film 121 to form the lower electrode 122. This metal layer is etched, leaving behind the portion that will become the lower electrode 122 of the capacitor 120, to form the lower electrode 122. Next, a dielectric film 123 is formed by CVD on the entire surface of the lower electrode 122. Thereafter, the unnecessary portion of the dielectric film 123 is etched away, and the dielectric film 123 of the capacitor 120 is formed.

[0057] Subsequently, a metal layer is formed on the entire surface of the dielectric film 123. This metal layer may be made of the Ti layer and Au layer used in the lower electrode 122. This metal layer faces the lower electrode 122 and is etched away, leaving only an area necessary to ensure the designed capacitance value, to form the upper electrode 124.

[0058] 4, a sixth insulating film 151, a first wiring layer 131, and a seventh insulating film 141 are formed. The sixth insulating film 151 is formed on the entire surface by, for example, a spin coating method. The sixth insulating film 151 covers the upper electrode 124, the dielectric film 123, and the insulating film 121.

[0059] Subsequently, the sixth insulating film 151 is etched together with the insulating film 121 to expose the surface of the semiconductor layer 101 at the end portion 150. In this etching, the surfaces of the drain electrode 112 and the upper electrode 124 are also exposed.

[0060] Thereafter, a first wiring layer 131 is formed on the entire surface. This first wiring layer 131 is etched except for the drain electrode 112, the upper electrode 124, and other portions used for wiring, etc. By this etching, the first wiring layer 131 connected to the drain electrode 112 and the first wiring layer 131 connected to the upper electrode 124 are formed. Next, a seventh insulating film 141 is formed on the entire surface by a CVD method. The seventh insulating film 141 covers the first wiring layer 131, the sixth insulating film 151, and the semiconductor layer 101 of the end portion 150.

[0061] 5, an eighth insulating film 152, a second wiring layer 132, and a fifth insulating film 142 are formed. The eighth insulating film 152 is formed on the surface of the seventh insulating film 141 by, for example, a spin coating method.

[0062] Subsequently, the seventh insulating film 141 is etched together with the eighth insulating film 152. By this etching, a fourth portion 181 of the seventh insulating film 141 is formed above the fourth region 171 in the end portion 150, and the eighth insulating film 152 remains above the fourth portion 181. Meanwhile, outside the fourth region 171 in the end portion 150, the surface of the semiconductor layer 101 is exposed. Furthermore, by this etching, the surface of the first wiring layer 131 is also exposed.

[0063] Thereafter, a second wiring layer 132 is formed on the entire surface. The second wiring layer 132 is etched except for the portions connected to the first wiring layer 131 and portions used for other wiring, etc. Next, a fifth insulating film 142 is formed on the entire surface by a CVD method. The fifth insulating film 142 covers the second wiring layer 132, the eighth insulating film 152, and a portion of the semiconductor layer 101 closer to the scribe region 103 than the fourth region 171.

[0064] 6, a fourth insulating film 153, a third wiring layer 133, and a first insulating film 143 are formed. The fourth insulating film 153 is formed on the surface of the fifth insulating film 142 by, for example, a spin coating method.

[0065] Subsequently, the fifth insulating film 142 is etched together with the fourth insulating film 153. By this etching, a third portion 182 of the fifth insulating film 142 is formed above the third region 172 at the end portion 150, and the fourth insulating film 153 remains above the third portion 182. At this time, the surface of the semiconductor layer 101 is exposed outside the third region 172 at the end portion 150. Furthermore, by this etching, the surface of the second wiring layer 132 is exposed as necessary.

[0066] The third region 172 is located outside the scribe region 103 of the fourth region 171 and is in contact with the fourth region 171. The fifth insulating film 142 is in contact with the seventh insulating film 141 exposed at the end of the fourth region 171 on the side where the scribe region 103 is located.

[0067] Thereafter, a third wiring layer 133 is formed on the entire surface. The third wiring layer 133 is etched except for the portion that connects to the exposed surface of the second wiring layer 132 and the portion that will be used for other wiring, etc. Next, a first insulating film 143 is formed on the entire surface. The first insulating film 143 covers the third wiring layer 133, the fourth insulating film 153, and the surface of the semiconductor layer 101 outside the scribe region 103 of the third region 172.

[0068] 7, a second insulating film 154, a fourth wiring layer 134, and a third insulating film 144 are formed. The second insulating film 154 is formed on the surface of the first insulating film 143 by, for example, spin coating.

[0069] Subsequently, the first insulating film 143 is etched together with the second insulating film 154. By this etching, a first portion 183 of the first insulating film 143 is formed above the first region 173 at the end portion 150, and the second insulating film 154 remains above the first portion 183. At this time, the surface of the semiconductor layer 101 is exposed outside the first region 173 at the end portion 150. Furthermore, by this etching, the surface of the third wiring layer 133 is exposed as necessary.

[0070] Thereafter, only the second insulating film 154 is selectively etched, leaving the first portion 183. This etching causes the sidewall of the second insulating film 154 to retreat from the end of the first region 173 inward (away from the scribe region 103) when viewed from the scribe region 103. As a result, a part of the first portion 183 extends from the sidewall of the second insulating film 154 toward the side where the scribe region 103 is located.

[0071] In this process, in the first stage, the second insulating film 154 and the first insulating film 143 are etched using a first mask. Then, in the second stage, only the second insulating film 154 is etched using a second mask that is different from the first mask. That is, this process involves two stages of etching. Compared to the first mask, the masked area of ​​the second mask is recessed inward (toward the side away from the scribe area 103). This recessed mask area forms a part of the first portion 183 that extends from the sidewall of the second insulating film 154 toward the side where the scribe area 103 is located.

[0072] The first region 173 is located outside the scribe region 103 of the third region 172 and is in contact with the third region 172. The first insulating film 143 is in contact with the fifth insulating film 142 exposed at the end of the third region 172.

[0073] Thereafter, a fourth wiring layer 134 is formed on the entire surface. The fourth wiring layer 134 is etched except for the portion connected to the third wiring layer 133 and the portion used for other wiring, etc.

[0074] Next, a third insulating film 144 is formed on the entire surface by CVD. The third insulating film 144 covers the fourth wiring layer 134, the second insulating film 154, and the outside of the first region 173 of the semiconductor layer 101. At this time, the third insulating film 144 contacts the upper surface and side surfaces of the portion of the first portion 183 that protrudes from the side surface of the second insulating film 154. Furthermore, the third insulating film 144 contacts the semiconductor layer 101 on the outside of the first region 173, towards the scribe region 103.

[0075] 8, a ninth insulating film 155 is formed. The ninth insulating film 155 is formed on the surface of the third insulating film 144 by, for example, spin coating. Then, the third insulating film 144 is etched together with the ninth insulating film 155. This etching leaves the second portion 184 of the third insulating film 144 and the ninth insulating film 155 above the second region 174 at the end 150. At this time, the surface of the semiconductor layer 101 is exposed outside the second region 174, toward the scribe region 103.

[0076] This etching also forms an opening 109 corresponding to the fourth wiring layer 134. The opening 109 serves as a pad for electrically connecting the fourth wiring layer 134 to the outside of the semiconductor device 100. The pad is, for example, a bonding pad connected to a bonding wire. Note that the surface of the end of the third portion 182 of the third insulating film 144 is exposed from the ninth insulating film 155.

[0077] 3 to 8 are performed on a semiconductor wafer. After the process of Fig. 8 is completed, the wafer is cut into individual semiconductor devices 100, or chips, as described below.

[0078] 9, a scribe area 103 is set on a semiconductor wafer 20 made up of a semiconductor layer 101 and a substrate 102. The scribe area 103 is an area to be cut by a dicing blade 104.

[0079] A gap is formed between the scribe region 103 and the second insulating film 154. The combined width of the scribe region 103 and the gap is formed to be sufficiently wider than the width of the dicing blade 104. As an example, the width of the dicing blade 104 is 50 μm, and the combined width of the scribe region and the gap is 100 μm. The gap is provided to prevent clogging of the dicing blade 104. This clogging occurs when the dicing blade 104 cuts the second insulating film 154.

[0080] Another purpose is to prevent cracks, or chipping, from occurring in the third insulating film 144 and the ninth insulating film 155 when the dicing blade 104 comes into contact with these films. Furthermore, it is possible to prevent the third insulating film 144 from peeling off from the semiconductor layer 101 due to the impact during cutting.

[0081] By cutting the scribe region 103 with a dicing blade 104, a plurality of individual semiconductor devices 100 are obtained from the semiconductor wafer 20.

[0082] In this manner, the semiconductor device 100 according to the first embodiment can be manufactured.

[0083] In this embodiment, the third insulating film 144 is in contact with the upper surface and side surfaces of the portion of the first portion 183 that protrudes from the second insulating film 154. Furthermore, the second portion 184 of the third insulating film 144 is in contact with the second region 174 of the semiconductor layer 101. This improves the adhesion between the first insulating film 143 and the third insulating film 144 and the semiconductor layer 101, making them more resistant to peeling. This improves the moisture resistance of the semiconductor device 100.

[0084] Furthermore, among the multiple insulating films (inorganic films) containing silicon nitride or silicon oxide, the third insulating film 144, which is the farthest from the HEMT 110 and the capacitor 120, provides stronger adhesion. This makes it particularly difficult for moisture to penetrate into the semiconductor device 100. This results in excellent moisture resistance.

[0085] In the first embodiment described above, a semiconductor device has been described in which the outermost third insulating film 144 is in contact with the upper surface and side surface of the portion of the first portion 183 that protrudes from the second insulating film 154 and is in contact with the semiconductor layer 101. However, the present invention is not limited to this configuration, and the following configurations are also possible. For example, the fifth insulating film 142 may be in contact with the upper surface and side surface of the portion of the fourth portion 181 that protrudes from the eighth insulating film 152 and is in contact with the semiconductor layer 101. Alternatively, the first insulating film 143 may be in contact with the upper surface and side surface of the portion of the third portion 182 that protrudes from the fourth insulating film 153 and is in contact with the semiconductor layer 101.

[0086] (Second embodiment) Next, a second embodiment will be described. The second embodiment relates to a semiconductor device including a HEMT. Fig. 10 is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0087] The semiconductor device 200 according to the second embodiment is, for example, an MMIC. The semiconductor device 200 differs from the first embodiment in that the tenth insulating film 145 covers the third insulating film 144.

[0088] The tenth insulating film 145 is formed to cover the sidewall of the opening 109 and the surface of the ninth insulating film 155. The tenth insulating film 145 is made of, for example, a SiN film or a SiO film. The tenth insulating film 145 is in contact with the second portion 184 of the third insulating film 144 above the second region 174 and is in contact with the fifth region 175 of the semiconductor layer 101.

[0089] In the manufacturing method of this embodiment, the manufacturing steps from Fig. 3 to Fig. 6 are the same as those in the first embodiment. Hereinafter, the manufacturing steps following Fig. 6 will be described with reference to Fig. 11, and the steps following Fig. 11 will be described with reference to Fig. 12.

[0090] 11, there are formed a second insulating film 154, a fourth wiring layer 134, and a third insulating film 144. The second insulating film 154 is formed on the surface of the first insulating film 143 by, for example, spin coating.

[0091] Next, the first insulating film 143 is etched together with the second insulating film 154. By this etching, a first portion 183 of the first insulating film 143 is formed above the first region 173 at the end portion 150, and the second insulating film 154 remains above the first portion 183. At this time, the surface of the semiconductor layer 101 is exposed outside the first region 173 at the end portion 150.

[0092] Thereafter, a fourth wiring layer 134 is formed on the entire surface. The fourth wiring layer 134 is etched except for the portion connected to the third wiring layer 133 and the portion used for other wiring, etc. Next, a third insulating film 144 is formed on the entire surface by the CVD method. The third insulating film 144 covers the fourth wiring layer 134, the second insulating film 154, and a portion of the semiconductor layer 101 closer to the scribe region 103 than the first region 173.

[0093] 12, a ninth insulating film 155 and a tenth insulating film 145 are formed. The ninth insulating film 155 is formed on the surface of the third insulating film 144 by, for example, spin coating.

[0094] Subsequently, the third insulating film 144 is etched together with the ninth insulating film 155. By this etching, a second portion 184 of the third insulating film 144 is formed above the second region 174 at the end portion 150, and the ninth insulating film 155 remains above the second portion 184. At this time, the surface of the semiconductor layer 101 is exposed outside the second region 174 at the end portion 150. Furthermore, by this etching, an opening 109 is formed that exposes the surface of the fourth wiring layer 134.

[0095] Thereafter, only the ninth insulating film 155 is selectively etched, leaving the second portion 184. This etching causes the sidewall of the ninth insulating film 155 to retreat from the end of the second region 174 inward (away from the scribe region 103) when viewed from the scribe region 103. As a result, a part of the second portion 184 extends from the sidewall of the ninth insulating film 155 toward the side where the scribe region 103 is located.

[0096] In this process, in the first step, the ninth insulating film 155 and the third insulating film 144 are etched using a third mask. Then, in the second step, only the ninth insulating film 155 is etched using a fourth mask different from the third mask.

[0097] The second region 174 is located outside the first region 173 on the side where the scribe region 103 is located, and is in contact with the first region 173. The third insulating film 144 is in contact with the first insulating film 143 exposed at the end of the first region 173.

[0098] Next, a tenth insulating film 145 is formed on the entire surface by the CVD method. The tenth insulating film 145 covers the fourth wiring layer 134, the ninth insulating film 155, and the outside of the second region 174 of the semiconductor layer 101. At this time, the tenth insulating film 145 contacts the upper surface and side surfaces of the portion of the second portion 184 that protrudes from the side surface of the ninth insulating film 155. Furthermore, the tenth insulating film 145 contacts the semiconductor layer 101 on the outside of the second region 174, towards the scribe region 103.

[0099] Subsequently, the tenth insulating film 145 is etched to leave a fifth portion 185 of the tenth insulating film 145 above the fifth region 175. At this time, the surface of the semiconductor layer 101 is exposed at a position closer to the scribe region 103 than the fifth region 175. This etching also exposes the surface of the fourth wiring layer 134 in the opening 109, and the tenth insulating film 145 remains on the sidewall of the opening 109.

[0100] Finally, similarly to the first embodiment, the scribe region 103 is cut with a dicing blade 104 to obtain a plurality of individual semiconductor devices 200.

[0101] In this manner, the semiconductor device 200 according to the second embodiment can be manufactured.

[0102] In this embodiment, the tenth insulating film 145 contacts the upper surface and side surfaces of the portion of the second portion 184 of the third insulating film 144 that protrudes from the ninth insulating film 155, and also contacts the semiconductor layer 101. Therefore, similar to the first embodiment, peeling of the third insulating film 144 and the tenth insulating film 145 can be suppressed. Furthermore, by increasing the number of films that are less permeable to moisture, penetration of moisture into the semiconductor device 200 can be further suppressed.

[0103] Therefore, in the second embodiment, the moisture resistance of the semiconductor device 200 can be improved more than in the first embodiment.

[0104] Furthermore, since the film covering the sidewall of the opening 109 is used as the tenth insulating film 145, the number of steps does not increase.

[0105] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a semiconductor device including a HEMT. Fig. 13 is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0106] The semiconductor device 300 according to the third embodiment is, for example, an MMIC. The semiconductor device 300 differs from the first embodiment in that the first insulating film 143 contacts the top surface and side surfaces of the third portion 182 of the fifth insulating film 142 on the third region 172.

[0107] Specifically, the first insulating film 143 has a portion that contacts the upper surface and side surface of the portion of the third portion 182 that extends from the fourth insulating film 153 toward the outer edge of the semiconductor substrate 10, and a first portion 183 that contacts the first region 173 of the semiconductor layer 101.

[0108] The manufacturing method of this embodiment is the same as that of the first embodiment in the steps shown in Fig. 3 to Fig. 5. Hereinafter, the manufacturing steps following Fig. 5 will be described with reference to Fig. 14, the steps following Fig. 14 will be described with reference to Fig. 15, and the steps following Fig. 15 will be described with reference to Fig. 16.

[0109] 14, a fourth insulating film 153, a third wiring layer 133, and a first insulating film 143 are formed. The fourth insulating film 153 is formed on the surface of the fifth insulating film 142 by, for example, spin coating.

[0110] Subsequently, the fifth insulating film 142 is etched together with the fourth insulating film 153. By this etching, a third portion 182 of the fifth insulating film 142 is formed above the third region 172 at the end portion 150, and the fourth insulating film 153 remains above the third portion 182. At this time, the surface of the semiconductor layer 101 is exposed outside the third region 172 at the end portion 150. By this etching, the surface of the second wiring layer 132 is exposed as necessary.

[0111] Thereafter, only the fourth insulating film 153 is selectively etched, leaving the third portion 182. This etching causes the sidewall of the fourth insulating film 153 to retreat from the end of the third region 172 inward (away from the scribe region 103) when viewed from the scribe region 103. As a result, a part of the third portion 182 extends from the sidewall of the fourth insulating film 153 toward the side where the scribe region 103 is located.

[0112] In this process, in the first stage, the fourth insulating film 153 and the fifth insulating film 142 are etched using a fifth mask. Then, in the second stage, only the fourth insulating film 153 is etched using a sixth mask different from the fifth mask.

[0113] Thereafter, a third wiring layer 133 is formed on the entire surface. The third wiring layer 133 is etched except for the portion connected to the second wiring layer 132 and the portion used for other wiring, etc.

[0114] Next, a first insulating film 143 is formed on the entire surface by a CVD method. The first insulating film 143 covers the third wiring layer 133, the fourth insulating film 153, and the outside of the third region 172 of the semiconductor layer 101. At this time, the first insulating film 143 contacts the upper surface and side surfaces of the portion of the third portion 182 that protrudes from the side surface of the fourth insulating film 153, and also contacts the surface of the semiconductor layer 101 at a position closer to the scribe region 103 than the third region 172.

[0115] 15, a second insulating film 154, a fourth wiring layer 134, and a third insulating film 144 are formed. The second insulating film 154 is formed on the surface of the first insulating film 143 by, for example, spin coating.

[0116] Subsequently, the first insulating film 143 is etched together with the second insulating film 154. By this etching, a first portion 183 of the first insulating film 143 is formed above the first region 173 at the end portion 150, and the second insulating film 154 remains above the first portion 183. At this time, the surface of the semiconductor layer 101 is exposed outside the first region 173 at the end portion 150. By this etching, the surface of the third wiring layer 133 is exposed as necessary.

[0117] Thereafter, only the second insulating film 154 is selectively etched, leaving the first portion 183. This etching causes the sidewall of the second insulating film 154 to retreat from the end of the first region 173 inward (away from the scribe region 103) when viewed from the scribe region 103. As a result, a part of the first portion 183 extends from the sidewall of the second insulating film 154 toward the side where the scribe region 103 is located.

[0118] In this process, in the first stage, the second insulating film 154 and the first insulating film 143 are etched using a seventh mask. Then, in the second stage, only the second insulating film 154 is etched using an eighth mask that is different from the seventh mask.

[0119] Thereafter, a fourth wiring layer 134 is formed on the entire surface. The fourth wiring layer 134 is etched except for the portion connected to the third wiring layer 133 and the portion used for other wiring, etc. Next, a third insulating film 144 is formed on the entire surface by a CVD method. The third insulating film 144 covers the fourth wiring layer 134, the second insulating film 154, and a portion of the semiconductor layer 101 that is closer to the scribe region 103 than the first region 173. At this time, the third insulating film 144 contacts the upper surface and side surface of the portion of the first portion 183 that protrudes from the side surface of the second insulating film 154, and also contacts the surface of the semiconductor layer 101 outside the first region 173.

[0120] 16, the ninth insulating film 155 is formed. Specifically, the ninth insulating film 155 is formed on the surface of the third insulating film 144 by, for example, a spin coating method.

[0121] Subsequently, the third insulating film 144 is etched together with the ninth insulating film 155. By this etching, a second portion 184 of the third insulating film 144 is formed above the second region 174 at the end portion 150, and the ninth insulating film 155 remains above the second portion 184. At this time, the semiconductor layer 101 is exposed outside the second region 174 at the end portion 150. Furthermore, this etching also forms an opening 109 that exposes the surface of the fourth wiring layer 134.

[0122] Finally, as in the other embodiments, the scribe region 103 is cut with a dicing blade 104 to obtain a plurality of individual semiconductor devices 300.

[0123] In this manner, the semiconductor device 300 according to the third embodiment can be manufactured.

[0124] In this embodiment, at the end portion 150, the first insulating film 143 contacts the upper surface and side surfaces of the portion of the third portion 182 that protrudes from the fourth insulating film 153, and also contacts the semiconductor layer 101. This makes it even more difficult for the first insulating film 143 to peel off from the semiconductor substrate 10. This makes it even more resistant to moisture penetration, and further improves the moisture resistance of the semiconductor device 300.

[0125] In this embodiment, the fifth insulating film 142 may be in contact with the upper surface and side surfaces of the fourth portion 181 and also with the semiconductor layer 101. In this case, the fifth insulating film 142 can be made even less likely to peel off from the semiconductor substrate 10. Therefore, the moisture resistance of the semiconductor device 300 can be further improved.

[0126] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a semiconductor device including a HEMT. Fig. 17 is a cross-sectional view showing the semiconductor device according to the fourth embodiment.

[0127] The semiconductor device 400 according to the fourth embodiment is, for example, an MMIC. The semiconductor device 400 differs from the first embodiment in that the semiconductor layer 101 is etched at the end portion 150 to form a plurality of planes of different heights. The fourth region 171, the third region 172, the first region 173, and the second region 174 are formed so that the semiconductor layer 101 becomes thinner in this order. Therefore, in the fourth region 171, the third region 172, the first region 173, and the second region 174, the outer regions have planes that are lower than the inner regions.

[0128] Here, an enlarged view of the semiconductor substrate 10 in the semiconductor device according to the fourth embodiment will be described with reference to FIG.

[0129] 18 , the fourth region 171, the third region 172, the first region 173, and the second region 174 each have a plane etched beyond the channel layer 162 and the electron supply layer 163 down to the buffer layer 161. The fourth region 171 has a fourth plane 14 that is lower than the surface of the buffer layer 161 before etching. The third region 172 has a third plane 13 that is lower than the fourth plane 14. The first region 173 has a first plane 11 that is lower than the third plane 13. The second region 174 has a second plane 12 that is lower than the first plane 11. The second plane 12 is closer to the bottom surface 19 of the semiconductor substrate 10 than the first plane 11. The semiconductor layer 101 is etched down to the buffer layer 161 so as not to affect the characteristics of the HEMT 110.

[0130] The manufacturing method of this embodiment is the same as that of the first embodiment in the steps shown in Fig. 3. Hereinafter, the manufacturing steps following Fig. 3 will be described using Fig. 19, and the steps following Fig. 19 will be described using Fig. 20. Similarly, the steps following Fig. 20 will be described using Fig. 21, the steps following Fig. 21 will be described using Fig. 22, and the steps following Fig. 22 will be described using Fig. 23.

[0131] 19, a sixth insulating film 151, a first wiring layer 131, and a seventh insulating film 141 are formed. The sixth insulating film 151 is formed on the entire surface by, for example, spin coating. The sixth insulating film 151 covers the upper electrode 124, the dielectric film 123, and the insulating film 121.

[0132] Subsequently, the sixth insulating film 151 is etched together with the insulating film 121 to expose the semiconductor layer 101 at the end portion 150. At this time, the semiconductor layer 101 is etched down to the buffer layer 161. By this etching, a fourth plane 14 is formed in the buffer layer 161 at the end portion 150, the fourth plane 14 being lower than the surface of the semiconductor layer 101 before etching. By this etching, the surfaces of the drain electrode 112 and the upper electrode 124 are also exposed.

[0133] Thereafter, a first wiring layer 131 is formed on the entire surface. This first wiring layer 131 is etched except for the drain electrode 112, the upper electrode 124, and other portions used for wiring, etc. By this etching, the first wiring layer 131 connected to the drain electrode 112 and the first wiring layer 131 connected to the upper electrode 124 are formed. Next, a seventh insulating film 141 is formed on the entire surface by a CVD method. The seventh insulating film 141 covers the first wiring layer 131, the sixth insulating film 151, and the semiconductor layer 101 of the end portion 150.

[0134] 20, an eighth insulating film 152, a second wiring layer 132, and a fifth insulating film 142 are formed. The eighth insulating film 152 is formed on the surface of the seventh insulating film 141 by, for example, spin coating.

[0135] Subsequently, the seventh insulating film 141 is etched together with the eighth insulating film 152. By this etching, a fourth portion 181 of the seventh insulating film 141 is formed above the fourth region 171 in the end portion 150, and the eighth insulating film 152 remains above the fourth portion 181. At this time, the buffer layer 161 is further etched outside the fourth region 171. By this etching, a third plane 13 that is lower than the fourth plane 14 of the fourth region 171 is formed in the buffer layer 161 outside the fourth region 171. This etching also exposes the surface of the first wiring layer 131.

[0136] Thereafter, a second wiring layer 132 is formed on the entire surface. The second wiring layer 132 is etched except for the portions connected to the first wiring layer 131 and portions used for other wiring, etc. Next, a fifth insulating film 142 is formed on the entire surface by a CVD method. The fifth insulating film 142 covers the second wiring layer 132, the eighth insulating film 152, and a portion of the semiconductor layer 101 closer to the scribe region 103 than the fourth region 171.

[0137] 21, a fourth insulating film 153, a third wiring layer 133, and a first insulating film 143 are formed. The fourth insulating film 153 is formed on the surface of the fifth insulating film 142 by, for example, spin coating.

[0138] Subsequently, the fifth insulating film 142 is etched together with the fourth insulating film 153. By this etching, a third portion 182 of the fifth insulating film 142 is formed above the third region 172 at the end portion 150, and the fourth insulating film 153 remains above the third portion 182. At this time, the buffer layer 161 is further etched outside the third region 172. By this etching, a first plane 11 that is lower than the third plane 13 of the third region 172 is formed in the buffer layer 161 outside the third region 172. By this etching, the surface of the second wiring layer 132 is exposed as necessary.

[0139] Thereafter, only the fourth insulating film 153 is selectively etched, leaving the third portion 182. This etching causes the sidewall of the fourth insulating film 153 to retreat from the end of the third region 172 inward (away from the scribe region 103) when viewed from the scribe region 103. As a result, a part of the third portion 182 extends from the sidewall of the fourth insulating film 153 toward the side where the scribe region 103 is located.

[0140] In this process, in the first stage, the fourth insulating film 153 and the fifth insulating film 142 are etched using a ninth mask. Then, in the second stage, only the fourth insulating film 153 is etched using a tenth mask that is different from the ninth mask.

[0141] Thereafter, a third wiring layer 133 is formed on the entire surface. The third wiring layer 133 is etched except for the portion in contact with the second wiring layer 132 and the portion used for other wiring, etc. Next, a first insulating film 143 is formed on the entire surface by a CVD method. The first insulating film 143 covers the third wiring layer, the fourth insulating film 153, and a portion of the semiconductor layer 101 that is closer to the scribe region 103 than the third region 172. At this time, the first insulating film 143 contacts the upper surface and side surface of the portion of the third portion 182 that protrudes from the side surface of the fourth insulating film 153, and also contacts the surface of the buffer layer 161 outside the third region 172.

[0142] 22, a second insulating film 154, a fourth wiring layer 134, and a third insulating film 144 are formed. The second insulating film 154 is formed on the surface of the first insulating film 143 by, for example, spin coating.

[0143] Next, the first insulating film 143 is etched together with the second insulating film 154. By this etching, a first portion 183 of the first insulating film 143 is formed above the first region 173 at the end portion 150, and the second insulating film 154 remains above the first portion 183. At this time, the buffer layer 161 is further etched outside the first region 173 at the end portion 150. By this etching, a second plane 12 that is lower than the first plane 11 of the first region 173 is formed in the buffer layer 161 outside the first region 173. By this etching, the surface of the third wiring layer 133 is exposed as necessary.

[0144] Thereafter, only the second insulating film 154 is selectively etched. This etching causes the sidewall of the second insulating film 154 to retreat from the end of the first region 173 inward (away from the scribe region 103) when viewed from the scribe region 103. As a result, a part of the first portion 183 extends from the sidewall of the second insulating film 154 toward the side where the scribe region 103 is located.

[0145] In this process, in the first stage, the second insulating film 154 and the first insulating film 143 are etched using an eleventh mask. Then, in the second stage, only the second insulating film 154 is etched using a twelfth mask that is different from the eleventh mask.

[0146] Thereafter, a fourth wiring layer 134 is formed on the entire surface. The fourth wiring layer 134 is etched except for the portion connected to the third wiring layer 133 and the portion used for other wiring, etc. Next, a third insulating film 144 is formed on the entire surface by a CVD method. The third insulating film 144 covers the fourth wiring layer 134, the second insulating film 154, and a portion of the semiconductor layer 101 that is closer to the scribe region 103 than the first region 173. At this time, the third insulating film 144 contacts the upper surface and side surface of the portion of the first portion 183 that protrudes from the side surface of the second insulating film 154, and also contacts the surface of the buffer layer 161 outside the first region 173.

[0147] 23, the ninth insulating film 155 is formed. Specifically, the ninth insulating film 155 is formed on the surface of the third insulating film 144 by, for example, spin coating.

[0148] Subsequently, the third insulating film 144 is etched together with the ninth insulating film 155. By this etching, the second portion 184 of the third insulating film 144 is formed above the second region 174 at the end portion 150, and the ninth insulating film 155 remains above the second portion 184. At this time, the buffer layer 161 having the same plane as the plane of the second region 174 is exposed outside the second region 174 at the end portion 150.

[0149] This etching also forms an opening 109 corresponding to the fourth wiring layer 134. Note that the side surface of the end of the second portion 184 of the third insulating film 144 is exposed from the ninth insulating film 155.

[0150] Finally, as in the other embodiments, the scribe region 103 is cut with a dicing blade 104 to obtain a plurality of individual semiconductor devices 400.

[0151] In this manner, the semiconductor device 400 according to the fourth embodiment can be manufactured.

[0152] In this embodiment, the semiconductor substrate 10 is formed with a fourth plane 14, a third plane 13, a first plane 11, and a second plane 12, each having different heights. Therefore, steps exist on the upper surface of the semiconductor substrate 10. Therefore, the seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 contact not only the upper surface of the semiconductor substrate 10 but also the wall surfaces of the steps. Therefore, the contact areas of the seventh insulating film 141, the fifth insulating film 142, the first insulating film 143, and the third insulating film 144 with the semiconductor substrate 10 are large, resulting in stronger adhesion. Therefore, according to the fourth embodiment, even better moisture resistance can be obtained.

[0153] Furthermore, because there are steps between the fourth plane 14, the third plane 13, the first plane 11, and the second plane 12, the distance that moisture penetrates from the outside to the inside of the semiconductor device 400 increases. By increasing the distance that moisture penetrates, the moisture resistance of the semiconductor device 400 can be improved.

[0154] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment relates to a semiconductor package. Fig. 17 is a cross-sectional view showing a semiconductor device according to the fifth embodiment.

[0155] The semiconductor package 500 according to the fifth embodiment includes the semiconductor device 100 according to the first embodiment, a die pad 105, leads 106, bonding wires 107, and a molding resin 108.

[0156] The semiconductor device 100 is fixed onto the die pad 105 using an adhesive, such as a die attach film or a die attach paste.

[0157] The bonding wire 107 electrically connects the bonding pad formed by the fourth wiring layer 134 to the lead 106. The lead 106 and the die pad 105 are made of, for example, metal.

[0158] The molding resin 108 covers the semiconductor device 100, the bonding wires 107, the die pad 105 except for its rear surface, and part of the leads 106. The molding resin 108 is, for example, a plastic molding resin.

[0159] The back surface of the die pad 105 is exposed from the molding resin 108 in order to dissipate heat from the semiconductor device 100, but this back surface may be covered with the molding resin 108.

[0160] In this embodiment, the semiconductor device 100 is described as a device in which multiple semiconductor elements are formed on a single chip, but these semiconductor elements may be separated into multiple semiconductor devices. In this case, the multiple semiconductor devices are each fixed onto the die pad 105 via an adhesive.

[0161] Furthermore, in this embodiment, the semiconductor device 100 has been described, but any of the semiconductor devices 200, 300, and 400 may be used.

[0162] As described above, in the fifth embodiment, semiconductor devices 100, 200, 300, and 400 with improved moisture resistance are used, so that a highly moisture-resistant semiconductor package can be provided even if a molding resin that easily transmits moisture is used.

[0163] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0164] 10: Semiconductor substrate 11: 1st plane 12:Second plane 13:Third plane 14: 4th plane 19: Bottom surface 20: Semiconductor wafer 100, 200, 300, 400: Semiconductor device 101: Semiconductor layer 102: Circuit board 103: Scribe area 104: Dicing blade 105: Die pad 106: Lead 107: Bonding wire 108:Molding resin 109:Aperture 110: High electron mobility transistor 111: Source electrode 112: Drain electrode 113: Gate electrode 114, 121: insulating film 120: Capacitor 122: Lower electrode 123: Dielectric film 124: Upper electrode 131: 1st wiring layer 132: 2nd wiring layer 133: 3rd wiring layer 134: 4th wiring layer 141: Seventh insulating film 142: Fifth insulating film 143: First insulating film 144: Third insulating film 145: 10th insulating film 150:End 151: Sixth insulating film 152: 8th insulating film 153: Fourth insulating film 154: Second insulating film 155: 9th insulating film 161: Buffer layer 162: Channel layer 163:Electron supply layer 171: 4th area 172: Third area 173:First area 174:Second area 175: 5th area 181: 4th part 182: 3rd part 183: Part 1 184:Second part 185: 5th part 500: Semiconductor packages

Claims

1. a semiconductor substrate; a semiconductor element formed on the semiconductor substrate; a first insulating film covering the semiconductor element; a second insulating film formed on the first insulating film; a third insulating film formed on the second insulating film; and the first insulating film and the third insulating film are less permeable to moisture than the second insulating film, the dielectric constant of the second insulating film is lower than the dielectric constants of the first insulating film and the third insulating film; the first insulating film has a first portion in contact with a first region on the upper surface of the semiconductor substrate; The semiconductor device, wherein the third insulating film has a second portion in contact with the top surface and side surfaces of the first portion and a second region of the top surface of the semiconductor substrate that is farther from the semiconductor element than the first region.

2. the first insulating film and the third insulating film contain silicon nitride or silicon oxide, The semiconductor device according to claim 1 , wherein said second insulating film includes polyimide.

3. The insulating film includes a plurality of inorganic films each of which is at least one type selected from the group consisting of a silicon nitride film and a silicon oxide film; 3. The semiconductor device according to claim 1, wherein the third insulating film is the farthest from the semiconductor element among the plurality of inorganic films.

4. The semiconductor substrate is a first plane formed in the first region; a second plane formed in the second region; and 3. The semiconductor device according to claim 1, wherein the second plane is closer to the bottom surface of the semiconductor substrate than the first plane.

5. The semiconductor substrate is A substrate; a semiconductor layer formed on the substrate, The semiconductor device according to claim 4 , wherein said second plane is formed in said semiconductor layer.

6. 3. The semiconductor device according to claim 1, further comprising a wiring layer formed on said second insulating film and covered with said third insulating film.

7. a fourth insulating film formed between the first insulating film and the semiconductor element; a fifth insulating film formed between the fourth insulating film and the semiconductor element; and the fifth insulating film is less permeable to moisture than the second insulating film and the fourth insulating film; the fourth insulating film has a lower dielectric constant than the first insulating film, the third insulating film, and the fifth insulating film; the fifth insulating film has a third portion in contact with a third region on the top surface of the semiconductor substrate that is closer to the semiconductor element than the first region, 3. The semiconductor device according to claim 1, wherein the first insulating film is in contact with an upper surface and a side surface of the third portion.

8. the fourth insulating film includes polyimide; 8. The semiconductor device according to claim 7, wherein said fifth insulating film contains silicon nitride or silicon oxide.

9. 3. The semiconductor device according to claim 1, wherein the semiconductor element includes a high electron mobility transistor.

10. 3. A monolithic microwave integrated circuit comprising the semiconductor device according to claim 1.

11. The semiconductor device according to claim 1 or 2, a resin that seals at least the top and side surfaces of the semiconductor device.

12. forming a semiconductor device on a semiconductor substrate; forming a first insulating film covering the semiconductor element and having a first portion in contact with a first region on the top surface of the semiconductor substrate; forming a second insulating film on the first insulating film; forming a third insulating film on the second insulating film; and the first insulating film and the third insulating film are less permeable to moisture than the second insulating film, the dielectric constant of the second insulating film is lower than the dielectric constants of the first insulating film and the third insulating film; A method for manufacturing a semiconductor device, wherein the third insulating film is formed to have a second portion that contacts the top surface and side surfaces of the first portion and a second region on the top surface of the semiconductor substrate that is farther from the semiconductor element than the first region.

Images