Semiconductor Devices

Abstract

To reduce a signal transmission loss in a semiconductor device.SOLUTION: A wiring substrate 10 includes a first signal pad 141a and a pair of first ground pads 142a. A semiconductor element 20 includes a second signal pad 221a and a pair of second ground pads 222a. A first bump 301 formed on the second signal pad 221a is electrically connected to the first signal pad 141a via a first bonding part 401. In each second ground pad 222a, a second bump 302a and a third bump 302b arranged on the second signal pad 221a side relative to the second bump 302a are formed. The second bump 302a is electrically connected to the first ground pad 142a via a second bonding part 402. A part of the second bonding part 402 is positioned on the first signal pad 141a side relative to the first ground pad 142a, and a distance between the first signal pad 141a and the second bonding part 402 is narrower than a distance between the first signal pad 141a and the first ground pad 142a.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices that handle high frequencies such as millimeter waves have been known. In such semiconductor devices, for example, a semiconductor element is mounted on a wiring substrate on which a wiring pattern is formed. The wiring pattern and the semiconductor element are electrically connected, for example, via bumps (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-230343 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device that handles high frequencies as described above, it is preferable to arrange the wiring patterns so as to minimize signal transmission loss on the wiring board.

[0005] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a semiconductor device capable of reducing signal transmission loss. [Means for solving the problem]

[0006] The semiconductor device includes a wiring board and a semiconductor element mounted on the wiring board, the wiring board including, on a side facing the semiconductor element, a first signal pad and a pair of first ground pads spaced apart from the first signal pad and arranged opposite each other with the first signal pad sandwiched between them in a plan view, the semiconductor element including, on a side facing the wiring board, a second signal pad and a pair of second ground pads spaced apart from the second signal pad and arranged opposite each other with the second signal pad sandwiched between them in a bottom view, the second signal pad having a first bump formed thereon. the first bump is electrically connected to the first signal pad via a first bonding portion, a second bump and a third bump are formed on each of the second ground pads and are arranged closer to the second signal pad than the second bump, at least the second bump is electrically connected to each of the first ground pads via a second bonding portion, a portion of the second bonding portion is located closer to the first signal pad than the first ground pad, and in a plan view, the distance between the first signal pad and the second bonding portion is narrower than the distance between the first signal pad and the first ground pad. [Effects of the Invention]

[0007] According to the disclosed technique, it is possible to provide a semiconductor device capable of reducing signal transmission loss. [Brief explanation of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a comparative example. [Figure 3] 1A and 1B are diagrams illustrating a semiconductor device according to a first modification of the first embodiment. [Figure 4] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second modification of the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a third modification of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] First Embodiment 1A and 1B are diagrams illustrating a semiconductor device according to a first embodiment. FIG. 1A is a cross-sectional view. FIG. 1B is a bottom view showing the side of a semiconductor element 20 facing a wiring substrate 10, mainly illustrating a wiring layer 22. FIG. 1C is a plan view showing the side of the wiring substrate 10 facing the semiconductor element 20, mainly illustrating a wiring layer 14.

[0011] Referring to FIG. 1, the semiconductor device 1 includes a wiring substrate 10, a semiconductor element 20, bumps 30, bonding portions 40, and an underfill resin 50.

[0012] 1 will be referred to as the upper side or one side, and the wiring board 10 side will be referred to as the lower side or the other side. Furthermore, the surface of each part facing the semiconductor element 20 will be referred to as the one side or upper side, and the surface facing the wiring board 10 will be referred to as the other side or lower side. However, the semiconductor device 1 can be used upside down or positioned at any angle. Furthermore, a planar view refers to viewing an object from the normal direction to the top surface of the semiconductor element 20, and a planar shape refers to the shape of the object viewed from the normal direction to the top surface of the semiconductor element 20.

[0013] The wiring board 10 includes an insulating layer 11, a wiring layer 12, an insulating layer 13, and a wiring layer 14.

[0014] The insulating layer 11 may be made of, for example, a non-photosensitive (thermosetting resin) epoxy insulating resin or polyimide insulating resin. Alternatively, the insulating layer 11 may be made of, for example, a photosensitive epoxy insulating resin or acrylic insulating resin. The insulating layer 11 may have a thickness of, for example, about 20 to 40 μm. The insulating layer 11 may contain a filler such as silica (SiO2).

[0015] The wiring layer 12 is formed on the insulating layer 11. For example, copper can be used as the material of the wiring layer 12. The thickness of the wiring layer 12 can be, for example, about 10 to 20 μm.

[0016] The insulating layer 13 is formed on the insulating layer 11 so as to cover the upper and side surfaces of the wiring layer 12. The material of the insulating layer 13 may be, for example, the same as that of the insulating layer 11. The thickness of the insulating layer 13 may be, for example, about 20 to 40 μm. The insulating layer 13 may contain a filler such as silica (SiO2).

[0017] The wiring layer 14 is formed on the insulating layer 13. The wiring layer 14 includes via wirings filled in via holes that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12, and pads and wiring patterns formed on the upper surface of the insulating layer 13. The wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via hole. The thickness of the wiring pattern that constitutes the wiring layer 14 can be, for example, about 10 to 20 μm.

[0018] The semiconductor element 20 is mounted on the wiring substrate 10. The semiconductor element 20 is an element that handles high frequency signals, for example, in the terahertz band, submillimeter wave band, millimeter wave band or higher.

[0019] The semiconductor element 20 has a semiconductor substrate 21 and a wiring layer 22. The semiconductor substrate 21 is a substrate made of, for example, silicon, GaAs, GaN, or the like. The wiring layer 22 is formed on the lower surface side of the semiconductor substrate 21. The wiring layer 22 is configured to include pads and wiring patterns.

[0020] The bumps 30 are formed on pads of the wiring layer 22. The bumps 30 are electrically connected to corresponding pads of the wiring layer 14 via bonding portions 40. An underfill resin 50 is filled between the semiconductor substrate 21 and the upper surface of the wiring substrate 10.

[0021] Here, the wiring layer 14 of the wiring board 10 and the wiring layer 22 of the semiconductor element 20 will be described in more detail.

[0022] 1(c), the wiring layer 14 includes a first signal pad 141a and a first wiring pattern 141b extending from the first signal pad 141a. The wiring layer 14 also includes a pair of first ground pads 142a and second wiring patterns 142b extending from each of the first ground pads 142a. The pair of first ground pads 142a are spaced apart from the first signal pad 141a and are arranged opposite each other with the first signal pad 141a in between in a plan view.

[0023] The pair of second wiring patterns 142b are spaced apart from the first wiring pattern 141b and are arranged opposite each other with the first wiring pattern 141b in between in a plan view. The first wiring pattern 141b and the pair of second wiring patterns 142b form a GSG (Grand / Signal / Grand) structure. A high-frequency signal from the semiconductor element 20 flows through the first wiring pattern 141b.

[0024] In FIG. 1(c), for convenience, the positions of a first bump 301, a second bump 302a, a third bump 302b, a first bonding portion 401, and a second bonding portion 402, which will be described later, as well as the wiring layer 14, are indicated by dashed lines.

[0025] 1(b), the wiring layer 22 includes a second signal pad 221a and a third wiring pattern 221b extending from the second signal pad 221a. The wiring layer 22 also includes a pair of second ground pads 222a and a fourth wiring pattern 222b extending from each of the second ground pads 222a. The pair of second ground pads 222a are spaced apart from the second signal pad 221a and are arranged opposite each other with the second signal pad 221a interposed therebetween in a bottom view. The pair of fourth wiring patterns 222b are spaced apart from the third wiring pattern 221b and are arranged opposite each other with the third wiring pattern 221b interposed therebetween in a plan view.

[0026] 1(b), the bump 30 includes a first bump 301, a second bump 302a, and a third bump 302b. Also, as shown in FIG. 1(c), the bonding portion 40 includes a first bonding portion 401 and a second bonding portion 402.

[0027] A first bump 301 is formed on the second signal pad 221a, and the first bump 301 is electrically connected to the first signal pad 141a via a first bonding portion 401. A second bump 302a and a third bump 302b are formed on each second ground pad 222a, the third bump 302b being disposed closer to the second signal pad 221a than the second bump 302a. At least the second bump 302a is electrically connected to each first ground pad 142a via a second bonding portion 402.

[0028] The electrical connection between the first ground pad 142a and the second ground pad 222a can be reliably established by the second bump 302a and the second bonding portion 402. Therefore, the third bump 302b may or may not be connected to the second bonding portion 402. In other words, it is sufficient that at least the second bump 302a of the second bump 302a and the third bump 302b is electrically connected to the first ground pad 142a via the second bonding portion 402. However, the second bonding portion 402 must be connected to the first ground pad 142a.

[0029] The first bump 301, the second bump 302a, and the third bump 302b are, for example, metal posts. Examples of metal posts include copper posts. The first bump 301, the second bump 302a, and the third bump 302b are, for example, columnar. In this embodiment, the first bump 301, the second bump 302a, and the third bump 302b are cylindrical. The diameter of the first bump 301 is equal to the diameter of the second bump 302a. The diameter of the third bump 302b is smaller than the diameter of the second bump 302a. By making the diameter of the third bump 302b smaller than the diameter of the second bump 302a, two bumps can be arranged even if the second ground pad 222a has a small area.

[0030] For example, solder can be used as the material of the first bonding portion 401 and the second bonding portion 402. Examples of the solder material include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Bi, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu.

[0031] A portion of the second joint 402 is located closer to the first signal pad 141a than the first ground pad 142a. In plan view, a distance P2 between the first signal pad 141a and the second joint 402 is narrower than a distance P1 between the first signal pad 141a and the first ground pad 142a. The distance P1 can be, for example, about 50 μm, and the distance P2 can be, for example, about 30 μm.

[0032] 2 is a cross-sectional view illustrating a semiconductor device according to a comparative example. In semiconductor device 1X, each pad on wiring layer 22 and each pad on wiring layer 14 are connected by one bump 30. Furthermore, bonding portion 40 does not protrude from each pad on wiring layer 14, and the spacing between adjacent pads constituting wiring layer 14 is P1.

[0033] Because high-frequency signals flow through the wiring layer 14, it is preferable that the spacing P1 be as narrow as possible. The narrower the spacing P1, the more the transmission loss of high-frequency signals can be reduced. However, the minimum value of spacing P1 is determined by the design rules for the wiring board 10, and spacing P1 cannot be made narrower than this. The design rules for the wiring board 10 are determined by the material used to form the wiring board 10 and the process for forming the wiring layer 14.

[0034] On the other hand, since the wiring layer 22 of the semiconductor element 20 is formed by a semiconductor process, fine wiring can be formed, and the interval between the second signal pad 221a and the second ground pad 222a can be made narrower than the interval P1. Therefore, as shown in Fig. 1, in the semiconductor device 1, in a plan view, the interval between the second signal pad 221a and the second ground pad 222a is made narrower than the interval P1 between the first signal pad 141a and the first ground pad 142a, and two bumps (a second bump 302a and a third bump 302b) are arranged on each second ground pad 222a.

[0035] This allows the bottom end of the third bump 302b to be closer to the first signal pad 141a, and the second bonding portion 402 provided near the bottom end of the third bump 302b to extend from above the first ground pad 142a toward the first signal pad 141a. This allows the spacing P2 to be narrower than the spacing P1. In other words, the semiconductor device 1 achieves the same effect as when the spacing P1 is narrowed, and can reduce transmission loss of high-frequency signals more than the semiconductor device 1X shown in FIG. 2. As a result, the antenna characteristics can be improved.

[0036] It is preferable that the third bump 302b partially or entirely protrudes from above the first ground pad 142a toward the first signal pad 141a in plan view, which makes it easy to make the second bonding portion 402 provided near the lower end of the third bump 302b protrude from above the first ground pad 142a toward the first signal pad 141a.

[0037] <Modification of the first embodiment> In the modified example of the first embodiment, examples in which the shape of the bumps or bonding portions is different are shown. Note that in the modified example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0038] 3 is a diagram illustrating a semiconductor device according to Modification 1 of the first embodiment. In the semiconductor device 1A shown in FIG. 3, the second bonding portion 402 includes a first portion 402a connected to the second bump 302a and a second portion 402b connected to the third bump 302b. The first portion 402a and the second portion 402b are spaced apart from each other and are not in contact with each other. In this manner, the second bonding portion 402 may be divided into a plurality of portions that are spaced apart from each other.

[0039] The electrical connection between the first ground pad 142a and the second ground pad 222a can be reliably established by the second bump 302a and the first portion 402a. Therefore, the third bump 302b does not need to be connected to the second portion 402b. However, the second portion 402b must be connected to the first ground pad 142a.

[0040] 4 is a cross-sectional view illustrating a semiconductor device according to Modification 2 of the first embodiment. In the semiconductor device 1B shown in FIG. 4, each bump 30 has a pointed tip and includes a wide portion 302c located on the semiconductor element 20 side and a narrow portion 302d protruding from the wide portion 302c toward the wiring substrate 10 side. In this way, the shape of each bump 30 may be other than cylindrical.

[0041] The bumps 30 shown in FIG. 4 can be formed on each pad constituting the wiring layer 22 by a wire bump method using a metal wire such as gold. Specifically, for example, a predetermined length of metal wire is extended from the capillary of a wire bonder, and the tip of the metal wire is rounded into a spherical shape by discharge. The capillary is then lowered to bring the spherical tip of the metal wire into contact with the pad and bonded to the pad by heating and ultrasonic vibration. Next, the metal wire is fixed with a clamper while the capillary is raised, and the metal wire is torn off. This forms a bump 30 with a pointed tip that is electrically connected to the pad.

[0042] The pointed tip of the bump 30 suppresses the amount of extrusion of the second bonding portion 402 by the bump 30, and reduces the possibility of short-circuiting between the first signal pad 141a and the second bonding portion 402.

[0043] 5 is a cross-sectional view illustrating a semiconductor device according to Modification 3 of the first embodiment. In the semiconductor device 1C shown in FIG. 5, each bump 30 is cylindrical and has the same diameter. If the second ground pad 222a has a relatively large area, each bump 30 can have only one type of shape. In this case, there is an advantage in manufacturing because there is no need to prepare multiple types of bumps 30.

[0044] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0045] 1, 1A, 1B, 1C 10. Wiring board 11,13 Insulating layer 12,14 wiring layer 20 Semiconductor elements 21 Semiconductor substrate 22 wiring layer 30 Bump 40 Joint 50 Underfill resin 141a First Signal Pad 141b First wiring pattern 142a 1st Ground Pad 142b Second wiring pattern 221a Second Signal Pad 221b Third wiring pattern 222a Second Ground Pad 222b 4th wiring pattern 301 First Bump 302a 2nd Bump 302b 3rd Bump 302c wide part 302d narrow section 401 1st joint 402 Second joint 402a Part 1 402b Part 2

Claims

1. A wiring board; a semiconductor element mounted on the wiring substrate, The wiring board has, on a side facing the semiconductor element, a first signal pad; a pair of first ground pads spaced apart from the first signal pad and arranged opposite to each other across the first signal pad in a plan view; The semiconductor element has, on the side facing the wiring board, a second signal pad; a pair of second ground pads spaced apart from the second signal pad and arranged opposite to each other across the second signal pad in a bottom view; a first bump is formed on the second signal pad, and the first bump is electrically connected to the first signal pad via a first bonding portion; a second bump and a third bump disposed closer to the second signal pad than the second bump are formed on each of the second ground pads, and at least the second bump is electrically connected to each of the first ground pads via a second bonding portion; a portion of the second joint portion is located closer to the first signal pad than the first ground pad; a first signal pad and a second bonding portion, the second bonding portion being spaced apart from each other in a plane view; a second signal pad and a first ground pad being spaced apart from each other in a plane view;

2. the second bump and the third bump are cylindrical, The semiconductor device according to claim 1 , wherein the diameter of said third bump is smaller than the diameter of said second bump.

3. the first bump, the second bump, and the third bump are cylindrical; The semiconductor device according to claim 1 , wherein the first bump, the second bump, and the third bump have the same diameter.

4. 2. The semiconductor device according to claim 1, wherein the first bump, the second bump, and the third bump each include a wide portion located on the semiconductor element side and a narrow portion protruding from the wide portion toward the wiring substrate side.

5. the second bonding portion includes a first portion connected to the second bump and a second portion connected to the third bump; The semiconductor device according to claim 1 , wherein the first portion and the second portion are spaced apart from each other.

6. 5. The semiconductor device according to claim 1, wherein the third bump partially or entirely protrudes from the first ground pad toward the first signal pad in a plan view.

7. 5. The semiconductor device according to claim 1, wherein a distance between the second signal pad and the second ground pad is narrower than a distance between the first signal pad and the first ground pad in a plan view.

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