Self-clearing data transfer support method, system, computer program, and computer-readable recording medium

Abstract

To provide a self-clearing data move assist (DMA) engine.SOLUTION: Aspects include receiving a request from a requesting system to move data from a source memory on a source system to a target memory on a target system. The receiving is at a first hardware engine configured to access the source memory and the target memory. In response to receiving the request, the first hardware engine reads the data from the source memory, and writes the data to the target memory. In response to the reading being completed, the first hardware engine transmits a data clearing request to a second hardware engine that is configured to access the source memory. The data clearing request specifies a location of the data in the source memory to be cleared.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates generally to computer processing, and more particularly to a self-clearing data move assist (DMA) engine. [Background technology]

[0002] DMA, short for "data movement assistance" or "direct memory access," refers to a feature of computer systems that allows certain hardware subsystems to access main system memory independently of the central processing unit (CPU). Without DMA, when the CPU is using programmed input / output (I / O), the CPU is typically fully occupied for the entire duration of the read or write operation and is therefore unavailable to perform other work. With DMA, the CPU initiates the data transfer first, and then the CPU can perform other operations while the transfer is in progress. The CPU receives an interrupt from the DMA controller or DMA engine when the I / O operation is complete. DMA is useful when the CPU cannot keep up with the data transfer rate or when the CPU needs to perform other work while waiting for the I / O data transfer to complete. Many hardware systems, including disk drive controllers, graphics cards, network cards, and sound cards, use DMA. DMA is also used for data transfers within multicore processor chips. A computer with DMA channels can transfer data to and from devices with much less CPU overhead than a computer without DMA channels. Similarly, processing elements within a multicore processor can transfer data to and from the multicore processor's local memory without monopolizing the multicore processor's processor time, allowing computation and data transfer to proceed simultaneously. Summary of the Invention [Problem to be solved by the invention]

[0003] The security of computer hardware, such as DMA engines, is becoming increasingly important as hardware is frequently used by many individual users in virtualized environments such as cloud systems. Even without malicious intent, the expanded use of virtualization in I / O adapters allows the workload of one process to be overlaid onto the remaining workspace of another process, allowing the latter process to view the leftover data. Unless software voluntarily clears this memory, sensitive data can remain exposed and become visible to unrelated, and potentially unsecured, processes. Embodiments of the present disclosure are directed to providing a self-clearing data movement assistance (DMA) engine. [Means for solving the problem]

[0004] An embodiment of the present invention is directed to a self-clearing data movement assist (DMA) engine. A non-limiting example of a computer-implemented method includes receiving a request from a requesting system to move data from a source memory of a source system to a target memory of a target system. The receiving is in a first hardware engine configured to access the source memory and the target memory. In response to receiving the request, the first hardware engine reads the data from the source memory and writes the data to the target memory. In response to completing the read, the first hardware engine transmits a data clear request to a second hardware engine configured to access the source memory. The data clear request specifies the location of the data in the source memory to be cleared.

[0005] Other embodiments of the present invention implement features of the above-described methods in computer systems and computer program products.

[0006] Further technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, reference is made to the detailed description and drawings.

[0007] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the conclusion of this specification. The foregoing and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram of a system for providing a self-clearing data movement assistance (DMA) engine in accordance with one or more embodiments of the present invention. [Figure 2] 1 is a flowchart of a method performed by a self-clearing DMA engine in accordance with one or more embodiments of the present invention. [Figure 3] FIG. 1 is a diagram of a cloud computing environment in accordance with one or more embodiments of the present invention. [Figure 4] FIG. 2 is a diagram of abstraction model layers in accordance with one or more embodiments of the present invention. [Figure 5] FIG. 1 is a diagram of a system for providing a self-clearing DMA engine in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] The diagrams depicted herein are exemplary. There may be many variations to the diagrams or the operations depicted in the diagrams without departing from the spirit of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Also, the term "coupled" and variations thereof indicate that there is a communication path between two elements, and do not necessarily imply a direct connection between the elements without an intervening element / connection between them. All of these variations are intended to be part of this specification.

[0010] One or more embodiments of the present invention provide a data movement assist engine (DMA) engine that automatically clears data read from a source storage location after moving the data to a target storage location. Thus, one or more embodiments of the present invention prevent any subsequent processes from seeing the data in the source location after moving the data to its new owner or location.

[0011] The current approach to clearing a source location after moving it involves the DMA engine issuing an interrupt to the requesting host processor when the data movement is complete. The host processor then issues a new command to the DMA engine to clear the data in the source location, for example, by writing all zeros or random data to the source location. The modern approach to clearing a source location is software-driven and requires two interrupts to the host processor's central processing unit (CPU): one when the data movement is complete and another when the clear operation is complete. Depending on how long it takes the CPU to issue the clear command, another process may already be using the source location and therefore potentially reading data that it should not have read.

[0012] One or more embodiments of the present invention address one or more of the above-mentioned deficiencies of modern systems by incorporating the clearing function into hardware, which prevents the clearing process from being overridden by software processes. Furthermore, performance is improved by not having a separate operation invoked to clear memory after moving the data to the target location. Furthermore, when interfacing to dynamic random access memory (DRAM), performance is improved by performing the wipe or clear closer to the time of the move or transfer, since the DRAM banks may still be open and in a lower latency state.

[0013] Turning now to Figure 1, a block diagram 100 of a system for providing a self-clearing DMA engine is generally shown, in accordance with one or more embodiments of the present invention. All or a portion of each of the components shown in Figure 1 may be performed by computer 501 of Figure 5, by cloud computing node 10 of Figure 3, or both. The components shown in the embodiment of Figure 1 include host system 170, DMA engine 110, DMA engine 135, and target system 150.

[0014] The host system 170 shown in Figure 1 includes, among other elements, a central processing unit (CPU) 175 and host memory 165. The target system 150 shown in Figure 1 includes, among other elements, a CPU 185 and target memory 155. The labels "host system" and "target system" refer to the processing performed by each of the processors in the data movement processing described herein, with the host system 170 controlling the DMA engines 110, 135 to perform the data movement. According to one or more embodiments of the present invention, the target system 150 can be a local system, such as a laptop or other mobile device.

[0015] 1 includes a read port (not shown) connected to read channel 130, which is coupled to host memory 165. Read channel 130 includes a read control bus for specifying a specific location in host memory 165 (e.g., by address and length) and a read data bus for returning read data to data buffer 140 on DMA engine 110. DMA engine 110 also includes a write port (not shown) connected to write channel 160, which is coupled to target memory 155. Write channel 160 includes a write control bus for specifying a location in target memory 155 and a write data bus for transferring data from data buffer 140 to a location in target memory 155. DMA engine 110 of FIG. 1 is a full-duplex state machine or processor that includes a bus-attached read port and a write port, configured such that the read port and the write port are coupled through data buffer 140.

[0016] DMA engine 135 shown in FIG. 1 includes a read port (not shown) connected to read channel 115, which is connected to target memory 155. Read channel 115 includes a read control bus for specifying a specific location in target memory 155 (e.g., by address and length) and a read data bus for returning read data from host memory 165 to data buffer 105 on DMA engine 135. DMA engine 135 also includes a write port (not shown) connected to write channel 190, which is connected to host memory 165. Write channel 190 includes a write control bus for specifying a location in host memory 165 and a write data bus for transferring data from data buffer 105 to a location in host memory 165. DMA engine 135 is a full-duplex state machine or processor with the read and write ports attached to buses connected such that the read and write ports are coupled through data buffer 105.

[0017] 1, DMA engine 110 and DMA engine 135 are instantiated symmetrically such that DMA engine 110 issues reads to host memory 165 and writes to target memory 155, and DMA engine 135 independently issues reads to target memory 155 and writes to host memory 165, thereby controlling data movement in both directions. DMA engine 110 is controlled via control port 120, and DMA engine 135 is controlled via control port 125. As shown in the embodiment of FIG. 1, CPU 175 of host system 170 sends descriptors to control port 120 of DMA engine 110, control port 125 of DMA engine 135, or both, via a control port (not shown) on host system 170 and control channel 145. Control port 120, 125 writes descriptors, which are sequences of instructions that explain to DMA engine 110, 135 where to move data (address) and how much data to move (length). DMA engine 110, 135 includes a descriptor parser to determine what action to take based on the descriptors it receives. According to one or more embodiments of the present invention, the DMA engine's descriptor parser in DMA engine 110, 135 can support multiple channels and can simultaneously maintain several separate sequences of transfer operations.

[0018] 1, a data clearing control channel 180 is cross-coupled between the two duplicated DMA engines 110, 135. According to one or more embodiments of the present invention, the CPU 175 issues a move descriptor or a read / write (R / W) descriptor to the DMA engine 110. The move descriptor specifies the number of bits to read, or length, starting at a specified address in the host memory 165 and an address in the target memory 155 to which the data should be written. In response to receiving the move descriptor, the DMA engine 110 will read data from the host memory 165, write data to the target memory 155, and remove data from the host memory 165.

[0019] According to one or more embodiments of the present invention, after the read phase of DMA engine 110 is completed, the read portion of the transfer descriptor (read address and length) sent to control port 120 of DMA engine 110 is queued to DMA engine 135 via data clear control channel 180 to issue a write request back to the original read address and length, removing or wiping the data from host memory 165 at the location specified by the read address and length. According to one or more embodiments of the present invention, all zeros or all ones are written to the read address location for the specified length. According to one or more embodiments of the present invention, a series of random bits or any meaningless data pattern is written to the location specified by the read address and length. In this way, the original data in host memory is cleared so that only a remaining copy of the data is at the target address in target memory 155.

[0020] A similar process can be implemented when data is read from target memory 155 and written to host memory 165. In this scenario, after the read phase of DMA engine 135 is completed, the read portion of the transfer descriptor (read address and length) sent to DMA engine 135's control port 125 is queued to DMA engine 110 via data clear control channel 180 to issue a write request back to the original read address and length, removing or wiping the data from target memory 155 at the location specified by the read address and length. According to one or more embodiments of the present invention, all zeros or all ones are written to the read address location for the specified length. According to one or more embodiments of the present invention, a series of random bits or any meaningless data pattern is written to the location specified by the read address and length. In this way, the original data in target memory 155 is cleared so that only a remaining copy of the data resides at the target address in host memory 165.

[0021] The embodiments described herein for block diagram 100 of FIG. 1 may be implemented in any suitable logic, which, in various embodiments, as referred to herein, may include any suitable hardware (e.g., a processor, an embedded controller, or an application specific integrated circuit, among others), software (e.g., an application, among others), firmware, or any suitable combination of hardware, software, and firmware.

[0022] Turning now to Figure 2, a flowchart of a method 200 performed by a self-clearing DMA engine is shown generally, in accordance with one or more embodiments of the present invention. All or a portion of the processing shown in Figure 2 may be performed by, for example, DMA engine 110 or DMA engine 135 of Figure 1.

[0023] In block 202 of FIG. 2, a request to move data from a source location to a target location is received. The request is received by a first hardware engine configured to read from the source location and write to the target location. According to one or more embodiments of the present invention, if the first hardware engine is a DMA engine coupled to another DMA engine, an instance of one of the coupled DMA engines receives the data movement request in the form of a descriptor, which is received via the DMA engine's control port. According to one or more embodiments of the present invention, the descriptor includes a list of instructions, including a read address (corresponding to the read port's memory address space), a write address (corresponding to the write port's memory address space), and a data count or length indicating how much data should be moved from the read space to the write space. According to one or more embodiments of the present invention, the descriptor can be chained to subsequent descriptors and can contain various address space identifiers (e.g., transaction identifiers).

[0024] For example, with reference to the components shown in Figure 1, the first hardware engine may be performed by DMA engine 110 coupled to DMA engine 135 via data clear control channel 180. In this example, the processing performed in block 202 of Figure 2 includes sending a descriptor by CPU 175 of host system 170 to DMA engine 110 via control channel 145. The descriptor may specify a read address in host memory 165, a write address in target memory 155, and a data count of the number of bits or bytes to move (starting at the read address).

[0025] At block 204, the data movement request is processed by a first hardware engine. According to one or more embodiments of the present invention, the processing includes reading data from a source memory and writing data to a target memory. When the read portion of the processing at block 204 is completed, processing at block 206 can be performed to remove the data from the source memory. The processing at block 206 begins with the first hardware engine transmitting a request to a second hardware engine to remove or clear the data from the source memory. In response to receiving the request, the second hardware engine clears the locations in the source memory, for example, by writing all zeros or a random value to the locations in the source memory. According to one or more embodiments of the present invention, the processing at block 206 overlaps in time with the processing at block 204, particularly with the writing of data to the target memory.

[0026] Referring to the above example, in block 204, read channel 130 is used to perform the read portion of the descriptor, thereby moving the data to data buffer 140 of DMA engine 110. Next, write channel 160 is used to perform the write portion of the descriptor, moving the data from buffer 140 of DMA engine 110 to target memory 155 of target system 150. According to one or more embodiments of the present invention, once the data has been moved to data buffer 140 of DMA engine 110, the processing in block 206 can be performed. In block 206, the descriptor received in block 202 is queued in data clearing control channel 180 as a write request to DMA engine 135. According to one or more embodiments of the present invention, the queued descriptor is generated by DMA engine 110 by utilizing the descriptor received in block 202 and modifying the descriptor to generate a write request to the source memory location. The write request can specify a value to be written to clear the source memory location. Writes are performed by DMA engine 135 through write channel 190. Note that read channel 115 is not used in this mode.

[0027] In block 208, the first hardware engine receives notification from the second hardware engine that the clearing of the source memory location is complete. In response to receiving the notification, the first hardware engine may notify the requesting system that the request to move the data is complete. According to one or more embodiments of the present invention, the notification to the requesting system may be delayed until all portions of the descriptor (including the data movement and clearing) have been executed.

[0028] Referring again to the example above, once the wipe write is completed by DMA engine 135, it notifies DMA engine 110 over secondary or data clearing control channel 180 that this clearing was successfully completed, and DMA engine 110 determines that this portion of the descriptor list is complete.

[0029] According to one or more embodiments of the present invention, the process shown in FIG. 2 is pipelined to allow DMA engine 110 reads to proceed ahead of wipes performed by DMA engine 135. In this mode, DMA engine 110 "scoreboards" all pending completions. Once all data movements and dependent wipes are complete, DMA engine 110 notifies host system 170's CPU 175 via control port 120 of the overall completion status of the conflicting descriptor chains. This entire process can occur simultaneously or sequentially by initiating descriptors on control ports 120 or 125. If an exception occurs (either within the DMA engine itself or via an error indication on the associated bus), the detection engine can notify host system 170's CPU 175 via control port 120 that the action and / or the associated wipe did not complete successfully and that host interaction is required before this memory can be reused.

[0030] A list of example descriptors follows:

[0031] sourceAddr=16, destinationAddr=256 len=16 (meaning wipes 16 to 31)

[0032] sourceAddr=32, destinationAddr=272 len=16 (meaning wipe 32 to 47)

[0033] sourceAddr=128, destinationAddr=288 len=16 (meaning wipe from 128 to 143)

[0034] In this example, according to one or more embodiments of the present invention, the requesting CPU may be notified once after all three portions of the descriptor list have been executed, i.e., when the data has been moved from the source storage location to the destination (or target) storage location and the data has been cleared from the source storage location. According to one or more other embodiments of the present invention, the requesting CPU may be notified after each portion of the descriptor list has been executed.

[0035] The process flow diagram of Figure 2 is not intended to indicate that operations should be performed in any particular order or that all of the operations shown in Figure 2 should be included in every case. Furthermore, the process shown in Figure 2 may include any suitable number of additional operations.

[0036] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementations of the teachings recited herein are not limited to cloud computing environments. Rather, embodiments of the invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0037] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and published with minimal administrative effort or interaction with the service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0038] The characteristics are as follows:

[0039] On-Demand Self-Service: Cloud customers can unilaterally provide computing power, such as server time and network storage, automatically as needed, without the need for human interaction with the service provider.

[0040] Broad Network Access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0041] Resource Pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with dynamic allocation and reallocation of various physical and virtual resources according to demand. Location independence is meant in that consumers generally have no control or knowledge of the exact location of the resources provided, and location may be specified at a higher level of abstraction (e.g., country, state, or data center).

[0042] Rapid Elasticity: Capacity is provisioned quickly and elastically, sometimes automatically, to quickly scale out, and can be quickly released to quickly scale in. To the consumer, the capacity available to provision often appears unlimited and can be purchased at any time in any quantity.

[0043] Metered Services: Cloud systems automatically control and optimize resource utilization by leveraging metering capabilities at several levels of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource utilization can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0044] The service model is as follows:

[0045] Software as a Service (SaaS): The consumer is provided with the ability to use the provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through a thin-client interface, such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0046] Platform as a Service (PaaS): The ability provided to a consumer is to deploy applications that the consumer creates or acquires, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the environment that hosts the applications.

[0047] Infrastructure as a Service (IaaS): The capability provided to a customer is the provision of processing, storage, networking, and other basic computing resources on which the customer can deploy and run any software, which may include operating systems and applications. The customer does not manage or control the underlying cloud infrastructure, but has limited control over the selection of operating systems, storage, deployed applications, and in some cases, networking components (e.g., host firewalls).

[0048] The implementation model is as follows:

[0049] Private Cloud: The cloud infrastructure is operated solely for the organization. The cloud infrastructure can be managed by the organization or a third party and can be on-site or off-site.

[0050] Community Cloud: Cloud infrastructure is shared by several organizations and supports a unique community of shared concerns (e.g., mission, security requirements, policies, and compliance considerations). Cloud infrastructure can be managed by the organization or a third party and can reside on-site or off-site.

[0051] Public cloud: The infrastructure is available to the general public or large industry organizations and is owned by organizations that sell cloud services.

[0052] Hybrid Cloud: A cloud infrastructure is a composition of two or more clouds (private, community, or public) that remain unique entities but are tied together with standard or proprietary technologies that allow for the portability of data and applications (e.g., cloud bursting for load balancing between clouds).

[0053] A cloud computing environment is service-oriented, with a focus on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0054] Referring now to FIG. 3, an exemplary cloud computing environment 50 is depicted. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10, and local computing devices used by cloud users, such as, for example, a personal digital assistant (PDA) or cellular phone 54A, a desktop computer 54B, a laptop computer 54C, or an automobile computer system 54N, or combinations thereof, can communicate with the cloud computing nodes 10. The nodes 10 can also communicate with each other. The nodes 10 can be grouped physically or virtually within one or more networks, such as private, community, public, or hybrid clouds, or combinations thereof, as described above (not shown). This enables the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service, eliminating the need for cloud users to maintain resources on their local computing devices. The types of computing devices 54A-54N shown in FIG. 3 are for illustrative purposes only, and it is understood that computing node 10 and cloud computing environment 50 can communicate with any type of computerized device over any type of network and / or network-addressable connection (e.g., using a web browser).

[0055] Referring now to Figure 4, a set of functional abstraction layers provided by the cloud computing environment 50 (Figure 3) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 4 are for illustrative purposes only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0056] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, RISC (reduced instruction set computer) architecture-based servers 62, servers 63, blade servers 64, storage devices 65, and network and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0057] The virtualization layer 70 provides an abstraction layer that can provide instances of virtual entities such as virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0058] In one example, the management layer 80 may provide the following functions: Resource provisioning 81 dynamically procures computing and other resources utilized to perform tasks within the cloud computing environment; Metering and pricing 82 tracks costs as resources are utilized within the cloud computing environment and bills or invoices for the usage of these resources; in one example, these resources may include application software licenses; Security validates cloud users and tasks and protects data and other resources; User portal 83 provides users and system administrators with access to the cloud computing environment; Service level management 84 allocates and manages cloud computing resources to meet required service levels; and Service level agreement (SLA) planning and fulfillment 85 pre-provisions and procures cloud computing resources to anticipate future requirements according to SLAs.

[0059] The workload tier 90 provides examples of functions that can utilize a cloud computing environment. Examples of workloads and functions that can be provided from this tier include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and data encryption / decryption 96.

[0060] It is understood that one or more embodiments of the present invention can be implemented in conjunction with any type of computing environment now known or later developed.

[0061] Turning now to FIG. 5, a computer system 500 for performing textbook content reorganization based on classroom analysis is generally illustrated, in accordance with one or more embodiments of the present invention. All or a portion of the computer system 500 illustrated in FIG. 5 may be executed by one or more cloud computing nodes 10 of FIG. 3. The methods described herein may be implemented in hardware, software (e.g., firmware), or a combination thereof. In one or more exemplary embodiments of the present invention, the methods described herein are implemented in hardware as part of a microprocessor of a special-purpose or general-purpose digital computer, such as a personal computer, workstation, minicomputer, or mainframe computer. Thus, the system 500 may include a general-purpose computer or mainframe 501 capable of simultaneously executing multiple instances of an operating system (O / S).

[0062] In one or more exemplary embodiments of the present invention, with respect to a hardware architecture such as that shown in FIG. 5 , a computer 501 includes one or more processors 505, a memory 510 coupled to a memory controller 515, and one or more input / output (I / O) devices 540, 545 (or peripherals) communicatively coupled via a local I / O controller 535. The I / O controller 535 may be, for example, but not limited to, one or more buses or other wired or wireless connections as known in the art. The I / O controller 535 may have additional elements omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communication. Furthermore, the local interface may include address, control, and / or data connections to enable appropriate communication between the aforementioned components. The I / O controller 535 may include multiple sub-channels configured to access the output devices 540 and 545. The sub-channels may include fiber optic communication ports.

[0063] Processor 505 is a hardware device for executing software stored in storage 520, such as cache storage, or memory 510, among other things. Processor 505 can be any custom-made or commercially available processor, a central processing unit (CPU), a coprocessor among several processors associated with computer 501, a semiconductor-based microprocessor (in the form of a microchip or chipset), a microprocessor, or generally any device for executing instructions.

[0064] The memory 510 may include any one or combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and non-volatile memory elements (e.g., ROM, erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), tape, compact disk read-only memory (CD-ROM), disk, diskette, cartridge, cassette, or the like). Moreover, the memory 510 may incorporate electronic, magnetic, optical, or other types of storage media, or combinations thereof. It should be noted that the memory 510 may have a distributed architecture in which various components are located remotely from each other but are accessible by the processor 505.

[0065] The instructions in memory 510 may include one or more separate programs, each containing an ordered list of executable instructions for performing logical functions. In the example of Figure 5, the instructions in memory 510 are a suitable operating system (OS) 511. The operating system 511 essentially controls the execution of other computer programs and provides scheduling, input / output control, file and data management, memory management, and communication control and related services.

[0066] According to one or more embodiments of the present invention, memory 510 may include multiple logical partitions (LPARs), each running an instance of an operating system. The LPARs may be managed by a hypervisor, which may be a program stored in memory 510 and executed by processor 505.

[0067] In one or more exemplary embodiments of the present invention, a conventional keyboard 550 and mouse 555 can be coupled to the input / output controller 535. Other output devices, such as I / O devices 540, 545, can include input devices, for example, but not limited to, printers, scanners, microphones, and the like. Finally, I / O devices 540, 545 can further include devices that communicate both input and output, for example, but not limited to, network interface cards (NICs) or modulators / demodulators (for accessing other files, devices, systems, or networks), radio frequency (RF) or other transceivers, telephone interfaces, bridges, routers, and the like. System 500 can further include a display controller 525 coupled to a display 530.

[0068] In one or more exemplary embodiments of the present invention, system 500 may further include a network interface 560 for coupling to a network 565. Network 565 may be an IP-based network for communication between computer 501 and any external servers, clients, and the like over a broadband connection. Network 565 transmits and receives data between computer 501 and external systems. In an exemplary embodiment, network 565 may be a managed IP network operated by a service provider. Network 565 may be implemented wirelessly using wireless protocols and technologies such as WiFi, WiMax, etc. Network 565 may also be a packet-switched network such as a local area network, a wide area network, a metropolitan area network, the Internet network, or other similar types of network environments. Network 565 may be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN), a personal area network (PAN), a virtual private network (VPN), an intranet, or other suitable network system and includes equipment for receiving and transmitting signals.

[0069] If computer 501 is a PC, workstation, intelligent device, or the like, the instructions in memory 510 may further include a basic input / output system (BIOS) (omitted for simplicity). The BIOS is a set of essential software routines that initialize and test hardware at startup, start OS 511, and support data transfer between hardware devices. The BIOS is stored in ROM so that computer 501 can execute the BIOS when it becomes active.

[0070] When computer 501 is operating, processor 505 is configured to execute instructions stored in memory 510, to communicate data to and from memory 510, and to generally control the operation of computer 501 in accordance with the instructions. According to one or more embodiments of the present invention, computer 501 is an example of cloud computing node 10 of FIG. 3.

[0071] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternate embodiments of the present invention may be devised without departing from the scope of the present invention. Various connections and relationships (e.g., over, below, adjacent, etc.) are indicated between elements in the following description and in the drawings. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, connections of entities may refer to direct or indirect connections, and relationships between entities may be direct or indirect relationships. Furthermore, various tasks and process steps described herein may be combined into a more comprehensive procedure or process having additional steps or functions not described in detail herein.

[0072] One or more of the methods described herein may be implemented using any one or a combination of techniques well known in the art, such as discrete logic circuits having logic gates for performing logic functions on data signals, application specific integrated circuits (ASICs) having appropriate combinatorial logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0073] For the sake of brevity, conventional techniques related to making and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for performing various technical features described herein are well known. Thus, for the sake of brevity, details of many conventional implementations are only briefly mentioned herein or are omitted entirely without showing details of well-known systems and / or processes.

[0074] In some embodiments, various functions or acts may be performed at a given location, or in conjunction with the operation of one or more devices or systems, or both. In some embodiments, some of a given function or act may be performed at a first device or location, and remaining functions or acts may be performed at one or more additional devices or locations.

[0075] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0076] In addition to the functional elements in the following claims, the corresponding structure, material, acts, and equivalents of all means or steps are intended to include any structure, material, or acts for performing a function in combination with other claim elements as explicitly claimed. This disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described to best explain the principles and practical application of the disclosure and to enable those skilled in the art to understand the disclosure in various embodiments with various modifications as suited to the particular uses envisioned.

[0077] The diagrams depicted herein are exemplary. There may be many variations to the diagrams or the steps (or operations) depicted therein without departing from the spirit of this disclosure. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Also, the term "coupled" indicates that there is a signal path between two elements, and does not imply a direct connection between elements with no intervening elements / connections between them. All of these variations are considered to be part of this disclosure.

[0078] The following definitions and abbreviations are for use in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to include a non-exclusive inclusion. For example, a structure, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements, but can include other elements not expressly listed or inherent to such structure, mixture, process, method, article, or device.

[0079] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are intended to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is intended to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include both an indirect and a direct connection.

[0080] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on equipment available at the time of filing this application. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0081] The present invention may be a system, method, or computer program product, or a combination thereof, at any level of technical detail of integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0082] A computer-readable storage medium may be any tangible device capable of retaining and storing instructions for use by an instruction-execution device. Computer-readable storage media may be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, or semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures with instructions recorded on them, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, should not be construed as being signals that are transitory in nature, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted through wires.

[0083] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium in the respective computing / processing device.

[0084] Computer-readable program instructions for carrying out operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuit devices, or object-oriented programming languages ​​such as Smalltalk, C++, or the like, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may run entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry devices, including, for example, programmable logic devices, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute computer readable program instructions by utilizing state information of the computer readable program instructions to individualize the electronic circuitry devices to implement aspects of the present invention.

[0085] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0086] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, the instructions of which execute by the processor of the computer or other programmable data processing apparatus to produce means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium such that the computer-readable storage medium comprises an article of manufacture containing instructions for performing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, and may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

[0087] Furthermore, the computer-readable program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device to perform a series of operational steps on the computer, other programmable apparatus, or other device to produce a computer-executed process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0088] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a special-purpose hardware-based system that performs the specified function or act or executes a combination of special-purpose hardware and computer instructions.

[0089] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments described herein. [Explanation of symbols]

[0090] 10 cloud computing nodes 50 Cloud Computing Environments 54A Personal Digital Assistants (PDAs), Cellular Telephones, and Computing Devices 54B Desktop Computers, Computing Devices 54C Laptop Computers, Computing Devices 54N Automotive computer systems and computing devices 60 Hardware and Software, Hardware and Software Layers 61 Mainframe 62 RISC architecture-based servers 63 servers 64 Blade Servers 65 Storage Devices 66 Networks and Networking Components 67 Network Application Server Software 68 Database Software 70 Virtualization, Virtualization Layer 71 Virtual Servers 72 Virtual Storage 73 Virtual Networks 74 Virtual Applications and Operating Systems 75 Virtual Clients 80 Management, management layer 81 Resources Provided 82 Metering and Pricing 83 User Portal 84 Service Level Management 85 Service Level Agreement (SLA) Planning and Fulfillment 90 workloads, workload tiers 91 Mapping and Navigation 92 Software Development and Lifecycle Management 93 Virtual Classroom Educational Delivery 94 Data Analysis Processing 95 Transaction Processing 96 Data Encryption / Decryption 100 Block Diagram 105 Data Buffers 110 DMA Engine 115 Read Channel 120 control port 125 control port 130 Read Channel 135 DMA engine 140 data buffers 145 Control Channel 150 Target Systems 155 Target Memory 160 write channels 165 host memory 170 Host System 175 Central Processing Unit (CPU) 180 Data Clear Control Channel 185 CPU 190 Write Channels 500 Computer Systems 501 General-purpose computers, mainframes 505 processor 510 memory 515 Memory Controller 520 Storage 525 Display Controller 530 Display 535 Local Input / Output Controller, Input / Output Controller 540 Input / Output (I / O) Devices, Output Devices 545 Input / Output (I / O) Devices, Output Devices 550 keyboard 555 Mouse 560 Network Interface 565 Network

Claims

1. receiving a request from a requesting system to move data from a source memory of a source system to a target memory of a target system, said receiving being in a first hardware engine configured to access said source memory and said target memory; In response to receiving the request to move the data from the source memory to the target memory, by the first hardware engine: reading said data from said source memory; writing the data to the target memory; and transmitting a data clear request to a second hardware engine configured to access the source memory in response to the read being completed, the data clear request specifying a location of the data within the source memory to be cleared. To implement Including, the first hardware engine is a first data movement assist (DMA) engine, and the second hardware engine is a second DMA engine coupled to the first DMA engine via a control channel to initiate the data clear request on the second DMA engine.

2. receiving, at the first hardware engine, a first notification from the second hardware engine indicating that the data clear request has completed; transmitting a second notification to the requesting system in response to receiving the first notification, the second notification indicating that the request to move data from the source memory to the target memory has been completed; The method of claim 1 further comprising:

3. 3. The method of claim 1, wherein the request is received from a central processing unit (CPU) of a host system.

4. 2. The method of claim 1, wherein the request to move data from the source memory to the target memory includes a descriptor, the descriptor including a read address in the source memory, a write address in the target memory, and a length of the data.

5. 5. The method of claim 4, further comprising generating, by the first DMA engine, the data clear request, wherein the generating comprises modifying the descriptor by removing the write address in the target memory and changing the read address in the source memory to a write address in the source memory.

6. 2. The method of claim 1, wherein the data clear request is executed by the second hardware engine, and wherein the executing includes overwriting the data in the source memory with one or both of static bits and random bits.

7. 1. A system comprising one or more processors for executing computer readable instructions, the computer readable instructions comprising: receiving a request from a requesting system to move data from a source memory of a source system to a target memory of a target system, said receiving being in a first hardware engine configured to access said source memory and said target memory; In response to receiving the request to move the data from the source memory to the target memory, by the first hardware engine: reading said data from said source memory; writing the data to the target memory; and transmitting a data clear request to a second hardware engine configured to access the source memory in response to the read being completed, the data clear request specifying a location of the data within the source memory to be cleared. To implement Including, the first hardware engine is a first data movement assist (DMA) engine, and the second hardware engine is a second DMA engine coupled to the first DMA engine via a control channel to initiate the data clear request on the second DMA engine; A system for controlling the one or more processors to perform operations.

8. The operation is receiving, at the first hardware engine, a first notification from the second hardware engine indicating that the data clear request has completed; transmitting a second notification to the requesting system in response to receiving the first notification, the second notification indicating that the request to move data from the source memory to the target memory has been completed; The system of claim 7 further comprising:

9. 9. The system of claim 7 or 8, wherein the request is received from a central processing unit (CPU) of a host system.

10. 10. The system of claim 9, wherein the request to move data from the source memory to the target memory includes a descriptor, the descriptor including a read address in the source memory, a write address in the target memory, and a length of the data.

11. 11. The system of claim 10, wherein the operation further comprises generating, by the first DMA engine, the data clear request, and wherein the generating comprises modifying the descriptor by removing the write address in the target memory and changing the read address in the source memory to a write address in the source memory.

12. 8. The system of claim 7, wherein the data clear request is executed by the second hardware engine, and wherein the executing includes overwriting the data in the source memory with one or both of static bits and random bits.

13. A computer program for causing a computer to execute the computer-implemented method according to any one of claims 1 to 6.

14. A computer-readable recording medium on which the computer program according to claim 13 is recorded.

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