High-speed, high-frequency package

Abstract

The device package includes a chip carrier having a cavity and one or more microwave waveguides configured to route signals. A chip is located within the cavity of the chip carrier, the chip including one or more pads. Each pad is aligned with a corresponding connector pad of one of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is coupled to the corresponding connector pad of the microwave waveguide via overlap capacitive coupling between the at least one pad and the aligned corresponding connector pad of the microwave waveguide.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to chip packaging, and more particularly to efficient packaging of superconducting devices. [Background technology]

[0002] In order for semiconductor chips to communicate with the outside world, they are typically encapsulated within a supporting case that not only facilitates communication with external components but also provides physical and thermal protection for the chip. Traditional packaging techniques typically rely on a "permanent" connection between the package and the encapsulated chip. Typical connections between pads on the chip and connector pads on the package may include permanent solder, wire bonds, thermosonic bonds, or other permanent bonding techniques, which make subsequent separation and replacement impractical. Summary of the Invention

[0003] According to one embodiment, a device package includes a chip carrier having a cavity and one or more microwave waveguides configured to route signals. A chip is located within the cavity of the chip carrier, the chip including one or more pads. Each pad is aligned with a corresponding connector pad of one of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is coupled to the corresponding connector pad of the microwave waveguide via an overlap capacitive coupling between the at least one pad and the aligned corresponding connector pad of the microwave waveguide.

[0004] In one embodiment, the chip is a quantum chip.

[0005] In one embodiment, the chip carrier is a printed circuit board (PCB).

[0006] In one embodiment, there is a block configured to press the chip into the cavity of the chip carrier, the chip may be a quantum chip, and the block may be a thermalization block operative to thermalize the quantum chip.

[0007] In one embodiment, the block includes one or more springs that operate to press the chip into the cavity of the chip carrier.

[0008] In one embodiment, the microwave waveguide is superconducting and comprises either a superconductor or superconductor-coated copper. For example, the microwave waveguide may comprise niobium or copper coated with a superconductor such as tin.

[0009] In one embodiment, the superconducting microwave waveguides of the chip carrier are routed in three dimensions onto a connector surface that includes a ball grid array (BGA).

[0010] In one embodiment, the alignment between the chip and the cavity of the chip carrier is within 0.2 times the width of the connector pad.

[0011] In one embodiment, the chip carrier includes a plurality of additional cavities. At least one additional cavity of the plurality of additional cavities includes a given chip having one or more pads located therein. Each pad of the given chip is aligned with a corresponding connector pad of the microwave waveguide of the chip carrier. At least one of the one or more pads of the given chip is coupled to its aligned corresponding connector pad of the chip carrier via overlap capacitive coupling.

[0012] In one embodiment, the chips are quantum chips and the given chip is not a quantum chip.

[0013] According to one embodiment, a chip packaging system includes a chip carrier having a cavity and one or more microwave waveguides configured to route signals. An interposer chip includes one or more pads and is located within the cavity of the chip carrier. One or more chips are bonded to the interposer chip. Each pad on the interposer chip is aligned with a corresponding connector on one of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is coupled to a corresponding connector pad on the microwave waveguide via overlap capacitive coupling between the at least one pad and the aligned corresponding connector pad on the microwave waveguide.

[0014] In one embodiment, the chip is a quantum chip and the chip carrier is a printed circuit board (PCB).

[0015] In one embodiment, there is a block configured to press the interposer chip into the cavity of the chip carrier.

[0016] In one embodiment, the block includes one or more springs that operate to press the interposer chip into the cavity of the chip carrier.

[0017] According to one embodiment, a method for packaging a chip includes providing a chip carrier having a cavity and one or more microwave waveguides for routing signals. A chip having one or more pads is guided into the cavity of the chip carrier. Each pad of the chip is aligned with a corresponding connector pad of one of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is coupled to the corresponding connector pad of the microwave waveguide via overlap capacitive coupling between the at least one pad and the aligned corresponding connector pad of the microwave waveguide.

[0018] In one embodiment, the chip is pressed into the cavity of the chip carrier by a thermal block.

[0019] In one embodiment, the forcing includes one or more springs in the thermal block that press the chip into the cavity of the chip carrier.

[0020] In one embodiment, the chip carrier includes a plurality of additional cavities. At least one additional cavity of the plurality of additional cavities includes a given chip having one or more pads located therein. Each pad of the given chip is aligned with a corresponding connector pad of the microwave waveguide of the chip carrier. At least one of the one or more pads of the given chip is coupled to its aligned corresponding connector pad of the chip carrier via overlap capacitive coupling.

[0021] In one embodiment, the functionality of the chip is determined, and if the chip is determined to be bad, it is removed and replaced with a new chip.

[0022] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0023] The drawings are of exemplary embodiments. They do not describe all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective explanation. Some embodiments may be practiced with additional components or steps, or without all components or steps shown, or both. When the same numeral appears in different drawings, the numeral refers to the same or similar components or steps. [Brief explanation of the drawings]

[0024] [Figure 1] (A) is a perspective view of a packaged chip consistent with an exemplary embodiment. (B) is a top view of the printed circuit board of (A) with a cutout consistent with an exemplary embodiment. (C) and (D) are top and bottom views of a chip with a waveguide launcher consistent with an exemplary embodiment. [Figure 2A] 1 is a cross-sectional view of a package consistent with an exemplary embodiment; [Figure 2B] FIG. 10 illustrates a cutout in a chip carrier configured to receive a chip, consistent with an exemplary embodiment. [Figure 3] FIG. 1 illustrates a multi-chip configuration of a package, consistent with an exemplary embodiment. [Figure 4] 1 is a cross section of a chip coupled to a printed circuit board by wire bonds, consistent with an illustrative embodiment. [Figure 5] 1 is a cross-sectional view of a chip coupled to a printed circuit board via capacitive coupling, consistent with an illustrative embodiment; [Figure 6] 1 is a cross-sectional view of a chip coupled to a printed circuit board having a spring-loaded thermalization structure, consistent with an exemplary embodiment. [Figure 7] 1 is a cross-sectional view of a structure having a chip bonded to a printed circuit board having a carrier chip, consistent with an illustrative embodiment. [Figure 8] Figures (A)-(C) provide exemplary simulation results of the coupling capacitance between the pads of the chip and the connector pads on the printed circuit board, for the case where the vertical distance between the coplanar waveguides is fixed at 100 nm. DETAILED DESCRIPTION OF THE INVENTION

[0025] overview In the following detailed description, numerous specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, or circuits, or combinations thereof, have been described at a relatively high-level, without detail, to avoid unnecessarily obscuring aspects of the present teachings.

[0026] In one aspect, spatially related terms such as "front," "rear," "top," "bottom," "below," "lower," "lower side," "upper," "upper," "side," "left," and "right" are used with reference to the orientation of the figures being described. Because components of embodiments of the present disclosure can be positioned in several different orientations, directional terms are used for illustrative purposes and are in no way limiting. It will therefore be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation of above and below. The device may be oriented differently (rotated 90 degrees or viewed or referenced in other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0027] As used herein, the terms "lateral" and "horizontal" refer to an orientation parallel to the first surface of the chip.

[0028] As used herein, the term "vertical" refers to an orientation that is disposed perpendicular to the first surface of the chip, chip carrier, or semiconductor body.

[0029] As used herein, the terms "coupled" and / or "electrically coupled" do not imply that elements must be directly coupled to one another, and intervening elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low-ohm electrical connection between the elements that are electrically connected to one another.

[0030] Terms such as first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated and listed items.

[0031] Example embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not necessarily indicative of the actual shape of a region of a device and are not intended to be limiting.

[0032] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below can be combined with elements of different embodiments.

[0033] The present disclosure generally relates to packaging that allows for fast and easy replacement of chips. By way of example only and not limitation, the concepts herein are discussed in the context of quantum technology and quantum chips, although it will be understood that these teachings may be applied to different types of chips as well. With respect to quantum technology, electromagnetic energy associated with a qubit can be stored, for example, in so-called Josephson junctions, as well as in capacitive and inductive elements used to form the qubit. Other examples may include spin qubits coupled to resonators or phase qubits, microfabricated ion traps, and the like. Other types of microwave components that can be tuned or easily replaced are similarly supported by the teachings herein, including (but not limited to) circulators, isolators, amplifiers, filters, active control electronics such as rapid single flux quantum (RSFQ), and the like.

[0034] In one example, to read out the qubit state, a microwave signal is applied to a microwave readout cavity that couples to the qubit at the cavity frequency. The transmitted (or reflected) microwave signal passes through multiple thermal isolation stages and low-noise amplifiers used to block or reduce noise and improve the signal-to-noise ratio. The amplitude and / or phase of the returned / output microwave signal carries information about the qubit state, such as whether the qubit has dephased to its ground state or excited state. The microwave signal carrying quantum information about the qubit state is typically weak (e.g., on the order of a few microwave photons). Various circuits and techniques can be used to measure this weak signal. To improve the signal-to-noise ratio of the output chain, low-noise quantum-limited amplifiers (QLAs), such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs), can be used as preamplifiers at the output of the quantum system to boost the quantum signal while adding a minimal amount of noise as dictated by quantum mechanics. In addition to Josephson amplifiers, certain Josephson microwave components using Josephson amplifiers or Josephson mixers, such as Josephson circulators, Josephson isolators, and Josephson mixers, can be used in scalable quantum processors.

[0035] The ability to incorporate more qubits is key to realizing the potential of quantum computers. Applicant has recognized that improvements can be made along various dimensions to increase the computational power and reliability of quantum computers. First, the number of qubits themselves. The more qubits a quantum processor has, the more states it can, in principle, manipulate and store. Second, low error rates, which relate to precisely manipulating qubit states and performing sequential operations that provide consistent results rather than simply unreliable data, are key. Third, qubit technology is still a developing field, and providing qubits with a predetermined frequency with high precision presents challenges. For example, in some scenarios, consistently producing qubits with a center frequency of 5.20 GHz may not be repeatedly achieved. Therefore, it is desirable to have a modular system with multiple quantum chips and to be able to easily replace qubits that do not have the desired center frequency or are simply defective.

[0036] Therefore, to improve the fault tolerance of quantum computer systems, a logical qubit must be stored using a large number of physical qubits. In this way, local information is delocalized, making the quantum computer less susceptible to local errors and the performance of measurements in the eigenbasis of the qubit, similar to the parity checks of classical computers, thereby leading to more fault-tolerant qubits.

[0037] In order for semiconductor chips, such as quantum chips, to communicate with the outside world, they are typically bonded or encapsulated in a support case that not only facilitates communication but also provides physical and thermal protection for the quantum chip. Existing support cases can be subject to a variety of challenges. For example, traditional bonding is a time- and resource-consuming process and may not provide adequate impedance matching at the transition between the chip and a chip carrier, such as a printed circuit board (PCB). Furthermore, traditional bonding can reduce the ability to create a cavity around the chip to efficiently guide the chip onto the PCB or to provide adequate access to relevant chip surfaces for processing or inspection.

[0038] Conventional packaging techniques may include vertical through-silicon vias (TSVs), which pose manufacturing challenges and can affect coherence during the manufacturing process. The package can even distort the chip during cooling. For example, point forces on the chip from pogo pins can lead to chip breakage. Differences in the expansion coefficients of the chip and package can distort the chip (e.g., laterally). Furthermore, in conventional quantum chip packages, the overlap of lossy / normal materials with the different modes of the qubit can induce losses, collectively referred to herein as package-induced decoherence.

[0039] The concepts discussed herein provide various improvements to the encapsulation of chips, such as quantum chips, as described in more detail below. For example, the lack of physical bonding between the chip's pads and corresponding connector pads on a chip carrier, such as a PCB, significantly reduces the effort and time required to bond the chip to the PCB. The easy and flexible removal of chips from the PCB allows chips to be easily and individually replaced with different chips that meet desired criteria. Such flexibility may be particularly useful, for example, in coherence experiments and materials evaluation. Additionally, chips can be easily replaced with ones that have a more desirable qubit frequency because there are no physical bonds to remove and reintroduce during replacement. The chip carrier and corresponding connector pads can be easily reused because there are no physical bonding wires connecting the chip to the PCB. Because the chip is not mechanically fixed to the chip carrier as in conventional packaging, strain during cooling is reduced. Furthermore, in some embodiments, the teachings herein facilitate multi-chip module devices.

[0040] The techniques described herein can be implemented in several ways. Exemplary implementations are provided below with reference to the following figures:

[0041] Exemplary Packaging Architecture 1(A)-1(D) collectively provide a system overview illustrating different aspects of the present packaging concept consistent with exemplary embodiments. More specifically, FIG. 1(A) provides a perspective view of a packaged chip 100A. In various scenarios, the packaged chip can operate at room temperature or cryogenic temperatures. Coaxial wires 102 can be coupled to various test and measurement instruments (e.g., operating at room temperature) to determine whether one or more chips connected to the chip carrier should be replaced by simply removing and plugging in the chip as described herein. In various embodiments, the wires on the chip carrier can be microstrip or coplanar waveguide (CPW) or both. In one embodiment, the chip carrier is a PCB.

[0042] FIG. 1(B) provides a top view 100B of the PCB of FIG. 1(A) with a cutout operable to accept the chip 100C. The chip 100C can be placed (e.g., plugged in) directly onto a connector pad (e.g., a coplanar waveguide (CPW) trace) of the PCB. In this regard, FIGS. 1(C) and 1(D) show top and bottom views, respectively, of the chip with a waveguide launcher 130. On the PCB 100B, there is an equivalent waveguide launcher (e.g., 130) that faces the chip's waveguide launcher. For example, the center wire of the waveguide launcher 130 is a signal wire, and the two outer wires are grounded. Each waveguide launcher serves as a pad that is connected via capacitive coupling.

[0043] Reference is now made to FIG. 2A, which provides a cross-sectional view of package 200A consistent with an exemplary embodiment. FIG. 2A includes chip 220 communicatively coupled to a PCB via capacitive coupling between pads on chip 220 and corresponding connector pads on PCB 228. The actual connector pads and chip pads are not shown in FIG. 2A but are described in more detail below in the context of FIG. 2B. For example, via capacitive coupling, signals from chip 220 are transmitted through connector pads on PCB 228 and travel through a CPW that connects to launch pads on PCB 228. Two fasteners 242 and 244 are used to press the chip into the PCB recess and align the chip, PCB, and thermalization block (described in more detail in connection with FIG. 5) relative to one another. These launch pads on chip 220 are aligned with corresponding connector pads on PCB 228, allowing communication by transmitting microwave signals via capacitive coupling. In this regard, Figure 2B illustrates a chip carrier (e.g., a PCB) having a cutout 200C configured to receive a chip 200B. For example, the chip 200B can be placed (e.g., upside down) onto the cutout 200C in the PCB such that the pads 130 (e.g., sometimes referred to herein as waveguides or waveguide launchers) on the chip are aligned with corresponding connector pads on the PCB within the cutout 200C.

[0044] Thus, a chip (which may be a quantum chip) can be placed (e.g., flip-chip) directly onto a cutout in a chip carrier (e.g., a PCB) without requiring a physical connection between the chip's pads and the connector pads on the chip carrier. For example, the architecture described herein does not require permanent solder, wire, thermosonic, or other permanent bonds between the chip and the PCB. Instead, the chip 200B is flipped over and placed onto the cavity of the chip carrier, with the pads on the chip directly aligned with and facing the connector pads on the chip carrier (e.g., PCB). The actual transmission of signals between the pads on the chip and the corresponding connectors on the chip carrier is via capacitive coupling (i.e., the large overlap capacitance between the pads on the chip and the corresponding connectors on the PCB). The chip and PCB are held together in a non-invasive, non-permanent, and easily removable manner to package the chip, as discussed in more detail below.

[0045] Thus, capacitive coupling between the pads on the chip (e.g., waveguide launchers) and the corresponding connector pads on the PCB facilitates communication between the chip and the PCB. CPWs on the PCB can be used to route signals between different chips and / or devices. In one embodiment, superconducting lines and / or vias can be used in the PCB (e.g., tin-coated copper) to route signals in three dimensions and / or connect signals to connector surfaces (e.g., ball grid arrays).

[0046] In one embodiment, the chip 200B is laterally aligned to better than a dimension of approximately 0.2*w, where w is the width of the connector (e.g., capacitor) pad. For example, the alignment is better than 50 μm. Applicant has determined that such a tolerance provides adequate overlap so that the desired overlap capacitance for reliable capacitive coupling is achieved between the pads of the chip and the connector pads on the chip carrier (e.g., a PCB with a cutout to accept the chip). Such alignment is provided by creating precise cutouts in the PCB 200C through which the chip 200B is guided. The chip 200B is pressed against the PCB to minimize the distance “d” (see FIG. 5) between the pads on the chip and the corresponding connector on the PCB. In various embodiments, minimizing the distance “d” can be accomplished using a spring-based mechanism or a thermal structure (e.g., a copper block) that clamps the chip 200B and PCB between the two components using fasteners (e.g., screws, clamps, etc.). These concepts are discussed in more detail below.

[0047] While chip carriers configured to accept a single chip are illustrated by way of example in FIGS. 1A and 2B, it will be understood that the teachings herein are not limited thereto. In this regard, reference is made to FIG. 3 , which illustrates a packaged multi-chip configuration 300 consistent with an exemplary embodiment. In various embodiments, the multi-chip configuration 300 can comprise an array of similar (e.g., qubit) chips 302 or a combination of different types of chips (e.g., control logic, amplifiers, readout circuits, power supplies, quantum chips, etc.) communicatively connected to a PCB 350 via capacitive coupling between the pads on the chips 302-324 and their corresponding connector pads on the multi-chip PCB 350. Two or more of the chips 302-324 can communicate with each other via capacitive coupling between pads on the chips and connector pads on the PCB 350. If any of the chips 302-324 is not functioning properly, that chip can be easily replaced with another chip by quickly removing the old chip and inserting a new one. This flexibility is achieved by the chips 302-324 being capacitively coupled rather than permanently attached to the PCB 350. In this way, the functionality of the multi-chip configuration 300 is facilitated and easily maintained over time.

[0048] To better understand the features of the teachings herein, it may be useful to provide a comparison with known packaging techniques. To that end, FIG. 4 provides a cross-section of a chip coupled to a PCB 410 by wire bonds 402. The structure 400 includes a thermalization structure 414, sometimes referred to as a (e.g., copper) pusher block, that operates to hold the chip 406 over a cavity 416. The quantum chip 406 itself is physically connected to the PCB 410 by permanent wire bonds (e.g., 402). Typically, there is a shield 404 that operates to encapsulate the quantum chip 406. The shield 404 is held on top of the PCB 410 by fasteners 412 that mechanically clamp or screw the shield 404 to the PCB 410 and the thermalization structure 414. A shield 408 may be present on the PCB. The PCB may include an RF connector 418 that operates to communicate with other components via RF signals. Because the wire bonds (eg, 402) are relatively permanent connections, the quantum chip 406 cannot be easily replaced.

[0049] In contrast, referring now to FIG. 5 , this figure is a cross-section of a chip 506 coupled to a chip carrier (e.g., PCB) 510 via capacitive coupling, consistent with an illustrative embodiment. The structure 500 includes a thermalization structure 514 that operates to hold the chip (e.g., quantum chip and / or control chip) 506 below a cavity 516. The thermalization structure 514 may comprise copper. In some embodiments, a shield 508 is present that completes the encapsulation of the chip 506 and operates to protect the chip surface from stray fields or external influences. The shield may be mechanically secured to the bottom surface of the chip carrier (e.g., PCB) 510 by a fixture 512 that mechanically clamps or screws both the shield 508 and the thermalization structure 514 to the PCB 510. The clamping provided by the fixture 512 ensures sufficient thermal contact between the thermalization structure 514 and the chip 506. Good thermal and electrical contact to ground is achieved using a copper block or through large ground contacts already present on all edges of the chip (e.g., where no waveguides are present). In one embodiment, a shield 502 is present on PCB 510 and provides a defined cavity that operates to protect the chip circuitry from electromagnetic (EM) interference.

[0050] The PCB 510 may include one or more RF connectors (e.g., 518 and 530) that operate to communicate with other components via RF signals. Importantly, the connection between the pads on the chip 506 and the connector pads on the PCB 510 is not a permanent connection (e.g., permanent solder, wire, thermosonic, or other permanent bonding). Rather, the one or more connections between the chip 506 and the chip carrier 510 are capacitive couplings between the pads on the chip 506 and the connector pads on the PCB 510, with a distance d. In one example, the overlap between the pads on the chip 506 and the chip carrier is approximately 500 μm. For a 100 μm-wide CPW launcher (sometimes referred to herein as the chip's pads), a coupling capacitance of 500 fF was observed, resulting in less than 5 dB of signal attenuation. This non-permanent connection allows the chip 506 to be easily removed from the chip carrier 510 and replaced. While distance "d" is shown as a visible gap in the enlarged view, it should be understood that this gap occurs despite chip 506 being pressed against PCB 510 by thermalization structure 514 and fixture 512. In particular, as previously indicated, distance "d" can be minimized by increasing the contact pressure between chip 506 and PCB 510. This results in a decrease in distance "d" and a corresponding increase in coupling capacitance between the pads of chip 506 and PCB 510. In some embodiments, coupling capacitance can be varied by controlling distance "d" based on mechanical pressure applied between the chip and chip carrier (e.g., via screw fixtures, springs, etc.).

[0051] Thus, the waveguides are brought toward the edge of the chip and configured as waveguide launchers, sometimes referred to herein as chip pads. The lateral dimension (w) of the chip pads is configured such that the impedance remains the same, but w increases in size, e.g., from 10 μm to 200 μm. A corresponding waveguide exists within the overlap region, exposed on the chip carrier (e.g., PCB) 510 side. In one embodiment, the length "l" is approximately 1 μm. Thus, when the chip is placed on the chip carrier, the two ends of these waveguides (e.g., the chip pads and the connectors on the chip carrier) form a plate capacitor with length l and width w. Applicant has determined that when "l" and "w" are sufficiently large (typically l = 500 μm, w = 100-200 μm), capacitive coupling is large enough that transmission from the chip to the PCB is sufficient, even when a separation "d" exists between the surface of the chip and the surface of the PCB (each with its corresponding waveguide). In this regard, Figures 8(A)-8(C) provide exemplary simulation results of the coupling capacitance between the pads of the chip and the connectors on the PCB (i.e., their corresponding CPWs) for a fixed vertical distance between the CPWs of 100 nm. Figure 8(C) shows that the capacitance is linear with the overlap length l.

[0052] FIG. 6 is a cross-sectional view of a chip 506 coupled to a PCB 510 having a spring-loaded thermalization structure 514, consistent with an exemplary embodiment. Many components of FIG. 6 are substantially similar to those of FIG. 5 and therefore will not be repeated here for brevity. The primary difference is the presence of one or more spring contacts 620 between the thermalization structure 514 and the chip 506, sometimes referred to herein as being spring-loaded. The spring load serves to provide a defined, constant force on the chip, which can compensate for shape changes due to cooling. Thus, the chip 606 is pressed against the connector pads of the chip carrier by the spring contacts pressing down on its backside. The actual coupling between the pads of the chip 606 and the connector pads on the PCB is via capacitive coupling, as described herein.

[0053] FIG. 7 is a cross-section 700 of a structure having a chip 706 coupled to a chip carrier (e.g., PCB) 510 having a carrier chip 608, consistent with an illustrative embodiment. Many components of FIG. 7 are substantially similar to those of FIGS. 5 and 6 and therefore will not be repeated here for brevity. One notable difference between FIGS. 6 and 7 is that the (e.g., qubit) chip 706 is not directly connected to the chip carrier (e.g., PCB) 510. Rather, the chip 706 is connected by a ball grid array (BGA) to an interposer chip 608, sometimes referred to herein as a control chip, which is coupled to the chip carrier 510 via capacitive coupling. FIG. 7 shows that the chip 706 resides within a cavity 716 in a shield 708. The quantum chip 706 may be coupled to the control chip 608 via superconducting interconnects (e.g., in-bumps), or the like. Advantageously, such sandwiched chips can be easily replaced and do not require wire bonding to a PCB.

[0054] In one embodiment, multiple similar type chips (e.g., quantum chips) or a combination of different type chips are coupled by "permanent" connections to interposer chip 608. Interposer chip 608 is itself coupled to chip carrier (e.g., PCB) 510 via capacitive coupling as described above.

[0055] The architectures discussed herein are useful in different fields, including, without limitation, microwave packaging (e.g., for quantum engineering, quantum chips, superconducting quantum chips), quantum technology (e.g., quantum processors, packaging of quantum systems, packaging of superconducting qubits, etc.), cryogenics (e.g., thermalization, signal delivery, cryogenic microwave measurements, etc.), etc.

[0056] conclusion The description of various embodiments of the present teachings has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0057] While the above describes what is believed to be the best mode and / or other examples, it will be understood that various modifications may be made thereto, that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied to numerous applications, only a few of which have been described herein. It is intended by the appended claims to claim all such applications, modifications, and variations that fall within the true scope of the present teachings.

[0058] The components, steps, features, objects, benefits, and advantages described herein are merely exemplary. Neither they nor the discussion thereof is intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise specified, all measurements, values, ratings, positions, dimensions, sizes, and other specifications set forth in this specification, including the appended claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they relate and those customary in the technical field to which they pertain.

[0059] Numerous other embodiments are contemplated, including embodiments having fewer, additional, or different or combinations of components, steps, features, objects, benefits, and advantages, including embodiments in which components and / or steps are arranged and / or ordered differently.

[0060] While the above has been described in connection with exemplary embodiments, it is understood that the term "exemplary" is intended merely as an example, not as best or optimal. Except as noted immediately above, nothing described or shown is intended to, or should be construed as, dedicating to the public any component, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0061] Terms and expressions used herein will be understood to have the ordinary meanings ascribed to such terms and expressions with respect to their corresponding respective fields of inquiry and study, unless a specific meaning is otherwise stated herein. Relationship terms, such as first and second, may be used solely to distinguish one entity or action from another and do not necessarily require or imply an actual relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements may include not only those elements, but also other elements not expressly listed or inherent in such process, method, article, or apparatus. An element preceded by "a" or "an" does not, without further constraints, exclude the presence of additional identical elements in a process, method, article, or apparatus that includes that element.

[0062] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. 1. A device package comprising: a chip carrier having cutouts and one or more microwave waveguides configured to route signals; a chip comprising a qubit and one or more pads, the chip being configured to be received within the cutout of the chip carrier and having cavities on its top and bottom surfaces; each pad is aligned with a corresponding one of the connector pads of one of the one or more microwave waveguides of the chip carrier; a chip-side waveguide connected to at least one of the one or more pads is coupled to the corresponding one of the microwave waveguides via overlap capacitive coupling between the at least one pad and the corresponding one of the aligned connector pads of the one of the microwave waveguides; The chip; A device package comprising:

2. A device package as described in claim 1, wherein the chip-side waveguide and the microwave waveguide are coplanar waveguides, the one pad is composed of multiple wires, and the corresponding one connector pad is composed of multiple wires.

3. 3. The device package of claim 1, wherein the chip carrier is a printed circuit board (PCB).

4. The device package of claim 1 , further comprising a block configured to press the chip into the cutout of the chip carrier.

5. The block is a thermalization block operative to thermalize the chip.

5. The device package of claim 4.

6. 5. The device package of claim 4, wherein the block includes one or more springs that operate to press the chip against the cutout in the chip carrier.

7. 7. The device package of claim 1, wherein the microwave waveguide is superconducting and comprises niobium or copper coated with a superconductor.

8. 8. The device package of claim 1, wherein the microwave waveguide of the chip carrier is three-dimensionally routed to a connector surface that includes a ball grid array (BGA).

9. The device package of any one of claims 1 to 8, wherein alignment between the chip and the cutout in the chip carrier is within 0.2 times the width of a connector pad.

10. the chip carrier comprises a plurality of additional cutouts; at least one additional cutout of the plurality of additional cutouts comprises a given chip having one or more pads located within the at least one additional cutout; each pad of the given chip is aligned with a corresponding connector pad of a microwave waveguide of the chip carrier; at least one of the one or more pads of the given chip is coupled to its aligned corresponding connector pad of the chip carrier via an overlapping capacitive coupling; The device package according to any one of claims 1 to 9.

11. The given chip is not a quantum chip.

11. The device package of claim 10.

12. 1. A chip packaging system comprising: a chip carrier having cutouts and one or more microwave waveguides configured to route signals; an interposer chip having one or more pads and received within the cutout of the chip carrier; one or more chips, each comprising a qubit, bonded to the interposer chip; each pad of the interposer chip is aligned with a corresponding connector pad of one of the one or more microwave waveguides of the chip carrier; an interposer chip-side waveguide connected to at least one of the one or more pads is coupled to the corresponding one of the microwave waveguides via overlap capacitive coupling between the at least one pad and the corresponding one of the aligned connector pads of the one of the microwave waveguides; the one or more chips; and configured to have cavities on top and bottom surfaces of the bonded one or more chips and the interposer chip.

13. The interposer chip side waveguide and the microwave waveguide are coplanar waveguides, the one pad is made up of a plurality of wires, the corresponding one connector pad is made up of a plurality of wires, and the chip carrier is a printed circuit board (PCB).

13. The chip packaging system of claim 12.

14. 14. The chip packaging system of claim 12 or 13, further comprising a block configured to press the interposer chip into the cutout of the chip carrier.

15. 15. The chip packaging system of claim 14, wherein the block includes one or more springs that operate to press the interposer chip against the cutout in the chip carrier.

16. 1. A method of packaging a chip, comprising: providing a chip carrier having a cutout and one or more microwave waveguides for routing signals; guiding a chip comprising a qubit and one or more pads into the cutout of the chip carrier, the chip being configured to have cavities on its top and bottom surfaces; aligning each pad of the chip with a corresponding one connector pad of one of the one or more microwave waveguides of the chip carrier; coupling a chip-side waveguide connected to at least one of the one or more pads to the corresponding one of the microwave waveguides via overlap capacitive coupling between the at least one pad and the corresponding one of the aligned connector pads of the one of the microwave waveguides; A method comprising:

17. 17. The method of claim 16, further comprising using a thermal block to press the chip into the cutout of the chip carrier.

18. 18. The method of claim 17, wherein the forcing includes one or more springs of the thermal block forcing the chip into the cutout of the chip carrier.

19. the chip carrier comprises a plurality of additional cutouts; at least one additional cutout of the plurality of additional cutouts comprises a given chip having one or more pads located within the at least one additional cutout; each pad of the given chip is aligned with a corresponding connector pad of a microwave waveguide of the chip carrier; at least one of the one or more pads of the given chip is coupled to its aligned corresponding connector pad of the chip carrier via an overlapping capacitive coupling; The method according to any one of claims 16 to 18.

20. determining the functionality of the chip; If the chip is determined to be defective, Removing the tip; replacing the tip with a new tip; The method of any one of claims 16 to 19, further comprising:

Images