Nanofabrication and design techniques for 3D-ICs and configurable ASICs

Abstract

Various embodiments of the present technology provide ultra-high density heterogeneous integration enabled by nano-precision pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques using prefabricated blocks (PFBs). These PFBs can be created on one or more source wafers. Pick-and-place techniques can then be used to selectively place the PFBs on destination wafers, thereby efficiently creating nanoscale aligned 3D stacked integrated circuits (N3SIs) and microscale modular assembled ASICs (M2A2s). Some embodiments include systems and techniques for using pick-and-place assembly to build semiconductor devices arbitrarily larger than the standard photolithography field size of 26 x 33 mm. [Selected Figure] Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 727,886, filed September 6, 2018, and U.S. Provisional Patent Application No. 62 / 884,524, filed August 8, 2019, which are incorporated by reference in their entireties for all purposes.

[0002] (Technical field) Various embodiments of the present invention relate generally to nanofabrication and design of integrated circuits. More particularly, some embodiments of the present technology relate to nanoscale aligned 3D stacked integrated circuits (N3-SI) and microscale modular assembled ASIC (M2A2) technologies for advanced semiconductor devices. [Background technology]

[0003] Only 70 years ago, inexpensive, universally available high-performance computers would have been considered a pipe dream. Rapid and consistent transistor scaling is the primary reason for today's cost-effective, high-performance computing devices. For most of the past 50 years, transistor scaling has been consistent enough to be codified into a law (Moore's Law). However, future progress in scaling faces several difficult challenges, the most recent of which relates to patterning sub-20 nm (half-pitch) features using photolithography in an economically viable manner. Summary of the Invention [Problem to be solved by the invention]

[0004] Today, individual transistors are routinely made at scales below 20 nm, but it is increasingly clear that the space underneath is shrinking rapidly. Advances in computing can no longer rely on improving performance via conventional scaling of transistors. Several challenges exist, including physical challenges, material challenges, power-thermal challenges, technological challenges, and economic challenges.

[0005] Physical challenges arise, for example, as transistors become smaller and smaller, and leakage current increases as a fraction of signal current, adversely affecting the performance and functionality of CMOS devices. Material challenges arise as feature sizes shrink, with currently used dielectric and interconnect materials no longer providing reliable insulation or conductivity. Power-thermal challenges arise as transistor supply voltages do not scale as rapidly as transistor size, thus increasing transistor power density, which poses challenges for power dissipation technologies. Examples of technology challenges include, but are not limited to, patterning sub-20 nm features, which require complex multiple patterning using 193 nm immersion tools or a switch to problematic EUV exposure tools.

[0006] Each of these factors significantly increases manufacturing and testing costs without a commensurate increase in functionality or performance, reducing semiconductor manufacturers' profits and ultimately reducing the incentives for aggressive scaling. [Means for solving the problem]

[0007] Systems and methods for nanofabrication and design of integrated circuits are described. More particularly, some embodiments of the present technology relate to nanoscale aligned 3D stacked integrated circuits (N3-SI) and microscale modular assembled ASIC (M2A2) technologies for advanced semiconductor devices. Some embodiments are directed to fabricating a desired size (e.g., 900mm 2The present invention provides a method for fabricating semiconductor devices having a die size greater than 900 mm. The method may include providing a first type of source wafer including high-resolution circuit elements partitioned into a number of prefabricated blocks (PFBs). In some embodiments, each PFB has a size of at most 900 mm. 2 A second type of source wafer may be provided. The second type of source wafer may include low-resolution circuit elements partitioned into multiple PFBs.

[0008] In some embodiments, the size of each PFB on the second type of source wafer is at most 1500 mm 2 PFBs from the first type of source wafer may be assembled on a product substrate, followed by assembly of PFBs from the second type of source wafer on the previously assembled PFB. The fully assembled group of high-resolution and low-resolution PFBs may then be functionally equivalent to a monolithically constructed SoC, but at a cost of 900 mm. 2 In some embodiments, the overlay accuracy between the high-resolution PFB and the low-resolution PFB may be better than 100 nm, 50 nm, 25 nm, or other resolution.

[0009] According to various embodiments, the first type source wafer and / or the second type source wafer may have multiple types of PFBs. In some embodiments, the PFBs may be less than 10 μm thick, less than 1 μm thick, less than 100 nm thick, or even smaller. In some embodiments, the low-resolution PFB may include only a metal layer and be referred to as a custom metal die (CMD). In some embodiments, a superstrate assembly can be used to pick and place the PFBs from the first and second source wafers. The superstrate assembly can have one or more connected or unconnected sub-superstrates. In some embodiments, an overlay control architecture can be used to control the distortion of the PFBs to the nanometer scale. The superstrate assembly and / or the sub-superstrate can have routing for a sacrificial layer etchant to etch the PFB tethers in situ. The superstrate assembly and / or the sub-superstrate can have airflow routing for vacuum pick-up.

[0010] In some embodiments, the pick-and-place assembly may be implemented with a wafer-thick PFB. For example, the pick-and-place assembly may be configured to provide a transparent, thermomechanically stable substrate, attach a source wafer containing the PFB to the transparent, thermomechanically stable substrate using an adhesive, dice the source wafer into the PFB, and pick and place the PFB from the transparent, thermomechanically stable substrate onto the product substrate using a nano-precision pick-and-place assembly process.

[0011] Some embodiments may test the PFBs on the source wafers to identify known good PFBs for assembly. For example, in some embodiments, testing may determine known good PFBs through functionality testing and logical connectivity testing. This may be performed, for example, using areas inside, around, or outside the PFBs on the first type source wafer and the second type source wafer. The overall goodness of the PFB may be estimated by testing select portions of the PFB and extrapolating using a statistical model.

[0012] Some embodiments provide a method for ensuring hardware security during the manufacture of semiconductor devices. In some embodiments, a first type of source wafer may be provided, including high-resolution circuit elements partitioned into multiple prefabricated blocks (PFBs). The first type of source wafer may be processed at one or more trusted or untrusted facilities. Some embodiments may use a second type of source wafer, including low-resolution circuit elements partitioned into multiple PFBs. The second type of source wafer may be processed at one or more trusted or untrusted facilities. PFBs from the first type of source wafer may be assembled onto a product substrate. PFBs from the second type of source wafer may then be assembled onto the previously assembled PFBs. This may create a group of fully assembled high-resolution and low-resolution PFBs that are functionally equivalent to a monolithically constructed SoC. In some embodiments, the assembly may be performed at a trusted facility.

[0013] Some embodiments include a method for fabricating semiconductor devices. One or more source wafers may be provided. The source wafer may have a grid of prefabricated blocks (PFBs) and a sacrificial layer that may be etched away to release the PFBs from the bulk of the one or more source wafers. A tether etch may be applied to create tethers beneath the PFBs. An etchant may be used to dissolve the tethers, releasing all PFBs on a single source wafer to a PFB chuck. One or more PFBs may be individually picked from the PFB chuck and placed on a product wafer using nano-precision alignment techniques. The PFBs may be bonded to the product wafer.

[0014] In some embodiments, a source wafer may be provided. The source wafer may have a grid of prefabricated blocks (PFBs) and a sacrificial layer that may be etched away to release the PFBs from the bulk of the source wafer. The source wafer with the sacrificial layer may be comprised of a substrate having two or more layers of different doping levels and / or types, grown, for example, using an epitaxial growth process. A tether etch may be applied to create tethers under the PFBs. An etchant may be used to dissolve the tethers, releasing all PFBs on a single source wafer to a PFB chuck. One or more PFBs may be individually picked from the PFB chuck and placed on a product wafer using nano-precision alignment techniques. The PFBs may be bonded to the product wafer.

[0015] In some embodiments, a source wafer with a grid of prefabricated blocks (PFBs) may be used. In some embodiments, the source wafer does not have a sacrificial layer, and a porosity creation process may be applied in conjunction with a porosity repelling field to create a buried sacrificial layer in the source wafer. A tether etch may be applied to create tethers in the buried sacrificial layer below the PFBs. An etchant may be used to dissolve the tethers, releasing all PFBs on a single source wafer to the PFB chuck. One or more PFBs may be individually picked from the PFB chuck and placed on a product wafer using nano-precision alignment techniques. The PFBs may be bonded to the product wafer.

[0016] In some embodiments, semiconductor devices may be fabricated using a first set of source wafers having a grid of prefabricated blocks (PFBs) and a second set of source wafers each having a grid of custom metal dies (CMDs). The CMDs from the second set may be assembled on top of the PFBs from the first set of source wafers. The first set of source wafers may then serve as product wafers.

[0017] In some embodiments, one or more source wafers may be provided or created that include a grid of prefabricated blocks (PFBs). Two or more layers of PFBs may then be assembled onto the product wafer. In some embodiments, the second, third, or subsequent layers of PFBs include only metal structures.

[0018] Embodiments of the present technology also include a computer-readable storage medium that includes a set of instructions for causing one or more processors to perform the methods, method variations, and other operations described herein.

[0019] Some embodiments provide a system for fabricating semiconductor devices. The system may include an etching chamber, a nano-precision pick-and-place assembly unit, a storage unit, a transfer arm, and / or other components (e.g., processing and testing units, etc.). The storage unit may internally store a plurality of source wafers and product wafers. In some embodiments, the plurality of source wafers may include a first type of source wafer and a second type of source wafer, each having a different prefabricated block. The transfer arm may be configured to transfer one or more of the source wafers to an etching chamber where tethered etching is applied. The transfer arm may also be configured to transfer one or more source wafers from the etching chamber to the nano-precision pick-and-place assembly unit upon completion of the tethered etching. The nano-precision pick-and-place assembly unit may assemble prefabricated blocks (PFBs) from the one or more source wafers into product substrates. In some embodiments, the system may be part of a minimal fab. The minimal fab may further include one or more test units for testing known good die in the multiple source wafers and / or one or more chemical mechanical polishing (CMP) units for polishing the top surfaces of the multiple source wafers.

[0020] While multiple embodiments are disclosed, still other embodiments of the present invention will become apparent to those skilled in the art from the following detailed description, which shows and describes illustrative embodiments of the invention. As will be understood, the present invention is capable of modification in various aspects, all without departing from the scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive.

[0021] Embodiments of the present technology will be described and explained with the aid of the accompanying drawings. [Brief explanation of the drawings]

[0022] [Figure 1]FIG. 1 illustrates an example of a pick-and-place sequence for assembling a 3D-IC that may be used in various embodiments of the present technology. [Figure 2] FIG. 1 illustrates an example of a pick-and-place sequence for a microscale module assembly ASIC (M2A2) that may be used in some embodiments of the present technology. [Figure 3] FIG. 1 illustrates the similarities between unit steps in nanoimprint lithography and pick-and-place assembly used in one or more embodiments of the present technique. [Figure 4] FIG. 1 illustrates an example of a pick-and-place stepper that may be used in various embodiments of the present technology. [Figure 5] 5A and 5B illustrate an example wafer stage configuration having a single stage with both source and product wafers on the same carriage, according to various embodiments of the present technology, and a multiple T-configuration stage, according to some embodiments of the present technology. [Figure 6] 1 is an example of a thermally actuated wafer chuck that may be used in some embodiments of the present technique. [Figure 7] 1 is an example of a topography-controlled thermally actuated wafer chuck that may be used in one or more embodiments of the present technique. [Figure 8] 1 is an example of a NIL template-based superstrate for 2D die pickup that may be used in various embodiments of the present technology. [Figure 9] 1 is an example of a NIL template-based superstrate for PFB pickup that may be used in some embodiments of the present technology. [Figure 10] 1 is an example of a massively parallel superstrate design that may be used in one or more embodiments of the present technology. [Figure 11] 1 is an example of a multi-zone superstrate chuck that may be used in various embodiments of the present technique. [Figure 12]1 is an example of a non-silicon source wafer for pick and place that may be used in some embodiments of the present technology. [Figure 13] FIG. 1 illustrates an example of a source wafer containing all PFBs within each wafer field in accordance with one or more embodiments of the present technique. [Figure 14] 1 is an example sequence for assembly of a CMD fabricated on an SOI wafer, according to various embodiments of the present technique. [Figure 15] 1 is an example sequence for assembly of a CMD fabricated on a Si wafer, according to some embodiments of the present technology. [Figure 16] 1 is an example sequence for pick-and-place assembly of PFB / 2D die / CMD on a regular Si wafer, in accordance with one or more embodiments of the present technology. [Figure 17] FIG. 1 is a schematic illustration of an example of a carrier substrate with microscale pinholes for improved thermal conductivity that may be used in various embodiments of the present technology. [Figure 18] 1 is an example sequence for pick-and-place assembly of PFB / 2D die / CMD on a regular Si wafer onto a roll-to-roll carrier substrate according to some embodiments of the present technology. [Figure 19] 1 is an example of a sequence for manufacturing (designing and configuring) a super-sized FPGA in accordance with one or more embodiments of the present technology. [Figure 20] 1 is an example of a sequence for fabricating (designing and organizing) a super-sized ASIC, according to various embodiments of the present technology. [Figure 21] 1 is an example of a memory PFB for a domain-specific SoC that may be used in some embodiments of the present technology. [Figure 22] 1 is an example of a digital logic PFB for a domain-specific SoC that may be used in one or more embodiments of the present technology. [Figure 23] 1 is an example of a mixed-signal PFB for a domain-specific SoC that may be used in various embodiments of the present technology. [Figure 24] 1 is an example of a sequence for organizing PFBs, FPGAs, ASICs, and other blocks to realize a domain-specific SoC, according to some embodiments of the present technology. [Figure 25] 1 is an example sequence for assembling a CMD onto an orchestrated PFB / other component-SoC to achieve a domain-specific SoC, according to one or more embodiments of the present technology. [Figure 26] 1 is an example of an M2A2-EDA flow for a logical PFB-based SoC, according to various embodiments of the present technology. [Figure 27] 1 is an example overview of a PFB design algorithm, according to some embodiments of the present technology. [Figure 28A] FIG. 1 illustrates an example of a dissimilarity cost analysis in a PFB design algorithm that may be used in one or more embodiments of the present technology. [Figure 28B] FIG. 1 illustrates an example of a dissimilarity cost analysis in a PFB design algorithm that may be used in one or more embodiments of the present technology. [Figure 28C] FIG. 1 illustrates an example of a dissimilarity cost analysis in a PFB design algorithm that may be used in one or more embodiments of the present technology. [Figure 28D] FIG. 1 illustrates an example of a dissimilarity cost analysis in a PFB design algorithm that may be used in one or more embodiments of the present technology. [Figure 29] 1 is an example of K-means clustering to create a final PFB in a PFB design algorithm that may be used in various embodiments of the present technology. [Figure 30] 1 is an example of a general overview of a PFB organization algorithm that may be used in some embodiments of the present technology. [Figure 31] 1 is an example of assembling a CMD using an orchestrated PFB-SoC to achieve a final SoC, according to one or more embodiments of the present technology. [Figure 32] 1 is an example of a process for integrating a PFB-assembled SoC to achieve a final SoC, according to various embodiments of the present technology. [Figure 33]1 is an example of an exemplary floorplan based on an ASIC and M2A2, according to various embodiments of the present technology. [Figure 34] 1 is an example of an exemplary floorplan based on an ASIC and M2A2, according to some embodiments of the present technology. [Figure 35] 1 is an example of a method for testing an M2A2-based SoC that may be used in one or more embodiments of the present technology. [Figure 36A] FIG. 1 illustrates an example of test logic for a PFB, CMD, and final-level SoC in an M2A2-based design that may be used in various embodiments of the present technology. [Figure 36B] FIG. 1 illustrates an example of test logic for a PFB, CMD, and final-level SoC in an M2A2-based design that may be used in various embodiments of the present technology. [Figure 36C] FIG. 1 illustrates an example of test logic for a PFB, CMD, and final-level SoC in an M2A2-based design that may be used in various embodiments of the present technology. [Figure 36D] 1 illustrates an example of test logic for a PFB, CMD, and final-level SoC in an M2A2-based design that may be used in various embodiments of the present technology. [Figure 36E] FIG. 1 illustrates an example of test logic for a PFB, CMD, and final-level SoC in an M2A2-based design that may be used in various embodiments of the present technology. [Figure 37] 1A-1C illustrate a split processing approach that may be used in some embodiments of the present technology. [Figure 38] FIG. 1 illustrates a split fabric (SDSF) with N-MAP in accordance with one or more embodiments of the present technology. [Figure 39] FIG. 1 is a block diagram illustrating an example of a vacuum-based pick-and-place assembly process modeled along the lines of J-FIL that may be used in various embodiments of the present technology. [Figure 40] 10A-10C illustrate access hole formation and encapsulation layer coating according to some embodiments of the present technology. [Figure 41] 14A-14D illustrate an example of a timed etch of a sacrificial layer leaving behind an ether in accordance with one or more embodiments of the present technology. [Figure 42] 1A-1C illustrate an example of a PFB being picked up from a source wafer, in accordance with various embodiments of the present technique. [Figure 43] 1 is an example of a process sequence for encapsulation layer removal in a default assembly configuration, according to some embodiments of the present technology. [Figure 44] 1 is an example of pick and place onto a product wafer using a die-by-die pickup superstrate, in accordance with one or more embodiments of the present technique. [Figure 45] 10 is an example process sequence for assembly configuration 2 where PFB metal contacts contact an areal array from a product wafer, according to various embodiments of the present technology. [Figure 46] FIG. 1 illustrates an example scenario where the gap pressure is significantly greater than atmospheric pressure during pick-up from a source wafer. [Figure 47] FIG. 10 illustrates a snapshot of a PFB during pick-up from a source wafer in accordance with one or more embodiments of the present technique. [Figure 48] 14A-14D show holes in a super straight pin that may be used in some embodiments of the present technology. [Figure 49] 10A-10C illustrate snapshots of a PFB prior to placement on a product wafer in accordance with various embodiments of the present technology. [Figure 50] 1A-1C illustrate domains for DSMC simulation of PFB pickup in accordance with various embodiments of the present technology. [Figure 51] 10 is a flowchart illustrating an example set of operations that may be used to derive a suction ensured pick-up plan in accordance with some embodiments of the present technology; [Figure 52] 1A-1C illustrate an example of a DSMC simulation of pressure, in accordance with various embodiments of the present technology. [Figure 53]10 is a plot showing an example of the change in average gap pressure in accordance with various embodiments of the present technology; [Figure 54] 10 is a plot of an example of a suction ensured motion plan for 2D die pickup from a source wafer, in accordance with various embodiments of the present technology; [Figure 55] 1 is a flowchart illustrating an example set of operations for deriving a placement time estimate that may be used in some embodiments of the present technology. [Figure 56] 10 is a plot showing an example of the change in average gap pressure for a PFB placement in accordance with one or more embodiments of the present technology. [Figure 57] 1 illustrates an example process flow for creating a buried sacrificial layer in bulk silicon, according to various embodiments of the present technique. [Figure 58] 1 is an example process flow for creating a buried sacrificial layer in bulk silicon, in accordance with some embodiments of the present technique. [Figure 59] FIG. 1 illustrates porosity rappelling in silicon coated with a thin chromium layer. [Figure 60] FIG. 1 illustrates a photoelectrochemical etcher for porosity creation that may be used in various embodiments of the present technique. [Figure 61] 1 illustrates an example of an air bearing for stiffness calculation, in accordance with various embodiments of the present technology; [Figure 62] FIG. 1 shows an example of an air bearing gap reduced by a factor of 10. [Figure 63] FIG. 1 illustrates an example of a PFB chuck showing the individual microvalve and pin layers. [Figure 64] 1 illustrates an example of a superlithography die using N-MAP, in accordance with various embodiments of the present technology. [Figure 65] FIG. 1 is a block diagram illustrating various components of a minimal fab that may be used in some embodiments of the present technology. [Figure 66] 1 is an example of a computer system that may be used in some embodiments of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0023] These drawings are not necessarily drawn to scale. Similarly, for the purposes of illustrating some embodiments of the present technology, some components and / or operations may be separated into different blocks or combined into a single block. Moreover, while the present technology is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described in detail below. However, the intention is not to limit the present technology to the specific embodiments described. On the contrary, the present technology is intended to cover all modifications, equivalents, and alternatives falling within the scope of the technology as defined by the appended claims.

[0024] Various embodiments of the present invention relate generally to nanofabrication and design of integrated circuits. More specifically, some embodiments of the present technology relate to nanoscale aligned 3D stacked integrated circuits (N3-SI) and microscale modular assembled ASIC (M2A2) technologies for advanced semiconductor devices. Traditional integrated architectures for semiconductor devices consist of a single transistor layer fabricated on high-quality silicon and multiple layers of conductive lines connecting the transistors in a hierarchical manner. Due to challenges associated with growing high-quality crystalline silicon on top of previously fabricated layers, devices have historically been limited to such architectures, i.e., a single densely packed transistor layer, instead of several stacks of heterogeneously integrated transistor layers.

[0025] However, scaling challenges are finally pushing the industry toward heterogeneous integration schemes. A range of methods is being explored, from package and bond pad level integration to sequential monolithic integration at the individual transistor level. Various embodiments of the present technology provide ultra-high density heterogeneous integration enabled by nano-precision pick-and-place assembly. For example, some embodiments provide the integration of modular assembly techniques using prefabricated blocks (PFBs). These PFBs can be fabricated on one or more source wafers. Pick-and-place techniques can then be used to selectively place the PFBs on destination wafers, thereby efficiently creating N3SI and M2A2. Some embodiments include systems and techniques for using pick-and-place assembly to build semiconductor devices arbitrarily larger than the standard photolithography field size of 26 x 33 mm.

[0026] While scaling is a central issue for the semiconductor industry, there are other problems that can also be addressed using the methods explored here. Hardware security is one such problem. For a device to move from initial design to large-scale processing manufacturing and deployment, it is necessary to share sensitive intellectual property across many organizations and state lines. With the information involved, untrusted members in the supply chain could potentially counterfeit the original design and / or insert malicious components into the device.

[0027] The semiconductor industry loses up to $4 billion annually due to intellectual property infringement, with an estimated $169 billion annually due to counterfeit ICs (including recycled, remarked, tampered, and overproduced ICs). Various embodiments of the present technology provide a split-fabrication approach as a solution to the hardware security problem. This can involve fabricating high-resolution front-end portions of a circuit at an advanced, possibly untrusted, foundry, while lower-resolution circuit fabrication occurs at a trusted (perhaps local or in-house) but less advanced foundry. Some embodiments thus enable the manufacture of semiconductor devices where hardware security is guaranteed, even when parts of the device are fabricated at untrusted facilities.

[0028] Additionally, some embodiments provide associated circuit design methodologies for the above applications. Some embodiments also include systems and methods for converting bulk silicon source wafers to include embedded sacrificial layers for pick-and-place assembly. Furthermore, methods are also provided for enabling nano-precision assembly through nanoscale airflow modeling during pick-and-place assembly. The concept of a semiconductor processing facility, or minimal fab, has significantly smaller footprint and capital requirements than traditional large-scale fabs, but can be used in conjunction with large-scale fabs for custom semiconductor device fabrication by entities / companies that do not necessarily specialize in semiconductor processing.

[0029] Various embodiments of the present technology provide a wide range of technical effects, advantages, and / or improvements to processing systems and components. For example, various embodiments include one or more of the following technical effects, advantages, and / or improvements: 1) enabling numerous applications requiring nanometer-precise assembly of circuit elements (e.g., applications such as 3D integrated circuits, dies with superlithographic form factors, hardware security, and high-mix, low-volume ASICs); 2) nanometer-precise assembly achieved by utilizing various techniques, including a novel process for creating buried sacrificial layers within bulk silicon source wafers; 3) use of a nanoscale airflow-aware superstrate design to pick circuit elements from a source wafer while maintaining lithographic accuracy and create nanometer-precise assembly; 4) integration of an in-air overlay correction method to create nanometer-precise assembly achieved by utilizing various techniques, further utilizing moiré-based alignment metrology for nanometer-precise placement of circuit elements on product wafers; and / or 5) a novel electronic design-by-design (EDA) scheme for high-mix, low-volume ASICs. Some embodiments may include other technical effects, advantages, and / or improvements as discussed herein.

[0030] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present technology. However, it will be apparent to one skilled in the art that embodiments of the present technology may be practiced without some of these specific details.

[0031] The techniques introduced herein can be embodied as dedicated hardware (e.g., circuits), as programmable circuitry appropriately programmed with software and / or firmware, or as a combination of dedicated and programmable circuitry. Accordingly, embodiments may include a machine-readable medium having stored thereon instructions used to program a computer (or other electronic device) to perform a process. Machine-readable media may include, but are not limited to, a floppy diskette, an optical disk, a compact disk-read-only memory (CD-ROM), a magneto-optical disk, a ROM, a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic or optical card, a flash memory, or any other type of medium / machine-readable medium suitable for storing electronic instructions.

[0032] Phrases such as "in some embodiments," "in some embodiments," "in an illustrated embodiment," "in another embodiment," and the like generally mean that the particular feature, structure, or characteristic that follows the phrase is included in at least one implementation of the technology and may be included in more than one implementation. Moreover, such phrases do not necessarily refer to the same or different embodiments.

[0033] Various embodiments of the present technology relate to systems and methods for fabricating 3D-ICs and microscale modular assembled ASICs (M2A2s) using nano-precision pick-and-place assembly techniques. Typical pick-and-place sequences for assembling 3D-ICs and M2A2s, according to various embodiments, are shown in Figures 1 and 2, respectively.

[0034] FIG. 1 illustrates an example pick-and-place sequence for assembling 3D-ICs that may be used in various embodiments of the present technology. As shown in FIG. 1, multiple different source wafers 110A-110N may contain various 2D dies that can be assembled using a pick-and-place process 120 to create a 3D-IC 130. The various embodiments of the 3D-IC process illustrated in FIG. 1 may be configured so that assembly can occur in a front-to-back (F2F), front-to-back (F2B), back-to-front (B2F), or back-to-back (B2B) manner. The B2F, F2B, and B2B stacked 3D-ICs can later be connected using, for example, through-silicon vias (TSVs). The F2F stacked 3D-ICs can be connected using interlayer vias (ILVs), as shown in callout 140, which shows an enlarged portion of the 3D-IC 130.

[0035] 2 illustrates an example pick-and-place sequence 200 for a microscale modular assembly ASIC (M2A2) that may be used in some embodiments of the present technology. As shown in the embodiment illustrated in FIG. 2, source wafers 210A-210N may include multiple source wafers 210A-210N, each including a different prefabricated block (PFB). According to various embodiments, source wafers 210A-210N may include multiple PFBs on a sacrificial layer (e.g., a buried oxide layer), as illustrated in cross section 215 of source wafer 210N.

[0036] The pick-and-place superstrate can be designed with programmable pick-up locations that allow the pick-and-place process 220 to pick up a source wafer and transfer one or more PFBs from the source wafer to a product substrate to create a customized assembled ASIC 230. As can be seen in callout 240, which shows an enlarged cross-sectional view of a portion 235 of ASIC 230, different PFBs 250 can be placed side-by-side in any desired order on a product substrate 260.

[0037] For any typical pick-and-place assembly sequence, errors may occur during various intermediate steps, all potentially contributing to the final overlay error. Table I provides an overview of these error sources.

[0038] [Table 1]

[0039] Various embodiments provide various techniques for reducing and / or eliminating the above-mentioned sources of overlay error. The overlay control techniques described in the following sections may be briefly referred to as "overlay control architectures." Unless otherwise specified, the disclosed methods may be applied to any of the applications explored herein.

[0040] (Machine design based on J-FIL STEPPER) Various embodiments of the present technology provide a novel design for a generic pick-and-place tool that integrates design elements from a nanoimprint lithography stepper. Figure 3 shows a generic pick-and-place assembly sequence 300 and a nanoimprint lithography sequence 350 side-by-side. For example, while NIL / J-FIL uses a glass template, some embodiments of the present technology incorporate a pick-and-place stepper that uses a vacuum superstrate. In some embodiments, the pick-and-place stepper can essentially be a NIL template modified with vacuum lines. NIL / J-FIL uses UV-curable resist. Some embodiments of the present technology can incorporate a pick-and-place stepper that can use a UV-curable liquid, which can be similar in formulation to the UV-curable resist. NIL / J-FIL uses Moiré-based overlay metrology and MSCS-based overlay correction. In various embodiments, overlay metrology in the pick-and-place stepper can also be performed using Moiré-based metrology. NIL / J-FIL includes a separation step after UV exposure where care is taken not to damage the hardened resist. Pick-and-place steppers used in various embodiments of the present technology can use similar controlled separation to pick up 2D dies from their source substrates.

[0041] FIG. 4 shows a pick-and-place stepper 400 modeled along the lines of a nanoimprint stepper. In the embodiment shown in FIG. 4, the stepper 400 can include a z-head assembly 410. The z-head assembly 410 can have one or more of the following features: a moving z-axis, in-line overlay metrology, a superstrate chuck, and vacuum and etchant routing. The z-head assembly 410 can be movably mounted on a granite bridge 420 on a granite base 430. A source wafer 440 and a product wafer 450 can be positioned on a wafer chuck assembly 460, which enables pick-and-place by a superstrate 470 located on the z-head assembly 410. Some embodiments can include an operating state 480 that includes both source and product substrates mounted on the same carriage.

[0042] Various embodiments of the stepper 400 can have one or more wafer stages. These can be air-bearing stages, roller-bearing stages, or any other variety / combination of stages capable of generating planar motion with nanometer precision while withstanding normal forces without loss of precision. FIGS. 5A and 5B show examples of wafer stage configurations used in some embodiments. In FIG. 5A, a single stage is shown with both the source and product wafers on the same carriage. In FIG. 5A, the source and product wafers 510 (and chuck assemblies) can be contained on a single stage carriage. The chuck assemblies can share (X,Y) degrees of freedom, but can have independent theta and higher-order actuation. In the case of a single stage, the stage can have multiple chucks to hold various source and product wafers (FIG. 5A).

[0043] FIG. 5B illustrates an embodiment having a multiple T-configuration stage. In a multiple T-configuration, the source and product wafers 520 (and chuck assemblies) can be arranged in a "T" shape (e.g., a top row with three chuck assemblies and a single chuck assembly directly below). In these embodiments, the (X, Y, theta) degrees of freedom can be independently controlled for each of the wafers 520. In some embodiments, additional higher degrees of freedom can be independently controlled. Thus, the stepper 400 can have multiple independent motion stages, each with its own single chuck or multiple chucks (FIG. 5B).

[0044] The wafer chuck can have thermal actuator units (heating / cooling elements) embedded within it. An example of such a chuck design is shown in Figure 6. The additional electrical wires and components required to control multiple thermal actuators can be housed in an assembly on the stage carriage, along with an on-board multiplexer to reduce the number of wiring connections through the stage wire tracks. Thermal actuators can be used not only to maintain the chuck at a desired constant temperature, but also to intentionally change the thermal profile to achieve a specific distortion profile, such as that shown in heating / cooling element 610. The cross-sectional view of the chuck at the bottom of Figure 6 shows fins 620 separating the heating elements. The following reference, incorporated herein by reference in its entirety for all purposes, describes such features: Ajay, Paras, et al., "Multi-Field Sub-5-nm Overlay in Imprint Lithography," Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 34.6 (2016): 061605. According to various embodiments, the wafer chuck can be made from a transparent material (in the relevant spectrum), such as alumina and transparent SiC, allowing for bottom-up metrology and adhesive-liquid curing. FIG. 7 is an example of a topography-controlled, thermally actuated wafer chuck that may be used in one or more embodiments of the present technology. In the embodiment shown in FIG. 7, wafer chuck 700 may further include an array of embedded z-actuators (piezoelectric, voice coil-based, etc.) to change the wafer topography during the pick-and-place step. In FIG. 7, a bottom view 710 is shown along with a cross-sectional view 720 along line AA.

[0045] The wafer chuck 700 can include topography control elements 730. As shown in cross-sectional view 720, each of these elements can include a thermal actuator 740, a thin top portion 750, and a topography control element 730 sandwiched between the thermal actuator 740 and a thick bottom portion 760. Thus, the wafer chuck 700 can set a desired topography on the pin surfaces 770. For example, in some embodiments, chirped moire alignment marks patterned on the wafer can be used to detect topography errors (as well as in-plane distortion) in an in-line manner. Superstrate-substrate topography matching is important in pick-and-place assembly, and even more so in NIL. This is because, during the pickup step, contact between the 2D die / PFB and the superstrate at different instances can create localized areas of premature sacrificial tether failure, increasing the likelihood of overlay loss, as can poorly matched superstrate-substrate topography. Furthermore, during the placement step, the range of in-liquid alignment to correct overlay errors due to topography mismatch (or other causes, for that matter) is reduced because the 2D die / PFB is held to the superstrate over a significantly smaller area compared to the NIL template (which reduces frictional resistance to sliding). To reduce the above eventuality, various embodiments correct both topography and overlay errors "in-air."

[0046] (Super Straight Design) Various embodiments of the present technology include the design of a superstrate based on a NIL fused silica template. Figure 8 shows an example of a NIL template-based superstrate for 2D die pickup that may be used in various embodiments of the present technology. Figure 9 shows an example of a NIL template-based superstrate for PFB pickup that may be used in some embodiments of the present technology. Fused silica has a low thermal expansion coefficient, making it suitable as a thermally stable substrate during pick-and-place assembly. It is also transparent to the visible, UV, and near-infrared spectrum, which allows for light transmission during metrology and resist / adhesive curing. It is also relatively easy to machine compared to other rigid substrates such as SiC and alumina. Fused silica templates for NIL are commercially available. Unless otherwise noted, this disclosure primarily explores two methods: gas-phase HF-based detack and tether-breaking-based detack. However, other embodiments of the present technology may use different techniques.

[0047] [Table 2]

[0048] A superstrate assembly may have a single superstrate or multiple connected or unconnected sub-superstrates. In the continuum of possible superstrate design choices, one possible asymptotic case is a superstrate assembly with thousands of individually actuatable sub-superstrates for thousands of possible picked PFBs.

[0049] 10 is an example of a massively parallel superstrate design 1000 that may be used in one or more embodiments of the present technology. As shown in the embodiment depicted in FIG. 10, the system may include a global z actuation axis 1010, a thermal actuator 1020, a superstrate chuck 1030 (e.g., with global airflow and / or etchant routing), a massively parallel superstrate assembly 1040, and a magnetic actuator 1050. In some embodiments, the global z actuation axis 1010 may be a voice coil actuator, a piezoelectric actuator, or the like.

[0050] In some embodiments, each sub-superstrate 1060 may be actuated using an actuator 1080 (e.g., a microscale piezoelectric element). The global superstrate assembly 1040 and / or the sub-superstrate 1060 may be fitted with thermal actuators 1020 to maintain the superstrate at a constant temperature or to actively vary the temperature of the superstrate for strain control, e.g., in conjunction with wafer thermal actuators. The superstrate may additionally use a mag actuator 1050 setup to strain the superstrate in a controlled manner for overlay correction. Each sub-superstrate assembly may have routing 1070 for a sacrificial layer etchant to etch the PFB / 2D die tether in-situ and airflow routing for vacuum pickup.

[0051] FIG. 11 is an example of a multi-zone superstrate chuck 1100 that may be used in various embodiments of the present technology. The superstrate chuck embodiment shown in FIG. 11 may have multiple zones 1110, providing a global source of airflow and etchant paths 1120 within a multi-layer superstrate assembly 1130. In some embodiments, the gas paths can be coated with Teflon, aluminum oxide, or some other inert material to protect the tool from corrosive etchants. Additionally, the global airflow can be directed away from critical areas within the tool and toward a waste outlet to ensure further protection from leaks and corrosion. Additionally, an air curtain can be established to further prevent the spread of leaked etchant.

[0052] To contain the gaseous etchant in the in situ etching chamber, the chamber can be sealed using, for example, a Teflon O-ring. Because the intent of gas-phase HF-based detachment is only to separate the 2D die as quickly as possible, rather than uniformity of the etch transient rate, the gas-phase HF etch can be performed at high temperatures using thermal actuators on the superstrate and wafer chuck and / or by heating the gas-phase HF itself before it enters the etching chamber.

[0053] Superstrate vacuum holes in superstrates made of fused silica can be made using computer numerically controlled (CNC) machining, laser machining, or a variety of other material removal techniques. The pins shown in Figures 8 and 9 can be made using chemical etching techniques such as buffered oxide etching or vapor phase HF etching.

[0054] (Heterogeneous material assembly) Various embodiments of the present technology can use 2D dies / PFBs made of non-silicon semiconductor materials, such as GaAs or InP, in pick-and-place assembly. One possible way to pick-and-place 2D dies / PFBs made of GaAs or InP is to have a suitable buried sacrificial layer that can be selectively etched away, preferably using a gaseous reactant. The encapsulation layer of these PFBs can be composed of materials that are resistant to gas-phase etchants, such as PTFE, parylene, or spin-on carbon. Figure 12 shows an example of a non-silicon source wafer 1200 for pick-and-place that may be used in some embodiments of the present technology. In the embodiment shown in Figure 12, the non-silicon source wafer 1200 can include a device layer 1210, a sacrificial layer 1220, and a bulk layer 1230. Several groups have previously explored this. See Table 3 for a summary of these efforts.

[0055] [Table 3]

[0056] (M2A2 cost sharing paradigm) Some embodiments may use separate source wafers for each PFB. However, this is not necessarily the case. A single source wafer may have multiple types of PFBs. FIG. 13 shows an example of a source wafer 1300 that includes all PFBs 1310A-1310C within each wafer field 1320, in accordance with one or more embodiments of the present technology. Other embodiments may include more or fewer types of PFBs on the source wafer. If all PFBs required for a design are present on a single wafer, only one expensive mask must be created, and mask cost amortization will be maximized.

[0057] (M2A2 paradigm: PFB assembly + custom metal die (CMDS)) In some embodiments, once the PFB layer is assembled, the wafer may be sent back to the fab for subsequent metallization. In many situations / applications, this may not be recommended. For example, a metallization fab may not accept wafers processed using non-standard equipment, such as a pick-and-place assembler. In applications with security concerns (e.g., defense applications) and highly competitive domains (e.g., emerging machine learning applications), designers may not prefer that wafers be returned to a third-party metallization fab, but may not have the financial resources to own a personal fab.

[0058] As one possible solution to the above, the metallization structure itself may be fabricated as a 2D die, i.e., a custom metal die (CMD), on a wafer with an embedded sacrificial layer and then picked and placed onto the PFB layer. In this way, the pick-and-place assembly step would now be the last step in the overall circuit fabrication process. Note that the fabrication of the PFB and CMD can be done in separate fabs. This can be beneficial if a designer has a preferred fab for the CMD that is different from the PFB fab.

[0059] FIG. 14 illustrates an example sequence 1400 for the assembly of a CMD fabricated on an SOI wafer, according to various embodiments of the present technology. As shown in FIG. 14 , a product wafer 1410 with an assembled PFB layer can be used along with a CMD 1420 on an SOI wafer 1430. Note that the metal size (and pitch) can decrease with increasing layer number 1440. This allows the correct metal pitch to face the PFB when the CMD is flipped. As shown in FIG. 14 , the process can include various steps such as through-hole etching 1450, encapsulation 1460, tether formation 1470, and pick-and-place 1480 (with or without flipping), which can be performed using D1, D2, and processes previously described in this disclosure. Additionally, in the embodiment illustrated in FIG. 14 , vias would have to be drilled into the thin silicon layer in the inverted CMD to access solder bumps 1490 for circuit packaging.

[0060] FIG. 15 illustrates an example sequence 1500 for assembly of a CMD fabricated on a Si wafer, according to some embodiments of the present technology. In the embodiment shown in FIG. 15, a product wafer 1510 with an assembled PFB layer can be provided, and a CMD can be fabricated on the Si wafer 1520. First, an oxide layer 1430 can be formed on top of the Si wafer 1520, which can then be encapsulated with an encapsulation layer 1540. A metal layer is then fabricated to create the CMD 1550. In some embodiments, a second encapsulation layer 1555 can be fabricated over the CMD 1550. Next, through-hole etching 1560, tether formation 1565, and pick-and-place 1570 (with or without inversion) are performed. In the embodiment shown in FIG. 15, deposition of the oxide layer on the Si can be achieved using standard semiconductor processes, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). In-situ ashing 1575 can be achieved using an in-tool oxygen plasma chamber. The ashing process can be timed so that the ashing stops when encapsulation layer 1, which is generally thinner than encapsulation layer 2, is etched away.

[0061] Note that in the sequence of Figure 15, the encapsulation layer is fairly thick. This is to provide additional mechanical support to the oxide layer during pick and place. The encapsulation layer material must be resistant to the sacrificial layer etchant, compatible with standard semiconductor processes, and easily etchable (preferably with a gaseous etchant) once pick and place is performed. This allows for direct connection 1580 to the package solder bumps. Table 4 provides a list of potential options.

[0062] [Table 4]

[0063] (M2A2 / 3D-IC paradigm: wafer-thick PFB / CMD / 2D die assembly) While some embodiments may utilize a sacrificial layer (e.g., see 1220 in FIG. 12 ) to facilitate separation of the PFB / CMD / 2D die from the bulk substrate, this configuration may not be preferred in various applications. For example, such a configuration may not be preferred if such a wafer with a buried sacrificial layer is not available and / or is not compatible with standard processes in the fab. As a solution to the above, pick-and-place can be performed on the 2D die / PFB, which is wafer-thick. The 2D die / PFB substrate may be Si, GaN, GaAs, or various other materials, as previously described.

[0064] FIG. 16 shows a sequence 1600 in which a source wafer is first bonded onto a transparent, thermally conductive carrier substrate using a UV detack adhesive. The source wafer 1610 (e.g., a 2D die / PFB on a regular Si wafer) may be coated with an encapsulation layer 3 1620. In some embodiments, encapsulation can be performed before the bonding step to protect against contaminants from the carrier substrate 1630 and debris generated during the dicing process. The carrier substrate may be a transparent, head-conductive carrier substrate in some implementations. Encapsulation is also relevant for non-semiconductor-grade carrier substrates, although the fabrication processes are generally not optimized to achieve semiconductor-grade particle levels.

[0065] This encapsulation layer may be made of, for example, polyimide. Wafer dicing 1640 is then performed to singulate the 2D die / PFB. Dicing may be performed using an ablative process such as laser cutting and / or a chemical process such as metal-assisted chemical etching (MACE), which exhibits the ability to etch holes deep into silicon. Any heat generated during the dicing process may be carried away through the conductive carrier substrate.

[0066] In-situ ashing 1660 can be performed to remove the encapsulation layer before pick-up by a pick-and-place superstrate 1670. The 2D die / PFB can be selectively detacked using selective UV exposure of a UV detack adhesive 1650 via a digital micromirror device (DMD) 1680. Examples of carrier substrate choices can be sapphire, transparent SiC, and display-grade glass. Display glass can have microscale pinholes to improve its conductivity.

[0067] 17 is an example schematic diagram of a carrier substrate 1700 with microscale pinholes 1710 for improved thermal conductivity that may be used in various embodiments of the present technology. The pinholes 1710 may be filled with a thermally conductive material, such as indium tin oxide (ITO) or aluminum-doped zinc oxide (AZO), which may be transparent. The glass substrate 1720 may further be coated on its top and bottom surfaces with transparent conductive films of ITO, AZO, and / or a metal mesh, for example, of copper. In some embodiments, the diameter 1740 of the pinholes 1710 may be between 10 microns and 100 microns.

[0068] Alternatively, in Figure 16, the 2D die / PFB may be selectively detacked using an infrared (IR) curable hydrogel-based adhesive, which allows the use of a regular silicon wafer as the carrier wafer, since silicon transmits IR radiation quite well.

[0069] FIG. 18 illustrates a sequence 1800 in which a source wafer is bonded onto a roll-to-roll metal substrate with micro-perforations. A source wafer 1810 (e.g., a 2D die or PFB on a regular Si wafer) can be provided. The source wafer can be aligned with a roll-to-roll carrier substrate 1820 with micro-perforations. In some embodiments, a slot-die coated adhesive 1830 can be used. Wafer dicing 1840 is then performed to singulate the 2D die / PFB. Any heat generated during the dicing process can be carried away through the conductive metal substrate. The 2D die / PFB can then be individually detached using selective O2 plasma ashing of the adhesive between the bonded 2D die / PFB. A superstrate 1850 and a chuck 1860 can be used to pick and place the die. According to some embodiments, the superstrate 1850 and the chuck 1860 can include vacuum holes 1870. A possible material choice for the metal roll can be steel. Micro-drilling may be performed using anisotropic processes such as reactive ion etching (RIE), laser machining, focused ion beam (FIB) machining, etc. This method has the advantage that pick-and-place assembly can be performed on a roll-to-roll system, which may improve the throughput of the assembly process.

[0070] (Machining of super-sized dies using PFB+CMD assembly) For applications requiring die sizes larger than the standard lithography field of 26 mm x 33 mm, the CMD is tessellated onto the PFB layer, possibly in a multi-layer stack, thereby ensuring die-wide metal connectivity across the 26 mm x 33 mm field area. Note that this is not necessarily a high-mix, low-volume application, and therefore the PFB can be field-scale in dimensions and custom-made for each new device.

[0071] (Design and EDA of super-sized FPGAs and ASICs using M2A2 technology) One of the major advantages of M2A2 technology is that it enables the fabrication of super-sized dies with dimensions larger than the field size. Current lithography technology limits the field size to 26 mm × 33 mm, making it impossible to fabricate super-sized dies using existing commercial processing techniques. Furthermore, as the die size approaches the field size, yields drop significantly. However, using M2A2 technology, an ASIC or FPGA die can be segmented into multiple smaller dies / partitions, which can then be assembled / organized using a pick-and-place mechanism. The following subsections describe the methodology for segmenting an ASIC or FPGA into smaller dies / partitions and the EDA methodology required to design and organize each of the smaller dies / partitions.

[0072] Various embodiments of the present technology include a technique for segmenting an ASIC or FPGA into smaller partitions and designing these partitions. The FPGA or ASIC-SoC can be designed using existing commercial / traditional or any other EDA flow. The FPGA or ASIC large die can then be divided into multiple smaller dies / partitions using any of the following methods: (1) random segmentation into partitions of desired smaller size; (2) uniform segmentation based on physical coordinates to achieve smaller partition sizes; or (3) partitioning based on objective function optimization using any of the following optimization techniques: machine learning (ML) learning techniques, annealing, linear / nonlinear discrete optimization, min-flow, min-cut, etc., using in-house, third-party, or newly developed software tools.

[0073] Once the partitions are designed, inter-partition connections are routed in higher metal layers using a custom metal die (CMD). Each partition consists of a base layer and front-end interconnects, and the CMD consists of higher metal layers for routing connections between different partitions. These higher metal layer connections can be routed using existing commercial EDA tools or any in-house / third-party or newly developed software tools. Compared to the ASIC flow, there may or may not be routing constraints such as higher pitch, higher width, extra routing blockages, etc.

[0074] 19-20 illustrate the concept of designing super-sized FPGA and ASIC-SoC using M2A2 technology. However, these embodiments are included for illustrative purposes only, and possible design and partitioning approaches are not limited to those shown in the embodiments.

[0075] (Design and EDA of Domain-Specific SOC based on PFB) Various embodiments of the present technology can use circuit design and EDA methodologies to implement and design configurable and / or high-performance and / or low-power domain-specific SoCs based on PFB. A specific SoC generally refers to an SoC (system-on-chip) that implements the functionality of a given domain. For example, an SoC that implements an image classifier belongs to one domain, and an SoC that performs communication operations belongs to another domain. Circuit design and EDA techniques have been implemented for PFB-configurable hardware accelerator domain SoCs. However, the idea of ​​designing PFB-configurable domain-specific SoCs is not limited to hardware accelerators alone, but can be extended to other domains such as communications, processors, controllers, and high-performance computing (HPC) for servers.

[0076] In recent years, the use of sensors for smart applications has increased exponentially. This has led to an explosion in the amount of data collected by sensors. Machine learning plays a key role in extracting meaningful information from sensor data. Machine learning typically uses neural network techniques to extract meaningful information. This analysis requires a significant amount of computation because data is collected at high speed and in large quantities. This necessitates the need for specialized hardware (called hardware accelerators) that can perform highly energy-efficient operations. Computation can be performed either at the cloud or edge level. Computation in the cloud can pose bandwidth challenges. Furthermore, high energy costs in communication are associated with cloud computing. Therefore, there is an increasing need to perform analysis locally at the sensor (edge) rather than in the cloud. Edge computing also addresses important issues related to privacy, latency, and security. However, edge computing devices have strict energy consumption constraints and require extended battery life. Therefore, there is a need to devise accurate and energy-efficient circuits for edge computing.

[0077] Machine learning algorithms are rapidly evolving to achieve better performance / accuracy. Furthermore, different tasks such as image classification, video classification, and speech recognition in hardware accelerators require different types of neural network architectures (different types of CNN (Convolutional Neural Network) and RNN (Recurrent Neural Network) architectures). Therefore, the number of devices / SoCs required to implement a specific application in this domain is low, but requires high performance and energy efficiency. With the scaling of CMOS process technology, the mask costs for fabricating nanoscale structures have become prohibitively expensive for these low-volume ASIC applications, forcing them to turn to highly suboptimal FPGAs.

[0078] Using M2A2 technology, various embodiments of the technology provide the following benefits for these types of SoCs: (1) configurability for designers to implement new and evolved neural network architectures using existing circuits (designed for existing neural networks); (2) using the same PFB across CNN or RNN architectures. For example, the same PFB can be used to implement convolutional layers in LeNet-5 and AlexNet architectures; and (3) using the same PFB across multiple neural network types, i.e., designing CNNs or RNNs using the same PFB. In this way, mask costs can be shared across multiple variants and types of neural networks that implement various applications in the hardware accelerator domain. Therefore, M2A2 technology can be used to design configurable, energy-efficient circuits for applications in this domain.

[0079] A typical neural network-based machine learning (ML) hardware accelerator includes different types of neuron layers, such as convolutional layers, activation layers, pooling layers, fully connected layers, etc. These layers are implemented in hardware using different signal processing and design domains, such as digital logic, analog domain processing, time domain processing, in-memory or near-memory computing, and mixed-signal design.

[0080] Various embodiments of the present technology provide novel architectures, designs, and EDA of highly configurable, energy-efficient circuits that implement various neural network-based machine learning applications. It is worth mentioning that this concept of achieving configurability and energy efficiency using PFB is not limited to the specific domain of machine learning (ML). The novel architectures and designs of energy-efficient circuits are described using one or more of the following features: 1. The convolutional layer, and / or activation layer, and / or pooling layer, and / or fully connected layer, and other functional blocks are implemented by "microscale circuits" based on one or more of signal processing techniques, i.e., time domain, and / or analog domain, and / or mixed-signal domain, in-memory computing, and / or near-memory computing, and / or digital domain processing techniques, and are referred to as PFBs. 2. There can be multiple types of PFBs, each with a different design configuration and which may include one or more of the following circuits: a. Static Random Access Memory (SRAM), b. Dynamic Random Access Memory (DRAM), c. Non-volatile memory (NVM); d. Digital synthesis blocks containing standard cells / logic gates that implement any function; e. Analog and mixed-signal components such as analog-to-digital converters (ADCs), and / or digital-to-analog converters (DACs), and / or voltage-controlled oscillators (VCOs), and / or time-to-digital converters (TDCs), etc. 3. Each type of PFB contains a finite number of layers, n, where n >= 1. To allow for configurability, all components may be unconnected and left open / floating. 4. A typical domain-specific SoC contains multiple instances of one or more types of PFBs described above (#2). 5. A typical domain-specific SoC may include custom ASIC blocks, FPGAs, memory blocks, other third-party IP (intellectual property) blocks, etc. 6. In this type of SoC, components (PFB, custom and other blocks) are wired together to implement a given function.

[0081] As mentioned above, PFBs are microscale circuits (typically sized between 50 μm x 50 μm and 5000 μm x 5000 μm) used to realize specific layers of neural networks. Each type of PFB can be designed randomly or with one of several objectives / considerations in mind: power, area, performance, PPA, energy efficiency, reduced data movement, neural network requirements, etc. It is worth mentioning that the design of PFBs is not limited to only these objectives.

[0082] 21 is an example of a memory PFB for a domain-specific SoC that may be used in some embodiments of the present technology. The memory PFB can be used for storage and / or computation purposes. The array dimensions can be selected randomly or based on specifications (storage and computation requirements to optimize PPA, energy efficiency, data movement, or any other metric). When determining the size based on specifications, various techniques can be used, such as circuit-based design techniques using existing in-house, existing third-party, or newly developed in-house / third-party software and / or hardware tools, machine learning-based supervised / unsupervised or any other learning techniques, optimization techniques (discrete, linear, nonlinear, etc.), graph techniques, etc.

[0083] The memory cells in these types of PFBs may or may not be connected to each other, determined randomly or based on a configurability vs. performance tradeoff using one of several optimization algorithms (see above). This type of PFB includes a base layer and n metal layers, where n>=1. These PFBs may include any memory technology and technology node. That is, they can be fabricated using any technology node, such as 14 nm, 20 nm, 28 nm, 45 nm, etc., using SRAM, DRAM, eDRAM, NVM, etc. FIG. 21 shows an example of a memory PFB for a domain-specific SoC. However, this embodiment is included for illustrative purposes only, and the possible design configurations of the memory PFB are not limited to those shown in the embodiment.

[0084] 22 illustrates an example of a digital logic PFB for a domain-specific SoC that may be used in one or more embodiments of the present technology. The digital logic PFB can be used to implement digitally synthesized macroblocks used for computation and other purposes. The standard cells and other components within these PFBs are placed and connected to one another using n metal layers (n>=1) either randomly or using optimization techniques (circuit-based design techniques using existing in-house, existing third-party, or newly developed in-house / third-party software and / or hardware tools, machine learning-based optimization, optimization techniques (discrete, linear, nonlinear, etc.), graph techniques, etc.) to optimize one or more of PPA, power, performance, area, energy efficiency, or any other metric.

[0085] These PFBs can also be constructed from standard mini-IP macroblocks such as comparators, shifters, pulse generators, etc. These IP macroblocks can be designed in-house or provided by third-party vendors. Furthermore, these PFBs may include FPGAs to implement any specific functionality. FIG. 22 shows an example embodiment that presents the concept of a digital logic PFB for a domain-specific SoC. However, this embodiment is included for illustrative purposes only, and the possible design configurations of the digital logic PFB are not limited to those shown in the embodiment.

[0086] 23 is an example of a mixed-signal PFB for a domain-specific SoC that may be used in various embodiments of the present technology. Mixed-signal and analog-domain PFBs can be used to implement analog-domain signal processing elements such as amplifiers (OPAMPs, OTAs, differential amplifiers, PLLs, etc.), VCOs, filters, etc. to generate the analog-domain signals required by the domain-specific SoC. These types of PFBs may or may not include mixed-signal domain elements such as ADCs, DACs, TDCs, DTCs, etc. to implement mixed-signal functions (e.g., MAC operations implemented in the analog time or voltage domain) required for analog or mixed-signal domain computation.

[0087] The components of this type of PFB may or may not be connected to each other using n metal layers (where n>=1). These PFBs can be designed entirely in-house, or some or all of the components of these types of PFBs can be provided by a third-party vendor. The placement and selection of which components to place on these types of PFBs can be determined randomly or based on circuit requirements using either circuit-based or other optimization techniques (some of which are described in #1 and #2). FIG. 23 is an example embodiment presenting the concept of a mixed-signal / analog-domain PFB for domain-specific SoCs. However, this embodiment is included solely for illustrative purposes, and the possible design configurations of a mixed-signal / analog-domain PFB are not limited to those shown in the embodiment.

[0088] Some embodiments provide circuit design and EDA methodologies for organizing PFBs and other IP blocks (e.g., FPGAs, custom ASICs, macroblocks, etc.) to realize domain-specific SoCs (e.g., hardware accelerators). Different types of PFBs and other IP blocks can be organized randomly or with one of several objectives / considerations in mind, such as power, area, performance, PPA, energy efficiency, reduced data movement, neural network requirements, etc.

[0089] It is worth noting that the organization of the PFB is not limited to these purposes. When organizing the PFB based on the optimization of some specific metrics / goals, various techniques can be used, such as circuit-based design techniques using existing in-house, existing third-party, or newly developed in-house / third-party software and / or hardware tools, supervised / unsupervised machine learning-based or any other learning techniques, optimization techniques (discrete, linear, nonlinear, etc.), graph techniques, etc. Figure 24 shows an example of a sequence for organizing the PFB, FPGA, ASIC, and other blocks to realize a domain-specific SoC according to some embodiments of the present technology. However, this embodiment is included for illustrative purposes only, and the possible design configurations of a domain-specific SoC based on the PFB are not limited to those shown in the embodiment.

[0090] The PFB-organized SoC consists of the base layer of transistors and front-end interconnects. Connections between components of the same or different PFBs are made using higher metal layers. The PFB-organized SoC is assembled with a custom metal die (CMD). These higher metal layers in the CMD can be designed / routed using existing commercial EDA tools or any in-house / third-party or newly developed software tools. Compared to the ASIC flow, routing constraints such as higher pitch, higher width, extra routing blockages, etc. may or may not exist.

[0091] 25 is an example of a sequence for assembling a CMD on an orchestrated PFB / other component-SoC to realize a domain-specific SoC in accordance with one or more embodiments of the present technology. However, this embodiment is included for illustrative purposes only, and possible approaches for designing / assembling a CMD with an orchestrated PFB are not limited to those shown in the embodiment.

[0092] (EDA Methodology for SOC Based on Logic PFB) FIG. 26 illustrates an example M2A2-EDA flow for a logical PFB-based SoC, according to various embodiments of the present technology. As shown in FIG. 26, a training set design can be provided to a PFB design generation module 2610. The baseline ASIC flow, the number of logical PFBs, and placement data for the design using technology libraries can be provided to a PFB compilation module 2620, which can design a PFB-based SoC. This design can be provided to a synthesis preparation module 2630, and a masking module 2640 can prepare post-mask ECOs for synthesis. An optimization module 2650 can perform one or more pre-CTS optimizations to produce a post-mask CTS 2660. A routing engine 2670 can create a post-mask route, which can be analyzed by a sign-off analysis module 2680. A decision block can determine whether the QoR has been met and submit a design update request or verification 2690 of the design to the foundry.

[0093] FIG. 27 illustrates an example overview of a PFB design algorithm 2700 according to some embodiments of the present technology. FIG. 28 illustrates an EDA methodology for design implementation of an SoC based on a logical PFB. In PFB design generation, a limited number of PFBs are generated based on timing and placement data from multiple baseline ASICs. Once the PFBs are generated, they serve as a design library. In the M2A2 design implementation phase, the PFBs are organized to meet the functional requirements of a given design. We refer to this design as a pre-placed PFB-SoC (pSoC). The PFB and pSoC design placement data are then processed to generate a netlist and a design exchange format (DEF) file. Next, post-mask ECO synthesis is performed using an industry-standard ECO tool (Cadence Conformal). This allows the design to be synthesized using spare cells pre-placed in the pSoC. These form the front-end design phase.

[0094] In the back-end design phase, pre-clock tree synthesis (pre-CTS) optimization is first performed using a commercial EDA tool (Cadence Innovus). To perform post-mask CTS, a commercial EDA tool (Cadence Innovus) is first used to construct a clock tree by inserting cells into desired regions within the SoC. The desired regions are the regions where spare clock buffers, inverters, and clock gating cells will be placed. Next, the newly added clock tree cells are mapped to existing spare cells using a minimum-cost bipartite matching algorithm. Once the clock tree is optimally constructed using the spare cells, routing and sign-off analysis are performed using a commercial EDA tool.

[0095] (Designing a logical PFB for a general-purpose or domain-specific SOC) The PFB design problem can be formulated as designing a limited number of general-purpose PFBs that can be used to implement multiple ASICs. Random selection and placement of standard cells in the PFBs can cause congestion, high interconnect delays, and timing closure issues. Furthermore, the design may end up using a large number of PFBs, which can degrade the PPA of the M2A2 design. On the other hand, greedy mapping-based clustering and iterative mapping-based clustering techniques can be used for PFB design. However, these methods do not guarantee a globally optimal solution because decisions are made iteratively based on the information available at each iteration rather than optimizing an overall objective function.

[0096] To design an optimal PFB, various embodiments use a PFB design algorithm ( FIG. 27 ) based on graph matching and unsupervised learning techniques. The idea is to design a PFB by learning from standard cell placement information of multiple baseline ASICs (training set designs). Some embodiments first identify regions in the training set designs that have similar standard cell placements. Then, regions with similar standard cell placements are grouped to generate a PFB. The similarity analysis is performed using graph matching techniques, while the grouping of similar regions is performed using the K-means algorithm. Random initialization of centroids (centers of mass) in K-means usually results in a suboptimal solution. To address this issue, we determined the positions of the initial centroids so that each centroid is within a unique cluster.

[0097] The PFB design algorithm can be divided into two stages: (1) generating an initial PFB that serves as the initial centroid for the k-means algorithm, and (2) performing k-means clustering to refine the initial PFB and generate a final set of PFBs. The details of the first stage are as follows: The training set design is synthesized and deployed using the baseline ASIC flow.

[0098] In step 1, the placement distribution and timing path attributes, such as timing path stages and clock periods, for all cells are obtained. All training set designs are placed adjacent to each other, and the cell placement information of these merged designs is processed. It is worth mentioning that the connectivity of cells in the training set designs is not considered because the PFB contains spare gates (standard cells with floating input and output pins). In step 2, the floorplan of the merged design is segmented into multiple small regions named bins. The dimensions of the bins are kept the same as the dimensions of the PFB (user input).

[0099] Steps 3 to 5 determine the similarity of standard cell placement across different bins. The relative position of the cell instance with respect to each bin is evaluated. The relative position of each cell within a bin is calculated with the lower left corner of the bin as the origin (Figure 28B). In step 3, the cell timing weight (cellTimingWeight) of each cell instance is evaluated, as given by equation (1). This is defined as the maximum product of the clock frequency and the number of stages in each timing path that passes through a given cell. Typically, an increase in the number of stages and / or a faster clock speed leads to a decrease in the timing slack margin at each stage in the timing path. Thus, the cell timing weight represents the timing criticality factor for a given cell. Next, a bin timing weight metric for each bin is calculated by accumulating the cell timing weight values ​​for all cells located in a given bin (Figure 28A). Bins in which critical timing path cells are located and / or bins with a larger number of cells have higher values ​​of the bin timing weight metric.

[0100]

number

[0101] where m is the total number of cells in the bin. In step 4, the most timing-critical bin (the bin with the highest bin timing weight) is assigned as the time-critical bin. All other bins are compared to the time-critical bin. The similarity analysis is performed using a bipartite graph. A bipartite graph is a set of graph vertices decomposed into two disjoint sets, e.g., A and B, where all edges connect vertices in A to vertices in B. Cells in a given bin (set A) are matched to cells in the time-critical bin (set B). Next, the edge cost (edgeCost) in the bipartite graph for each pair of cells is evaluated. This represents the timing-weighted Manhattan distance between the cells in the given bin and the cells in the time-critical bin. The Manhattan distance between the relative positions of the cells in the given bin and the time-critical bin is calculated (Figure 28B). Next, the edge cost metric is calculated by multiplying the cell timing weight by the distance with the mapped cells in that time-critical bin, as given in Equation (3).

[0102]

number

[0103] where x is a cell in the bin and y is a cell in the time-critical bin. In step 5, the matching cost of all cells in a given bin is evaluated as given in equation (4). Cells in a given bin are mapped to logically equivalent cells in the time-critical bin so as to minimize the total cost of matching (edge ​​cost) in the bipartite graph (Figure 28D).

[0104] To optimize runtime, a minimum-cost bipartite graph matching algorithm is implemented with O(n log n) time complexity, where n is the number of matched vertices. For cells that are not matched to cells in the time-critical bin, a penalty cost is determined, as given in Equation (5). For each non-matching cell, its edge cost is calculated by multiplying the Manhattan distance between the given cell and the farthest bin edge by its cell time weight. The penalty cost is then calculated by adding the edge costs for all non-matching cells and multiplying it by a penalty coefficient (p, set by the user based on the #PFB type). The dissimilarity cost for each bin, given in Equation (6), is then calculated by adding the matching cost and penalty cost of all logic-type cells placed in the bin. This qualitatively represents the dissimilarity in standard cell placement between a given bin and the time-critical bin (Figure 28).

[0105]

number

[0106] where m = # cells of a given logic type, q = # non-matching cells, n = total logic types of cells placed in the bin, and p = penalty factor.

[0107] Bins with a dissimilarity cost less than the dissimilarity cost threshold are grouped together. The value of the dissimilarity cost threshold represents the maximum allowable variation in the relative position of cells placed in a given bin with respect to the time-critical bin. Next, a bin timing weight metric is evaluated, which qualitatively represents the relative size of the clusters formed by the grouped bins. This metric is compared to a grouping threshold determined based on the number of PFB types (user input). If the grouping bin weight (groupedBinsWeight) exceeds the grouping threshold, the time-critical bin is assigned as the initial PFB. All grouped bins are assigned as matching bins. Otherwise, no initial PFB is formed. This process of generating initial PFBs is repeated until the required number of initial PFBs is obtained. Note that in subsequent iterations, only non-matching bins are considered. Finally, the remaining non-matching bins are matched to one of the initial PFBs with the lowest dissimilarity cost.

[0108] Now, a K-means clustering algorithm is performed to improve the initial PFB design. FIG. 29 shows an example of K-means clustering to generate a final PFB in a PFB design algorithm that may be used in various embodiments of the present technology. Each bin is matched to one of the initial PFBs (2910 and 2920) with the lowest dissimilarity cost. Once all bins have been assigned to one of the initial PFBs, the initial PFB design is updated (2930) based on the matching bins. Standard cells are added / removed / moved in the initial PFB to reduce its dissimilarity cost with respect to the matching bins. This can be seen as moving each centroid to the center of its cluster. The k-means algorithm is run iteratively until no improvement in the dissimilarity cost is observed or is minimized. Finally, standard cell placement legalization is performed on each PFB to minimize total cell displacement.

[0109] (Organization of logical PFBs for generic or domain-specific SOCs) FIG. 30 shows an example of an overview of a PFB organization algorithm that may be used in some embodiments of the present technology. The goal of the PFB organization algorithm shown in FIG. 30 is to select and place PFBs on a substrate so that the PFB-organized SoC can achieve the functionality of a given design with an optimal PPA. To achieve this, synthesis and placement of a given design are first performed using a baseline ASIC flow to obtain a standard cell placement distribution. Then, PFBs are organized on the SoC to resemble the standard cell placement of the ASIC design. The details of the algorithm are as follows: Next, placement and timing information of cells in the ASIC design are processed. In the next step, the entire ASIC design floorplan is segmented into multiple small regions named bins (3010). The dimensions of the bins are kept the same as the dimensions of the PFBs. Next, cell timing weights and bin timing weights are determined for all cells and bins using equations (1) and (2). In the next step, valid PFB sites with standard cell utilization greater than a threshold (depending on area constraints) are defined.

[0110] Next, all bins with valid PFB sites are matched to PFBs using a minimum-cost bipartite graph matching technique. A given bin is compared to each PFB and mapped to the bin with the lowest dissimilarity cost (calculated using equations (4)-(6) 3020). This assigns the PFB of the standard cell placement that is most similar to the standard cell placement of the PFB site. This step is repeated (3030) until one PFB has been assigned to each valid PFB site. Once all PFBs have been assigned, it is guaranteed that the count of sequential elements (flip-flops, latches, etc.) in the pre-placement PFB design is not less than the required count (used in the baseline ASIC).

[0111] This can be achieved by (1) setting higher cell timing weights for sequential elements. Therefore, the dissimilarity cost of sequential elements is higher, and sequentially dominated / dominated PFBs are assigned to PFB sites with higher sequential elements. (2) It can also be achieved by adding PFBs to the design so that the required number of sequential elements is placed in the PFB-organized SoC. Once the PFB selection is refined, placement validation of the PFBs in the design is performed. In this step, the PFBs are aligned to standard cell rows to minimize the total PFB displacement (3040). This step also ensures that the space between PFBs is an integer multiple of the filler PFB dimensions, so that filler cell PFBs can be inserted in vacant locations to meet density requirements. Finally, the PFB placement data is fed to an ECO tool (Cadence Conformal) to perform post-mask ECO synthesis using the spare cells pre-placed in the PFB-organized SoC.

[0112] FIG. 31 illustrates an example of assembling a CMD using an organized PFB-SoC to achieve a final SoC in accordance with one or more embodiments of the present technology. FIG. 32 illustrates an example of a combined process of a PFB-organized SoC to achieve a final SoC in accordance with various embodiments of the present technology. FIG. 33 illustrates an example of an exemplary floorplan based on an ASIC and M2A2 in accordance with various embodiments of the present technology. FIG. 34 illustrates an example of an exemplary floorplan based on an ASIC and M2A2 in accordance with some embodiments of the present technology. These embodiments are included for illustrative purposes only, and possible approaches to designing / assembling an organized PFB are not limited to those shown in the embodiments.

[0113] (Logical PFB Design and Organization Considerations for Generic or Domain-Specific SOCs) PFB sizing is an engineering optimization problem that depends on various design and cost tradeoffs. Smaller PFB size results in less PFB size versatility, which increases the number of PFB types required and leads to increased NRE cost. On the other hand, smaller PFB size results in less area overhead for M2A2 designs compared to ASICs, thereby improving PPA. Therefore, PFB dimensions need to be carefully selected by understanding the tradeoff between NRE cost and the impact of PPA on M2A2 designs.

[0114] To determine the optimal number of PFB types, the PFB design algorithm (k-means) is run for different values ​​of k. The smallest value of k for which increasing k does not further reduce the dissimilarity cost is selected as the limiting (optimal) number of PFB types. This ensures that the minimum number of PFBs is designed that achieves reasonably good similarity in standard cell placements across the regions / bins of the training set design.

[0115] For a given design to be successfully synthesized, it is essential to have the required number of standard cells in the PFB-organized SoC. If there are an insufficient number of contiguous cells compared to the number of contiguous cells required for the given design, the design may not be synthesized. The proposed PFB organization algorithm ensures that a sufficient number of contiguous cells are placed in the PFB-organized SoC. In the case of insufficient combinations of standard cells, post-mask ECO synthesis (using existing EDA tools) is performed to realize the required logic function using spare combinational logic gates. If synthesis still fails after applying the logic reconfiguration technique, additional PFBs are organized to ensure that a straight floorplan is maintained. In the worst case, adding a single PFB to the floorplan can increase the floorplan area by an entire row / column of PFBs. This overhead is accounted for in the M2A2 area calculation. Our analysis found that a single PFB inclusion followed by post-mask ECO synthesis can successfully synthesize a design.

[0116] To alleviate routing congestion during synthesis, a maximum placement utilization can be set and / or some spare cell instances can be assigned as "unusable" in highly utilized PFBs. If synthesis fails due to a missing spare gate, a duplicate PFB is placed adjacent to the original PFB and synthesis is run again.

[0117] PFBs are generated by applying a learning technique (k-means algorithm) to a training set of designs belonging to a specific set of functional categories. Therefore, a given design with a similar "functional configuration" can be realized using the proposed M2A2 based PFB. It is well suited for low-volume ASICs that require multiple variants of similar functional designs. Note that the limited PFB may not realize "arbitrary" designs with functional configurations very different from the training set designs. A given arbitrary design may not be synthesized correctly because the PFB has not been trained on such a set of designs. This limitation is common to training on labeled datasets in machine learning and is not specific to the proposed M2A2 methodology. This limitation can be mitigated by extending existing PFB libraries to understand the functional configuration of new designs, at the expense of increased NRE costs due to additional PFBs.

[0118] In the latest CMOS nodes, not only the bottom metal layers (M0 and M1) but also the intermediate metal layers (M2 to M5) require critical mask sets, which incur high NRE costs. In such scenarios, the PFB may need to include intermediate metal layers, and it is no longer possible to include only spare standard cells. This can limit the flexibility of the PFB design and may result in a significant increase in the number of PFB types and / or high PFB instances required to organize the design. Therefore, a trade-off analysis between the PFB types, the number of metal layers in the PFB, and the PPA of the M2A2 design is necessary.

[0119] (PFB-based SOC (generic or domain-specific) testing Various embodiments of the present technology provide systems and techniques for testing aspects of SoCs based on PFBs. These SoCs may be general-purpose ASIC applications such as processors, controllers, communications, etc., or domain-specific applications such as hardware accelerators. One of the main advantages of M2A2 technology is its ability to improve yield for medium to large die. This is due to the fact that M2A2 technology orchestrates PFBs to realize the final SoC.

[0120] Regardless of the size of the PFB-based SoC, the PFB size remains the same (much smaller). For example, assume that the PFB is 500 μm × 500 μm in size and the final SoC dimensions are 40 mm × 40 mm. Due to the 26 mm × 33 mm field size limitation in current lithography technology, this SoC cannot be fabricated using existing commercial processing techniques. Furthermore, as the die size approaches the field size, the yield decreases. However, with M2A2 technology, the PFB is fabricated with high yield at the 500 μm × 500 μm scale using existing commercial processing, and then 6,400 such PFBs ((40 mm × 40 mm) / (500 μm × 500 μm)) are knitted / assembled to realize the final SoC. Furthermore, even if there are defective PFB dies, they will not be assembled to realize the final SoC. In this way, the yield of M2A2-enabled designs is significantly better than existing ASICs, FPGAs, etc., especially for supersized designs.

[0121] To achieve a high-yield design using M2A2 technology, various embodiments may do one or more of the following: 1) find known good PFB die that can be assembled to realize the front-end layer of a PFB-based SoC; 2) find known good custom metal die (CMD) die that can be assembled with the PFB-organized design; or 3) verify that the final SoC (assembled with PFB and CMD) is a known good die.

[0122] Test approaches / methodologies to address the above requirements are discussed below. To determine a known good PFB die, functionality and connectivity testing is performed using any of the standard test techniques such as built-in self-test (BIST), scan chain based testing (boundary, partial, etc.), stuck-at-fault techniques, and other standard commercial test techniques for functional, structural, physical, and connectivity. This test logic can reside inside the PFB area or outside the PFB area (the space used to organize the PFB).

[0123] Another possible technique is to place logic / memory cells / etc. with critical / complex / challenging requirements for fabrication / lithography (yield-challenging) outside the PFB (this space is used to fabricate the PFB). This test logic, similar to the critical functional logic of the PFB, is tested. Based on yield analysis and statistics using existing or newly developed in-house / third-party tools, it can be determined whether the PFB is a known good PFB. The custom metal die (CMD) is tested for connectivity. Connectivity testing can use commercial third-party, in-house, or newly developed test software. Some additional metal layers, pins, and ports may be routed / added / placed on the CMD solely for testing purposes to determine whether the CMD is a known good die. Once the known good PFB is fabricated and the known good CMD is assembled, the final completed SoC-level test is performed. At this level, both functional and connectivity level testing is performed using any of the standard testing techniques such as built-in self-test (BIST), scan chain based testing (boundary, partial, etc.), stuck-at-fault techniques, and other standard commercial testing techniques for functional, structural, physical, and connectivity.

[0124] FIG. 35 illustrates an example method 3500 for testing an M2A2-based SoC that may be used in one or more embodiments of the present technology. In the embodiment shown in FIG. 35, a PFB test operation 3510 tests a PFB to determine whether the die is a known good die. A CMD test operation 3520 tests a CMD to determine whether the CMD is a known good die. If the PFB test operation 3510 or the CMD test operation 3520 identifies a bad PFB or CMD, the location of the bad element can, in some embodiments, be added to a disable list. A compilation operation 3530 compiles known good PFBs and assembles known good CMDs onto the compiled PFBs to complete the SoC. This can be performed, for example, based on the disable list or blacklist created from the test operations 3510 and / or 3520. An SoC test operation 3540 then tests the completed SoC.

[0125] FIGS. 36A through 36E show examples of PFBs, CMDs, and final-level SoC test logic in M2A2-based designs that may be used in various embodiments of the present technology. These embodiments are included for illustrative purposes only, and possible approaches for testing PFBs, CMDs, and SoCs assembled with PFBs and CMDs are not limited to those shown in the embodiments. FIGS. 36A and 36B show individual PFBs. In many cases, it is not possible to test the entire PFB. Thus, some embodiments allow for integration of test logic around the PFB while retaining functional components (e.g., memory arrays, etc.) within. In FIG. 36C, known good PFBs can be organized together. FIGS. 36D and 36E show different cross sections of the metal layers.

[0126] (EDA Methodology for Logical Partitioning in 3D-SOC) In recent years, 2D scaling based on Moore's Law for transistors has approached fundamental physical limits, necessitating a paradigm shift to sustain progress in integrated circuits. At the same time, demand for energy-efficient advanced computing and memory is reaching unprecedented levels driven by consumer mobile devices, IoT, and high-end cloud computing applications such as machine learning and big data analytics. In the field of high-performance, data-rich computing, 3D integrated circuit (3D-IC) technology is being explored to create compact, heterogeneously integrated logic-logic or logic-memory 3D-ICs. Traditional 2D-ASIC designs can be stacked multiple layers / hierarchies on top of each other to form 3D systems-on-chips (SoCs). This results in better power and performance metrics in a smaller footprint. A typical 2D-ASIC-SoC contains millions of standard cells. The 3D design partitioning problem deals with the optimal allocation of cells to each layer / hierarchy within the 3D stack. Optimal means that cells are placed to achieve the lowest power-performance area (PPA).

[0127] (3D-ASIC design partitioning problem) At the most advanced design nodes (20nm and below), delay is dominated by wire delay and power is dominated by leakage power. Wire delay is proportional to the wirelength of a net. Reducing wirelength results in lower delay (meaning higher performance) and lower power (fewer buffers required and higher VT cells to meet frequency targets). To reduce wirelength, cells can be placed in 3D space instead of 2D space. Cells can be placed in multiple hierarchies, i.e., multiple 2D planes can be stacked on top of each other. The 3D design partitioning problem deals with the optimal allocation of cells in different hierarchies such that the PPA is minimized.

[0128] This problem can be solved using various approaches, such as iterative greedy approaches, simulated annealing, graph-based techniques, and optimization techniques based on an objective function. Various embodiments of the present technology can use optimization techniques to solve this problem. This problem is an optimization problem, and various embodiments minimize an objective function under a set of given constraints. This optimization problem belongs to the class of NP-hard problems, which can be solved efficiently and optimally using one or more of the following methods: linear programming (LP), and / or integer linear programming, and / or mixed integer programming (MIP) models.

[0129] The details of the proposed methodology are described below. It is worth mentioning that the analysis presented below is for two tiers (tier 0 and tier 1). However, this analysis (the same methodology) can be scaled / generalized to any (larger) number of tiers.

[0130] (Problem formulation - objective function and constraints) Consider an ASIC design with n cells (nodes) and k nets (edges). The objective is to minimize the overall edge cost in a design partitioned into two hierarchies (hierarchy 0 and hierarchy 1) to obtain the best PPA. The objective function can be given by Equation (7).

[0131]

number

[0132] where γ is the total number of nets (edges) in the design (graph).

[0133] The edge cost refers to the 2D timing and physical realizations in the design, as well as the 3D via and routing disturbances. It is given by Equation (8).

[0134]

number

[0135] However, α i,j represents the timing coefficient, and β i,j represents the 3D via and routing interference penalty coefficients (self-routing interference and routing interference to neighboring cells) of cell i and cell j, and x i , y i , z i are the X, Y, and Z coordinates of cell i, where |x i -x j | + |y i -y j | represents the 2D Manhattan distance between cell i and cell j, where

[0136]

number

[0137] Combining equations (7) and (8), the objective function is given by equation (9).

[0138]

number

[0139] where n is the total number of cells, m i is the total number of cells connected to cell i.

[0140] In this design, cells can only be placed in standard cell rows, i.e., the y-coordinate value of a cell is a multiple of the standard cell height. Taking this into consideration, the objective function is given by Equation (10).

[0141]

number

[0142] where h is the standard cell height and r i is the row number of cell i, and r j is the row number of cell j, where row number r is Z + belongs to Z+ represents the set of positive integers. i,j , β i,j is the design coefficient / constant.

[0143] The constraints for the above problem are as follows, given by equations (11) to (15).

[0144] Decision variable (x i ,r i ) upper and lower bounds:

[0145]

number

[0146] where R + represents the set of positive real numbers, and Z + represents the set of positive integers, and x 2D and r 2D is the x coordinate (center of the cell horizontally) and row number of any cell in the 2D design (plane). i ,r i ,z i ) are the X coordinate, row number, and Z coordinate of cell i, respectively.

[0147]

number

[0148] Non-overlapping cells in the design (same level / plane): where x i and x j is the central horizontal coordinate, and r i and r j is the row number, and z i and z j is the Z coordinate, and w i and w j are the widths of cell i and cell j, respectively.

[0149] Area balancing constraints for each tier / layer:

[0150]

number

[0151] Here, Σw on the left side i h (i = 1 to n) represents the total standard cell area. h is the height of the standard cell. w i is the width of standard cell i. p i,k is 1 if cell i is assigned to layer k. Valid values ​​of k are 0 and 1. is a region relaxation factor that can be determined heuristically.

[0152] Pre-deployed MIVs for power delivery networks should be considered. These MIV sites are reserved and should not be used for signaling MIVs. This can be added as an upfront constraint or taken care of during the MIV certification phase (no upfront constraint is required).

[0153] For F2F or F2B-3D techniques, the placement of IO ports or pads can be considered to limit the search space for finding the optimal solution. Thus, the problem is to solve equation (10) under constraints (11) to (15).

[0154] As described above, various embodiments use the coefficient (α i,j ,β i,j ) can be evaluated. The parameter α represents the timing profile weight of the net with cell i as the driver cell and cell j as the receiver cell. It is determined based on the following factors: Clock frequency: For a given net passing through cell i and cell j, obtain a list of timing paths passing through these cells. The valid timing path with the fastest clock frequency (lowest clock period) is considered in determining α. # Stages of Timing Path and Slack Profile: The more stages a timing path has, the more constrained the timing path is. The more stages there are, the lower the timing budget per stage / net. Therefore, we can evaluate the slack associated with each net. If the slack / stage value is small, α will be small. # fanout of source cell: For a given net, if a source cell has a high fanout, the slew rate of the source cell will be low, which limits the timing budget of the nets that pass through this source cell. Delay per micron: For a given technology, the delay per micron is estimated. This is used to determine α.

[0155] The parameter β represents the 3D via and routing disturbance penalty factor for cell i and cell j, which is determined based on the following factors: ●Parasitic capacitance (R MIV ,C MIV ) and MIV dimensions: MIV size (diameter and depth) and parasitic capacitance (R MIV ,C MIV ) determines the coupling capacitance between the two dies. If the size of the monolithic interlevel via (MIV) is large, the MIV parasitics will be larger. ●#Fanout (impact of routing disturbance on adjacent cells): If the fanout of the source or receiver cell is high, more routing resources are required. When an MIV is inserted, obstructions are created on more paths. Therefore, the higher the fanout, the higher the impact of routing disturbance caused by MIV insertion on adjacent cells. ● Self-routing obstruction impact: MIV insertion creates routing obstructions, which add some detours to the 2D routing of the same net. This factor should be considered in determining β. Layer distance: Die-to-die coupling capacitance depends on the MIV size and the distance between layers, and begins to dominate when the layer distance is less than 1 micron.

[0156] (hardware security) While scaling is a central issue for the semiconductor industry and the primary goal of this paper, there are other problems that can also be addressed using the methods explored here. Hardware security is one such problem, which we will briefly discuss below.

[0157] Moving a device from initial design to large-scale fabrication manufacturing and deployment requires the sharing of sensitive intellectual property across many organizations and state lines. With relevant information, untrusted members of the supply chain could potentially counterfeit the original design and / or insert malicious components into the device. The semiconductor industry loses up to $4 billion annually due to intellectual property infringement, with an estimated $169 billion annually due to counterfeit ICs (including recycled, remarked, tampered, and overproduced ICs). A split-fabrication approach has been proposed as a solution to the hardware security problem. This involves fabricating the high-resolution front-end portion of the circuit at an advanced, possibly untrusted, foundry, while fabricating the lower-resolution circuit at a trusted (perhaps local or in-house) but less advanced foundry (see Figure 37).

[0158] 37 is a diagram 3700 illustrating a split processing approach that may be used in some embodiments of the present technology. However, split manufacturing does not guarantee security. For example, if processing up to metal layer n occurs in an advanced but untrusted foundry (where n>=2), there is a possibility of Trojan insertion or reverse engineering of chip connectivity (where n>3). On the other hand, if processing is done up to metal layer 1 in an untrusted foundry, the back-end layers cannot be manufactured using existing trusted foundry infrastructure for advanced CMOS nodes.

[0159] (Split Design / Fab Approach for Hardware Security Using N-MAP) Various embodiments can assemble a limited number of carefully designed front-end PFBs and connect them using back-end metal layers, thereby achieving ASIC-like power, performance, and area specifications. Some embodiments of the EDA methodology can be adapted with N-MAP to enable robust hardware security solutions. By fabricating front-end circuit elements as part of the PFB in a potentially untrusted fab and connecting them together using a PFB containing only metal layers (hereafter referred to as a custom metal die, or CMD), various embodiments can essentially split the IC design so that the untrusted fab has no way of knowing the final configuration and functionality of the completed device. Assuming the front-end PFB contains circuit elements up to or below metal layer 2, assembly would require an overlay accuracy of approximately 17 nm (μ + 3σ) at the 14 nm node.

[0160] FIG. 38 is a diagram 3800 illustrating a split fab with N-MAP (SDSF) in accordance with one or more embodiments of the present technology. As shown in FIG. 38, untrusted facilities 3810 (e.g., P1, P2, and P3) can be used for PFBs (e.g., PFB1, PFB2, and PFB3). The PFBs can be the same or different. Similarly, additional potentially untrusted facilities (e.g., C1 and C2) can be used to create CMDs (e.g., CMD1 and CMD2). The CMDs can be the same or different. In some embodiments, the PFB facilities can be the same or different from the CMD facilities. The PFBs and CMDs can be transferred to a trusted facility 3820. Using pick-and-place assembly, the trusted facility 3820 can create the completed SoC.

[0161] The source wafer should ideally be fab-agnostic. Because bulk silicon is the most commonly used substrate in semiconductor processing, the source wafer should ideally also be bulk silicon. Some embodiments can use various methods for creating a buried sacrificial layer in bulk silicon after PFB processing (and before pick-and-place). In this manner, the PFB wafer can be fabricated at one foundry, while the CMD wafer can be fabricated at a second foundry. Then, in trusted facility 3820, the front end of SoC 3830 can be fabricated from multiple PFB wafers (or a single wafer with multiple PFBs) using the pick-and-place techniques described herein. A pick-and-place assembly can then place the CMD onto the front end of SoC 3830 to create the finished SoC 3840.

[0162] FIG. 39 is a block diagram 3900 illustrating an example of a vacuum-based pick-and-place assembly process modeled along the lines of J-FIL that may be used in various embodiments of the present technology. The source wafer undergoes the following preprocessing steps prior to pick-and-place assembly (see, for example, FIGS. 40 and 41). Chemical-mechanical polishing (CMP) may be necessary for PFB bonding later in the process sequence, which requires a mirror-polished bonding surface. An encapsulation layer coating can be used to protect the polished surface from contamination as well as to protect the circuit elements in the PFB from chemical attack during tether formation. An access hole etch can be used to create access holes that are etched down to the buried sacrificial layer. In some embodiments, a second encapsulation layer coating can be used to protect the sides of the PFB. Next, a tether etch can be applied, which may include partially etching off the buried sacrificial layer so that the tether structure remains. The etch can be performed using a gas-phase etchant to prevent collapse of the PFB due to stiction.

[0163] In the default assembly configuration, the PFB metal contacts face the product wafer. For this configuration, pick-and-place assembly can be performed in three stages. In the first stage, the PFB chuck attaches itself to all PFBs (on a single source wafer) using vacuum suction (see, for example, Figure 42). A vapor-phase etchant is dispensed through intermittent holes on the PFB chuck to etch away the tethers, after which the PFBs are lifted from the source wafer. The PFB chuck serves as a temporary storage for the PFBs. As long as the vacuum suction is maintained and the temperature conditions are stable, the PFBs remain attached to the chuck with lithographic precision. Note that the suction areas on the PFB chuck are individually addressable to enable subsequent die-by-die pickup.

[0164] Before picking and placing the PFB onto a product wafer, the encapsulation layer on the PFB must be removed. During this stage of processing, the PFB is oriented toward the PFB chuck, with the encapsulation layer sandwiched between the PFB and the chuck. To flip the orientation, the PFB is transferred to a second PFB chuck (see, for example, Figure 43) and then transferred to an atmospheric pressure O2 plasma asher. The asher removes the encapsulation layer along with any organic contaminants on the PFB. The PFB is then returned to the first PFB chuck.

[0165] The third and final step involves a die-by-die pickup superstrate, which picks up individual PFBs from the PFB chuck and places (and bonds) them onto a product wafer (see, e.g., Figure 44). The die-by-die pickup superstrate ensures that only known good PFBs are picked up, thereby enabling the high yield requirements of N-MAP.

[0166] Figure 45 shows a process sequence 4500 for a second assembly configuration in which the PFB metal contacts contact the surface array from the product wafer. The PFB chuck (think of it as the bulk pickup superstrate) and die-by-die pickup superstrate are critical parts of the assembly process. They ensure that lithographic accuracy is maintained as the PFB is transferred from the source wafer to the product wafer. During pickup from the source wafer, it is important that the pressure differential between the top and bottom of the PFB is sufficient to keep it attached to the PFB chuck. This is primarily a concern during pickup from the source wafer. When the PFB is picked up from the source wafer and transferred, for example, from the PFB chuck to the die-by-die pickup superstrate, the chuck can assist the pickup by pressurizing one side of the PFB. However, pressurizing one side of the PFB during pickup from the source wafer creates significant engineering challenges.

[0167] Figure 46 shows an example scenario 4600 where the gap pressure is significantly greater than atmospheric pressure during pickup from the source wafer. Because all of the PFB must be picked up during bulk pickup, maintaining 2 atmospheres of pressure across the area of ​​a 300 mm wafer on one side of the PFB, for example, requires the z-actuator and translation stage to support approximately 7 kN of extra load. Also, the high pressure creates sealing issues at the edge and superstrate of the source wafer. While these are not fundamental challenges, from an engineering perspective, it is preferable to keep the pressure close to 1 atmosphere.

[0168] Therefore, without the ability to pressurize one side of the PFB and with limited air transport across the millimeter-scale length and micron- to submicron-thin gap (between the PFB and the source wafer), careful analysis of the airflow during pickup is required to ensure consistent suction. The super-straight pins can serve a variety of functions. For example, they can seal the access hole, thereby helping to maintain vacuum suction. Furthermore, they can support the PFB against the vacuum suction force while preventing scratches or damage to the PFB. The pin geometry (size, pitch, and distribution) can be selected in various embodiments to satisfy the above two conditions while keeping the PFB-pin contact area as low as possible. Additionally, in some embodiments, they can be coated with a conductive layer and have patterned irregularities on their PFB-facing surfaces to reduce adhesion effects. Note that by appropriately modifying the pin pitch, arbitrarily thin PFBs can be held against vacuum forces. It should be noted that this superstrate feature offers significant advantages over grinding-based methods for processing and handling thin PFBs along with sacrificial layer-compatible pick-and-place assembly. Ground wafers are inherently limited to micron-scale (approximately 10 μm or greater) thicknesses due to the parallelism limitations of the top and bottom surfaces of the source wafer.

[0169] Adhesion between the superstrate and PFB can lead to undesirable stiction problems. Adhesion is a complex phenomenon caused by the interaction of three main forces: 1) surface tension, 2) van der Waals forces, and 3) electrostatic forces. Surface tension is caused by the interaction of adsorbed moisture on the contact surfaces. To minimize surface tension, dry conditions should be actively maintained within the pick-and-place tool. Van der Waals forces are caused by the instantaneous polarization of atoms and molecules (due to quantum mechanical effects) and are only relevant at gap scales below 100 nm. To reduce these forces, the surface of the superstrate pin should have patterned roughness of approximately 100 nm (Ra) or greater. Electrostatic forces are caused by charge generation and charge transfer during contact and are generally the most difficult to eliminate. Some embodiments of the present technology can reduce electrostatic interactions, minimizing contact charging, by using materials with low contact potentials between the contacting surfaces. Furthermore, some embodiments can use conductive materials that are highly insulating and do not readily form native oxides. The contact surfaces can be roughened to minimize the contact area. Also, local deformation at the contact site, which can increase the net adhesive force, can be reduced by using a hard material.

[0170] In some embodiments, a superstrate material that is resistant to the sacrificial layer etchant (e.g., vapor-phase HF) can be used. The superstrate material may be semiconductor-grade, available in large form factors, and micromachinable. Furthermore, in some embodiments, the superstrate material may have high hardness to withstand wear over multiple pick-and-place cycles and to reduce stiction issues. The superstrate material used in some embodiments may have thermal properties similar to those of the source and product wafers. Ideally, the superstrate material should be transparent to light in the visible or IR spectrum (to facilitate overlay metrology). Given these constraints, the choice of superstrate material is quite limited. Silicon, sapphire, fused silica, and silicon carbide (SiC) are likely the only common materials that satisfy all or most of the above. Of these, only silicon has a wide variety of micromachining techniques available for it and is likely the best choice of superstrate material.

[0171] (Airflow mechanism for vacuum-based pick-and-place assembly) Figure 47 is a diagram 4700 showing a snapshot of a PFB during pickup from a source wafer, in accordance with one or more embodiments of the present technology. As shown in Figure 47, as the PFB is lifted from the source wafer, two competing effects occur: 1) rarefaction of the air as the gap between the PFB and the source wafer widens, and 2) pressure equalization as air rushes in from the edges of the PFB. However, the large pores (tens of microns wide) in the superstrate maintain the pressure at approximately 1 atmosphere.

[0172] These have significantly different time scales.

[0173]

number

[0174] VverticalPressureFront and V lateralPressureFront and V soundAtRTP and are roughly equal, gap PFBToSubstrate is approximately 1 μm, and width PFB If we set the time to about 5 mm, pressureEqualization is time rarefaction is about three orders of magnitude larger than p. Thus, if the PFB is picked up faster than the pressure in the gap equalizes, the PFB risks losing attraction. Indeed, over millimeter-scale regions, p superstrate A local p slightly lower than gap can lead to significant distortion of the PFB, potentially resulting in loss of overlay as well as damage to the PFB circuit elements. superstrate is about 0.1 atmospheres, and the average p gap Ga p superstrate Approximately 5% lower than the thickness PFB When the gap is about 1 μm, a deviation of about 30 μm occurs at the center of the local area. PFBToSubstrate If p is less than 30 μm, it is likely that the PFB has crashed into the source wafer. Therefore, a good rule of thumb during pick-up is to apply a minimum pressure p gap min =k pressureMargin *p superstrate In the subsequent analysis, k pressureMargin =5, p superstrate = 0.1 atmospheres, p gap min = 0.5 atmospheres. Various embodiments are pressureEqualization A more accurate estimate of may be used, from which a suction-ensuring superstrate motion plan can be derived.

[0175] As the PFB is forced against the product wafer for placement and bonding, two competing effects occur (roughly time-reversed versions of the corresponding effects during pick-up): 1) compression of the air as the gap between the PFB and the product wafer contracts, and 2) pressure equalization as the air protrudes toward the edge of the PFB, although the large holes in the superstrate maintain the pressure at approximately 1 atmosphere.

[0176] Air compression increases the stiffness of the air between the PFB and the product wafer, providing a potential mechanism for in-air overlay correction during PFB placement. The compressed air eventually dissipates as the air protrudes toward the edge. Some embodiments may use an estimate for this dissipation time, which can subsequently inform tool designers about the timescale available for in-air overlay correction.

[0177] FIG. 48 shows holes in the superstrate pins 4810 that may be used in some embodiments of the present technology. The PFB is attached to the superstrate. Pulling the PFB creates suction forces that can damage the PFB. Some embodiments may use holes in the superstrate to prevent suction. FIG. 49 shows a snapshot 4900 of the PFB before it is placed on a product wafer in various embodiments of the present technology. Various embodiments may use holes in the superstrate to prevent suction. PFB and thickness sacrificialLayer At various values ​​of , the results of the PFB pick-up simulation can be used to derive the suction securing motion plan of the PFB chuck.

[0178] FIG. 50 shows the domain for a DSMC simulation 5000 of a PFB pickup in various embodiments of the present technology. To reduce the complexity of the simulation, the following preliminary assumptions are made. First, the gap between the PFB and the source wafer is assumed to be cubic. The access holes, which constitute a small fraction of the gap volume, are not modeled. Second, given the two-fold rotational symmetry of the cubic shape with respect to airflow, only one-quarter of the volume is modeled. Finally, the edges of the PFB are assumed to be at 1 atmosphere. This is ensured by large holes in the streets of the PFB chuck, which maintain a pressure of approximately 1 atmosphere.

[0179] The eigenstates of air outside the simulation domain are defined as follows: 1) Air is 1.901×10 25 m -3 and 0.546 x 10 25 m -3 The simulation volume is assumed to consist of two molecular species (N2 and O2) present at number densities of 1000 kJ / s, which correspond to the number densities of these species in air at 1 atmosphere. 2) The air is assumed to be stationary (zero net velocity). The simulation volume can be discretized using hexahedral mesh elements, with a size ∂ ... mesh =33nm.

[0180] In some embodiments, the following boundary conditions can be used: The silicon surfaces at the top and bottom of the simulation region are modeled as walls, and the wall-air collisions are modeled using a mixed (diffusive and specular) wall interaction model. The wall temperature is set to 300K. Of the four vertical faces of the simulation region, two are set as inlet boundaries, through which air at 1 atmosphere pressure can flow in or out, and the other two are symmetric boundaries as shown in Figure 50.

[0181] The external parameters for the simulation are thickness sacrificialLayer and width PFB Due to computational constraints, small width PFB and thicknesssacrificialLayer In the current simulation set, the simulation is performed with only width PFB is kept below 60 μm, and the thickness sacrificialLayer is kept below 2.5 μm. The data can then be extrapolated to millimeter-wide volumes. sacrificialLayer and width PFB For a given set of values ​​of , a suction-secure pick-up plan can be developed.

[0182] Figure 51 is a flowchart 5100 illustrating an example set of operations that may be used to derive a suction-assured pickup plan in accordance with some embodiments of the present technology. Figure 52 shows an example DSMC simulation 5200 of pressure in accordance with various embodiments of the present technology. Figure 53 shows various values ​​of gap PFBToSubstrate In the case of width PFB = avg(p gap ) change 5300. Note that the pressure equalization rate begins to drop significantly near a gap of about 100 nanometers, which is likely when molecular flow begins to dominate.

[0183] Figure 54 shows the thickness sacrificialLayer =0.01μm, width PFB 5 shows a suction-enhanced motion plan 5400 derived for thickness = 5 mm. The suction-enhanced motion plan is for 2D die pickup from a source wafer. Here, thickness sacrificialLayer =0.01μm, width PFB = 5 mm. The motion plan ensures suction as long as the slope of gap versus time is lower at any particular gap value than the corresponding slope in the constrained motion plan above.

[0184] (DSMC simulation of PFB placement) The PFB placement simulation used in some embodiments can include the simulation domain and intrinsic parameters that are the same as for the pickup. The extrinsic parameters are: gapPFBToProductWafer and width PFB Due to computational constraints, simulations may be performed only with small values ​​of gap and width in some embodiments. In the current set of simulations, PFB is kept below 20 μm, and the gap PFBToProductWafer The gap is kept below 4 μm. However, the data can be extrapolated to millimeter-wide volumes. PFBToProductWafer and width PFB For a given set of values ​​of , the placement time estimate is derived as follows:

[0185] 55 is a flowchart 5500 illustrating an example set of operations for deriving a deployment time estimate that may be used in some embodiments of the present technology. FIG. 56 is a plot 5600 illustrating an example of the change in average gap pressure for PFB deployment in one or more embodiments of the present technology. As shown in FIG. 56, based on the algorithm described above, width PFB = avg(p gap ) change. The estimated deployment time is approximately 10 ms. Note that this can be increased by dispensing a more volatile liquid at the edge of the PFB to constrict the airflow.

[0186] (Source wafer for N-MAP) In some embodiments, it may be assumed that a source wafer with a suitable sacrificial layer is available, and given this assumption, the remainder of the N-MAP process can be explored. As previously mentioned, the source wafer should ideally be fab agnostic. <100> Oriented silicon is the most widely used substrate in semiconductor processing, so the source wafer should also be this. However, bulk silicon does not contain any buried sacrificial layers and therefore cannot be used for N-MAP in this native form.

[0187] If a buried sacrificial layer could be created in a fab-processed bulk silicon wafer without damaging the circuit elements, it would be an ideal technology choice for the source wafer. On the other hand, SOI substrates already contain a buried sacrificial layer and do not require any additional post-fab process development. However, SOI substrates are currently processed by only one of the four major semiconductor fabs worldwide. Various embodiments provide technology options for the source wafer, ranging from SOI on the one hand to (potential) methods for creating a post-fab bulk silicon sacrificial layer on the other hand. Each has its own advantages and risks.

[0188] Table 5.2 below shows three technology options for the source wafer.

[0189] [Table 5]

[0190] SOI is the default choice in many embodiments because it already includes a buried sacrificial layer. However, SOI is currently processed only in the largest fabs, i.e., global foundries. Furthermore, SOI would have a significant cost barrier for memory applications.

[0191] BESL, based on the second variant of FIPOS, requires collaboration with the fab to process the epitaxial wafers needed to create the porous underlayer. However, the recent implementation of epitaxial wafers in advanced logic devices such as FinFETs and gate-all-around FETs creates opportunities for this in the logic space. A third option, and the most favorable from an applicability perspective, is post-fab creation of a sacrificial layer in bulk Si.

[0192] (Creating buried sacrificial layers in bulk silicon) Figure 57 illustrates an example process flow 5700 for creating a buried sacrificial layer in bulk silicon, according to various embodiments of the present technology. As shown in Figure 57, the porous layer can be subsequently oxidized to create a post-fab buried sacrificial oxide layer. However, this process sequence is not ideal because it creates a large kink under the PFB due to the isotropic propagation of porosity. Figure 58 illustrates an alternating sequence 5800 in which application of an electric field near the surface of the silicon wafer can repel pores (necessary for porosity creation), potentially stopping the vertical etch front and significantly reducing or even eliminating the kink.

[0193] (Experimental verification) Figure 59 shows porosity rappelling in silicon coated with a thin chromium layer. In this case, the metal layer voltage V metal was simply the electrolyte potential. Anodization was performed using an in-house etcher. Figure 60 shows a photoelectrochemical etcher for porosity creation that may be used in various embodiments of the present technology.

[0194] (Air bearing stiffness) Figure 61 shows an example of an air bearing for stiffness calculation 6100, according to various embodiments of the present technology. The air bearing stiffness at a particular gap can be found using the ideal gas equation of state for the gas. Figure 62 shows an example 6200 of an air bearing gap reduced by a factor of 10. As an example, decreasing the gap from about 1 μm to about 100 nm increases the air bearing stiffness by about 100 times.

[0195] (PFB chuck) The distribution of PFB chuck pins needs to be modified based on the PFB dimensions. To avoid having to fabricate a new valve array for each new type of PFB, the valve array may reside on a separate layer and be attached to the pin layer using vacuum suction. The pin layer would be fabricated for each specific PFB type and attached to the valve layer using a vacuum-based method, allowing for quick attachment and detachment of the two layers. For the design shown in the figure below, the pitch of the microvalve array should be approximately 70% of the smallest PFB dimension (likely encountered). In this configuration, the microvalve array should be able to control airflow in any PFB form factor. Figure 63 shows an example PFB chuck 6300 showing separate microvalve and pin layers.

[0196] (Superlithography die using N-MAP) Figure 64 illustrates an example N-MAP superlithography die 6400, in accordance with various embodiments of the present technology. More specifically, Figure 64 illustrates an example approach whereby PFBs each smaller than 26mm x 33mm in size can be tessellated into a superlithography form factor and joined using CMD to form a superlithography system-on-chip (SoC).

[0197] (Minimal Fab) FIG. 65 is a block diagram 6500 illustrating various components of a minimal fab that can be used in some embodiments of the present technology. The minimal fab embodiment shown in FIG. 65 has a significantly smaller footprint and capital requirements than traditional large-scale fabs, but can be used in conjunction with large-scale fabs for fabrication of custom semiconductor devices by entities / companies that do not necessarily specialize in semiconductor processing. The minimal fab described above includes an N-MAP tool, a die test station, and several other auxiliary tools, such as a CMP station and a bake station. Note that the bake station is for improving bond quality after the bonding step in a nano-precision pick-and-place assembly tool. FIG. 65 also illustrates a PFB chuck in an inverted configuration. In this configuration, inversion of the PFB is not required.

[0198] (Overview of an Exemplary Computer System) Aspects and implementations of the design tools and / or processing systems of the present disclosure have been described in the general context of various steps and operations. Various of these processes and operations may be performed by hardware components or may be embodied in computer-executable instructions that may be used to cause a general-purpose or special-purpose processor (e.g., within a computer, server, or other computing device) that is programmed with the instructions to perform the steps or operations. For example, the steps or operations may be performed by a combination of hardware, software, and / or firmware.

[0199] 66 is a block diagram illustrating an example machine representing a computerized systemization of a design tool and / or processing system. A design tool and / or processing system controller 6600 may communicate with entities including one or more users 6625, client / terminal devices 6620, user input devices 6605, peripheral devices 6610, optional coprocessor device(s) (e.g., cryptographic processor device) 6615, and a network 6630. A user may interact with the controller 6600 via a terminal device 6620 over the network 6630.

[0200] A computer may use a central processing unit (CPU) or processor to process information. A processor may include a programmable general-purpose or special-purpose microprocessor, a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), an embedded component, a combination of such devices, etc. A processor executes program components in response to user- and / or system-generated requests. One or more of these components may be implemented in software, hardware, or both hardware and software. A processor passes instructions (e.g., operational instructions and data instructions) that enable various operations.

[0201] The controller 6600 may include a clock 6665, a CPU 6670, memory such as a read only memory (ROM) 6685 and a random access memory (RAM) 6680, a coprocessor 6675, etc. These controller components are connected to a system bus 6660, which may be connected to an interface bus 6635 via the system bus 6660. Additionally, a user input device 6605, a peripheral device 6610, a coprocessor device 6615, etc. may be connected to the system bus 6660 via the interface bus 6635. The interface bus 6635 may be connected to a number of interface adapters, such as a processor interface 6640, an input / output (I / O) interface 6645, a network interface 6650, and a memory interface 6655.

[0202] The processor interface 6640 may facilitate communication between the coprocessor device 6615 and the coprocessor 6675. In one implementation, the processor interface 6640 may expedite encryption and decryption of requests or data. The input / output (I / O) interface 6645 facilitates communication between the user input device 6605, peripheral device 6610, coprocessor device 6615, etc. and components of the controller 6600 using protocols for handling audio, data, video interfaces, wireless transceivers, etc. (e.g., Bluetooth, IEEE 1394a-b, serial, Universal Serial Bus (USB), Digital Visual Interface (DVI), 802.11a / b / g / n / x, cellular, etc.). The network interface 6650 may communicate with the network 6630. Via the network 6630, the controller 6600 may be accessible to a remote terminal device 6620. The network interface 6650 may use a variety of wired and wireless connection protocols, such as direct connection, Ethernet, and wireless connections such as IEEE802.11a-x.

[0203] Examples of network 6630 include the Internet, a local area network (LAN), a metropolitan area network (MAN), a wide area network (WAN), a wireless network (e.g., using the Wireless Application Protocol (WAP)), a secure custom connection, etc. Network interface 6650, in some aspects, may include a firewall that manages and / or controls permissions to access / proxy data within a computer network and can track various levels of trust between different machines and / or applications. A firewall may be any number of modules having any combination of hardware and / or software components that can enforce a predetermined set of access rights between specific sets of machines and applications, between machines, and / or between applications, for example, to regulate traffic flow and resource sharing between these various entities. A firewall may also manage and / or utilize access control lists that detail, for example, permissions, including access and operation rights to objects, by individuals, machines, and / or applications, and the circumstances under which the permissions are available. Other network security functions performed by or included in the functionality of a firewall may be, for example, but not limited to, intrusion prevention, intrusion detection, next generation firewall, personal firewall, etc., without departing from the novel techniques of the present disclosure.

[0204] The memory interface 6655 may communicate with a number of storage devices, such as the storage device 6690, removable disk devices, etc. The storage interface 6655 may use a variety of connection protocols, such as Serial Advanced Technology Attachment (SATA), IEEE 1394, Ethernet, Universal Serial Bus (USB), etc.

[0205] User input devices 6605 and peripheral devices 6610 may be connected to the I / O interface 6645 and potentially other interfaces, buses, and / or components. User input devices 6605 may include card readers, fingerprint readers, joysticks, keyboards, microphones, mice, remote controls, retina readers, touch screens, sensors, etc. Peripheral devices 6610 may include antennas, audio devices (e.g., microphones, speakers, etc.), cameras, external processors, communication devices, radio frequency identifiers (RFID), scanners, printers, storage devices, transceivers, etc. Coprocessor devices 6615 may be connected to the controller 6600 via an interface bus 6635 and may include a microcontroller, processor, interface, or other device.

[0206] Computer-executable instructions and data may be stored in memory accessible by the processor (e.g., registers, cache memory, random access memory, flash memory, etc.). These stored instruction codes (e.g., programs) may coordinate processor components, a motherboard, and / or other system components to perform desired operations. The controller 6600 can use various forms of memory, including on-chip CPU memory (e.g., registers), RAM 6680, ROM 6685, and storage devices 6690. The storage devices 6690 can use any number of tangible and non-transitory storage devices or systems, such as fixed or removable magnetic disk drives, optical drives, solid-state memory devices, and other processor-readable storage media. The computer-executable instructions stored in memory may include a design tool and / or fabrication platform having one or more program modules, such as routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. For example, the memory can include an operating system (OS) component 6695, modules and other components, database tables, etc. These modules / components may be stored and accessed from storage devices, including from external storage devices accessible via an interface bus.

[0207] The database component can store programs that are executed by a processor to process stored data. The database component may be implemented in the form of a relational, scalable, and secure database. Examples of such databases include DB2, MySQL, Oracle, Sybase, etc. Alternatively, the database may be implemented using a variety of standard data structures, such as arrays, hashes, lists, stacks, structured text files (e.g., XML), tables, etc. Such data structures may be stored in memory and / or structured files.

[0208] The controller 6600 may be implemented in a distributed computing environment where tasks or modules are performed by remote processing devices linked through a communications network, such as a local area network (LAN), a wide area network (WAN), or the Internet. In a distributed computing environment, program modules or subroutines may be located in both local and remote memory storage devices. Distributed computing may be used to aggregate processing resources and / or distribute loads. Alternatively, aspects of the controller 6600 may be electronically distributed via the Internet or other networks (including wireless networks). Those skilled in the art will recognize that portions of the design tool and / or processing system may reside on a server computer and corresponding portions may reside on a client computer. Data structures and data transmission specific to aspects of the controller 6600 are also encompassed within the scope of this disclosure.

[0209] (Conclusion) Unless the context clearly dictates otherwise, throughout the specification and claims, words like "comprises," "comprising," and the like should be construed in an inclusive sense, rather than an exclusive or exhaustive sense. That is, "including, but not limited to." As used herein, the words "connected," "coupled," or any variation thereof, mean any direct or indirect connection or coupling between two or more elements. The coupling or connection between elements may be physical, logical, or a combination thereof. Furthermore, when used herein, words like "here," "on," "below," and similar words refer to this application as a whole and not to any particular portions of this specification. Where the context permits, words in the above Detailed Description using the singular or plural may also include the plural or singular, respectively. Where the context permits, words in the above Detailed Description using the singular or plural may also include the plural or singular, respectively. The word "or," in connection with a list of two or more items, includes all of the following interpretations of the word: That is, any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0210] The above detailed description of examples of the present technology is not intended to be exhaustive or to limit the present technology to the precise form disclosed above. While specific examples of the present technology are described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of the present technology. For example, while processes or blocks are presented in a given order, alternative implementations may perform routines including steps or use systems including blocks in a different order. Some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternatives or subcombinations. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are sometimes shown as being performed sequentially, these processes or blocks may instead be performed or implemented in parallel, or may be performed at different times. Furthermore, any specific numbers referenced herein are merely examples, and alternative implementations may employ different values ​​or ranges.

[0211] The teachings of the technology provided herein may be applied to other systems, not necessarily the system described above. Elements and operations of the various examples described above may be combined to provide further implementations of the technology. Some alternative implementations of the technology may include fewer elements as well as additional elements relative to the implementations described above.

[0212] These and other changes can be made to the technology in light of the above detailed description. The above description describes certain examples of the technology and sets forth the best mode contemplated; however, no matter how detailed the above appears in text, the technology can be practiced in many ways. Details of the system, while encompassed by the technology disclosed herein, may vary considerably in specific implementations. As noted above, specific terms used in describing certain features or aspects of the technology should not be construed as suggesting that the terms are redefined herein to be limited to specific features, features, or aspects of the relevant technology. In general, the language used in the following claims should not be construed as limiting the technology to the specific examples disclosed herein, unless such language is expressly defined in the detailed description section above. Thus, the actual scope of the technology encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology under the scope of the claims.

[0213] To reduce the number of claims, certain aspects of the present technology are presented below in certain claim forms, but Applicant contemplates various aspects of the present technology in any number of claim forms. For example, while only one aspect of the present technology is recited as a computer-readable medium claim, other aspects may likewise be embodied as a computer-readable medium claim or in other forms, such as in means-plus-function claims. Claims intended to be treated under 35 U.S.C. §112(f) begin with the phrase "means for," but the use of the term "for" in any other context is not intended for treatment under 35 U.S.C. §112(f). Accordingly, Applicant reserves the right to pursue additional claims after the filing of this application to pursue such additional claim forms in this application or any continuing application.

Claims

1. 1. A method for fabricating a semiconductor device, comprising: Each is 900 mm ２ providing a first type of source wafer containing circuit elements of a first type of resolution divided into a number of smaller prefabricated blocks (PFBs); providing a second type of source wafer including circuit elements of a second type of resolution divided into a number of PFBs, wherein the first type of resolution has a higher resolution than the second type of resolution; Assembling the PFB of the first type of source wafer and the PFB of the second type of source wafer on a previously assembled PFB to form a group of assembled PFBs, wherein the group of assembled PFBs has a resolution of the same type as the resolution of the first type. A method characterized by:

2. 2. The method of claim 1, wherein the first and second type source wafers are silicon wafers or non-silicon wafers including GaAs, InP, SiC, and sapphire.

3. 10. The method of claim 1, wherein a source wafer has a sacrificial layer that is etched away to remove the PFB from a majority of the source wafer.

4. 10. The method of claim 1, wherein the source wafer with the sacrificial layer comprises a substrate having two or more layers of different doping levels and / or types grown using an epitaxial growth process.

5. 2. The method of claim 1, wherein the overlay accuracy of the circuit elements of the first and second types of resolution divided into PFBs is better than 100 nm.

6. 2. The method of claim 1, wherein an overlay accuracy between a PFB of a circuit element of the first type of resolution and a PFB of a circuit element of the second type of resolution is better than 50 nm.

7. 2. The method of claim 1, wherein the PFB of the first type of source wafer and the PFB of the second type of source wafer are less than 10 [mu]m thick.

8. 8. The method of claim 7, wherein a superstrate assembly is used to pick and place the PFB of the first type source wafer and the PFB of the second type source wafer, wherein the superstrate assembly has one or more connected or unconnected sub-superstrates.

9. 10. The method of claim 8, further comprising controlling distortion of the PFB of the first type source wafer and the PFB of the second type source wafer to the nanometer scale using an overlay control architecture.

10. providing a transparent substrate; Attaching the first type source wafer or the second type source wafer containing PFB to the transparent substrate using a UV detack adhesive.

10. The method of claim 1, further comprising:

11. testing a PFB of the first type of source wafer and a PFB of the second type of source wafer to identify a known PFB for the assembly; wherein the test determines a known PFB through functionality testing and logical connectivity testing, and the test utilizes an area inside, around, or outside the PFB of the first type source wafer and the PFB of the second type source wafer.

2. The method of claim 1 .

12. 12. The method of claim 11, wherein selected portions of the PFB are tested to estimate the overall PFB quality by extrapolating using a statistical model.

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