Multi-die IC package

Abstract

To provide an integrated circuit (IC) package that prevents an unwanted current from flowing between two units that share a ground conductor.SOLUTION: An IC package (100) includes a first die (102) overlying a substrate (116). The first die (102) includes a first metal pad (130) on a second surface (118) opposite a first surface (108), a dielectric layer (106) having a first surface (119) in contact with the second surface (118) of the first die (102), and a second die (104) having a surface (120) in contact with a second surface (121) of the dielectric layer (106). The second die (104) includes a second metal pad (132) aligned with the first metal pad (132) of the first die (102). A plane (136) perpendicular to the second surface (118) of the first die (102) intersects the first metal pad (130) and the second metal pad (132).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates to integrated circuit (IC) packages, and more particularly to IC packages with multiple dies. [Background technology]

[0002] Galvanic isolation is the principle of isolating functional sections of an electrical system, preventing current flow and disallowing a direct conduction path. Energy or information can still be exchanged between sections through other mechanisms, such as capacitance, inductance, or electromagnetic waves. Galvanic isolation is used where two or more electrical circuits communicate, but such circuits have grounds that may be at different potentials. Galvanic isolation is an effective method of breaking ground loops by preventing unwanted current from flowing between two units that share a ground conductor. Galvanic isolation can also be used for safety, preventing accidental current from reaching ground through the human body.

[0003] Capacitors can provide galvanic isolation by passing alternating current (AC) and blocking direct current, and thus can couple AC signals between circuits at different DC voltages. Summary of the Invention

[0004] A first example relates to an integrated circuit (IC) package including a first die having a first surface overlying a substrate. The first die includes a first metal pad on a second surface opposite the first surface and a dielectric layer having a first surface in contact with the second surface of the first die. The IC package also includes a second die having a surface in contact with the second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

[0005] A second example relates to an IC package. The IC package includes a first die having a first surface overlying a first substrate, the first die including a first metal pad on a second surface opposite the first surface. The IC package also includes a second die including a second metal pad aligned with the first metal pad. A first protective overcoat layer contacts the second surface of the first die. The first protective overcoat layer includes a first recess exposing a third metal pad disposed on the second surface of the first die. A second protective overcoat layer contacts the first surface of the second die. A non-conductive die adhesive (NCDA) layer is sandwiched between the first protective overcoat and the second protective overcoat. The NCDA layer overlies a portion of the first protective overcoat layer spaced from the first recess. The first metal pad and the second metal pad form a capacitor coupling the first die to the second die. The IC package further includes a second substrate contacting a second surface of the second die, and a second recess extending through the second substrate and the insulating layer of the second die exposing a portion of the metal layer to provide a fourth metal pad.

[0006] A third example relates to a method for forming an IC package. The method includes applying a protective overcoat to a first die wafer including a first die and a second die wafer including a second die. A first surface of the first die overlies a substrate, and a second surface of the first die includes a first metal pad. The second surface of the first die faces the first surface of the first die. The method includes singulating the first die from the first die wafer and the second die from the second die wafer. The method also includes applying an NCDA layer to the second surface of the first die and aligning second metal pads disposed on the surface of the second die to the first metal pads of the first die. The method further includes bonding the second die to the NCDA layer to form a capacitor including the first metal pad and the second metal pad. The capacitor couples the first die to the second die. [Brief explanation of the drawings]

[0007] [Figure 1]1 shows a diagram of an example integrated circuit (IC) package with galvanically isolated first and second dies.

[0008] [Figure 2] 2 illustrates another example of an IC package with galvanically isolated first and second dies.

[0009] [Figure 3] 1 illustrates yet another example of an IC package with galvanically isolated first and second dies.

[0010] [Figure 4] 1 shows a flowchart of an exemplary method for forming an IC package.

[0011] [Figure 5] 5 illustrates a first stage of packaging for an IC package formed by the method of FIG. 4.

[0012] [Figure 6] 5 illustrates a second stage of packaging for an IC package formed by the method of FIG. 4.

[0013] [Figure 7] 5 illustrates a third stage of packaging for an IC package formed by the method of FIG. 4.

[0014] [Figure 8] 5 illustrates a fourth stage of packaging for an IC package formed by the method of FIG. 4.

[0015] [Figure 9] 1 illustrates another exemplary method for forming an IC package.

[0016] [Figure 10] 10 illustrates a first stage of packaging for an IC package formed by the method of FIG. 9.

[0017] [Figure 11] 10 illustrates a second stage of packaging for an IC package formed by the method of FIG. 9.

[0018] [Figure 12] 10 illustrates a third stage of packaging for an IC package formed by the method of FIG. 9.

[0019] [Figure 13] 10 illustrates a fourth stage of packaging for an IC package formed by the method of FIG. 9.

[0020] [Figure 14] 10 illustrates a fifth stage of packaging for an IC package formed by the method of FIG. 9. DETAILED DESCRIPTION OF THE INVENTION

[0021] This specification relates to an integrated circuit (IC) package including a galvanically isolated and capacitively coupled first die and second die. The first die and second die include embedded circuitry. Because the first die and second die are galvanically isolated, the embedded circuitry of the first die can have a ground potential that is different from the ground potential of the embedded circuitry of the second die. The first die has a first surface overlying a first substrate, and the first die has a first metal pad on a second surface opposite the first surface. A first protective overcoat contacts the second surface of the first die. The second die has a first surface contacting the second protective overcoat. The second die includes a second metal pad aligned to the first metal pad. The first metal pad and the second metal pad form nodes of a capacitor that couples the first die to the second die.

[0022] A non-conductive die attach (NCDA) layer is sandwiched between a first protective overcoat and a second protective overcoat. In some examples, multiple NCDA layers and / or spacers are sandwiched between the first protective overcoat and the second protective overcoat. The combination of the first protective overcoat, the second protective overcoat, and the NCDA layer (and / or other layers) interposed between the first metal pad of the first die and the second metal pad of the second die forms a dielectric layer. The first metal pad of the first die and the second metal pad of the second die are separated by the dielectric layer, thereby forming a capacitor for capacitively coupling the first die to the second die.

[0023] Wire bonds may also be used to couple the first die and the second die to other components, such as other dies and / or external lead components, of the IC package. In particular, a first recess in the first protective overcoat exposes a third metal contact disposed on the second surface of the first die. Similarly, a second substrate (e.g., formed of silicon) contacts the second surface of the second die. The second substrate includes a second recess exposing a fourth metal pad disposed on the second surface of the second die. Wire bonds are coupled to the respective third and fourth metal pads to couple the first and second dies to other components of the IC package.

[0024] By implementing the IC package in this manner, electrical isolation such as functional isolation, basic isolation, or reinforced isolation can be achieved. Also, because the first die and the second die are galvanically isolated, different processing techniques can be employed to manufacture the first die and the second die, especially in situations where the maximum voltage of the first die is different from the maximum voltage of the second die.

[0025] 1 shows a diagram of an example of an IC package 100 in a state for completing packaging. The IC package 100 includes a first die 102 and a second die 104. The first die 102 and the second die 104 include respective embedded circuits. In one orientation, the second die 104 overlaps the first die 102, and the first die 102 and the second die 104 are separated by a dielectric layer 106.

[0026] A first surface 108 of the first die 102 overlies the substrate 116. The substrate 116 may be formed of silicon. A second surface 118 of the first die 102 faces the first surface 108. In some examples, the second surface 118 of the first die 102 is referred to as the face of the first die 102. In one orientation, the second surface 118 of the first die 102 is below the dielectric layer 106, such that the first surface 119 of the dielectric layer 106 abuts the second surface of the first die 102.

[0027] The second die 104 includes a first surface 120 and a second surface 122. The second surface 122 of the second die 104 faces the first surface 120 of the second die 104. In some examples, the second die 104 has a smaller footprint than the first die 102. The die footprint refers to the area of ​​the surface of the respective die. In some examples, the first surface 120 of the second die 104 faces the second surface 121 of the dielectric layer 106. The second surface 121 of the dielectric layer 106 faces the first surface 119 of the dielectric layer 106.

[0028] In some examples, the dielectric layer 106 is implemented using a single layer of a homogenous material, such as a protective overcoat for the first die and the second die and a layer of non-conductive die attach (NCDA), such as a layer formed of epoxy. In other examples, the dielectric layer 106 can be implemented with multiple layers of dissimilar materials, such as a protective overcoat for the first die and the second die, multiple layers of NCDA, and spacers sandwiched between the multiple layers of NCDA.

[0029] The first die 102 and the second die 104 include embedded circuitry. The first die 102 and the second die 104 may be formed using different materials and / or processing techniques. In this manner, the materials and / or manufacturing techniques for fabricating the first die 102 and the second die 104 can be independently selected based on the operating parameters (e.g., maximum voltage) of the first die 102 and the second die 104.

[0030] In some examples, the arrangement of the first die 102 and the second die 104 is referred to as a face-to-face configuration. The first die 102 includes a first metal pad 130 (e.g., a connector), and the second die 104 includes a second metal pad 132. The first metal pad 130 and the second metal pad 132 are congruent and aligned. Thus, in one orientation, a plane such as plane 136 extending perpendicular to the second surface 118 of the first die 102 intersects the first metal pad 130 and the second metal pad 132. The first metal pad 130 forms a first node of the capacitor 140, and the second metal pad 132 forms a second node of the capacitor 140.

[0031] The first die 102 and the second die 104 are galvanically isolated and capacitively coupled via the capacitor 140. In this manner, the circuitry embedded in the first die 102 communicates with the circuitry embedded in the second die 104 via the capacitor 140. Because the first die 102 and the second die 104 are galvanically isolated, in some instances, the first die 102 and the second die 104 have grounds at different potentials. In one example of a high-voltage application, the ground of the first die 102 has a high voltage difference (e.g., a voltage difference of about 40 volts (V) or more) with the ground of the second die 104. Indeed, in some instances, such as a situation in which the first die 102 has circuitry for driving a motor and the second die 104 controls the motion of the first die 102, the ground voltage of the first die 102 can be 1 kilovolt (kV) or more greater than the ground voltage of the second die 104.

[0032] The first die 102 includes a third metal pad 150 disposed on the second surface 118 of the first die 102. A first wirebond 152 is coupled to the third metal pad 150. Additionally, a fourth metal pad 154 is disposed on the second surface 122 of the second die 104. A second wirebond 156 is coupled to the fourth metal pad 154. The first wirebond 152 and the second wirebond 156 are coupled to other components of the IC package, such as other dies and / or leads of the IC package.

[0033] The IC package 100 provides a simple design for achieving galvanic isolation. In some examples, the IC package 100 achieves basic isolation, while in other examples, the IC package 100 achieves reinforced isolation. As described above, the first die 102 and the second die 104 embed circuits with different ground potentials. Wafer materials and processing techniques selected for the particular voltage ranges and / or other operating parameters of the first die 102 and the second die 104 may be used. In contrast, in situations where the circuits of the first die 102 and the second die 104 are integrated based on a particular technology that provides isolation, the designer may be limited to using that single particular type of material and processing technique.

[0034] 2 shows a detailed view of an example of an IC package 200 in a state for completing packaging. The IC package 200 can be used to implement the IC package 100 of FIG. 1. The IC package 200 includes a first die 202 and a second die 204 that are galvanically isolated.

[0035] A first surface 208 of the first die 202 overlies a first substrate 210. The first substrate 210 may be formed of silicon. A first protective overcoat 212 is applied to a second surface 214 of the first die 202, the second surface 214 facing the first surface 208. In some examples, the surface 214 of the first die 202 is referred to as the face of the first die 202.

[0036] The second die 204 includes a first surface 220 and a second surface 222. The second surface 222 of the second die 204 faces the first surface 220 of the second die 204. The first surface 220 of the second die 204 is referred to as the face of the second die 204. In some examples, the second die 204 has a smaller footprint than the first die 202. A second protective overcoat 224 is adhered to the first surface 220 of the second die 204.

[0037] The first die 202 and the second die 204 include embedded circuitry. The first die 202 and the second die 204 may be formed using different materials and / or processing techniques. In this manner, the materials and / or processing techniques for manufacturing the first die 202 and the second die 204 can be independently selected based on the operating parameters of the first die 202 and the second die 204.

[0038] The NCDA layer 226 is adhered to the first protective overcoat 212 and the second protective overcoat 224. In other words, the NCDA layer 226 is sandwiched between the first protective overcoat 212 and the second protective overcoat 224. In some examples, the NCDA layer 226 is mounted using epoxy.

[0039] In some examples, the arrangement of the first die 202 and the second die 204 is referred to as a face-to-face configuration. The first die 202 includes a first metal pad 230 (e.g., a connector), and the second die 204 includes a second metal pad 232. The first metal pad 230 and the second metal pad 232 may each have a diameter in the range of 40 to 200 micrometers (μm). The first metal pad 230 and the second metal pad 232 are congruent and aligned within manufacturing tolerances (e.g., ±10 μm). Thus, in one orientation, a plane, such as plane 236, extending perpendicular to the second surface 214 of the first die 202 intersects the first metal pad 230 and the second metal pad 232. The first metal pad 230 forms a first node of the capacitor 240, and the second metal pad 232 forms a second node of the capacitor 240.

[0040] The first protective overcoat 212 and the second protective overcoat 224 may each be formed of a stack of materials. For example, the first protective overcoat 212 and the second protective overcoat 224 may be formed using a first layer of silicon dioxide (SiO) at least about 1 μm (e.g., ±0.7 μm) thick, a second layer of silicon oxynitride (SiON) at least about 1 μm (e.g., ±0.7 μm) thick, and a third layer of silicon dioxide (SiO) at least about 10 μm (e.g., ±8 μm) thick. The NCDA layer 226 may also have a thickness of at least about 6 μm (e.g., ±4 μm). The combination of the first protective overcoat 212, the second protective overcoat 224, and the NCDA layer 226 may be used to implement the dielectric layer 106 of FIG. 1. In this situation, the first metal pad 230 and the second metal pad 232 are separated by a distance of about 30 μm (eg, ±22.8 μm).

[0041] The first die 202 and the second die 204 are galvanically isolated and capacitively coupled via the capacitor 240. In this manner, circuitry embedded in the first die 202 can communicate with circuitry embedded in the second die 204 via the capacitor 240, and vice versa. Because the first die 202 and the second die 204 are galvanically isolated, in some instances, the first die 202 and the second die 204 have grounds at different potentials. In one example of a high-voltage application, the ground of the first die 202 has a high voltage difference (e.g., a voltage difference of about 40 V or more) with the ground of the second die 204. Indeed, in some instances, such as a situation in which the first die 202 includes circuitry for driving a motor and the second die 204 controls the operation of the first die 202, the ground voltage of the first die 202 can be 1 kV or more higher than the ground voltage of the second die 204.

[0042] In some examples, a first recess 242 is etched in the first protective overcoat 212. The first recess 242 in the first protective overcoat 212 exposes a third metal pad 250 disposed on the second surface 214 of the first die 202. The first recess 242 is spaced apart from the NCDA layer 226. In other words, in examples including the first recess 242, the first NCDA layer 226 is applied to a portion of the first protective overcoat 212 that overlies the first die 202 and is spaced apart from the first recess 242. Thus, the first NCDA layer 226 does not overlap or cover the first recess 242. A first wire bond 252 is bonded to the third metal pad 250. Additionally, a second substrate 254 (e.g., formed of silicon) contacts the second surface 222 of the second die 204. In particular, the second surface 222 is proximate to the insulating layer 255 of the second die 204, and the second substrate 254 contacts the insulating layer 255 of the second die 204. A second recess 256 formed using a backside processing technique is etched into the second substrate 254 and the insulating layer 255 of the second die 204, exposing a portion of the metal layer in the second die 204 to provide the fourth metal pad 260. Thus, in some examples, the opening in the second substrate 254 and the insulating layer 255 that forms the recess 256 is self-aligned. The insulating layer 255 of the second die 204 also separates the fourth metal pad 260 from the substrate 254. A second wire bond 262 is coupled to the fourth metal pad 260. First wirebond 252 and second wirebond 262 may be coupled to other components of IC package 200, such as other dies and / or external leads of IC package 200.

[0043] The IC package 200 provides a simple design for achieving galvanic isolation. In some examples, the IC package 200 achieves basic isolation, while in other examples, the IC package 200 achieves reinforced isolation. Also, as noted above, in some examples, the first die 202 and the second die 204 embed circuits with different maximum voltages. Therefore, wafer materials and processes selected for the particular voltage ranges and / or other operating parameters of the first die 202 and the second die 204 may be employed. In contrast, in situations where the circuits of the first die 202 and the second die 204 are integrated using a single technology, the designer may be limited to using a single type of material and processing technique.

[0044] 3 shows a detailed view of an IC package 300 in a state for completing packaging. The IC package 300 can be used to implement the IC package 100 of FIG. 1. The IC package 300 includes a first die 302 and a second die 304 that are galvanically isolated.

[0045] A first surface 308 of the first die 302 overlies a first substrate 310. The first substrate 310 can be silicon. A first protective overcoat 312 is applied to a second surface 316 of the first die 302, the second surface 316 facing the first surface 308. In some examples, the second surface 316 of the first die 302 is referred to as the face of the first die 302.

[0046] The second die 304 includes a first surface 320 and a second surface 322. The second surface 322 of the second die 304 faces the first surface 320 of the second die 304. The first surface 320 of the second die 304 is referred to as the face of the second die 304. In some examples, the second die 304 has a smaller footprint than the first die 302. A second protective overcoat 324 is adhered to the first surface 320 of the second die 304.

[0047] The first die 302 and the second die 304 include embedded circuitry. The first die 302 and the second die 304 may be formed using different materials and / or processing techniques. In this manner, the materials and / or processing techniques for manufacturing the first die 302 and the second die 304 can be independently selected based on the operating parameters of the first die 302 and the second die 304.

[0048] A spacer plate 326 is sandwiched between the first protective overcoat 312 and the second protective overcoat 324. The spacer plate 326 is formed from a non-conductive material. In some examples, the spacer plate 326 is formed using a silicon dioxide (SiO2) material such as fused silica or quartz.

[0049] A first NCDA layer 328 is adhered to the first protective overcoat 312 and the spacer plate 326. Thus, the first NCDA layer 328 is sandwiched between the first protective overcoat 312 and the spacer plate 326. A second NCDA layer 330 is adhered to the second protective overcoat 324. Thus, the second NCDA layer 330 is sandwiched between the second protective overcoat 324 and the spacer plate 326. In some examples, the first NCDA layer 328 and the second NCDA layer 330 are formed using epoxy.

[0050] In some examples, the arrangement of the first die 302 and the second die 304 is referred to as a face-to-face configuration. The first die 302 includes a first metal pad 332 (e.g., a connector), and the second die 304 includes a second metal pad 334. The first metal pad 332 and the second metal pad 334 may each have a diameter of approximately 120 μm (e.g., ±80 μm). The second die 304 is aligned to the first die 302 such that the first metal pad 332 and the second metal pad 334 are congruent and aligned within a manufacturing tolerance (e.g., ±10 μm). Thus, in one orientation, a plane such as plane 338 extending perpendicular to the second surface 316 of the first die 302 intersects the first metal pad 332 and the second metal pad 334. First metal pad 332 forms a first node of capacitor 340, and second metal pad 334 forms a second node of capacitor 340. Compared to IC package 200 of Figure 2, IC package 300 has a thinner first protective overcoat 312 and a thinner second protective overcoat 324. Spacer plate 326 compensates for the reduced thickness of first protective overcoat 312 and second protective overcoat 324.

[0051] The first protective overcoat 312 and the second protective overcoat 324 may each be formed from a stack of materials. For example, the first protective overcoat 312 and the second protective overcoat 324 may be formed using a first layer of silicon dioxide (SiO) at least about 1 μm (e.g., ±0.7 μm) thick and a second layer of silicon oxynitride (SiON) at least about 1 μm (e.g., ±0.7 μm) thick. The first NCDA layer 328 and the second NCDA layer 330 may each have a thickness of at least about 6 μm (e.g., ±4 μm). The spacer plate 326 may each have a thickness of at least about 20 μm (e.g., ±10 μm). The combination of the first protective overcoat 312, the second protective overcoat 324, the first NCDA layer 328, the second NCDA layer 330, and the spacer plate 326 may be used to implement the dielectric layer 106 of FIG. 1. In this situation, the first metal pad 332 and the second metal pad 334 are separated by a distance of about 36 μm (eg, ±20.8 μm).

[0052] The first die 302 and the second die 304 are galvanically isolated and capacitively coupled via the capacitor 340. In this manner, circuitry embedded in the second die 304 can communicate with circuitry embedded in the second die 304 via the capacitor 340, and vice versa. Because the first die 302 and the second die 304 are galvanically isolated, the first die 302 and the second die 304 have different ground potentials. In one example of a high-voltage application, the ground of the first die 302 has a high voltage difference (e.g., a voltage difference of about 40 V or more) with the ground of the second die 304. Indeed, in some examples, such as a situation in which the first die 302 includes circuitry for driving a motor and the second die 304 controls the movement on the first die 302, the ground voltage of the first die 302 can be 1 kV or more greater than the ground voltage of the second die 304.

[0053] In one example, a first recess 342 is etched in the first protective overcoat 312. The first recess 342 in the first protective overcoat 312 exposes a third metal pad 350 disposed on the second surface 316 of the first die 302. The first recess 342 is spaced apart from the first NCDA layer 328. In other words, in an example including the first recess 342, the first NCDA layer 328 is applied to a portion of the first protective overcoat 312 that overlies the first die 302 and is spaced apart from the first recess 342. Thus, the first NCDA layer 342 does not overlie or cover the first recess 342. A first wire bond 352 is coupled to the third metal pad 350. Additionally, a second substrate 354 (e.g., formed using silicon) contacts the second surface 322 of the second die 304. In particular, the second die 304 includes an insulating layer 355 proximate the second surface 322 of the second die 304. Thus, in some examples, the second substrate 354 contacts the insulating layer 355 of the second die 304. A second recess 356 etched into the second substrate 354 and the insulating layer 355 of the second die 304 using a backside processing technique exposes a portion of the metal layer of the second die 304 to provide a fourth metal pad 360 within the second die 304. Thus, in some examples, the opening formed in the second substrate 354 and the insulating layer 355 of the second die 304 that forms the second recess 356 is self-aligned. Additionally, an insulating layer 355 of the second die 304 separates a fourth metal pad 360 from the substrate 354. A second wirebond 362 is bonded to the fourth metal pad 360. The first wirebond 352 and the second wirebond 362 are bonded to other components of the IC package 300, such as other dies and / or external leads of the IC package 300.

[0054] The IC package 300 provides a simple design for achieving galvanic isolation. In some examples, the IC package 300 achieves basic isolation, while in other examples, the IC package 300 achieves reinforced isolation. Also, as noted above, in some examples, the first die 302 and the second die 304 embed circuits with different maximum voltages. Therefore, wafer materials and processing techniques selected for the particular voltage ranges and / or other operating characteristics of the first die 302 and the second die 304 may be employed. In contrast, in situations where the circuits of the first die 302 and the second die 304 are integrated onto a single die, the designer may be limited to using a single type of material and processing technique.

[0055] FIG. 4 illustrates a method 400 for forming an IC package. The method 400 can be used to form, for example, the IC package 100 of FIG. 1 and / or the IC package 200 of FIG. 2. The IC package thus includes a first die and a second die, such as the first die 202 and second die 204 of FIG. 2. The method 400 is described with reference to FIGS. 5-8, which illustrate stages in the fabrication of the IC package 200 of FIG. 2. Additionally, FIGS. 2 and 5-8 use the same reference numbers to indicate the same structures.

[0056] At 405, a protective overcoat is applied to the die wafers including the first and second dies, which may be referred to as the first die wafer and second die wafer, respectively. More specifically, as shown in Figure 5, first protective overcoat 212 and second protective overcoat 224 are applied to first die wafer 280 including first die 202 and second die wafer 282 including second die 204, respectively, as shown in Figure 5. First die 202 also overlies a first substrate, such as first substrate 210, as shown in Figure 5.

[0057] Referring back to FIG. 4 , at 410, a first recess is patterned and etched in a first protective overcoat applied to the first die wafer. At 412, the backside of the second die wafer is patterned, and the pattern on the backside of the second die wafer is aligned to the pattern on the front side of the second die wafer. At 413, a second recess is etched in the second substrate and insulating layer on the backside of the second die wafer in an area overlying the second die. In some examples, the second recess in the second substrate and insulating layer is formed using a backside processing technique. As shown in FIG. 6 , the first recess 242 exposes the third metal pad 250 of the first die 202, and the second recess 256 exposes a portion of the metal layer of the second die 204 to provide the fourth metal pad 260.

[0058] Referring back to FIG. 4 , at 414, the first die and the second die are singulated from the first die wafer and the second die wafer. In some examples, the first die and the second die may be singulated using a laser process or a cutting process. At 415, an NCDA layer is applied to the first die, as shown by NCDA layer 226 in FIG. 7 . As illustrated in FIG. 7 , NCDA layer 226 is applied to a portion of first protective overcoat 212 of first die 202 that is spaced from first recess 242. Referring back to FIG. 4 , at 420, the first metal pads of the first die and the second metal pads on the second die are aligned, and the second die is attached to the NCDA layer. At 425, the second die is bonded to the NCDA layer. 8, the second metal pad 232 is aligned to the first metal pad 230 such that the plane 236 extends through the first metal pad 230 and the second metal pad 232 to form a capacitor. Referring back to FIG. 4, at 430, wire bonds are attached to the metal pads exposed by the first and second recesses to form the IC package 200 shown in FIG.

[0059] FIG. 9 illustrates a method 1000 for forming an IC package. The method 1000 can be used to form, for example, the IC package 100 of FIG. 1 and / or the IC package 300 of FIG. 3. The IC package thus includes a first die and a second die, such as the first die 302 and second die 304 of FIG. 2. The method 1000 is described with reference to FIGS. 10-14, which illustrate stages in the fabrication of the IC package 300 of FIG. 3. Additionally, FIGS. 3 and 10-14 use the same reference numbers to indicate the same structures.

[0060] At 1005, a protective overcoat is applied to the die wafers including the first and second dies, which may be referred to as the first die wafer and second die wafer. More specifically, as shown in FIG. 10 , first protective overcoat 312 and second protective overcoat 324 are applied to first die wafer 380 including first die 302 and second die wafer 382 including second die 304, respectively. Also shown in FIG. 10 , the first die overlies first substrate 310. Referring back to FIG. 9 , at 1010, first recesses are etched in the first protective overcoat applied to the first wafer including the first die. At 1012, the backside of the second die wafer is patterned, and the pattern on the backside of the second die wafer is aligned to the pattern on the front side of second die wafer 282. At 1013, a second recess is etched into the second substrate and insulating layer on the backside of the second die wafer in an area overlying the second die. In some examples, the second recess in the second substrate and insulating layer is formed using backside processing techniques. As shown in FIG. 11 , the first recess 342 exposes the third metal pad 350 of the first die 302, and the second recess 356 exposes the metal layer of the second die 304 to provide the fourth metal pad 360.

[0061] Referring back to FIG. 9 , at 1014, the first die and the second die are singulated from the first die wafer and the second die wafer, respectively. In some examples, the first die and the second die may be singulated using a laser process and cutting process. At 1015, a first NCDA layer is applied to the first die. FIG. 12 shows the first NCDA layer 328 applied to the second surface 316 of the first die 302. As shown in FIG. 12 , the first NCDA layer 328 is applied to a portion of the first protective overcoat 312 of the first die 302 that is spaced from the first recess 342.

[0062] Referring back to FIG. 9 , at 1020, a spacer plate is attached onto the first NCDA layer. At 1025, a second NCDA layer is attached to the spacer plate. FIG. 13 shows a spacer plate 326 attached onto the first NCDA layer 328 and a second NCDA layer 330 attached onto the spacer plate 326. Referring back to FIG. 9 , at 1030, a first metal pad of the first die and a second metal pad of the second die are aligned. At 1035, the second die is attached to the second NCDA layer. As shown in FIG. 14 , a second metal pad 334 is aligned to the first metal pad 332, such that a plane 338 extends through the first metal pad 332 and the second metal pad 334 to form a capacitor. Referring back to FIG. 9, at 1040, wire bonds are attached to the metal pads exposed by the first recess 342 and the second recess 356 to form the IC package 300 illustrated in FIG.

[0063] The foregoing is exemplary. Of course, it is not possible to describe every possible combination of components or methodologies, but one of ordinary skill in the art will recognize that many more combinations and permutations are possible. Accordingly, this specification embraces all such changes, modifications, and variations that fall within the scope of this application, including the appended claims.

Claims

1. A method comprising: forming a first dielectric layer on a first surface of a first die, the first die including first metal pads on the first surface, the first dielectric layer covering the first metal pads; forming a second dielectric layer on a second surface of a second die, the second die including second metal pads on the second surface, the second dielectric layer covering the second metal pads; applying a first non-conductive die adhesive (NCDA) layer over a portion of the second dielectric layer, the first NCDA layer covering the first metal pad; adhering the second die to the first die such that the first NCDA layer is located between the first and second dielectric layers; Including, A first metal pad is aligned to the second metal pad to form a capacitor including a dielectric layer comprising the first and second dielectric layers and the first NCDA layer.

2. 10. The method of claim 1, 11. The method of claim 10, further comprising etching a first opening in the first dielectric layer before bonding the second die to the first die, the first opening being laterally spaced from the first NCDA layer and exposing a third metal pad at the first surface.

3. The method according to claim 2, The method further comprising attaching a bond wire to the third metal pad after bonding the second die to the first die.

4. The method of claim 1, the method further comprising: prior to bonding the second die to the first die, etching a second opening through the substrate facing a third surface of the second die opposite the second surface and an insulating layer of the second die at the third surface, the second opening overlying the first NCDA layer and exposing a fourth metal pad at the third surface.

5. The method according to claim 4, The method further comprising attaching a bond wire to the fourth metal pad after bonding the second die to the first die.

6. The method of claim 1, placing a spacer plate on the first NCDA layer; applying a second NCDA layer onto the spacer plate; The method further comprises:

7. The method according to claim 6, the capacitor dielectric layer further comprising the spacer plate and the second NCDA layer; 8. The method of claim 6, comprising: The method, wherein the spacer plates comprise a silicon dioxide (SiO 2 ) material and the first and second NCDA layers comprise epoxy.

9. The method of claim 1, The method wherein the first and second metal pads fit within manufacturing tolerances.

10. The method of claim 1, a plane perpendicular to a first surface of the first die intersects the first metal pad and the second metal pad.

11. The method of claim 1, The method, wherein the first die is galvanically isolated from the second die.

12. The method of claim 1, The method, wherein the first die has a first ground potential and the second die has a second ground potential different from the first ground potential.

13. The method of claim 1, The method, wherein the first die has a first operating voltage and the second die has a second operating voltage different from the first operating voltage.

14. The method of claim 1, The method, wherein the first die comprises a first semiconductor material and the second die comprises a second semiconductor material different from the first semiconductor material.

15. A method for forming an integrated circuit (IC) package, comprising: applying a protective overcoat to a first wafer including a first die and a second wafer including a second die, the first die having a first surface facing a substrate and a second surface opposite the first surface, the first die including first metal pads on the second surface; singulating the first die from the first wafer and singulating the second die from the second wafer; applying a non-conductive die attach (NCDA) layer to a portion of the protective overcoat on a second surface of the first die; aligning second metal pads located on a third surface of the second die to the first metal pads, the third surface of the second die facing the second surface of the first die; adhering the second die to the first die such that a second surface of the first die faces a third surface of the second die; Including, the first metal pad, the second metal pad, and the NCDA layer disposed between the first and second metal pads form a capacitor coupling the first die to the second die.

16. The method of claim 15, etching the first recesses in the protective overcoat on the first wafer before singulating the first die from the first wafer such that third metal pads on the second surface of the first die are exposed through the first recesses; Etching second recesses in the second wafer before singulating the second die from the second wafer, the second recesses extending through a second substrate facing a fourth surface of the second die opposite the third surface and an insulating layer of the second die at the fourth surface, such that fourth metal pads at the fourth surface of the second die are exposed through the second recesses; The method further comprises:

17. The method of claim 16, The method, wherein the insulating layer separates the fourth metal pad from the second substrate.

18. The method of claim 16, The method, wherein the first recess is laterally spaced from the NCDA layer.

19. The method of claim 16, attaching a first wire bond to the third metal pad; attaching a second wire bond to the fourth metal pad; The method further comprises:

20. The method of claim 15, the capacitor includes a dielectric layer having the protective overcoat on a second surface of the first die, the protective overcoat on a third surface of the second die, and the NCDA layer disposed between the protective overcoats.

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