solar cells

Abstract

To optimize a manufacturing method of an N-type TOPCon solar cell.SOLUTION: A solar cell can be prepared as follows: providing an N-type silicon substrate; depositing a tunnel passivation structure on a first surface of the N-type silicon substrate, and then depositing a mask layer on the tunnel passivation structure; cleaning a second surface of the N-type silicon substrate; performing boron diffusion treatment on the cleaned second surface of the N-type silicon substrate and annealing treatment on the tunnel passivation structure in the same environment so that a first emitter layer is formed on the second surface of the N-type silicon substrate and the tunnel passivation structure is crystallized; performing laser patterning on the first emitter layer to form a second emitter region; depositing a passivation and anti-reflection film; and forming a first electrode disposed in electrical contact with the second emitter region and a second electrode disposed in electrical contact with the tunnel passivation structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application relates to solar cells. [Background technology]

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells use an ultra-thin oxide layer as a passivation layer. N-type TOPCon cells are expected to enter large-scale mass production in 2022, exceeding 40 GW in scale, gradually replacing p-type cells as the market leader. Currently, n-type TOPCon cells typically use boron doping to form the emitter structure. The emitter typically employs a uniform junction, resulting in suboptimal metal contact recombination, short-wave response, and recombination speed. To achieve lower metal contact recombination, a boron-doped junction depth of 0.7 μm or greater is generally required. However, because boron atoms themselves are relatively difficult to dope, achieving a junction depth of 0.7 μm or greater requires temperatures of over 970°C and a time of over 3 hours. This increases power consumption and equipment losses during cell manufacturing, and the long high-temperature period also increases wafer quality requirements, significantly increasing the cost of electricity generation per kWh. The electrochemical capacitance-voltage (ECV) doping concentration-depth curve (ECV doping curve) of the boron emitter fabricated by this method is shown in Figure 3 (the conventional boron emitter in Figure 3 represents the ECV doping curve of the boron emitter). Therefore, the structure of the N-type TOPCon battery needs to be further optimized. Summary of the Invention [Means for solving the problem]

[0003] The solar cell of the present application is an N-type silicon substrate having a first surface and a second surface; a tunnel passivation structure and a first passivation anti-reflection film formed on the first surface; a boron-doped emitter structure layer formed on the second surface; a second passivation anti-reflection film formed on the emitter structure layer; A first electrode; a second electrode, the emitter structure layer includes a first emitter layer and a second emitter region, wherein a junction depth of the first emitter layer is less than a junction depth of the second emitter region, and a total doping amount of boron in the first emitter layer is less than a total doping amount of boron in the second emitter region; the first electrode is disposed in electrical contact with the second emitter region; The second electrode is disposed in electrical contact with the tunnel passivation structure.

[0004] The solar cell of the present application has a selective emitter structure and a large junction depth in the metal contact region, which meets metallization requirements. The shallow junction depth in regions other than the metal contact region improves optical response. Furthermore, the total boron doping amount in the first emitter layer is less than the total boron doping amount in the second emitter region. This cell structure meets the photoelectric conversion performance of the solar cell and significantly shortens the high-temperature time of the boron diffusion process during manufacturing, thereby reducing the manufacturing cost of the solar cell.

[0005] In one embodiment, the tunnel passivation structure includes a tunnel oxide layer and a passivation contact material layer, and the tunnel oxide layer is disposed between the N-type silicon substrate and the passivation contact material layer.

[0006] In one embodiment, the constituent material of the passivation contact material layer is one or more selected from doped amorphous silicon, doped polycrystalline silicon, and silicon carbide.

[0007] In one embodiment, the second electrode is disposed in electrical contact with the passivating contact material layer.

[0008] In one embodiment, the first emitter layer has a junction depth of 0.7 μm or less.

[0009] In one embodiment, the second emitter region has a junction depth of 0.8 μm or more.

[0010] In one embodiment, the boron doping concentration of the second emitter region is 2×10 19 atm / cm 3 The following is the result.

[0011] In one embodiment, the peak point in the ECV doping curve of the first emitter layer is located at a depth of 0.05 to 0.5 μm from the surface of the first emitter layer.

[0012] In one embodiment, in an ECV doping curve of the first emitter layer, in a depth range of 0.02 to 0.6 μm from the surface of the first emitter layer, the difference between the maximum boron doping concentration and the minimum boron doping concentration in the first emitter layer is greater than one order of magnitude.

[0013] In one embodiment, in an ECV doping curve of the second emitter region, in a depth range of 0.05 to 0.7 μm from the surface of the second emitter region, the difference between the maximum and minimum boron doping concentrations in the second emitter region is less than one order of magnitude.

[0014] In one embodiment, the sheet resistance of the first emitter layer is greater than the sheet resistance of the second emitter region.

[0015] In one embodiment, the first emitter layer has a sheet resistance of 150 ohm / sq or more, and the second emitter region has a sheet resistance of 150 ohm / sq or less.

[0016] In one embodiment, the width of the first electrode is smaller than the width of the second emitter region.

[0017] In one embodiment, the material of the passivation anti-reflection coating is one or a combination of two or more selected from aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a structural schematic diagram of a solar cell according to the present invention. [Figure 2] 1 is a flowchart of a method for manufacturing a solar cell according to the present application. [Figure 3] 1 shows ECV doping curves in the first emitter layer and second emitter region of the solar cell of Example 1 and an ECV doping concentration-depth curve of a conventional boron emitter. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described in more detail below with reference to the drawings and examples, which will make the features and advantages of the present invention more apparent.

[0020] As used herein, the term "exemplary" means "serving as an example or example, or illustrative." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to other embodiments. While the drawings illustrate various aspects of the embodiments, the drawings are not necessarily drawn to scale unless specifically noted.

[0021] Furthermore, the technical features according to different embodiments of the present application described below can be combined with each other as long as they are not inconsistent with each other.

[0022] As shown in FIG. 1 , the solar cell of the present application includes an N-type silicon substrate 1 having a first surface and a second surface, a tunnel passivation structure 2 and a first passivation anti-reflection film 6 formed on the first surface, a boron-doped emitter structure layer formed on the second surface, a second passivation anti-reflection film 5 formed on the emitter structure layer, a first electrode 7, and a second electrode 8. The emitter structure layer includes a first emitter layer 3 and a second emitter region 4. The junction depth of the first emitter layer 3 is smaller than the junction depth of the second emitter region 4. The maximum boron doping concentration of the first emitter layer 3 is greater than the maximum boron doping concentration of the second emitter region 4. The total boron doping amount of the first emitter layer 3 is smaller than the total boron doping amount of the second emitter region 4. A first electrode 7 is arranged in electrical contact with the second emitter region 4 , and a second electrode 8 is arranged in electrical contact with the tunnel passivation structure 2 .

[0023] In this application, the front surface is the surface onto which sunlight is incident, and the back surface is the surface opposite to the surface onto which sunlight is incident. In Figure 1, the upper surface of the N-type silicon substrate 1 is the front surface (second surface), and the lower surface is the back surface (first surface).

[0024] The structure of the solar cell will be described below with reference to the manufacturing process. As shown in Figure 2, the solar cell can be manufactured as follows.

[0025] At S1, an N-type silicon substrate is provided.

[0026] In S2, a tunnel passivation structure is deposited on a first surface of the N-type silicon substrate, and a mask layer is deposited on the tunnel passivation structure.

[0027] In S3, the second surface of the N-type silicon substrate is cleaned.

[0028] In S4, a first emitter layer is formed on the second surface of the N-type silicon substrate, and a boron diffusion process is performed on the cleaned second surface of the N-type silicon substrate in the same environment so as to crystallize the tunnel passivation structure, and an annealing process is performed on the tunnel passivation structure.

[0029] In S5, the first emitter layer is subjected to a laser patterning process to form a second emitter region.

[0030] In S6, a passivation anti-reflective coating is deposited.

[0031] At S7, a first electrode is formed in electrical contact with the second emitter region, and a second electrode is formed in electrical contact with the tunnel passivation structure.

[0032] Prior to the manufacturing process, the N-type silicon substrate may be cleaned and polished in preparation for the next step.

[0033] Then, as shown in FIG. 1 , a tunnel passivation structure 2 is deposited on the first surface (backside) of the N-type silicon substrate 1. The tunnel passivation structure 2 may be any of various tunnel passivation structures that can be used in TOPCon cells. For example, it may include a tunnel oxide layer 21 and a passivation contact material layer 22, with the tunnel oxide layer 21 being disposed between the N-type silicon substrate 1 and the passivation contact material layer 22. In one embodiment, the tunnel oxide layer 21 may be made of a material such as silicon oxide. In one embodiment, the passivation contact material layer 22 may be made of one or more materials selected from the group consisting of doped amorphous silicon, doped polycrystalline silicon, and silicon carbide material SiCx, such as a phosphorus-doped polycrystalline silicon layer or a silicon carbide material.

[0034] Thereafter, a cleaning process is performed on the second surface (front surface) of the N-type silicon substrate 1 to remove unnecessary material layers, such as polycrystalline silicon layers, that are generated by wrap-around on the surface. After cleaning, a texturing process can be performed to increase the surface area, reduce the surface reflectance, and remove impurities, thereby forming a texture.

[0035] Then, a first emitter layer 3 is formed on the second surface of the N-type silicon substrate 1, and a boron diffusion process is performed on the cleaned second surface of the N-type silicon substrate 1 in the same environment to crystallize the tunnel passivation structure 2. The tunnel passivation structure 2 is then annealed. Boron diffusion is performed on the second surface (front) of the N-type silicon substrate 1 to form the first emitter layer 3, which is a p-type silicon layer. When performing the process in the same environment, in addition to diffusing boron on the second surface (front) of the N-type silicon substrate 1 to form the p-type silicon layer (first emitter layer 3), annealing is simultaneously performed on the previously formed tunnel passivation structure 2. During the high-temperature boron diffusion process, the crystallization of the material of the passivation contact material layer 22 and the redistribution of the doping elements are completed, thereby improving the passivation ability of the passivation contact structure. This eliminates the need for a separate annealing process for the tunnel passivation structure 2 and avoids the adverse effects of high temperatures on the silicon wafer and the layers thereon. In one embodiment, the boron source used in the boron diffusion process is BCl3, BBr3, or the like. In this application, the boron diffusion process is performed at a low temperature and for a short time, resulting in a relatively shallow junction depth of the formed p-type silicon layer (first emitter layer 3), with the junction depth of the first emitter layer 3 being 0.7 μm or less, thereby improving optical response. In one embodiment, the temperature of the same environment is 300 to 970°C, and the treatment time at 800 to 970°C is less than 3 hours. In one embodiment, the sheet resistance of the first emitter layer 3 is 150 ohm / sq or greater.

[0036] In one embodiment, the junction depth of the first emitter layer 3 may be 0.7 μm or less, which can improve the optical response. Figure 1 shows the junction depth h1 of the first emitter layer 3, which corresponds to the thickness of the first emitter layer 3, and the thickness of the first emitter layer 3 means the distance from the surface to where the first emitter layer 3 exists.

[0037] The first emitter layer 3 is then subjected to laser patterning to form the second emitter region 4. The laser patterning process employs laser light of one or more wavelengths, such as ultraviolet, green, or infrared light, with a pulse width of nanoseconds, picoseconds, or femtoseconds and an average power of 5 to 200 W. For example, a green nanosecond laser with a laser power of 30 W and a wavelength of 532 nm can be used. As shown in FIG. 1 , the laser patterning process promotes boron doping, forming the second emitter region 4 with a junction depth, doping concentration, and sheet resistance different from those of the first emitter layer 3. In this application, the junction depth h1 of the first emitter layer 3 is smaller than the junction depth h2 of the second emitter region 4. FIG. 1 shows the junction depth h2 of the second emitter region 4, which corresponds to the thickness of the second emitter region 4. The thickness of the second emitter region 4 refers to the distance from the surface to where the second emitter region 4 is located. In one embodiment, the junction depth h2 of the second emitter region 4 is 0.8 μm or greater. However, the junction depth h2 of the second emitter region 4 typically does not exceed 5 μm. As will be described later, the second emitter region 4 is in electrical contact with the first electrode 7, and this junction depth h2 satisfies metallization requirements. The first emitter layer 3 and the second emitter region 4 together constitute an emitter structure layer.

[0038] For the first emitter layer 3, the peak point on the ECV doping concentration-depth curve (ECV doping curve) is not at the silicon wafer surface, but at an internal position at a depth of approximately 0.02 to 0.5 μm from the surface of the first emitter layer. The doping curve for the first emitter layer 3 has a relatively large variation range, with the doping concentration varying significantly within a depth range of 0.02 to 0.6 μm, and the difference between the maximum and minimum boron doping concentrations is greater than one order of magnitude. For example, the boron doping concentration in the first emitter layer 3 is 2×10 19 ~1×10 18 atm / cm 3 , or 3 × 10 19 ~5×10 17 atm / cm 3 The steep diffusion junction type of the first emitter layer 3 can be realized with a relatively short boron diffusion time, which reduces the manufacturing cost.

[0039] For the second emitter region 4, the ECV doping concentration-depth curve (ECV doping curve) in the second emitter region 4 is flatter, the doping concentration is almost unchanged in the depth range of 0.05 to 0.7 μm, and the difference between the maximum and minimum boron doping concentrations is less than one order of magnitude, for example, when the boron doping concentration in the second emitter region 4 is 1×10 19 ~1×10 18 atm / cm 3 , 5×10 18 ~5×10 19 atm / cm 3 , or 1 × 10 19 ~1×10 20 atm / cm 3 The more moderately doped junction type of the second emitter region 4 forms a good metal contact, reducing the contact resistivity and the recombination current density in the metal region, thereby improving the photoelectric conversion efficiency of the solar cell.

[0040] In one embodiment, the first emitter layer 3 has a higher sheet resistance than the second emitter region 4. In one embodiment, the sheet resistance of the first emitter layer 3 is 150 ohm / sq or more, and the sheet resistance of the second emitter region 4 is 150 ohm / sq or less.

[0041] The silicon wafer surface is then cleaned. This cleaning process can clean the mask layer on the tunnel passivation structure on the backside and the oxide layer on the frontside. The cleaning process can be performed using alkaline cleaning and / or acid cleaning. For alkaline cleaning, a potassium hydroxide solution or a sodium hydroxide solution can be used as a cleaning agent, and for acid cleaning, a HF solution or an HCl solution can be used as a cleaning agent.

[0042] Then, passivation anti-reflection coatings are deposited on both sides of the silicon wafer. Various methods known in the art can be used to deposit the passivation anti-reflection coatings, and the materials for the passivation anti-reflection coatings can be one or a combination of various commonly used passivation anti-reflection coating materials, such as aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. The passivation anti-reflection coatings can be composed of a single layer of material or a multilayer structure composed of multiple materials. As shown in FIG. 1, the second passivation anti-reflection coating 5 is located on the front side, and the first passivation anti-reflection coating 6 is located on the back side.

[0043] Thereafter, metal electrode portions are deposited. As shown in Figure 1, the metal electrode portions include a first electrode 7 located on the front side and arranged to be in electrical contact with the second emitter region 4, and a second electrode 8. The second electrode 8 is located on the back side and arranged to be in electrical contact with the tunnel passivation structure 2, in particular the passivation contact material layer 22. The deposition of the metal electrodes can be carried out by conventional methods such as screen printing.

[0044] In one embodiment, as shown in Figure 1, the width of the first electrode 7 is smaller than the width of the second emitter region 4. In Figure 1, the width w1 of the first electrode 7 and the width w2 of the second emitter region 4 are the distances between the edges of the first electrode 7 and the second emitter region 4 in the x direction, respectively. This allows the first electrode region to be completely covered by the second emitter region 4, which has the advantage of effectively reducing metallic recombination in the first electrode region, lowering the recombination current density, and improving the battery open-circuit voltage. [Example]

[0045] The n-type silicon wafer is subjected to wet chemical cleaning to remove surface damage and impurities, and then the surface is polished with an alkaline solution to form a surface with a reflectivity greater than 30% and high flatness, which better achieves the passivation effect of the rear passivation contact structure.

[0046] A tunnel silicon oxide layer and a doped polysilicon layer are deposited on the backside of a silicon wafer by PECVD, where the tunnel silicon oxide layer is 0.9-2 nm thick and the doped polysilicon layer is 75-150 nm thick, and then a silicon oxide layer mask with a thickness of 10-50 nm is deposited on the outer layer.

[0047] Wet chemical cleaning is used to remove the wrap-around polycrystalline silicon layer on the surface, and then alkaline texturing is performed on the surface to form a pyramidal structure on the front side of the silicon wafer, while the back side retains its original structure under the protection of a mask.

[0048] A silicon wafer is placed in a tubular diffusion furnace, and BCl3 and oxygen gas are introduced at temperatures above 800°C. BCl3 reacts with the surface of the silicon wafer to form boron atoms, which then diffuse into the silicon wafer, forming the first emitter. A boron-rich silicon oxide layer, i.e., borosilicate glass (BSG), is also formed on the surface. The boron diffusion conditions are as follows: deposition step: BCl3 flow rate 300 sccm, oxygen gas flow rate 200 sccm, temperature 850°C, and time 15 minutes. The subsequent heating step for junction formation is performed at 930°C and time 30 minutes. The sheet resistance of the first emitter is 150-250 ohm / sq, the junction depth of the first emitter is 0.5 μm, and the BSG thickness is 10-150 nm. At the same time, the high temperature and time of boron diffusion allows the doped polycrystalline silicon layer on the backside to complete the crystallization and redistribution of the doping elements, thereby improving the passivation ability of the passivation contact structure.

[0049] A patterning process is performed on the front surface of borosilicate glass using a long-pulse laser or a short-pulse laser with a high overlap ratio. The laser power is 30 W, the spot width is 60-200 μm, and the spot shape is circular, elliptical, or rectangular. After the laser process, the sheet resistance is reduced to 150 ohm / sq or less, the junction depth of the diffused second emitter is 0.7 μm or more, and the surface doping concentration is 1×10 19 cm -3 decreases to.

[0050] The surface of the silicon wafer is wet chemically cleaned to remove the front BSG layer, the laser damage layer, and the back mask.

[0051] A second passivation anti-reflective coating is formed by depositing aluminum oxide to a thickness of 2 to 20 nm on the front surface of the silicon wafer using the ALD method, and then depositing one or a combination of silicon oxynitride and silicon oxide to a thickness of 50 to 200 nm on the front surface using the PECVD method.

[0052] A first passivation anti-reflection film is formed by depositing one or a combination of at least two of silicon oxynitride and silicon oxide to a thickness of 30 to 200 nm on the back surface of the silicon wafer by PECVD.

[0053] Finger electrodes and busbar electrodes are printed on the back surface by screen printing, and finger electrodes are printed on the front surface by screen printing above the second emitter in the laser processing area. The width of the front electrode is less than 50 μm. After that, high-temperature sintering is performed to form an ohmic contact between the metal electrode and the emitter electrode.

[0054] FIG. 3 shows the ECV doping curves of the first emitter layer and the second emitter region of the solar cell obtained in Example 1 (in FIG. 3, the first emitter layer shows the ECV doping curve of the first emitter layer, and the second emitter region shows the ECV doping curve of the second emitter region), where the first emitter layer has a steep diffusion junction type and the second emitter region has a more gradual doping junction type.

[0055] Compared with the solar cell manufactured in Example 1 of CN110299422A, the solar cell obtained in Example 1 of the present application has a shallower first emitter depth, a junction depth of less than 0.7 μm, a better short-wave response of the cell, and a higher short-circuit current density of 40.3 mA / cm 2 to 40.6mA / cm 2 improved to.

[0056] Compared with the solar cell manufactured in Example 1 of CN110299422A, the depth of the second emitter after laser doping of the solar cell obtained in Example 1 of the present application is deeper than 0.7 μm, and the electrode contact resistance is lower, 1.5 ohm / cm 2 to 0.9 ohm / cm 2 It dropped to.

[0057] In the description of this application, the orientations or positional relationships indicated by terms such as "upper," "lower," "inner," "outer," "front," "rear," "left," "right," etc. are based on the orientations or positional relationships in the operating state of this application and are intended merely to simplify the description and explanation of this application, and do not indicate or imply that the referenced devices or parts must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as limitations on this application.

[0058] The above describes a preferred embodiment of the present invention, but the present invention is not limited to the above embodiment and can be implemented in various modifications within the scope of the gist of the present invention.

Claims

1. A method for manufacturing a solar cell, comprising: providing an N-type silicon substrate; depositing a tunnel passivation structure on a first surface of the N-type silicon substrate and depositing a mask layer on the tunnel passivation structure; cleaning the second surface of the N-type silicon substrate; performing a boron diffusion process on the second surface of the N-type silicon substrate after cleaning, thereby forming a first emitter layer on the second surface of the N-type silicon substrate, and simultaneously crystallizing the tunnel passivation structure at a temperature of the boron diffusion process; performing a laser patterning process on the first emitter layer to promote boron diffusion in the laser-irradiated region to form a second emitter region; depositing a passivation anti-reflective coating on both sides of the N-type silicon substrate; forming a first electrode disposed in electrical contact with the second emitter region and a second electrode disposed in electrical contact with the tunnel passivation structure; The temperature of the boron diffusion treatment is 300 to 970°C, and the treatment time at 800 to 970°C is less than 3 hours; a junction depth of the first emitter layer is smaller than a junction depth of the second emitter region; a maximum boron doping concentration of the first emitter layer is greater than a maximum boron doping concentration of the second emitter region, and a total boron doping amount of the first emitter layer is less than a total boron doping amount of the second emitter region; the first emitter layer has a curve showing the relationship between the boron doping concentration and the depth, in which the difference between the maximum boron doping concentration and the minimum doping concentration in a depth range of 0.02 to 0.6 μm from the surface of the first emitter layer is greater than one order of magnitude; In the second emitter region, the difference between the maximum boron doping concentration and the minimum boron doping concentration in a depth range of 0.05 to 0.7 μm from the surface of the second emitter region on a curve showing the relationship between the boron doping concentration and the depth is less than one order of magnitude. How solar cells are manufactured.

2. The tunnel passivation structure includes a tunnel oxide layer and a passivation contact material layer, and the tunnel oxide layer is disposed between the N-type silicon substrate and the passivation contact material layer. The method for manufacturing the solar cell according to claim 1 .

3. The passivation contact material layer is made of one or more of the following materials: doped amorphous silicon, doped polycrystalline silicon, and silicon carbide. The method for manufacturing a solar cell according to claim 2 .

4. The second electrode is disposed in electrical contact with the passivation contact material layer. The method for producing a solar cell according to claim 2 or 3.

5. the junction depth of the first emitter layer is 0.7 μm or less; The junction depth of the second emitter region is 0.8 μm or more. The method for manufacturing the solar cell according to claim 1 .

6. The maximum point on the curve showing the relationship between the boron doping concentration and the depth of the first emitter layer is at an internal position at a depth of 0.05 to 0.5 μm from the surface of the first emitter layer. The method for manufacturing the solar cell according to claim 1 .

7. The sheet resistance of the first emitter layer is 150 ohm / sq or more, and the sheet resistance of the second emitter region is 150 ohm / sq or less. The method for manufacturing the solar cell according to claim 1 .

8. The width of the first electrode is smaller than the width of the second emitter region. The method for manufacturing the solar cell according to claim 1 .

9. Before depositing the passivation anti-reflective coating, cleaning is performed. The method for manufacturing the solar cell according to claim 1 .

10. The material of the passivation anti-reflection film is one or a combination of two or more selected from aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. The method for manufacturing the solar cell according to claim 1 .

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