Flying capacitor multilevel rectifier and control method thereof

Abstract

To provide a flying capacitor multi-level (FCML) rectifier and control methods thereof.SOLUTION: A FCML rectifier operates with an input voltage (Vin) and includes an inductor (L), a plurality of upper switches (S1'...SN'), and a plurality of lower switches (S1...SN). The upper and lower switches are electrically connected in series. The inductor is coupled between the input voltage and a midpoint between the upper switches and the lower switches. At a critical transition point, at least one of first and second modulation schemes is performed. In the first modulation scheme, a rising edge of the control signal of any one lower switch is controlled to be synchronous with a rising edge of the control signal of at least one another lower switch for achieving zero voltage switching (ZVS). In the second modulation scheme, a phase-shift of the control signals and a switching frequency are controlled to achieve ZVS of the switch with minimum conduction loss.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a flying capacitor multilevel (FCML) rectifier and a control method thereof, and more particularly to an FCML rectifier that can achieve ZVS (zero voltage switching) of switches over the entire operating range and a control method thereof. [Background technology]

[0002] As the switching frequency of AC-DC power converters increases to reduce the size of passive components such as boost inductors and EMI (electromagnetic interference) filters, the need to achieve soft switching in today's high-performance power supplies is becoming more and more pressing. For example, see the following articles: (i) "Z. Liu, F.C. Lee, Q. Li and Y. Yang, 'Design of GaN-Based MHz Totem-Pole PFC Rectifier,' in IEEE Journal of Emerging and Selected Topics in Power Electronics."

[0003] Figure 1A shows a conventional PFC (power factor correction) boost rectifier operating in either triangular or critical conduction mode. Figure 1B shows a schematic of the inductor current of the PFC boost rectifier of Figure 1A in critical conduction mode. Figure 1C shows the operating waveforms of the switching node voltage and inductor current of the PFC boost rectifier of Figure 1A at 50 Hz or 60 Hz line frequency operation. This modulation mode allows the input current to be automatically shaped without active control, while ensuring zero-voltage turn-on of all semiconductors by using valley current switching. Of course, this modulation also allows the switching frequency to be variable over the line cycle, as shown in Figure 1D.

[0004] A useful method for reducing the voltage stress on the device and simultaneously increasing the effective frequency of the boost inductor is to use a multilevel converter circuit. See, for example, the following articles: (i) "TA Meynard and H. Foch, 'Multi-level conversion: high voltage choppers and voltage-source inverters,' PESC '92 Record. 23rd Annual IEEE Power Electronics Specialists Conference"; (ii) "Q. Huang, Q. Ma, P. Liu, AQ Huang and MA de Rooij, '99% Efficient 2.5-kW Four-Level Flying Capacitor Multilevel GaN Totem-Pole PFC,' in IEEE Journal of Emerging and Selected Topics in Power Electronics." Multilevel circuits allow the use of lower-voltage-rated semiconductor devices, which often offer superior performance and cost compared to higher-voltage-rated semiconductor devices. These circuits also increase the effective frequency of passive components compared to standard two-level circuits, aiding in the miniaturization of passive components. However, achieving ZVS in multilevel circuits has not been widely explored and requires further consideration. Of particular interest are FCML converters, which utilize relatively small ceramic capacitors to clamp the voltage between semiconductor devices. Figure 2A shows an example of a three-level FCML boost converter. In this converter, the two inner switches, S1 and S1′, are gated in a complementary manner, while the two outer switches, S2 and S2′, are similarly gated using time-multiplexed gate signals. As shown by the example gate pulses in Figure 2B, the rising edge of switch S1 is 180° out of phase with the rising edge of switch S2, and both rising edges have the same duty cycle, governed by the input-output voltage relationship of the boost converter, as shown in Equation (1).

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[0005] This phase-shift modulation scheme, as shown in Figure 2C, results in balanced flying capacitor voltages and reduced switching node dv / dt, making it very widely adopted in FCML converters. By using this modulation scheme, the steady-state value of the flying capacitor voltage is V Bus / 2, and the blocking voltage of each device is V Bus This modulation scheme also results in an inductor's effective switching frequency that is twice the device's switching frequency, as shown in Figure 2B.

[0006] However, as shown in "ME Blackwell, A. Stillwell and R.C.N. Pilawa-Podgurski, "Dynamic Level Selection for Full Range ZVS in Flying Capacitor Multi-Level Converters," 2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL), 2018," ZVS becomes difficult to achieve in FCML converters with phase-shifted gating signals because the inductor current ripple collapses at certain operating duty cycles, as shown in the line-cycle operation of Figure 3. The inductor current ripple is a function of v in (t)=V Bus Note that the switching node voltage waveform becomes zero at the operating point where ≈ 1 / 2. These operating points are highlighted and enlarged for clarity in Figure 3. The root cause of the inductor current ripple collapse is evident from the enlarged switching node voltage waveform.

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[0007] This phenomenon is further demonstrated in Figure 4 for 3- to 6-level FCML converters. It is very clear to observe that in such multilevel converters operating with standard phase-shift modulation, the normalized inductor current ripple becomes zero at certain duty cycles. Generally, in an FCML converter, the inductor ripple current becomes zero when the input voltage of the boost stage is equal to one of the flying-capacitor voltages. Because a PFC boost converter requires the duty cycle to vary from 0 to 1, these operating points where the inductor current effective ripple is zero occur more frequently in higher-level FCML boost converters.

[0008] Achieving ZVS in FCML converters without sacrificing their promising features, such as reduced voltage stress and low dv / dt over most of the operating range, is addressed in "ME Blackwell, A. Stillwell, and R.C.N. Pilawa-Podgurski, "Dynamic Level Selection for Full-Range ZVS in Flying Capacitor Multi-Level Converters," 2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL), 2018. However, the specified modulation scheme requires the flying capacitor voltage to be rebalanced to another value, resulting in undesirable transients in the converter's operation. In PFC converters, these transients occur every line cycle, significantly complicating converter operation.

[0009] Therefore, there is a need to provide a flying capacitor multilevel rectifier and a control method thereof that overcomes the drawbacks arising from the prior art. Summary of the Invention

[0010] An object of the present invention is to provide an FCML rectifier and a control method thereof that can achieve ZVS of the switches over the entire operating range.

[0011] According to one aspect of the present disclosure, there is provided an FCML rectifier configured to operate with an input voltage. The FCML rectifier includes a switching converter stage and a control circuit. The switching converter stage has an input terminal and first and second phase terminals, and includes an inductor, N upper switches, N lower switches, N-1 flying capacitors, and an output capacitor, where N is an integer greater than or equal to 1. The inductor is coupled to the input voltage and the input terminal. The N upper switches are electrically connected in series between the input terminal and the first phase terminal and operate at the same duty cycle. First and Nth upper switches are coupled to the input terminal and the first phase terminal, respectively. The N lower switches are electrically connected in series between the input terminal and the second phase terminal and operate in a complementary manner to the N upper switches. The first and Nth lower switches are coupled to the input terminal and the second phase terminal, respectively. The nth flying capacitor is coupled between a common node between the nth upper switch and the (n+1)th upper switch and a common node between the nth lower switch and the (n+1)th lower switch, where n is a positive integer less than N. The control circuit is configured to provide control signals to operate the N upper switches and the N lower switches. During a critical turning point, the control circuit is adapted to perform at least one of first and second modulation schemes. In the first modulation scheme, the control circuit controls a rising edge of a control signal for any one of the N lower switches to be synchronized with a rising edge of a control signal for at least one other of the N lower switches to achieve ZVS of the switches. In the second modulation scheme, the control circuit controls a phase shift between the rising edge of the control signal for the N lower switches and a switching frequency of the switches to achieve ZVS of the switches with minimal conduction loss.

[0012] According to another aspect of the present disclosure, there is provided a control method for the FCML rectifier of the present disclosure. The control method includes executing at least one of first and second modulation schemes during a critical turning point. When the first modulation scheme is executed, a rising edge of a control signal for any one of the N lower switches is controlled to be synchronized with a rising edge of a control signal for at least one other of the N lower switches to achieve ZVS of the switch. When the second modulation scheme is executed, a phase shift between the rising edges of the control signals for the N lower switches and the switching frequencies of the switches are controlled to achieve ZVS of the switch with minimal conduction loss. [Brief explanation of the drawings]

[0013] [Figure 1A] FIG. 1A shows a conventional PFC boost rectifier.

[0014] [Figure 1B] FIG. 1B shows a schematic diagram of the inductor current of the PFC boost rectifier of FIG. 1A under critical conduction mode.

[0015] [Figure 1C] FIG. 1C shows schematic operating waveforms of the switching node voltage and inductor current of the PFC boost rectifier of FIG. 1A.

[0016] [Figure 1D] FIG. 1D shows the variation of the switching frequency of the PFC boost rectifier of FIG. 1A over a line cycle.

[0017] [Figure 2A] FIG. 2A shows a conventional three-level FCML boost converter.

[0018] [Figure 2B-C] 2B and 2C show schematic operating waveforms of the three-level FCML boost converter of FIG. 2A.

[0019] [Figure 3] Figure 3 shows the waveforms of the switching node voltage and inductor current for a complete line cycle of a conventional three-level FCML boost converter.

[0020] [Figure 4] Figure 4 shows the normalized current ripple of the boost inductor over the entire range of duty cycles in a 2-6 level FCML PFC converter employing a conventional phase-shift modulation scheme.

[0021] [Figure 5] FIG. 5 is a schematic circuit diagram illustrating an FCML rectifier according to one embodiment of the present disclosure.

[0022] [Figure 6A-B] FIG. 6A shows a schematic diagram of a conventional modulation scheme for an FCML rectifier at the critical turning point.

[0023] FIG. 6B schematically illustrates a first modulation scheme of an FCML rectifier at a critical turning point, according to one embodiment of the present disclosure.

[0024] [Figure 7A-B] FIG. 7A shows a schematic diagram of the switching node voltage and inductor current waveforms when using the conventional modulation scheme of FIG. 6A at the critical turning point.

[0025] FIG. 7B schematically illustrates waveforms of the switching node voltage and inductor current while using the first modulation scheme of FIG. 6B at a critical turning point.

[0026] [Figure 8] Figure 8 shows the waveforms of the switching node voltage and inductor current over a full line cycle when using the first modulation scheme with redundant states at the critical turning points of the three-level FCML rectifier.

[0027] [Figure 9A-B]FIG. 9A shows a four-level FCML rectifier.

[0028] FIG. 9B shows a schematic representation of the input voltage of the four-level FCML rectifier of FIG. 9A over a full line cycle.

[0029] [Figure 10A-C] 10A, 10B, and 10C schematically illustrate a conventional modulation scheme and two variations of the first modulation scheme of the present disclosure utilizing redundant states of a four-level FCML rectifier at the critical turning point of vin(t)=2VBus / 3.

[0030] [Figure 10D-F] 10D, 10E, and 10F schematically illustrate a conventional modulation scheme and two variations of the first modulation scheme of the present disclosure utilizing redundant states of a four-level FCML rectifier at the critical turning point of vin(t)=VBus / 3;

[0031] [Figures 11A-F] 11A, 11B, 11C, 11D, 11E and 11F show schematic diagrams of the sequence of switching states of a four-level FCML rectifier operating near vin=2VBus / 3.

[0032] [Figure 12A] FIG. 12A shows the waveform of the inductor current over a full line cycle when using the first modulation scheme with redundant states at the critical turning points of a three-level FCML rectifier.

[0033] [Figure 12B-D] 12B, 12C and 12D schematically illustrate the conventional modulation scheme and the first and second modulation schemes of the present disclosure for a three-level FCML rectifier at the critical turning point.

[0034] [Figure 13A]FIG. 13A shows the waveforms of the switching node voltage and inductor current of a three-level FCML rectifier at a critical turning point according to the first modulation scheme of the present disclosure.

[0035] [Figure 13B] FIG. 13B shows the waveforms of the switching node voltage and inductor current of a three-level FCML rectifier at the critical turning point according to the second modulation scheme of the present disclosure.

[0036] [Figure 13C] FIG. 13C shows the waveforms of the switching node voltage and inductor current over a full line cycle when using the second modulation scheme at the critical turning point of the three-level FCML rectifier.

[0037] [Figure 14] FIG. 14 shows a schematic diagram of one implementation of the second modulation scheme proposed in FIG. 12D.

[0038] [Figure 15A-B] 15A and 15B show the same critical turning points to achieve boundary conduction mode operation with similar inductor current ripple for two different choices of control variables DΦ and fs for the rectifier with D>0.5.

[0039] [Figure 15C-D] 15C and 15D show the same critical turning points to achieve boundary conduction mode operation with similar inductor current ripple for two different choices of control variables DΦ and fs for the rectifier with D<0.5.

[0040] [Figure 16] FIG. 16 shows an example control strategy that uses a phase shift variable DΦ in conjunction with the switching frequency fs to make the actual current ripple equal to the desired current ripple.

[0041] [Figure 17]Figure 17 shows the waveforms of the inductor current and switching node voltage along the control variable DΦ.

[0042] [Figure 18A-B] 18A and 18B show transition waveforms between two-level switching and three-level switching by using a phase shift variable DΦ in the modulation scheme of FIG. 12D.

[0043] [Figure 19] Figure 19 shows the waveforms of the switching node voltage and inductor current over a full line cycle when using a conventional modulation scheme at the critical turning points of a four-level FCML rectifier.

[0044] [Figure 20A-B] 20A and 20B show the waveforms of the switching node voltage and inductor current over a full line cycle when using two variants of the first modulation scheme with redundant states at the critical turning points of a four-level FCML rectifier.

[0045] [Figure 21] Figure 21 shows the waveforms of the switching node voltage and inductor current over a full line cycle when using the second modulation scheme at the critical turning point of the four-level FCML rectifier.

[0046] [Figure 22] FIG. 22 illustrates the variation of switching frequency over a line cycle for the four-level FCML rectifier of FIG. 9A in one embodiment.

[0047] [Figure 23] FIG. 23 illustrates a schematic diagram of a three-phase N-level FCML rectifier according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0048] The present invention will now be described more specifically with reference to the following embodiments. It should be noted that the following description of preferred embodiments of the present invention is presented herein for purposes of illustration and description only and is not intended to be exhaustive or limited to the precise form disclosed. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact with each other, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations being discussed. Furthermore, spatially relative terms such as "below," "belower," "lower," "upper," "upper," etc. may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. When an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or intervening elements may be present. While the broad ranges and parameters of the present disclosure are approximations, the numerical values ​​are described as precisely as possible in the specific examples. Furthermore, it will be understood that terms such as "first," "second," and "third" in the claims are used to describe various elements, but these elements should not be limited by these terms; although these elements may be represented by different reference numerals in each embodiment, these terms are merely used to distinguish one element from another.For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the exemplary embodiments. Furthermore, terms such as "and / or" can be used herein to include any or all combinations of one or more of the associated listed items. While the numerical ranges and parameters set forth regarding the broad scope of the invention are approximations, the numerical values ​​reported in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain errors, necessarily resulting in standard deviations found in their respective testing measurements. Additionally, as used herein, the term "about" generally means away from a given value or a range of 10%, 5%, 1%, or 0.5%. Alternatively, the term "about" means within the acceptable standard error of an average recognized in the art. In all cases, all numerical ranges, amounts, values, and percentages, such as numbers, durations, temperatures, operating conditions, and ratios of amounts of materials disclosed herein, should be understood as modified by the term "about." Accordingly, unless otherwise indicated, the numerical parameters of the invention and proposed claims should be subject to desirable variances to approximations. At the very least, the number of significant digits for each numerical parameter should be reported and accounted for by applying conventional rounding techniques. Ranges may be expressed herein as from one endpoint to the other endpoint, or to both endpoints. Unless otherwise specified, all ranges disclosed herein are inclusive.

[0049] 5 is a schematic circuit diagram illustrating an FCML rectifier according to one embodiment of the present invention. As shown in FIG. 5, the FCML rectifier operates by converting an input voltage V in The FCML rectifier is configured to operate at a frequency of 1000 kHz, and includes a switching converter stage and a control circuit (not shown). The switching converter stage has an input terminal, a first phase terminal, and a second phase terminal. N ' inductor L, N upper switches S1'...S N ′, N lower switches S1...S N, N-1 flying capacitors C1...C N-1 , and the output capacitor C out where N is an integer greater than 1. The FCML rectifier shown in Figure 5 is an (N+1) level rectifier. The inductor L is connected to the input voltage V in and the input terminal. N upper switches S1′...S N The first upper switch S1′ and the Nth upper switch S2′ are electrically connected in series between the input terminal and the first phase terminal. N The N upper switches S1'...S' are coupled to the input terminal and the first phase terminal, respectively. N The N lower switches S1...S' operate with the same duty cycle. N are electrically connected in series between the input terminal and the second phase terminal, and include a first lower switch S1 and an Nth lower switch S2. N are respectively coupled to the input terminal and the second phase terminal. N are the N upper switches S1′...S N The nth flying capacitor C n is the nth and (n+1)th upper switches S n ′ and S n+1 ' and the common node between the nth and (n+1)th lower switches S n and S n+1 where n is a positive integer less than N. The output capacitor C out are electrically connected between the first and second phase terminals. The control circuit controls the N upper switches S1′...S N ′ and N lower switches S1...S N During the critical turning point, the control circuit is configured to perform at least one of a first and a second modulation scheme. In the first modulation scheme, the control circuit controls the N lower switches S1...S to achieve ZVS of the switches. N The rising edge of the control signal of any one of the N lower switches S1...S NIn the second modulation scheme, the control circuit controls the phase shift and switching frequency of the switches to achieve zero voltage switching (ZVS) with minimal conduction losses. The first and second modulation schemes are described in detail below.

[0050] Taking the FCML rectifier in FIG. 5 where N is 2 as an example, FIG. 6A schematically illustrates a conventional modulation scheme of the FCML rectifier at the critical turning point, and FIG. 6B schematically illustrates a first modulation scheme of the FCML rectifier at the critical turning point according to one embodiment of the present disclosure. in (t)=V Bus To avoid the problems associated with the loss of ZVS at √Hz (near √Hz / 2), a new modulation scheme is introduced in Figure 6B. In the first modulation scheme shown in Figure 6B, the phase shift between the rising edges of the control signals for the lower switches S1 and S2 is reduced from 180° to zero, which reduces the switching node voltage V sw is 0 and V Bus and the switch is now switching redundantly. Note that the duty cycle of the switch is still determined by the step-up relationship between the input and output voltages, but as a result of using the redundant switching states, much larger volt-seconds are applied across inductor L. Note also that the frequency multiplication effect on inductor L is no longer maintained. With the redundant switching states, the ripple frequency of inductor L becomes the same as the switching frequency of the switch. However, in this embodiment, this modulation scheme is only used for a narrow range of the line cycle, so this modulation scheme reduces the inductor current i L This makes the voltage Vcc negative, which helps achieve ZVS across the critical turning point of the FCML rectifier. An important difference between the conventional modulation scheme and the first modulation scheme proposed in this embodiment is shown in Figures 6A and 6B.

[0051] Figure 7A shows the waveforms of the switching node voltage and inductor current during the critical turning point when using the conventional modulation scheme of Figure 6A. Figure 7B shows the waveforms of the switching node voltage and inductor current during the critical turning point when using the first modulation scheme of Figure 6B. As shown in Figures 7A and 7B, it is clear how an increase in the voltage at the switching node increases the inductor current ripple. Also, note that because the voltage applied to inductor L increases, the inductor ripple is relatively high compared to conventional modulation, even though the switching frequency of the switch is much higher. However, because ZVS is achieved, the losses due to high-frequency switching can be kept relatively small.

[0052] FIG. 8 shows waveforms of the switching node voltage and inductor current over an entire line cycle when using the first modulation scheme with redundant states during the critical turning point of one embodiment of a three-level FCML rectifier. Note that, in stark contrast to FIG. 3, in this embodiment, the inductor current always touches negative values, essentially enabling ZVS of the switch throughout the entire line cycle. These waveforms are obtained using the same power stage inductance values ​​as those used in FIG. 3. However, at the same time, near the critical turning point, the inductor current ripple is significantly higher than necessary to achieve ZVS. This excess current ripple is a result of the limited number of switching states (and redundant states) available in the three-level FCML rectifier. For higher-level converters, other switching states can be intelligently utilized to reduce the excess current ripple in inductor L.

[0053] As an example of more available switching states, FIG. 9A shows a four-level FCML rectifier (i.e., the FCML rectifier of FIG. 5 with N=3). FIG. 9B shows a schematic of the input voltage of the four-level FCML rectifier over a line cycle. As shown in FIG. 9B, the four-level FCML rectifier operates at a voltage of v in (t)=V Bus / 3 and v in(t)=2V Bus However, since the four-level circuit has more switching states available than the three-level circuit, the additional switching states can be intelligently utilized to reduce the inductor current ripple to the value required to enable ZVS of the switches.

[0054] An example switching waveform is shown below: in (t)=2V Bus 10A to 10C show the results for the vicinity of / 3. in (t)=V Bus 10D-10F for the vicinity of / 3. Proposed Modulation Scheme 1 in FIGS. 10B and 10E and Proposed Modulation Scheme 2 in FIGS. 10C and 10F are different variations of the first modulation scheme of the present disclosure. Proposed Modulation Scheme 1, in both cases (FIGS. 10B and 10E), Bus ) shows a scenario where redundant switching states are used to combine input voltages. To keep the effective frequency of the current ripple in inductor L the same, this modulation requires a device switching frequency of 3f0, where f0 is the switching frequency of the switches in the standard conventional modulation scheme shown in Figures 10A and 10D. However, Figures 10C and 10F show the proposed modulation scheme 2, where redundant states in the immediate vicinity of the average voltage that needs to be combined at the switching node are used to reduce the inductor current ripple. These redundant states (v in (t)=2V Bus / 3 is (V Bus / 3,V Bus ), v in (t)=V Bus / 3 is (0,2V BusUtilizing a modulation scheme (modulation scheme 2) not only provides a reduced switching frequency of the switches (here, 2f0), but also helps reduce the inductor current ripple compared to proposed modulation scheme 1. Furthermore, the use of appropriate redundant states also limits the dv / dt at the switching nodes, thereby improving EMI performance compared to modulation schemes using other switching states. As a result, proposed modulation scheme 2 enables ZVS of the switches while simultaneously reducing the additional inductor current ripple at the critical turning point.

[0055] In one embodiment, in the first modulation scheme, the switching node voltages across the N bottom switches are n*V Bus The inverter may switch between a first voltage and a second voltage during a critical turning point near an input voltage equal to 0 / N, where the first voltage is between 0 and n*V Bus / N, and the second voltage is n*V Bus / N and V Bus For example, the first voltage is (n-1)*V Bus / N and the second voltage is (n+1)*V Bus / N may also be used.

[0056] The switching combinations used to synthesize the switching states should be carefully selected to maintain charge balance on the flying capacitors. As shown in Figures 11A-11F, v in =2V Bus For a four-level FCML rectifier operating near V / 3 (i.e., the FCML rectifier of FIG. 5 where N is 3), in this embodiment, the correct sequence of switching states should ensure both charging and discharging of the flying capacitors in a switching cycle to facilitate voltage balancing. Figures 11A-11F show the v, ... sw =V Bus / 3 and v sw =V BusThe switching cycle begins in Figure 11A with switches S1, S2, and S3' on. This causes the voltage at the switching node to rise to V Bus The direction of current flow is shown in the figure. During this time, flying capacitor C2 is discharged. In Figure 11B, the voltage of the switching node is V Bus To achieve this, all the upper switches S1', S2', and S3' are turned on. In this state, both flying capacitors C1 and C2 are inactive. Both switch pairs S1, S1' and S2, S2' change state during this time. Next, Figure 11C shows the next switching state where switch pairs S2, S2' and S3, S3' change state. During this state, flying capacitor C1 is charged according to the current flow direction and the applied switching node voltage is V Bus During the next state shown in Figure 11D, all the top switches S1', S2', S3' are again turned on by commutating switch pairs S2, S2' and S3, S3'. The applied switching node voltage is V Bus In Figure 11E, the switch pairs S1, S1' and S3, S3' are commutated, and the switching node voltages are V Bus / 3. In this state, the current paths show that flying capacitor C1 is discharged and flying capacitor C2 is charged. Finally, the switching cycle is completed with the commutation of switch pairs S1, S1' and S3, S3', as shown in Figure 11F. During this period, the applied switching node voltages are again V Bus Thus, neither flying capacitor C1 nor C2 is charged or discharged. After this, the FCML rectifier returns to the state shown in FIG. 11A by commutating the switch pairs S1, S1′ and S2, S2′.

[0057] FIG. 12A further highlights the problem with the first modulation scheme proposed for a three-level FCML rectifier (i.e., the FCML rectifier of FIG. 5 where N is 2). For one embodiment of a three-level FCML rectifier, the available states of the switching node voltage are 0, V Bus / 2, and V Bus As can be seen in the switching waveforms during the line cycle, the first proposed modulation scheme using redundant switching states is v in (t)=V Bus When active near √√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√√ Φ T s =Φ / (360°)T s where Φ is the phase shift. The current ripple of the inductor L (i.e., the inductor current ripple) is expressed by the variable D Φ and switching frequency f s =1 / T s D ≤ 0.5 and D ≥ D Φ If: it is controllable using

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[0058] The duty cycle D is still the output voltage control (i.e., D=1-v in (t) / V Bus ) and the required inductor current ripple Δi L is approximately twice the average inductor current (Δi L =2〈i L 〉). Using equations (2) and (3), the phase shift Φ and switching frequency f s can be optimally selected together to achieve the goal of achieving ZVS while simultaneously reducing additional conduction losses in the system. This modulation scheme is shown as minimum RMS current modulation in Figure 12D, and is the second modulation scheme of the present disclosure mentioned above.

[0059] Figure 13A shows the D Φ =0, f s =f s、max FIG. 13B shows the enlarged waveforms near the critical turning point under the first modulation scheme with D to achieve ZVS with minimum conduction losses (i.e., minimum RMS current stress). Φ and f s 13C shows an enlarged waveform near the critical turning point under a second modulation scheme where v is selected. An exemplary line periodic waveform illustrating this second modulation scheme (i.e., minimum RMS current modulation) for a three-level FCML rectifier is shown in FIG. 13C. In contrast to FIG. 12A, v in (t)=V Bus It is clearly observed that during the critical turning point at / 2, the inductor current ripple remains high enough to allow boundary conduction mode operation.

[0060] In this embodiment, the flying capacitor voltage is V BusTo ensure that the quiescent current remains at / 2, period doubling modulation must be enabled as shown in Figure 14. Note how the control signals for switches S1 and S2 switch over two consecutive switching periods. In the first period, switch S1 is gated before switch S2, and in the second period, switch S2 is gated before switch S1. This strategy helps balance the voltages on the flying capacitors, as shown in the 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 2020.

[0061] D Φ and f s Note also that many possible combinations of D allow for the same inductor current ripple from equations (2) and (3). As an example, Figures 15A and 15B show the relationship between two different control variables D Φ and f s Figure 15C and Figure 15D show the same critical turning point to achieve boundary conduction mode operation with similar inductor current ripple for a choice of duty cycle D greater than 0.5. Φ and f s Two different combinations of f are used. The main difference in this case is that the duty cycle D is less than 0.5. In some embodiments, from these different operating options, the switching frequency and phase shift are selected based on practical considerations. For example, the switching frequency f s must have a maximum limit, and abrupt changes in phase shift must also be avoided to mitigate undesirable transients in the flying capacitor voltage and inductor current.

[0062] Figure 16 shows the phase shift variable D Φ and switching frequency f s, which makes the second modulation scheme optimal in terms of effective current stress and achieving ZVS. Φ But, v in (t)=V Bus Note how it changes linearly near the critical turning point at / 2. Φ For a linear profile of , the switching frequency f s can be calculated using equation (2) or (3) depending on the duty cycle D.

[0063] It is important to note that in some embodiments, the flying capacitor voltage and inductor current do not exhibit abrupt transients resulting from this modulation scheme because the variables are changed smoothly. Also, in some embodiments, the switching frequency may always be clamped below some maximum allowable limit determined by the rectifier inductor design during the entire line cycle operation. This effect may result in higher than desired inductor current ripple, as seen in the actual current ripple profile.

[0064] In one embodiment, FIG. 17 illustrates how the switching waveforms (i.e., the waveforms of the inductor current and the switching node voltage) are controlled by the control variable D Φ 12D, implemented as shown in FIG. 16. FIG. 17 clearly shows how the inductor current ripple is successfully reduced to only the required amount by using the modulation scheme of FIG. 12D implemented as shown in FIG. 16. It can be observed that there is no significant overshoot in the inductor current when the second modulation scheme is employed to ensure ZVS. Overall, the inductor current appears smooth. The sharp contrast between this waveform and the one shown in FIG. 12A is highlighted, demonstrating how the effective current is controlled by using the proposed modulation scheme of this embodiment.

[0065] 18A and 18B show the phase shift variable D in the proposed modulation scheme of the embodiment of FIG. 12D. ΦFigure 18 shows the transition waveforms between two-level and three-level switching using the second modulation scheme. In particular, Figure 18A shows a smooth transition from two-level switching to three-level switching, and Figure 18B shows a smooth transition back from three-level switching to two-level switching. These transitions are important to enable the FCML rectifier to achieve ZVS using the second modulation scheme without causing abrupt changes in the capacitor voltage or inductor current. Both transitions appear normal and do not cause any undesirable effects on the inductor current or capacitor voltage.

[0066] The proposed modulation scheme of the present disclosure can be extended to an M-phase N-level FCML rectifier. As an example, first, FIG. 19 shows the waveforms of the switching node voltage and inductor current over an entire line cycle when using a conventional modulation scheme during the critical turning points of a four-level FCML rectifier. As shown in FIG. 9A, since there are two flying capacitors in this circuit, it is easy to observe that there are four critical points in the line cycle. Using the first modulation scheme of the present disclosure, ZVS of all switches can be achieved. However, since more states are available in a four-level FCML rectifier, there are two possible approaches to the first modulation scheme to achieve ZVS. FIG. 20A shows the waveforms of the maximum and minimum voltages, i.e., (0, V), during the critical turning points. Bus) is applied to the switching node, which results in additional current, as shown in Figures 10B and 10E. A second strategy of reducing the voltage swing, as shown in Figures 10C and 10F, can reduce the current peaks, as shown in Figure 20B. Finally, Figure 21 shows the waveforms of the switching node voltage and inductor current over an entire line cycle when using the second modulation scheme during the critical turning point of a four-level FCML rectifier. As previously discussed for the three-level converter, many possible combinations of phase shift and frequency can be used to achieve the desired ripple current. An example frequency profile is shown in Figure 22. This frequency profile, combined with the controlled phase shift between the gate signals of the four-level FCML rectifier shown in Figure 9A, results in seamless ZVS with minimal circulating current throughout the entire line cycle, as shown in Figure 21.

[0067] In the case of an M-phase, N-level FCML rectifier, the FCML rectifier operates with M input voltages of M phases, respectively. Furthermore, the FCML rectifier includes M switching converter stages coupled to the M input voltages, each of which is coupled to a corresponding input voltage via its inductor L. FIG. 23 schematically illustrates a three-phase, N-level FCML rectifier according to one embodiment of the present disclosure. In the embodiment illustrated in FIG. 23, the FCML rectifier operates with three input voltages V AN , V BN , and V CN The proposed modulation scheme of this disclosure allows for ZVS to be maintained throughout the entire line cycle with minimal circulating current.

[0068] From the above, the present invention provides an FCML rectifier and a control method thereof that can achieve ZVS of the switches over the entire operating range. According to a first modulation scheme of the present disclosure, ZVS is achieved by simply adjusting the phase shift between the rising edges of the control signals of the switches. According to a second modulation scheme of the present disclosure, the phase shift and switching frequency of the switches are jointly selected to achieve ZVS and simultaneously reduce additional conduction losses.

[0069] While the present invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiments.

Claims

1. 1. A flying capacitor multilevel rectifier configured to operate with an input voltage, comprising: a switching converter stage having an input terminal and first and second phase terminals; a control circuit configured to provide control signals to operate the N upper switches and the N lower switches; The switching converter stage comprises: an inductor coupled to the input voltage and the input terminal; the N upper switches electrically connected in series between the input terminal and the first phase terminal and configured to operate at the same duty cycle, wherein a first and an Nth upper switch are coupled to the input terminal and the first phase terminal, respectively, and N is an integer greater than 1; the N lower switches being electrically connected in series between the input terminal and the second phase terminal, and configured to operate complementarily with the N upper switches, with first and Nth lower switches being coupled to the input terminal and the second phase terminal, respectively; N-1 flying capacitors, where the nth flying capacitor is coupled between a common node between the nth upper switch and the (n+1)th upper switch and a common node between the nth lower switch and the (n+1)th lower switch, where n is a positive integer less than N; an output capacitor electrically connected between the first phase terminal and the second phase terminal; and the control circuit is configured to switch to and execute one of the first and second control methods at a critical turning point of the boundary conduction mode; In the first control method, the control circuit controls a rising edge of a control signal of any one of the N lower switches to coincide with a rising edge of a control signal of at least one other of the N lower switches in order to achieve ZVS of the switches; In the second control method, the control circuit controls the phase shift between rising edges of the control signals of the N lower switches and the switching frequencies of the switches to achieve ZVS of the switches with minimum conduction loss.

2. 2. The flying capacitor multilevel rectifier of claim 1, wherein in the first control scheme, switching node voltages across the N lower switches switch between zero and a bus voltage of the flying capacitor multilevel rectifier during the critical turning point.

3. 2. The flying capacitor multilevel rectifier of claim 1, wherein in the first control scheme, n*V Ｂｕｓ During the critical turning point centered about the input voltage equal to V / N, switching node voltages across the N lower switches switch between a first voltage and a second voltage, where V Ｂｕｓ is the bus voltage of the flying capacitor multilevel rectifier, and the first voltage is between 0 and n*V Ｂｕｓ / N, and the second voltage is n*V Ｂｕｓ / N and V Ｂｕｓ Among them is the flying capacitor multilevel rectifier.

4. 2. The flying capacitor multilevel rectifier of claim 1, wherein in the first control scheme, n*V Ｂｕｓ During the critical turning point centered on the input voltage equal to (n-1)*V Ｂｕｓ / N and (n+1)*V Ｂｕｓ / N, where V Ｂｕｓ is the bus voltage of the flying capacitor multilevel rectifier.

5. 2. The flying capacitor multilevel rectifier of claim 1, wherein in the first control scheme, all switches are controlled by the control circuit to maintain ampere-second or charge balance of the N-1 flying capacitors.

6. 2. The flying capacitor multilevel rectifier of claim 1, wherein in the second control scheme, the control circuit controls the phase shift and the switching frequency to generate a current ripple in the inductor based on a bus voltage of the flying capacitor multilevel rectifier and voltages of the N-1 flying capacitors.

7. 2. The flying capacitor multilevel rectifier of claim 1, wherein in the second control scheme, the control circuit controls the phase shift and the switching frequency according to the input voltage and a bus voltage of the flying capacitor multilevel rectifier so as to make the inductor current ripple substantially equal to twice an average inductor current.

8. 8. The flying capacitor multilevel rectifier of claim 7, wherein in the second control scheme, the control circuit generates the phase shift by rotating rising and falling edges between two consecutive switching cycles to maintain charge balance on the N-1 flying capacitors.

9. 2. The flying capacitor multilevel rectifier of claim 1, comprising M switching converter stages operating with M input voltages of M phases, respectively, and coupled to the M input voltages via the inductors, where M is an integer greater than 1.

10. 1. A method for controlling a flying capacitor multilevel rectifier, comprising: the flying capacitor multilevel rectifier is configured to operate with an input voltage and includes a switching converter stage; the switching converter stage comprises an input terminal, a first phase terminal, a second phase terminal, an inductor, N upper switches, N lower switches, N−1 flying capacitors, and an output capacitor, where N is an integer greater than 1; the N upper switches are electrically connected in series between the input terminal and the first phase terminal and operate at the same duty cycle, and first and Nth upper switches are respectively coupled to the input terminal and the first phase terminal; the N lower switches are electrically connected in series between the input terminal and the second phase terminal and operate complementarily with the N upper switches, respectively, and first and Nth lower switches are coupled to the input terminal and the second phase terminal, respectively; an nth flying capacitor coupled between a common node between the nth upper switch and the (n+1)th upper switch and a common node between the nth lower switch and the (n+1)th lower switch, where n is a positive integer less than N; and the output capacitor electrically connected between the first phase terminal and the second phase terminal; The control method includes: a step of switching to and executing one of the first and second control methods at a critical turning point of the boundary conduction mode; When the first control method is executed, in order to achieve zero voltage stability of the switches, a rising edge of a control signal of any one of the N lower switches is controlled to coincide with a rising edge of a control signal of at least one other of the N lower switches; When the second control method is executed, the phase shift between rising edges of the control signals of the N lower switches and the switching frequencies of the switches are controlled to achieve ZVS of the switches with minimum conduction loss.

11. 11. The control method of claim 10, wherein when the first control strategy is executed, switching node voltages across the N lower switches switch between zero and a bus voltage of the flying capacitor multilevel rectifier during a critical turning point.

12. 11. The control method according to claim 10, wherein when the first control method is executed, n*V Ｂｕｓ During the critical turning point centered about the input voltage equal to V / N, switching node voltages across the N lower switches switch between a first voltage and a second voltage, where V Ｂｕｓ is the bus voltage of the flying capacitor multilevel rectifier, and the first voltage is between 0 and n*V Ｂｕｓ / N, and the second voltage is n*V Ｂｕｓ / N and V Ｂｕｓ A control method that is between.

13. 11. The control method according to claim 10, wherein when the first control method is executed, n*V Ｂｕｓ During the critical turning point centered around the input voltage equal to (n-1)*V Ｂｕｓ / N and (n+1)*V Ｂｕｓ / N, where V Ｂｕｓ is the bus voltage of the flying capacitor multilevel rectifier.

14. 11. The control method of claim 10, wherein when the first control scheme is executed, all switches are controlled to maintain ampere-second or charge balance of the N-1 flying capacitors.

15. 11. The control method according to claim 10, wherein when the second control scheme is executed, the phase shift and the switching frequency are controlled based on a bus voltage of the flying capacitor multilevel rectifier and voltages of the N-1 flying capacitors to generate a current ripple in the inductor.

16. 11. The control method of claim 10, wherein when the second control strategy is executed, the phase shift and the switching frequency are controlled in response to the input voltage and a bus voltage of the flying capacitor multilevel rectifier to make a current ripple in the inductor substantially equal to twice an average current of the inductor.

17. 17. The control method of claim 16, wherein when the second control scheme is executed, the phase shift is generated by rotating rising and falling edges between two consecutive switching cycles to maintain charge balance on the N-1 flying capacitors.

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