Dual Damascene Crossbar Array for Disabling Defective Resistive Switching Devices Within the Array

Abstract

A method for fabricating a dual damascene crossbar array is provided. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, the dual damascene structure including a top electrode layer and a first via, the first via being formed between the first memory device and the top electrode layer. Embodiments for the dual damascene crossbar and for disabling a memory device in the dual damascene crossbar are also provided.

Description

[Background technology]

[0001] The present invention relates generally to methods for fabricating semiconductor devices and the resulting structures, and more particularly to a dual damascene crossbar array structure constructed and arranged to disable defective resistive switching devices within the array.

[0002] Resistive random access memory (RRAM) is a nanoscale nonvolatile memory (NVM). RRAM offers simple storage cell components, high density, low power, high endurance, fast write, read, and erase speeds, and excellent scalability. A typical RRAM storage cell is a two-terminal device fabricated as a metal-insulator-metal (MIM) structure, also known as a resistive switching device (RSD) or cross-point device. The insulator can be a binary metal oxide, making MIM / RSD storage cells compatible with silicon-based complementary metal-oxide-semiconductor (CMOS) fabrication processes. When a sufficient electrical signal is applied between the metal electrodes of the MIM / RSD, the resistance value of the insulator can be switched from one resistance state to another. The insulator retains its current-carrying resistance state until it is changed by applying an appropriate electrical signal between the metal electrodes.

[0003] RRAM, along with logic circuits used to address, read, and write individual RRAM cells, can be implemented in arrays (e.g., RRAM cell arrays) that are compatible with a variety of electronic circuits and devices, including neuromorphic architectures. Multiple pre-neurons and post-neurons can be connected through an array of RRAM, naturally representing a fully connected neural network. Summary of the Invention

[0004] Embodiments of the present invention are directed to a method for fabricating a dual damascene crossbar array. A non-limiting example of the method includes forming a bottom electrode layer on a substrate, forming a first memory device on the bottom electrode layer, and forming a dual damascene structure on the first memory device, the dual damascene structure including a top electrode layer and a first via, the first via being formed between the first memory device and the top electrode layer.

[0005] Embodiments of the present invention are directed to a dual damascene crossbar array including one or more memory devices of the dual damascene crossbar array, a bottom electrode coupled to the one or more memory devices, one or more vias coupled to each memory device, and a top electrode layer coupled to the one or more vias, wherein the one or more vias are disposed between the memory devices and the top electrode layer.

[0006] An embodiment of the present invention is directed to a method for disabling memory devices in a dual damascene crossbar array. The method includes identifying a faulty memory device in the dual damascene crossbar array, the crossbar array including one or more memory devices in the dual damascene crossbar array, a bottom electrode coupled to the one or more memory devices, one or more vias coupled to each memory device, and a top electrode layer coupled to the one or more vias, the one or more vias being disposed between the memory devices and the top electrode layer. The method also includes disabling the faulty memory device in the dual damascene crossbar array and operating the remaining one or more memory devices in the dual damascene crossbar array.

[0007] Additional technical features and benefits will be realized through the practice of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, please refer to the detailed description and drawings.

[0008] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the conclusion of this specification. The foregoing and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 is a simplified block diagram illustrating a cross-sectional view of a two-terminal resistive switching device (RSD) that can be used as a storage cell of an RRAM structure that can incorporate embodiments of the present invention. [Figure 1B] FIG. 1B is an IV curve illustrating the switching behavior of the RSD component shown in FIG. 1A. [Figure 2] 1B is a simplified block diagram illustrating how the RSD components shown in FIG. 1A can be utilized as addressable RRAM cells in an RRAM crossbar array that can incorporate aspects of the present invention. [Figure 3] 1A-1C are cross-sectional views of a substrate / wafer after various fabrication operations on a semiconductor structure to form a crossbar array according to an embodiment of the present invention; [Figure 4] 1A-1C are cross-sectional views of a substrate / wafer after various fabrication operations on a semiconductor structure to form a crossbar array according to an embodiment of the present invention; [Figure 5] 1A-1C are cross-sectional views of a substrate / wafer after various fabrication operations on a semiconductor structure to form a crossbar array according to an embodiment of the present invention; [Figure 6] 1A-1C are cross-sectional views of a substrate / wafer after various fabrication operations on a semiconductor structure to form a crossbar array according to an embodiment of the present invention; [Figure 7]FIG. 1 illustrates an exemplary system coupled to a crossbar array in accordance with an embodiment of the present invention. [Figure 8] FIG. 1 is a first diagram of a system according to an embodiment of the present invention. [Figure 9] FIG. 1 is an alternative view of a system according to one or more embodiments of the present invention. [Figure 10] 1 is a flow chart illustrating a method according to one or more embodiments of the present invention.

[0010] The diagrams shown herein are exemplary. There are many variations to the diagrams and the operations described therein without departing from this invention. For example, actions can be performed in a different order, or actions can be added, deleted, or modified. Also, the term "coupled" and variations thereof describe having a communication path between two elements and do not imply a direct connection between the elements without an intervening element / connection between the elements. All of these variations are considered to be part of this specification.

[0011] In the accompanying drawings and the detailed description of the embodiments described below, various elements shown in the drawings are labeled with two- or three-digit reference numbers. With few exceptions, the left-most digit(s) of each reference number corresponds to the figure in which the element is first shown. DETAILED DESCRIPTION OF THE INVENTION

[0012] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Moreover, various task and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functionality not described in detail herein. In particular, because the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted altogether without providing details of the well-known processes.

[0013] Now, providing an overview of technology more specifically related to embodiments of the present invention, in an RRAM crossbar array, typical device failure modes are unformable devices and over-formed devices that create shorts within the crossbar array. In the case of un-formed failures, the problem is less severe because the corresponding crosspoint device does not contribute to the crossbar array's computations. However, in the case of over-formation, the resistance of the failed crosspoint device is significantly lower than the remaining crosspoint devices connected to the same row and column. Crosspoint devices in rows and columns of the crossbar array become unusable due to the severe current draw from the failed (over-formed) crosspoint devices.

[0014] These high current draws can cause problems, including power supplies that may meet or exceed limits and become damaged. High currents amplify parasitic wire resistance effects, and voltage drops at other crosspoint devices connected to the same row / column can vary widely within the crossbar array. Also, current readout circuits can become damaged or reach their limits, causing operations to fail.

[0015] Briefly outlining aspects of the present invention, one or more embodiments of the present invention address the above-described shortcomings of the prior art by providing a crossbar array configured and arranged to disable specific defective devices in an RRAM dual damascene crossbar array by leveraging increased current-induced electromigration properties while maintaining stable operation of the rest of the array. Generally, an IC includes a network of conductors and interconnect structures that couple signals to and from the IC's various logic circuits and memories. Electromigration occurs in the conductors and interconnect structures due to momentum transfer of electrons moving through the medium. Over time, the electrons can damage the conductors and adversely affect their performance, which can result in unreliable and unpredictable circuit performance. As IC features shrink in size, electromigration becomes a more significant factor. Embodiments of the present invention leverage the electromigration properties of conductors and interconnect structures to disable defective crosspoint devices in the crossbar array. In embodiments of the present invention, high currents can be passed through the crosspoint devices of the crossbar array, causing voids to form in the connections due to electromigration. The voids disable devices in the array while allowing the remaining devices in the crossbar array to remain operational. The above-described aspects of the present invention address the shortcomings of the prior art by enabling the crossbar array structure to disable defective devices in the array by inducing voids in the channels coupled to the devices.

[0016] Describing embodiments of the present invention in more detail, FIG. 1A illustrates a simplified block diagram showing a cross-sectional view of a two-terminal RSD component that can be used as a storage cell in an RRAM structure (e.g., crossbar array 200 shown in FIG. 2) that can incorporate embodiments of the present invention. RSD storage cell 100 includes a top electrode 102, a metal oxide 104 active region, and a bottom electrode 106 configured and arranged as shown. When a sufficient electrical signal (e.g., voltage) is applied between top electrode 102 and bottom electrode 106, the resistance of metal oxide 104 can be switched from one resistance state to another. Metal oxide 104 retains its current-carrying resistance state until it is changed by applying an appropriate electrical signal between top electrode 102 and bottom electrode 106.

[0017] FIG. 1B is an IV curve diagram illustrating the switching behavior of the RSD memory cell 100. The operating principle of the RSD memory cell 100 is based on reversible resistance switching (RS) between at least two stable resistance states, a high resistance state (HRS) and a low resistance state (LRS), which occur in the metal oxide 104. Generally, the operation of changing the resistance of the memory cell 100 from the high resistance state (HRS) to the low resistance state (LRS) is called the SET process, and the reverse process is defined as the RESET process. The high resistance state (HRS or LRS) can be retained after the cancellation of electrical stress, indicating the nonvolatility of RRAM. During the initial write operation, a voltage greater than the SET voltage is required to "turn on" the resistance switching behavior of the metal oxide 104 for subsequent cycles. This is often referred to as the formation process or electroforming process.

[0018] Based on the electrical polarity relationship between the SET and RESET processes, the resistive switching behavior of the storage cell 100 can be divided into two modes, known as the unipolar mode (not shown) and the bipolar mode (shown in FIG. 1B). In the unipolar switching mode, both the SET and RESET transitions are achieved by applying voltages of the same polarity (e.g., positive voltages). In the bipolar switching mode, the SET and RESET transitions are performed by applying voltages of opposite polarity (e.g., positive voltage SET and negative voltage RESET). In both cases, the current is limited by a compliance level during the abrupt SET transition to appropriately control the size of the current-conducting filament (CF) and the corresponding LRS resistance value.

[0019] FIG. 2 shows a simplified block diagram illustrating how the RSD memory cell 100 shown in FIG. 1A can be utilized as an addressable cross-point memory cell 100A in an RRAM crossbar array 200 that can incorporate aspects of the present invention. The array 200 includes vertical conductive top electrode lines 202 (e.g., word line rows), conductive bottom electrode lines 204 (e.g., bit line columns), and an RSD memory cell 100A at the intersection of each top electrode line 202 and bottom electrode line 204. In embodiments of the present invention, the memory cells 100A can be configured to operate in the same manner as the memory cell 100 shown in FIG. 1A. Each memory cell 100A can be accessed for read and write operations by biasing the corresponding top electrode line 202 and bottom electrode line 204.

[0020] 3-6 illustrate various cross-sectional views of a dual damascene crossbar array structure 300 after various fabrication operations in accordance with one or more embodiments of the present invention. The final crossbar array structure 300 shown in Figure 6 provides a more detailed implementation of the crossbar array 200 shown in Figure 2, where bottom electrode line 204 corresponds to bottom electrode 308, top electrode line 202 corresponds to top electrodes 606A, 606B, and 606C, and RSD memory cell 100A corresponds to memory devices 404A, 404B, and 404C.

[0021] 3 illustrates a cross-sectional view of a structure 300 after an initial series of fabrication operations according to an embodiment of the present invention. Structure 300 includes a substrate 302. Substrate 302 can be any suitable substrate material, such as, for example, single crystal Si, SiGe, SiC, a III-V compound semiconductor, a II-VI compound semiconductor, or a semiconductor-on-insulator (SOI).

[0022] In one or more embodiments of the present invention, substrate 302 is formed by depositing and planarizing a layer of substrate material (not shown). A hard mask (not shown) is deposited on the substrate material, patterned, and etched to form substrate 302 having the structure shown in FIG. 3. A barrier layer 304 is deposited (e.g., using ALD) on exposed portions of substrate 302. Barrier layer 304 may comprise any suitable barrier-type material, such as, for example, tantalum nitride (TaN), and may be used to prevent diffusion of metal fill materials (e.g., 308) into other layers of structure 300.

[0023] 3 , a liner 306 is formed on the barrier layer 304. The liner 306 is conformally deposited (e.g., by atomic layer deposition (ALD)). In some embodiments of the present invention, the liner 306 is conformally formed to a thickness of about 1 nm to about 7 nm, although other thicknesses are within the contemplated scope of the present invention. In one or more embodiments of the present invention, the liner 306 may include a material such as ruthenium (Ru), cobalt (Co), tantalum (Ta), tungsten (W), or titanium (Ti). The liner 306 may aid in forming a metal layer for the bottom electrode layer 308. For example, the liner 306 may facilitate the formation of a bottom electrode copper layer having low critical dimensions.

[0024] 3, a bottom electrode layer 308 is deposited on the liner 306. In one or more embodiments of the present invention, the bottom electrode layer 308 includes, but is not limited to, copper (Cu). In one or more embodiments of the present invention, the bottom electrode layer 308 can function as an interconnect layer for connecting devices on different layers (not shown). Chemical mechanical planarization (CMP) is used to planarize the top surface of the structure 300.

[0025] 4 illustrates structure 300 after one or more processes have been performed in accordance with one or more embodiments of the present invention. In one or more embodiments of the present invention, an insulator layer 402 is deposited on structure 300. Insulator layer 402 is patterned (not shown) and etched to form trenches in insulator layer 402 for memory devices 404A, 404B, and 404C. In this non-limiting example, three memory devices 404A, 404B, and 404C are formed and shown in FIG. 4, although fewer than three memory devices 404A, 404B, and 404C may be provided.

[0026] 5 shows structure 300 after additional fabrication operations have been performed to form dielectric layer 502, etch stop layer 504, dielectric layer 506, and dual damascene trenches 508, 510, and 512. In an embodiment of the invention, dielectric layer 502 is formed by depositing and planarizing dielectric layer 502 over structure 300. Dielectric layer 502 may include any suitable dielectric material, including but not limited to silicon dioxide (SiO2).

[0027] In one or more embodiments of the present invention, layer 504 is deposited over dielectric layer 502. Layer 504 provides more control in creating the desired dimensions for the via during the etching process. In one or more embodiments of the present invention, layer 504 is an etch stop layer, which may be silicon nitride (SiN) as a non-limiting example.

[0028] In one or more embodiments of the invention, layer 506 is formed over layer 504. The top electrode layer of the crossbar array is formed in dielectric layer 506, and dual damascene trenches 508, 510, 512 are formed in dielectric layers 502 and 506 by an etching process, such as RIE. As shown, trenches 508, 510, 512 are dual damascene such that an upper region of each of trenches 508, 510, 512 is formed in dielectric layer 506 with substantially parallel sidewalls, and a lower region of each of trenches 508, 510, 512 is formed in dielectric layer 502 with tapered (or angled) sidewalls. After the upper region of each of trenches 508, 510, 512 is formed, an etching process may be employed to form the tapered / angled sidewalls. According to an embodiment of the present invention, the lower regions of dual damascene trenches 508, 510, 512 are via regions in which via 620 (shown in FIG. 6) is formed. According to an embodiment of the present invention, the upper regions of dual damascene trenches 508, 510, 512 are line (or top electrode) trench regions in which line layers of top electrodes 606A, 606B, 606C (shown in FIG. 6) are formed.

[0029] FIG. 5 shows that the shape of trenches 404A, 404B, and 404C relative to via 620 (via 620 is shown in FIG. 6 ) is tapered as a result of the etching process. The dimensions (e.g., height, width) of via 620 are such that increased current can induce voids in via 620 due to electromigration. Additionally, the dimensions (e.g., height, width) of the line portions of top electrodes 606A, 606B, and 606C above via 620 encourage void formation in the via region rather than in the line portions of top electrodes 606A, 606B, and 606C or top electrodes 606A, 606B, and 606C. The current provided through memory devices 404A, 404B, and 404C can range from a few milliamperes to hundreds of milliamperes or amperes. This applied current must be sufficiently above the normal operating current range or threshold to allow the electromigration process to open voids in the selected vias 620 of the memory devices 404A, 404B, 404C.

[0030] FIG. 6 illustrates structure 300 after one or more processes have been performed in accordance with one or more embodiments of the present invention. A barrier layer 602 is deposited within dual damascene trenches 508, 510, and 512 formed in FIG. 5. Barrier layer 602 is a diffusion barrier similar to barrier layer 304. In one or more embodiments, layer 602 is conformally deposited on the sidewalls of trenches 508, 510, and 512. As shown in FIG. 6, a liner 604 is deposited on barrier layer 602. A metal, such as copper, is deposited in each of trenches 508, 510, and 512 to form line layers for top electrodes 606A, 606B, and 606C (corresponding to top electrode lines 202) and vias 620 for corresponding memory devices 404A, 404B, and 404C, respectively, where memory devices 404A, 404B, and 404C correspond to junction 100A in FIG. 2.

[0031] In one or more embodiments of the present invention, a dual damascene process is performed to form the line portions of the top electrodes 606A, 606B, and 603C and the via 620 below the line portions of the top electrodes 606A, 606B, and 603C. The dual damascene process simultaneously forms two features: the lines of the top electrodes 606A, 606B, and 606C and the via 620. For example, the trenches 508, 510, and 512 for the via layer and the lines of the top electrodes 606A, 606B, and 606C are filled at the same time in the same metal deposition step. CMP can be performed to remove excess metal deposition.

[0032] The dimensions of the via 620 should be smaller than the line dimensions of the top electrodes 606A, 606B, and 606C, which allows the via 620 to quickly form voids when high currents are applied to the selected memory devices 404A, 404B, and 404C, disabling the memory devices 404A, 404B, and 404C in the crossbar array, thereby preventing the underlying memory devices 404A, 404B, and 404C from contributing to the function of the crossbar array.

[0033] In a non-limiting example, the height of the via 620 is 1.25 to 2 times the critical dimension (CD) of the via. In a non-limiting example, the interconnect or line portion of the top electrode has a CD of 18 nm, while the via portion has a CD of approximately 12 to 14 nm. As shown in Figure 6, the via 620 formed in the trenches 508, 510, and 512 has tapered sidewalls. This increases the chance of void formation in the via 620, potentially disabling failed devices in the crossbar array. The narrower dimensions of the via 620 allow for void formation due to electromigration in that region due to increased current.

[0034] As shown in FIG. 6, the critical dimension CD1 of the bottom of the via 620 is smaller than the critical dimension CD2 of the top of the via 620. The tapered sidewall angle of the via 620 results in the bottom via CD1 being significantly smaller than the top via CD2, e.g., CD1=10 nm and CD2=14 nm. In one or more embodiments of the present invention, the height (h1) of the via 620 is 1.25 to 2 times CD1 or CD2. In one or more embodiments of the present invention, the CD2 of the top of the via 620 is smaller than the CD of the line layer. For example, the CD of the line portion of the top electrodes 606A, 606B, and 606C is 18 nm. CMP can be performed to planarize the structure 300.

[0035] FIG. 7 illustrates a system 700 incorporating a crossbar array 704. As shown, logic regions 702 are coupled to the crossbar array 704 via interconnects 706. The interconnects 706 may be copper interconnects, and in one or more embodiments of the present invention, the interconnects 706 may reside within a barrier layer 708. In this non-limiting example, the system 700 includes three memory devices 710, 712, and 714. Each of the memory devices 710, 712, and 714 is formed on a bottom electrode 716. Additionally, each memory device 710, 712, and 714 is coupled to a respective via 718, 720, and 722. Each via is coupled to a respective top electrode layer 724, 726, and 728.

[0036] FIG. 8 shows a first diagram of system 700 after a void has formed in a via corresponding to a defective memory device 712. In the perspective view shown in FIG. 8, memory devices 710, 712, and 714 are formed on a common bottom electrode 716. In one or more embodiments of the present invention, memory device 712 may be determined to be bad or defective using various testing techniques. Once a device is identified and determined to be bad, it may be disabled by applying a current to the device at a location in the array to induce a void through electromigration. By applying a high current to memory device 712, a void 802 forms in the via of memory device 712. Due to the effects of electromigration and the dimensions of the via, void 802 disables memory device 712.

[0037] FIG. 9 shows an alternative view of system 700. As shown, line portions of top electrode layer 726 are coupled to memory devices 902, 712, and 904. Memory device 712 is formed on bottom electrode 716 (shown in FIG. 8). Memory devices 902 and 904 are formed on adjacent bottom electrode layers 906 and 908, respectively. FIG. 9 also shows vias 910, 720, and 912 corresponding to memory devices 902, 712, and 904, respectively. A void 802 has been induced in via 720, disabling the defective memory device 712.

[0038] FIG. 10 illustrates a flowchart of a method 1000 for forming a dual damascene crossbar array according to one or more embodiments. The method 1000 begins at block 1002 and proceeds to block 1004, which forms a bottom electrode layer on a substrate. The bottom electrode layer provides contacts for memory devices. Block 1006 forms the memory devices on the bottom electrode layer. The memory devices are RRAMs. Block 1008 forms a dual damascene structure on the memory devices, the dual damascene structure including a top electrode layer and a via, the via being formed between the memory devices and the top electrode layer. In one or more embodiments of the present invention, the via is a tapered via, with the top of the via coupled to a line portion of the top electrode layer and the bottom of the via coupled to the memory devices. The critical dimension of the line portion of the top electrode layer is larger than the critical dimension of the via. This ensures that, if a void is induced, the void is formed in the via and not in the top electrode layer, so that the remaining devices in the row / column remain operational. Method 1000 ends at block 1010. It is understood that method 1000 is not intended to be limiting in scope and different steps may be incorporated into method 1000.

[0039] One or more aspects of the present invention improve upon the prior art by providing the ability to disable individual memory devices in a crossbar array structure while maintaining operability of the remaining devices in the crossbar array.

[0040] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternate embodiments may be devised without departing from the scope of the present invention. While various connections and relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and in the drawings, those skilled in the art will recognize that many of the relationships described herein are independent of orientation, provided that the described functionality is maintained even when the orientation is changed. These connections and / or relationships may be direct or indirect, unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, a connection of entities may refer to either a direct or indirect connection, and a relationship between entities may be a direct or indirect relationship. As an example of an indirect relationship, reference in this description to forming layer "A" on layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layers "A" and "B," as long as the relevant properties and functionality of layers "A" and "B" are not substantially altered by that intermediate layer.

[0041] The following definitions and abbreviations should be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements, but can include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0042] Moreover, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, 5, etc. The term "plurality" is understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include indirect and direct connections.

[0043] When reference is made herein to "one embodiment," "an embodiment," "an exemplary embodiment," or the like, the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0044] For purposes of the following description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the described structures and methods as oriented in the drawings. The terms "resting," "uppermost," "on," "overlying," or "topmost" mean that a first element, such as a first structure, resides on a second element, such as a second structure, such as an interface structure, where intervening elements may reside between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layers at the interface of the two elements.

[0045] Spatially relative terms, such as "below," "below," "below," "above," "above," etc., may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown. For example, if a device in a figure is inverted, an element described as "below" or "below" another element or feature would then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an up and down orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein will be interpreted accordingly.

[0046] The phrase "selective to," e.g., "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0047] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on equipment available at the time of filing. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0048] The term "conformal" (eg, conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness varies by less than 15% of the nominal thickness of the layer.

[0049] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In an epitaxial deposition process, chemical reactants provided by source gases can be controlled, and system parameters can be set to ensure that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about the surface so that they are oriented in the crystalline configuration of the atoms on the deposition surface. The epitaxially grown semiconductor material can have substantially the same crystalline properties as the deposition surface from which it is formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystalline surface can have a {100} orientation. In some embodiments of the present invention, the epitaxial growth and / or deposition process may be selective to form on semiconductor surfaces and not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0050] As previously described herein, for the sake of brevity, the prior art related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, by way of background, a more general description of semiconductor device fabrication processes that may be utilized in implementing one or more embodiments of the present invention will be provided. While the specific fabrication operations used in implementing one or more embodiments of the present invention may be individually known, the combination of inventive operations and / or resulting structures described is unique. Thus, the unique combination of operations described in connection with fabricating semiconductor devices in accordance with the present invention utilizes a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraphs.

[0051] Generally, the various processes used to form microchips that are packaged into ICs fall into four broad categories: deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical vapor deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry) and chemical-mechanical planarization (CMP). Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, typically by diffusion or ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The anneal serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the substrate's conductivity to be changed by the application of voltage. By fabricating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of three-dimensional relief images or patterns on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called a photoresist. Lithography and etching pattern transfer steps are repeated multiple times to build the complex structures that make up the transistors and the numerous wires that connect the circuit's millions of transistors.Each pattern printed on the wafer is aligned with a previously formed pattern, gradually building up conductors, insulators, and selectively doped regions to form the final device.

[0052] The flowcharts and block diagrams in the figures illustrate possible implementations of methods of manufacture and / or operation according to various embodiments of the present invention. Various functions / operations of the methods are represented in the flow diagrams by blocks. In some alternative embodiments, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved.

[0053] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements over technology found in the marketplace of the embodiments, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. 1. A method for fabricating a dual damascene crossbar array, comprising: forming a bottom electrode layer on a substrate; forming a first memory device on the bottom electrode layer; forming a dual damascene structure on the first memory device; the dual damascene structure comprising a top electrode layer and a first via, the first via being formed between the first memory device and the top electrode layer, the method further comprising: forming interconnects coupling said dual damascene crossbar array to logic regions; wherein the interconnect is configured to pass an increased current through the first memory device to induce voids in the first via.

2. forming a second memory device on the bottom electrode layer; forming a second via for the second memory device; 2. The method of claim 1, wherein the second via is formed between the second memory device and another line portion different from the line portion connected to the first via in the top electrode layer.

3. 10. The method of claim 1, wherein the via is a tapered via, the via including a top portion coupled to the top electrode layer having a first critical dimension (CD) and a bottom portion coupled to a first memory device having a second CD.

4. The method of claim 3 , wherein the first CD is greater than the second CD.

5. The method of claim 4 , wherein a CD of the line of the top electrode layer is greater than the second CD of the via.

6. The method of claim 1 , wherein the current is greater than an operating current threshold of the dual damascene crossbar array.

7. 1. A dual damascene crossbar array, comprising: one or more memory devices of said dual damascene crossbar array; a bottom electrode coupled to the one or more memory devices; one or more vias coupled to each memory device; a top electrode layer coupled to the one or more vias; a logic region coupled to said dual damascene crossbar array via interconnects; the one or more vias are disposed between the memory devices and the top electrode layer, each of the one or more vias is respectively coupled to a different line portion of the top electrode layer, and the interconnect is configured to pass an increased current through one or more of the one or more memory devices to induce voids in one or more of the one or more vias.

8. 8. The dual damascene crossbar array of claim 7, wherein each of the one or more vias is tapered, and each of the one or more vias includes an upper portion coupled to the top electrode layer having a first critical dimension (CD) and a lower portion coupled to the memory device having a second CD.

9. 9. The dual damascene crossbar array of claim 8, wherein each of said one or more vias has a CD in the range of 12 to 14 nm.

10. The dual damascene crossbar array of claim 8 , wherein the first CD is greater than the second CD.

11. The dual damascene crossbar array of claim 10 , wherein a CD of the line portion of the top electrode layer is greater than the second CD of the via.

12. The dual damascene crossbar array of claim 11 , wherein the line portions of the top electrode layer have a CD of 18 nm.

13. 12. The dual damascene crossbar array of claim 11, wherein a height of each of the one or more vias is between 1.25 and 2 times at least one of the first CD or the second CD of the via.

14. 8. The dual damascene crossbar array of claim 7, wherein the bottom electrode layer is formed on a liner comprising at least one of tungsten (W), titanium (Ti), ruthenium (Ru), tantalum (Ta), and cobalt (Co).

15. The dual damascene crossbar array of claim 7 , wherein the current is greater than an operating current threshold of the dual damascene crossbar array.

16. 1. A method for disabling memory devices in a dual damascene crossbar array, comprising: and identifying defective memory devices in the dual damascene crossbar array, the dual damascene crossbar array comprising: one or more memory devices of said dual damascene crossbar array; a bottom electrode layer coupled to the one or more memory devices; one or more vias coupled to each memory device; a top electrode layer coupled to the one or more vias; a logic region coupled to said dual damascene crossbar array via interconnects; the one or more vias are disposed between the memory devices and the top electrode layer, each of the one or more vias being respectively coupled to a different line portion of the top electrode layer, and the interconnects are configured to pass an increased current through one or more of the one or more memory devices to induce voids in one or more of the one or more vias; disabling the defective memory devices of the dual damascene crossbar array by creating the voids in vias corresponding to the defective memory devices; and operating one or more remaining memory devices of said dual damascene crossbar array; A method comprising:

17. 17. The method of claim 16, wherein each of the one or more vias is tapered, and each of the one or more vias includes a top portion coupled to the top electrode layer having a first critical dimension (CD) and a bottom portion coupled to the memory device having a second CD.

18. 17. The method of claim 16, wherein disabling the defective memory devices of the dual damascene crossbar array comprises passing a current through the defective memory devices to disable the defective memory devices.

19. 17. The method of claim 16, wherein the current is greater than an operating current threshold of the dual damascene crossbar array.

20. 20. The method of claim 17, wherein a CD of a line portion of the top electrode layer is greater than the second CD of the one or more vias.

Images