Imaging device and control method thereof

Abstract

To suitably perform pixel readout processing while preventing an increase in circuit scale.SOLUTION: An imaging apparatus comprises: M detection elements that each have a detection pixel detecting incident of photons and a generation unit generating a readout request and data; a readout circuit that receives the readout request and data from each of the M detection elements; and a control pulse supply unit that supplies control pulses to the M detection elements and the readout circuits. The generation unit has a cycle counter that counts the number of delay cycles from when the readout request is issued until when the readout request is permitted, a coordinate holding unit that holds position coordinate information on the detection element corresponding to the generation unit, and a data generation unit that generates data including the number of delay cycles and the position coordinate information. The readout circuit has a time counter that counts time based on the control pulse. The readout circuit determines the generation unit corresponding to the readout request and the generation timing at which the readout request is generated based on the number of delay cycles included in the data corresponding to the received readout request and a counter value of the time counter.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] Photoelectric conversion devices are known that digitally count the number of photons arriving at an avalanche photodiode (APD) and output the counted value as a photoelectrically converted digital signal from the pixel. Digitizing pixel signals offers significant advantages in terms of noise and signal processing, and imaging devices with an array of multiple pixels that output photoelectrically converted digital signals are becoming increasingly popular. Patent Document 1 discloses a method for measuring the time when the number of counted photons reaches a threshold in a time shorter than one frame in an imaging device, and determining the number of photons per frame from the time information and the number of photons.

[0003] Furthermore, APDs are widely used as distance measuring devices that use the ToF (Time of Flight) method. This ToF method involves emitting light and detecting the light reflected by an object to be measured, and converting the light into the distance to the object based on the time difference between emission and detection. The time difference is derived, for example, using a time counter, a TDC (Time to Digital Converter). With the ToF method using an APD, a single measurement cannot distinguish between photons detected by reflected light and photons detected by ambient light. Patent Document 2 discloses a method for calculating distance from the peak value of a histogram generated by repeatedly emitting and detecting light, for example, several thousand times, and storing the results.

[0004] Thus, in both the imaging device typified by Patent Document 1 and the ranging device typified by Patent Document 2, it is necessary to increase the resolution of the time counter in order to perform highly accurate processing. However, a time counter with high time resolution leads to an increase in circuit size, making it difficult to provide a time counter for each pixel. Patent Document 2 discloses a technique for suppressing the increase in circuit size by connecting one time counter to multiple pixels. Furthermore, Non-Patent Document 1 discloses a technique for suppressing the increase in circuit size by connecting, for each row consisting of multiple pixels, a number of time counters that is fewer than the number of pixels per row. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 9,210,350 [Patent Document 2] International Publication No. 2019 / 065174 [Non-patent literature]

[0006] [Non-Patent Document 1] Zhang, C., "CMOS SPAD Sensors for 3D Time-of-Flight Imaging, LiDAR and Ultra-High Speed ​​Cameras", doctoral thesis, Delft University of Technology, 2019 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in ToF applications, neither the configurations of Patent Document 2 nor Non-Patent Document 1 can detect simultaneous photon reception by multiple pixels sharing a time counter. Patent Document 2 sets the photon detection periods of each pixel sharing a time counter to be temporally exclusive, thereby preventing simultaneous photon reception in the system. Non-Patent Document 1 detects the collision of received light pulses when two or more pixels sharing a time counter simultaneously receive photons, but ignores the colliding received light pulses. In distance measurement sensors such as ToF, the probability of simultaneous photon detection increases when a time counter is shared among multiple pixels in a high-resolution pixel array. Therefore, ignoring the simultaneous detection of two or more photons results in a decrease in ranging accuracy.

[0008] On the other hand, applying the technology of Patent Document 2 to an image sensor that forms images like those of Patent Document 1 leads to a decrease in frame rate. Also, applying the technology of Non-Patent Document 1 results in missing pixels.

[0009] The present invention has been made in view of the above problems, and has as its object to provide a technique for performing pixel readout processing in an appropriate manner while suppressing an increase in circuit scale. [Means for solving the problem]

[0010] In order to solve the above-mentioned problems, an imaging device according to the present invention has the following arrangement: M (M is an integer of 2 or more) detection elements each having a detection pixel that detects the incidence of a photon and a generation unit that generates a read request and data based on the photon detection at the detection pixel; a read circuit that receives read requests and data from each of the M detector elements; a control pulse supply unit that supplies control pulses to the M detection elements and the readout circuit; Equipped with The generation unit of each of the M detection elements a cycle counter that counts the number of delay cycles from when the read request is issued until when the read request is permitted; a coordinate storage unit that stores position coordinate information of a detection element corresponding to the generation unit; a data generating unit that generates the data including the number of delay cycles and the position coordinate information; and The readout circuit includes: A time counter that counts time based on the control pulses and, Memory and and The read circuit determines the number of delay cycles included in the data corresponding to the received read request and the counter value of the time counter. , applicable Determines when a read request is generated and recording the generation timing at a position in the memory corresponding to the position coordinate information included in the data corresponding to the received read request. do. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a technique for performing pixel readout processing in an appropriate manner while suppressing an increase in circuit scale. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 illustrates an example of the configuration of an imaging device. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a sensor chip. [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of a circuit chip. [Figure 4] FIG. 2 is a diagram showing an equivalent circuit of a pixel and a signal processing unit. [Figure 5] FIG. 2 is a diagram illustrating an example of the configuration of a pulse processing unit 220 according to the first embodiment. [Figure 6] FIG. 2 is a diagram showing the configuration of a signal readout circuit and connections to a signal processing unit. [Figure 7] 10 is a timing chart showing the operation of the signal processing unit and the row readout circuit. [Figure 8] FIG. 10 is a diagram illustrating an example of the configuration of a pulse processing unit 220 according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0014] (First embodiment) As a first embodiment of an imaging device according to the present invention, an imaging device using an avalanche photodiode (APD) as a photoelectric conversion element will be described below. Note that although the imaging device is described here, it may also be a distance measuring device.

[0015] <Device configuration> 1 is a diagram showing an example of the configuration of an imaging device 100 according to the first embodiment. The imaging device 100 is configured by stacking and electrically connecting two chips: a sensor chip 11 and a circuit chip 21. The sensor chip 11 includes a pixel region 12. The circuit chip 21 includes a pixel circuit region 22 that processes signals detected in the pixel region 12, and a readout circuit region 23 that reads out signals from the pixel circuit region 22.

[0016] FIG. 2 is a diagram showing an example of the configuration of the sensor chip 11. The pixel region 12 of the sensor chip 11 includes a plurality of pixels 101, which are detection pixels, arranged on a two-dimensional surface across multiple rows and columns. Each pixel 101 has a photoelectric conversion unit 102 including an avalanche photodiode (APD). FIG. 2 shows m×n pixels 101 arranged in m rows from the first row to the mth row and n columns from the first column to the nth column, along with reference symbols indicating the row and column numbers. For example, the unit pixel 11 arranged in the first row and third column (i.e., m=1, n=3) is labeled "P13." The number of rows and columns of the pixel array constituting the pixel region 12 is not particularly limited.

[0017] 3 is a diagram showing an example of the configuration of the circuit chip 21. The circuit chip 21 includes a pixel circuit region 22 and a control circuit region .

[0018] The pixel circuit region 22 includes a plurality of signal processing units 103 arranged on a two-dimensional surface across multiple rows and columns. Fig. 3 shows some of the m x n signal processing units 103 arranged from the first row to the mth row and the first column to the nth column, along with reference symbols indicating the row and column numbers. For example, the signal processing unit 103 arranged in the first row and third column (i.e., m = 1, n = 3) is assigned the reference symbol "S13." Note that the number of rows and columns of the signal processing unit array constituting the pixel circuit region 22 is not particularly limited.

[0019] The control circuit region 23 includes a control pulse generation circuit 110 and a signal readout circuit 111. Control lines 112 and data signal lines 113 are arranged in each row of the signal processing unit array in the pixel circuit region 22, extending in a first direction (the horizontal direction in FIG. 3). The control lines 112 and data signal lines 113 are respectively connected to a plurality of signal processing units 103 lined up along the first direction. The first direction in which the control lines 112 extend may be referred to as the row direction or the horizontal direction. Furthermore, a readout request signal line 114 is connected to each row of the signal processing unit array in the pixel circuit region 22 in a manner that connects a plurality of signal processing units 103 lined up along the first direction.

[0020] The control line 112 of each row is connected to a control pulse generation circuit 110. The control pulse generation circuit 110, which is a control pulse supply unit, supplies a control signal for driving the signal processing unit 103 to the signal processing unit 103 via the control line 112. The control pulse generation circuit 110 and the signal readout circuit 111 are connected via a control line 115. The control pulse generation circuit 110 supplies a control signal for driving the signal readout circuit 111 in synchronization with the signal processing unit 103 via the control line 115. The control pulse generation circuit 110 may generate the control signal based on an external trigger (not shown), or may generate the control signal based on an internal signal.

[0021] The data signal line 113 and read request signal line 114 of each row are connected to a signal read circuit 111. The data signal line 113 is a signal line for transmitting a plurality of data generated by the signal processing unit 103, which is a data generating unit. The plurality of data are pixel counter values, read cycle counter values, and position coordinate information, which will be described in detail later. The read request signal line 114 is a signal line for transmitting read requests issued by each signal processing unit 103. The signal read circuit 111 obtains a plurality of data from the data signal line 113 in response to the read request on the read request signal line 114.

[0022] FIG. 4 is a diagram showing an equivalent circuit of the pixel 101 in FIG. 2 and the signal processing unit 103 in FIG. 3. A combination of a pixel 101 and a corresponding signal processing unit 103 constitutes a detection element. The pixel 101 in the sensor chip 11 includes an APD 201, which is a photoelectric conversion unit. When light is incident on the APD 201, a charge pair corresponding to the incident light is generated by photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage is supplied to the anode and cathode so that the APD 201 performs avalanche multiplication. With such a voltage supplied, charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0023] When a reverse bias voltage is supplied, there are two modes: Geiger mode and linear mode. Geiger mode is a mode in which the potential difference between the anode and cathode is greater than the breakdown voltage. Linear mode is a mode in which the potential difference between the anode and cathode is close to or less than the breakdown voltage. An APD operating in Geiger mode is called a single photon avalanche diode (SPAD). For example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1V.

[0024] The signal processing unit 103 in the circuit chip 21 is made up of a pulse generating unit 210 and a pulse processing unit 220. The pulse generating unit 210 includes a quench element 211 and a waveform shaping unit 212. The quench element 211 is connected to a power supply that supplies voltage VH and the APD 201. The quench element 211 has a function of converting changes in avalanche current generated in the APD 201 into a voltage signal. The quench element 211 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has the function of suppressing avalanche multiplication by suppressing the voltage supplied to the APD 201 (quench operation).

[0025] The waveform shaping unit 212 shapes the potential change of the cathode of the APD 201 obtained upon photon detection and outputs a pulse signal. The waveform shaping unit 212 may be, for example, an inverter circuit or a buffer circuit. The pulse processing unit 220 receives the photon detection pulse generated by the pulse generating unit 210 and transfers a plurality of data via the data signal line 113.

[0026] 5 is a diagram showing an example of the configuration of the pulse processing unit 220 according to the first embodiment. The pulse processing unit 220 includes a pixel counter 221, a read request unit 222, a read cycle counter 223, and a coordinate holding unit 224.

[0027] The pixel counter 221 is a counter that counts the number of pulse signals output from the pulse generation unit 210 (i.e., the number of detected photons). The pixel counter 221 starts or stops counting based on a drive signal received via the control line 112. The pixel counter 221 is, for example, an 8-bit counter that outputs a saturation pulse signal when it reaches a saturation value (all bits are "1"). The pulse signal output by the pixel counter 221 may be issued when the counter value exceeds a predetermined threshold. If the counter does not reach saturation within a certain period of time, the pixel counter 221 receives a transfer permission signal from the read request unit 222 and transfers the pixel counter value to the signal readout circuit 111 via the data signal line 113.

[0028] The read request unit 222 transmits a read request to the signal read circuit 111 via a read request signal line 114 based on the saturation pulse signal output from the pixel counter 221 or the drive signal received via the control line 112. Specifically, the read request is transmitted by setting the read request signal line 114 to a High level. Furthermore, when the read request unit 222 receives a saturation pulse signal, it issues a read request issue signal to a read cycle counter 223.

[0029] The read request unit 222 controls the read request depending on whether or not there is a "high priority read request" from another signal processing unit with a higher priority. Priorities are predetermined for each of the multiple signal processing units 103 and stored in the read request unit 222. In FIG. 3, for example, the leftmost signal processing unit 103 (i.e., S11) has the highest priority, and the priority is determined to decrease as the column number progresses horizontally (i.e., S11 → S12 → S13). This simplifies the wiring of the read request line 114. Of course, the method of assigning priorities is not limited to this. Furthermore, the signal processing unit with the highest priority operates in the same manner as the configuration example shown in FIG. 5, assuming that the read request of the signal processing unit with the highest priority is always stopped (the read request signal line 114 is at a low level).

[0030] Next, a method for controlling read requests by the read request unit 222 will be described. When no read request has occurred in the signal processing unit to which the read request unit 222 belongs, the read request unit 222 transmits a high-priority read request from another signal processing unit with a higher priority as is. On the other hand, when a read request has occurred in the signal processing unit to which the read request unit 222 belongs, and a read request from another signal processing unit with a higher priority has occurred (High), the read request unit 222 transmits the read request to the signal read circuit 111. At the same time, the read request of the signal processing unit to which the read request unit 222 belongs is extended by one cycle. Furthermore, if a read request issue signal has been issued to the read cycle counter 223, the read request is similarly extended. In other words, the counter value of the read cycle counter 223 is the number of delay cycles.

[0031] If a read request from another signal processing unit 103 with a higher priority is stopped (low), the read request unit 222 determines that the read request of its own signal processing unit is permitted, stops the read request signal (low), and issues a transfer permission signal. If the read request unit 222 issues a read request in response to a saturation pulse signal, it issues a transfer permission signal to the read cycle counter 223 and coordinate holding unit 224. On the other hand, if the read request unit 222 issues a read request in response to a drive stop signal, it issues a transfer permission signal to the pixel counter 221 and coordinate holding unit 224.

[0032] The read cycle counter 223 is a (for example, 8-bit) counter that counts the number of cycles from the issuance of a read request to the time when reading is permitted. The read cycle counter 223 starts counting upon receiving a read request issuance signal from the read request unit 222, stops counting upon receiving a transfer permission signal, and transmits the read cycle counter value to the signal read circuit 111 via the data signal line 113.

[0033] The coordinate holding unit 224 holds information indicating pixel positions. Upon receiving a transfer permission signal from the read request unit 222, the coordinate holding unit 224 transmits position coordinate information to the signal read circuit 111 via the data signal line 113.

[0034] FIG. 6 is a diagram showing the configuration of the signal readout circuit 111 and the connection with the signal processing unit 103. As shown in FIG.

[0035] The signal readout circuit 111 includes a row readout circuit 230 connected to each row, and a memory 231 that stores readout signal values. The row readout circuit 230 includes a data receiving unit 232, a time counter 233, and a time calculation unit 234. The data receiving unit 232 receives a readout request from the signal processing unit 103 via a readout request signal line 114, and acquires position coordinate information of the data signal line 113 and a pixel counter value or a cycle counter value.

[0036] The time counter 233 receives a control signal from the control pulse generating circuit 110 via the control line 115 and measures the exposure time. The time counter 233 also transmits the counter value at the timing of receiving the read request to the time calculation unit 234. The time calculation unit 234 calculates the value obtained by subtracting the read cycle counter value of the data receiving unit 232 from the time counter value of the time counter 233 as the time value at which the read request pulse of the signal processing unit 103 was generated. The time calculation unit 234 also receives position coordinate information from the data receiving unit 232 and records the calculated time value at an address on the memory 231 based on the position coordinate information.

[0037] The greater the number of simultaneously generated read requests from the pixel counter 221, the longer the wait time for the read requests. In other words, the value that the read cycle counter should count depends on the number of simultaneously generated read requests. Therefore, the number of counter bits of the read cycle counter 223 should be selected so that it can count the value obtained by multiplying the number of connected signal processing units 103 (M units, where M is an integer equal to or greater than 2) by the number of read cycles. For example, if 256 pixels (M=256) are connected and readout can be performed in one cycle, an 8-bit counter is used. If 256 pixels are connected and readout takes three cycles, an 11-bit counter is used. This allows the timing of a read request to be accurately calculated in any case. The number of counter bits of the read cycle counter 223 may also be determined according to priority. The signal processing unit with the highest priority always has its read request granted, so it does not need to have a read cycle counter 223. However, for ease of design, it is generally preferable to use a similar configuration, even if it is somewhat redundant. Of course, the number of counter bits of the read cycle counter 223 is not limited to these.

[0038] <Device Operation> 7 is a timing chart showing the control of read requests in four (i.e., M=4) signal processing units 103 and the operation of the row readout circuit 230. Here, four of the n signal processing units in the first row (here, signal processing units S11 to S14) are shown as an example, and it is assumed that there are no readout requests from the other signal processing units 103. Note that the illustrated timing chart is an example that satisfies this embodiment, and this embodiment is not limited to the transition timing of these signals.

[0039] T0 to T6 are the times at the rising edges of CLK. Here, an example is shown in which the pixel counters of the signal processing units S11 to S14 exceed the thresholds between T0 and T6, and the readout request is established. Note that among the signal processing units S11 to S14, the smaller the horizontal number, the higher the readout priority.

[0040] First, each of the signals shown in Fig. 7 will be described. The pixel counter saturation pulse is a signal that the pixel counter 221 issues upon receiving a pulse from the pulse generation unit 210. The read request is a signal that the read request unit 222 issues in synchronization with CLK upon receiving a pixel counter saturation pulse. The read cycle counter is the counter value of the read cycle counter 223. The time counter is the counter value of the time counter 233. The pulse detection time is an output signal of the calculation result of the time calculation unit 234. The position coordinate information is position coordinate information that the row readout circuit 230 receives from the signal processing unit.

[0041] Signal processing units S11, S12, and S14 issue pixel counter saturation pulses at any timing between times T0 and T1, and signal processing unit S13 issues pixel counter saturation pulses at any timing between times T1 and T2.

[0042] The signal processing unit S11 receives the pixel counter saturation pulse and issues a read request at time T1. As described above, the signal processing unit S11 has the highest priority, so it stops issuing read requests at time T2. Also, at time T2, the signal processing unit S11 transfers "1" as the read cycle counter value and "1" as the position coordinate information.

[0043] The signal processing unit S12 receives the pixel counter saturation pulse and issues a read request at T1. At T2, it receives the read request signal issued by the signal processing unit S11 as an arbitration signal and extends the read request. It also counts up the read cycle counter. At T3, in response to the read request from the signal processing unit S11 being stopped, it transfers "2" as the read cycle counter value and "2" as the position coordinate information.

[0044] Similarly, the signal processing unit S13 issues a read request at T2. At T3, the read request is extended and the read cycle counter is counted up. At T4, "2" is transferred as the read cycle counter value and "3" is transferred as the position coordinate information.

[0045] Similarly, the signal processing unit S14 issues a read request at T1. At T2 to T4, the read request is extended and the read cycle counter is counted up. At T5, "4" is transferred as the read cycle counter value and "4" is transferred as the position coordinate information.

[0046] The row readout circuit 230 calculates the pulse detection time, which is the time when S11 detected the pixel counter saturation pulse, by subtracting the readout cycle counter received from S11 at T3 from the time counter. The row readout circuit 230 also records the calculated pulse detection time in a memory address corresponding to the position coordinate information received at the same time. Similarly, the row readout circuit 230 also records the calculated pulse detection time in a memory address based on the position coordinate information at T4 to T6.

[0047] In this example, the pulse detection times of the signal processing units S11 to S14 are as follows: This makes it possible to calculate accurate times regardless of the delay time (number of delay cycles) caused by the extension of the read request. S11: 13-1=12 S12: 14-2=12 S13: 15-2=13 S14: 16-4=12

[0048] As described above, according to the first embodiment, the timing of generating a read request is calculated using a read cycle counter. This makes it possible to accurately calculate the timing of generating a read request even if read requests collide among multiple pixels that share a time counter and a data signal line. In particular, by sharing a time counter with multiple pixels, which has a large circuit scale, it is possible to reduce the circuit scale of the pixel circuit region 22.

[0049] As a result, the circuit area per pixel can be reduced, making it possible to realize a high-resolution pixel array. Also, by sharing a time counter that is always running, it is possible to significantly reduce power consumption. Although a readout cycle counter is added to each signal processing unit, the operating time is limited, so the impact on power consumption can be kept small.

[0050] (Second embodiment) The second embodiment describes a configuration that is effective for sensors that do not have a pixel counter, such as ToF. In the first embodiment, a pixel counter is provided, and each pixel that shares a time counter can calculate the exact time at which the read requests were made and sequentially read out even if all read requests are issued simultaneously. However, if a certain number of read requests or more collide, the readout can be stopped. This reduces the number of bits in the read cycle counter and the circuit size while still allowing accurate time calculation for collisions between read requests that occur frequently and are relatively few in number.

[0051] <Device configuration> 8 is a diagram showing an example of the configuration of a pulse processing unit 220 according to the second embodiment. Note that other configurations are the same as those in the first embodiment (FIGS. 1 to 4), and therefore descriptions thereof will be omitted.

[0052] The pulse processing unit 220 includes a read request unit 300, a read cycle counter 301, and a coordinate holding unit 224. The coordinate holding unit 224 operates in the same manner as in the first embodiment, so the same reference numerals are used and the description will be omitted.

[0053] The read request unit 300 receives the photon detection pulse output from the pulse generation unit 210 and transmits a read request to the signal read circuit 111 via the read request signal line 114. The read request unit 300 also issues a read request issuance signal to the read cycle counter 301. The read request unit 300 controls the read request depending on whether or not there is a "high priority read request" from another signal processing unit with a higher priority. Priorities are determined in advance for each of the multiple signal processing units 103 and are held in the read request unit 300. The pulse processing unit in the signal processing unit with the highest priority operates in the same manner as the configuration example shown in FIG. 8, assuming that the high priority read request is always stopped (low).

[0054] Next, a method for controlling read requests by the read request unit 300 will be described. When no read request has occurred in the signal processing unit to which the read request unit 300 belongs, the read request unit 300 transmits a high-priority read request from another signal processing unit with a higher priority as is. When a read request has occurred in the signal processing unit to which the read request unit 300 belongs, and at the same time a read request from another signal processing unit with a higher priority has occurred (High), the read request unit 300 transmits the read request to the signal read circuit 111 and extends the read request of the signal processing unit to which the read request unit 300 belongs by one cycle. Furthermore, when a read request issuance signal has been issued to the read cycle counter 301, the read request is similarly extended.

[0055] If a read request from another signal processing unit 103 with a higher priority is stopped (low), the read request unit 300 determines that the read request of the signal processing unit to which it belongs has been permitted, and stops the read request (low). Furthermore, the read request unit 300 issues a transfer permission signal (high) to the read cycle counter 301 and the coordinate holding unit 224. Furthermore, if a read request clear signal is received from the read cycle counter 301, it determines that the read request for the pixel corresponding to the signal processing unit to which it belongs has not been permitted within a specified time, stops the read request (low), and waits for the reception of a new photon detection pulse.

[0056] The read cycle counter 301 is a (for example, 3-bit) counter that counts the number of cycles from the issuance of a read request to the time when reading is permitted. The read cycle counter 301 starts counting upon receiving a read request issuance signal from the read request unit 300, stops counting upon receiving a transfer permission signal, and transmits the read cycle counter value to the signal read circuit 111 via the data signal line 113. On the other hand, if a carry occurs from the most significant bit of the read cycle counter before receiving the transfer permission signal (i.e., if the count value is saturated), the read cycle counter 301 issues a request clear signal to the read request unit 300.

[0057] The greater the number of read requests simultaneously generated by the pulse generation unit 210, the longer the waiting time for the read requests. On the other hand, since the read cycle counter 301 can clear read requests, if simultaneous detection of photons occurs at a certain number of pixels or more, which is a low probability, the readout can be canceled while preparing for the reception of the next photon. For example, if 256 pixels are connected and readout can be performed in one cycle, a 3-bit counter can be used to allow simultaneous detection of photons from up to eight pixels while reducing the circuit size. Even if 256 pixels are connected and readout takes three cycles, a 5-bit counter can be used to simultaneously detect photons from up to eight pixels. Note that the number of counter bits in the read cycle counter 301 is not limited to this.

[0058] As described above, according to the second embodiment, it is possible to accurately calculate the time for collisions of read requests, which occur frequently and are relatively few in number, while reducing the number of bits of the read cycle counter and reducing the circuit scale.

[0059] (Other Examples) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0060] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0061] 103 signal processing unit; 112 control line; 113 data signal line; 114 read request signal line; 210 pulse generation unit; 220 pulse processing unit

Claims

1. M (M is an integer of 2 or more) detection elements each having a detection pixel that detects the incidence of a photon and a generation unit that generates a read request and data based on the photon detection at the detection pixel; a read circuit for receiving read requests and data from each of the M detector elements; a control pulse supply unit that supplies control pulses to the M detection elements and the readout circuit; Equipped with The generation unit of each of the M detection elements a cycle counter that counts the number of delay cycles from when the read request is issued until when the read request is permitted; a coordinate storage unit that stores position coordinate information of a detection element corresponding to the generation unit; a data generating unit that generates the data including the number of delay cycles and the position coordinate information; and The readout circuit includes: a time counter that counts time based on the control pulse; Memory and and The read circuit determines a generation timing at which the read request was generated based on the number of delay cycles included in the data corresponding to the received read request and the counter value of the time counter, and records the generation timing at a position in the memory corresponding to the position coordinate information included in the data corresponding to the received read request. An imaging device characterized by:

2. the generation unit of each of the M detection elements further includes a pixel counter that counts the number of photons detected in the detection pixel; The data generating unit generates the data including the number of detected photons, the number of delay cycles, and the position coordinate information.

2. The imaging device according to claim 1.

3. The readout circuit includes: a first receiving unit that receives a read request from each of the M detecting elements via a first signal line shared by the M detecting elements; a second receiving unit that receives data from each of the M detecting elements via a second signal line shared by the M detecting elements; Further having 3. The imaging device according to claim 1, wherein the imaging device is a lens.

4. The read circuit determines the time obtained by subtracting the time indicated by the number of delay cycles included in the data from the time indicated by the time counter as the generation timing.

4. The imaging device according to claim 3.

5. The generating unit generates the read request when the count value of the pixel counter exceeds a threshold.

3. The imaging device according to claim 2.

6. The threshold is the saturation value of the pixel counter 6. The imaging device according to claim 5.

7. the cycle counter issues a read request clear signal when the count value of the cycle counter is saturated before the read request is permitted; When the read request clear signal is issued, the generation unit stops the read request in the generation unit and waits for a new photon detection in the detection pixel.

7. The imaging device according to claim 1, wherein the imaging device comprises: a first lens;

8. The cycle counter is a counter capable of counting a value obtained by multiplying M by the number of read cycles.

8. The imaging device according to claim 1, wherein the imaging device comprises: a first lens;

9. The M detection elements are arranged on a two-dimensional plane, The position coordinate information is based on the position coordinates of the corresponding detection element on the two-dimensional surface.

9. The imaging device according to claim 1, wherein the imaging device comprises: a first lens;

10. The detection pixel is an avalanche photodiode (APD).

10. The imaging device according to claim 1, wherein the imaging device comprises: a first lens;

11. A control method for an imaging device, comprising: The imaging device is M (M is an integer of 2 or more) detection elements each having a detection pixel that detects the incidence of a photon and a generation unit that generates a read request and data based on the photon detection at the detection pixel; a read circuit for receiving read requests and data from each of the M detector elements; a control pulse supply unit that supplies control pulses to the M detection elements and the readout circuit; Equipped with The generation unit of each of the M detection elements a cycle counter that counts the number of delay cycles from when the read request is issued until when the read request is permitted; a coordinate storage unit that stores position coordinate information of a detection element corresponding to the generation unit; a data generating unit that generates the data including the number of delay cycles and the position coordinate information; and The readout circuit includes: a time counter that counts time based on the control pulse; Memory and and The control method includes: a step of determining, by the read circuit, a generation timing of the read request based on the number of delay cycles included in data corresponding to the received read request and the counter value of the time counter; the reading circuit recording the generation timing at a position in the memory corresponding to the position coordinate information included in the data corresponding to the received read request; Contains A control method comprising:

Images