Semiconductor structures and methods

Abstract

The present disclosure relates to a semiconductor structure (100) comprising a crystalline silicon substrate (110) having a surface (111) and a crystalline silicon oxide superstructure (120) on the surface (111) of the silicon substrate (110), the silicon oxide superstructure (120) having a thickness of at least two monolayers and a (1x1) planar structure using Wood's notation. The present disclosure also relates to a method for forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, the method comprising providing a silicon substrate having a substantially clean deposition surface in a vacuum chamber and oxidizing the silicon substrate at an oxidation temperature T in the range of 100-530°C. O The silicon substrate is heated to 1000 K, and molecular oxygen (O2) is injected at 1×10 -8 ~1×10 -4 Oxidation pressure P in the mbar range O and oxygen dose D in the range of 0.1 to 10,000 L (Langmuir) O and a process of supplying the same into a vacuum chamber.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor structures and methods of forming the same. In particular, the present disclosure relates to silicon oxide structures for surface passivation of silicon-based semiconductor devices. [Background technology]

[0002] Silicon is the most common substrate material for conventional semiconductor devices such as transistors, capacitors, diodes, photodiodes, and other types of microelectronic and photonic components. In all such devices, the interface quality of the substrate is of paramount importance.

[0003] In conventional devices, the surface of a silicon substrate is typically passivated by growing a layer of thermal oxide on the surface. However, known oxidation methods result in the silicon oxide layer becoming amorphous. The amorphous nature of such an oxide layer inevitably creates defect states in the passivated silicon surface, which inevitably degrades the performance of devices fabricated on conventionally passivated substrates. Furthermore, conventional oxidation procedures rely on relatively high processing temperatures, which can degrade the properties of the silicon substrate and / or structures fabricated on such substrates. In light of these challenges, it may be desirable to develop new solutions related to the passivation of silicon surfaces.

[0004] Patent Document 1 discloses a method for forming a monolayer of crystalline silicon dioxide by self-limitingly depositing a monoatomic layer of oxygen on an existing silicon surface. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2006 / 0003500 Summary of the Invention

[0006] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] According to a first aspect, there is provided a semiconductor structure comprising a crystalline silicon substrate having a surface and a crystalline silicon oxide superstructure on the surface of the silicon substrate, the silicon oxide superstructure having a thickness of at least two monolayers and a (1x1) planar structure using Wood's notation.

[0008] According to a second aspect, there is provided a method for forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, the method comprising the steps of providing a silicon substrate having a substantially clean deposition surface in a vacuum chamber, and oxidizing the silicon substrate at an oxidation temperature T in the range of 100 to 530°C. O The silicon substrate is heated to 1000 K, and molecular oxygen (O2) is injected at 1×10 -8 mbar (millibar) ~ 1 × 10 -4 Oxidation pressure P in the mbar range O and oxygen dose D in the range of 0.1 to 10,000 L (Langmuir) O and a process of supplying the same into a vacuum chamber.

[0009] This results in the formation of a crystalline silicon oxide superstructure on the deposition surface, the silicon oxide superstructure having a thickness of at least two molecular layers and a (1x1) planar structure using Wood's notation.

[0010] According to a third aspect, the present disclosure relates to the use of a crystalline silicon oxide superstructure having a (1x1) planar structure in Wood's notation in a semiconductor structure to passivate the surface of a crystalline silicon substrate.

[0011] In an embodiment of the third aspect, the semiconductor structure is a semiconductor structure according to the first aspect or any embodiment of the first aspect. In particular, it will be appreciated that in a semiconductor structure according to the first aspect or any embodiment of the first aspect, a crystalline silicon oxide superstructure according to the third aspect can be used to passivate the surface of a crystalline silicon substrate.

[0012] The present disclosure will be better understood from the following detailed description read in light of the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 shows a cross-sectional view of a semiconductor structure. [Figure 2] A method for forming a semiconductor structure is presented. [Figure 3] 3a, 3b, and 3c show scanning tunneling microscope images of the silicon sample. [Figure 4] 4a and 4b show scanning tunneling microscope images of another silicon sample. DETAILED DESCRIPTION OF THE INVENTION

[0014] Unless specifically stated to the contrary, any of the foregoing drawings may not be drawn to scale, as elements of any of the drawings may be drawn in inaccurate proportions relative to other elements of the drawings to emphasize particular structural aspects of the embodiments of the drawings.

[0015] Furthermore, corresponding elements in any two drawing embodiments of the foregoing drawings may not be in proportion to each other in the two drawings in order to emphasize specific structural aspects of the two drawing embodiments.

[0016] FIG. 1 schematically illustrates a partial cross-sectional view of a semiconductor structure 100 according to one embodiment.

[0017] As used herein, "semiconductor" can refer to a material, such as silicon (Si), that has a conductivity intermediate between that of conductive materials, such as metals, and insulating materials, such as many plastics and glass. Semiconductors, such as Si, may or may not have a crystalline structure.

[0018] As used herein, the "crystalline" structure of a material may refer to the constituent elements, such as atomic nuclei, of said material that form an ordered three-dimensional crystal lattice.

[0019] Furthermore, a "semiconductor structure" can refer to a structure that may include all or only a portion of structural portions, layers, and / or other elements of a complete, operational semiconductor component, element, or apparatus, such as a transistor, e.g., a power transistor or phototransistor, a capacitor, a diode, e.g., a photodiode or power diode, a microprocessor, or a photonic device, e.g., a display, a photodetector, or a solar cell. When forming only a portion of such a component, element, or device, the term "structure" can be considered a structure or building block "for" such component, element, or device. In particular, semiconductor structures generally may comprise non-semiconductor materials, such as conductors and / or insulators, in addition to semiconductor materials.

[0020] In the embodiment of FIG. 1, the semiconductor structure 100 comprises a crystalline silicon substrate 110 .

[0021] Throughout this disclosure, "substrate" can refer to a solid that provides a surface, which may be flat or slightly curved, so that material may be placed, deposited, etched, and / or engraved onto that surface. For example, the substrate may comprise a wafer including a semiconductor material such as Si that is suitable for fabricating various semiconductor structures and / or devices, such as integrated circuits, solar cells, or photodetectors.

[0022] As used herein, a "surface" can refer to a finite portion of a generalization of a plane, which can have a non-zero curvature, possibly a position-dependent curvature, and can preferably be smooth. Furthermore, a surface can be connected, i.e., not divided into two separate sub-surfaces, or can be path-connected. Some surfaces can also be simply connected. Additionally or alternatively, a surface can refer to a portion of the outer boundary of a body or element. A surface can specifically refer to a portion or part of the outer boundary of a body or element that is visible from a particular viewing direction.

[0023] The silicon substrate 110 of the embodiment of Figure 1 has a surface 111. In other embodiments, the silicon substrate may generally comprise a surface.

[0024] Surface 111 in the embodiment of Figure 1 is a crystalline surface. In other embodiments, the silicon substrate may at least partially, i.e., partially or entirely, have a crystalline surface.

[0025] Throughout this specification, a "crystalline surface" can refer to the surface of a piece of crystalline material having translational symmetry such that a two-dimensional lattice and / or a two-dimensional unit cell is defined. Additionally or alternatively, a crystalline surface can refer to a surface of a crystalline body, which may or may not extend (substantially) along a crystalline plane of the bulk lattice of said crystalline body.

[0026] Although the surface 111 of the silicon substrate 110 is depicted as a single line segment in FIG. 1, the surface of the silicon substrate may generally include any number of any type of features typical of a crystalline surface, such as adatoms, step adatoms, kink atoms, step atoms, and / or surface vacancies.

[0027] In the embodiment of FIG. 1, the semiconductor structure 100 also includes a crystalline silicon oxide superstructure 120 on the surface 111 of the silicon substrate 110 .

[0028] In this disclosure, a "superstructure" can refer to a layer disposed on any structure, e.g., a crystalline structure, portion, or element. Additionally, a "layer" can refer to a generally sheet-shaped element disposed on a surface or body. Additionally or alternatively, a layer can refer to one of a series of superimposed, overlapped, or stacked generally sheet-shaped elements.

[0029] Additionally, "silicon oxide" may refer to a binary compound containing Si and oxygen (O). Silicon oxide may be stoichiometric silicon oxide (SiO2) and / or non-stoichiometric silicon oxide (SiO X Silicon oxide may or may not contain trace amounts of elements other than Si or O as impurities.

[0030] The silicon oxide superstructure 120 of the embodiment of FIG. 1 has a thickness of at least two monolayers. In particular, the silicon oxide superstructure 120 has a thickness of about 3 nanometers (nm). In general, a thicker silicon oxide superstructure can reduce the density of pinholes and / or other defects within the silicon oxide superstructure, while a thinner silicon oxide superstructure can improve the performance of a semiconductor device including the silicon oxide superstructure. In other embodiments, the silicon oxide superstructure can have any thickness of at least two monolayers, such as 1 nm, 2 nm, or 3 nm or more, and / or 10 nm, 7 nm, or 5 nm or less.

[0031] Throughout this specification, "thickness" can refer to an elemental measurement measured perpendicular to the surface of a silicon substrate. Additionally, a thickness of "at least two monolayers" can refer to the combined thickness of at least two units of a repeating structural motif of silicon dioxide, e.g., a crystalline polymorph of quartz (e.g., α-quartz). Additionally or alternatively, a thickness of at least two monolayers can refer to a thickness of about 0.5 nm, or 0.7 nm, or 1 nm or greater.

[0032] Although the silicon oxide superstructure 120 is shown in FIG. 1 as having a constant thickness, the silicon oxide superstructure can generally have a position-dependent, substantially constant, or constant thickness.

[0033] The silicon oxide superstructure 120 of the embodiment of Figure 1 has a (1x1) planar structure using Wood's notation. Such a structure of the silicon oxide superstructure can generally improve the surface quality of the silicon substrate by reducing the surface defect density. In other embodiments, the silicon oxide superstructure can generally have such a structure.

[0034] As known to those skilled in the art, "Wood's notation" is a method for specifying the crystalline structure of an ordered superstructure, such as a layer on the surface of a crystalline substrate, in terms of surface lattice vectors that are derived from the bulk lattice vectors of the crystalline substrate. Use of Wood's notation can be used when the microstructure of the superstructure has symmetry properties that are related to the symmetry properties of the crystalline substrate.

[0035] Here, the term "(1x1) planar structure" can refer to the crystalline microstructure of a superstructure, e.g., an epitaxial superstructure, having a crystal plane extending (substantially) parallel to the surface of a crystal substrate. The crystal plane can have a unit cell, e.g., a primitive unit cell, with two lattice vectors whose lengths can be expressed as (1x1) using Wood's notation. The (1x1) planar structure can specifically refer to a (1x1)R0° structure. In particular, the (1x1) silicon oxide superstructure may or may not refer to a (1x1)R0°-SiO2 structure.

[0036] The presence of a (1x1) silicon oxide superstructure on the surface of a crystalline silicon substrate can generally be directly and positively verified by combining, for example, three types of standard surface characterization methods. First, the superstructure to be tested must be exposed, if necessary, as a layer. X-ray photoelectron spectroscopy (XPS) may then be used to confirm the presence of silicon oxide on the surface. XPS can be followed by low-energy electron diffraction (LEED) analysis. If the LEED analysis shows a (1x1) pattern, scanning tunneling microscopy (STM) can be used. If the STM does not reveal features indicative of the typical reconstruction pattern of a clean, unoxidized silicon surface, but instead reveals features indicative of a row-like pattern with inter-pattern spacings similar and / or substantially equal (e.g., within 25%, 20%, or 10%) to the relevant lattice constant of the surface of the crystalline silicon substrate, then a (1x1) silicon oxide superstructure is present on the surface.

[0037] In the embodiment of FIG. 1 , the semiconductor structure 100 further includes a dielectric capping layer 130 on the silicon oxide superstructure 120. Such a capping layer can generally passivate the silicon oxide superstructure and extend its lifetime. Additionally or alternatively, such a capping layer can facilitate utilization of the semiconductor structure in semiconductor devices such as field-effect transistors or capacitors where a dielectric layer with a sufficiently large thickness and / or dielectric constant is required. In other embodiments, the semiconductor structure may or may not include a capping layer on the silicon oxide superstructure.

[0038] As used herein, a "capping layer" may refer to a layer disposed on a silicon oxide superstructure and may at least partially, i.e., partially or completely, cover said silicon oxide superstructure.

[0039] 1 embodiment may be amorphous. In other embodiments in which the semiconductor structure includes a capping layer, the capping layer may have any suitable at least partially ordered (e.g., crystalline, semi-crystalline, or quasi-crystalline) or disordered (e.g., amorphous) structure.

[0040] 1 embodiment can have a thickness of about 10 nm. A higher thickness of the capping layer can increase the passivation effect provided by the capping layer, while a lower thickness can provide other advantageous features in the semiconductor device. In other embodiments in which the semiconductor structure includes a capping layer, the capping layer can have any suitable thickness, for example, a thickness of 1 nm, 2 nm, or 5 nm or more, and / or a thickness of 500 nm, 250 nm, or 100 nm or less.

[0041] 1 embodiment may comprise a dielectric material having a dielectric constant (K) greater than or equal to 10. Examples of such materials include hafnium oxide (HfO2), tantalum oxide (Ta2O5), hafnium silicate (HfSiO4), titanium oxide (TiO2), strontium titanate (SrTiO3), barium titanate (BaTiO3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), cerium oxide (CeO 2) , yttrium oxide (YO), or mixtures thereof. In other embodiments, the capping layer can include any suitable dielectric material, such as an oxide, nitride, oxynitride, silicate, and / or titanate, which may or may not have a dielectric constant of 10 or greater, 20 or greater, or 50 or greater.

[0042] It should be understood that any of the foregoing embodiments of the first aspect can be used in combination with each other, in other words, several embodiments may be combined together to form further embodiments of the first aspect.

[0043] The foregoing primarily discusses structural and material aspects of semiconductor structures. In the following, greater emphasis will be placed on aspects related to methods for forming semiconductor structures. The implementation methods, definitions, details, and advantages described above related to structural and material aspects apply mutatis mutandis to the methods and aspects discussed below. The same also applies conversely.

[0044] It is to be particularly understood that the method according to the second aspect may be used to provide a semiconductor structure according to the first aspect, and any of the embodiments described in relation to the first aspect. Correspondingly, any semiconductor structure according to any embodiment of the first aspect may be fabricated using the method according to the second aspect.

[0045] FIG. 2 illustrates a method 200 for forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, according to one embodiment.

[0046] 2, method 200 includes providing a silicon substrate having a substantially clean deposition surface in a vacuum chamber in process 201. In other embodiments, a method for forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate may generally include providing a silicon substrate.

[0047] As used herein, a "process" may refer to a series of one or more steps that lead to an end result. As such, a process may be a single-step process or a multi-step process. Furthermore, a process may be divisible into multiple sub-processes, and the individual sub-processes of such multiple sub-processes may or may not share common steps. As used herein, a "step" may refer to an action taken to achieve a predetermined end result.

[0048] Throughout this disclosure, "providing" can refer to the available arrangement of an element or portion in question. "Providing" can include at least partially forming, creating, or manufacturing the element or portion in question. Additionally or alternatively, providing can include the available arrangement of a previously prepared, created, or manufactured element or portion. For example, the process of providing a silicon substrate may or may not include one or more steps performed to form a substantially clean deposition surface of said silicon substrate.

[0049] Throughout this specification, a "deposition surface" can refer to a surface of a silicon substrate onto which additional materials can be introduced and / or adsorbed. In terms of crystal orientation, the deposition surface can be, for example, a silicon {100}, silicon {111}, or silicon {110} surface. In some embodiments, the deposition surface can be a relaxed and / or reconstructed surface, such as a Si(100)(2x1) or Si(111)(7x7) surface. In some embodiments, the deposition surface can be an adsorbate-terminated surface, such as a hydrogen-terminated surface, e.g., Si(100)(1x1)-H.

[0050] A "substantially clean" deposition surface can refer, for example, to a deposition surface that is substantially free of native silicon oxide and other types of impurity atoms, where "substantially free" means that the concentration of foreign atoms and molecules on the silicon surface is less than 3×10 13 cm -2 Such a substantially clean deposition surface may be provided in a clean state beforehand, i.e., prior to the method of forming a semiconductor structure. Alternatively, cleaning of the deposition surface may be included in such a method. Such cleaning may be performed by any suitable cleaning process.

[0051] In the process 201 for providing a silicon substrate of the embodiment of Figure 2, the deposition surface may be a silicon {100} surface. In other embodiments, the deposition surface may be, for example, a silicon {100}, silicon {111}, or silicon {110} surface.

[0052] 2, the process 201 of providing a silicon substrate includes an optional process 202 of cleaning the deposition surface to remove possible native oxides and / or other impurities therefrom prior to the process of providing molecular oxygen. In other embodiments, the process of providing a silicon substrate may or may not include such a process of cleaning the deposition surface. In some embodiments, the deposition surface of the crystalline silicon substrate may be pre-cleaned, for example, by another party.

[0053] The process 202 for cleaning the deposition surface of the embodiment of Figure 2 includes an RCA cleaning step 203. Such an RCA cleaning step may generally facilitate the process of cleaning the deposition surface and / or allow the deposition surface to be cleaned at a lower temperature. In other embodiments, the process for cleaning the deposition surface may or may not include an RCA cleaning step.

[0054] As used herein, an "RCA cleaning step" can refer to a cleaning step in which a deposition surface is exposed to an aqueous SC-1 solution containing water (HO), hydrogen peroxide (HO), and ammonium hydroxide (NHOH), and / or an SC-2 solution containing HO, HO, and hydrochloric acid (HCl). In the RCA cleaning step, silicon oxide may or may not be stripped from the deposition surface after the SC-1 and / or SC-2 immersion by immersing the deposition surface in an aqueous hydrofluoric acid (HF) solution and / or by exposing the deposition surface to HF vapor. Such HF treatments may generally enable high-throughput removal of silicon oxide impurities at lower processing temperatures.

[0055] The process 202 for cleaning the deposition surface of the embodiment of FIG. 2 further includes a pre-annealing step 204 following the RCA cleaning step 203. The pre-annealing step 204 includes a pre-annealing temperature (T A ) and 1 × 10 -4 Pre-annealing pressure (P A ) and pre-annealing duration (t A ) annealing the crystalline silicon substrate for a pre-annealing period of 1000 .mu.m. Such a pre-annealing step can reduce the defect density on the deposition surface of the silicon substrate. In particular, such a reduction in defect density can result in a T low enough for use in metallization samples. A In other embodiments, the process of cleaning the deposition surface may or may not include such a pre-annealing step. In embodiments in which the process of cleaning the deposition surface includes such a pre-annealing step, the crystalline silicon substrate may or may not be annealed under a hydrogen (H) or O ambient. In some embodiments, the process of cleaning the deposition surface includes the T of the pre-annealing step 204 of the embodiment of FIG. A , P A , and / or t A Different from T A , P A , and / or t A In the above embodiment, a pre-annealing step may be performed at a temperature in the range of 210 to 290°C, 220 to 280°C, or 230 to 270°C. A , 1×10 -5 mbar, 1 × 10 -6 mbar, or 1 × 10 -7 P below mbar A , and / or t for 5, 10, or 30 minutes or more A can be used, for example. In some embodiments, the process for cleaning the deposition surface can include an HF dip and / or an HF vapor treatment after the pre-annealing step.

[0056] In the embodiment of FIG. 2, in process 205, the method 200 includes oxidizing a silicon substrate at an oxidation temperature T in the range of 100 to 530° C. O Such a T O This may enable the formation of a crystalline silicon oxide superstructure on a crystalline silicon substrate. O The process can provide a sufficiently low diffusivity of silicon and / or oxygen nuclei to inhibit the formation of a buried oxide layer within the silicon substrate. In other embodiments, methods for forming a crystalline silicon substrate and a semiconductor structure comprising a crystalline silicon oxide superstructure on a silicon substrate can generally include such a process. In other embodiments, a T in the range of 100-530°C, or 150-520°C, or 200-500°C, or 250-480°C, or 300-460°C, or 350-450°C can be used. O can be used.

[0057] In the embodiment of FIG. 2, the method 200 includes, in process 206, heating a silicon substrate to an oxidation temperature T O While maintaining the temperature at 1×10 -8 mbar (millibar) ~ 1 × 10 -4 Oxidation pressure P in the mbar range O Oxygen dose D in the range of 0.1 to 10,000 L (Langmuir) O The method further comprises the step of supplying a crystalline silicon oxide superstructure onto a deposition surface at a rate of 1×10 to 1×10 sq. m. by such means, a crystalline silicon oxide superstructure is formed on the deposition surface, the silicon oxide superstructure having a (1×1) planar structure using Wood's notation. In another embodiment, a method for forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate generally comprises such a process. In the other embodiment, a crystalline silicon oxide superstructure is formed on a deposition surface at a rate of 1×10 to 1×10 sq. m. by such means, the silicon oxide superstructure has a (1×1) planar structure using Wood's notation. -8 mbar~1×10 -5 mbar, or 1 × 10 -7 mbar~1×10 -6 mbar, or 5 × 10 -7 mbar~5×10 -5 P in the mbar range OIn another embodiment, D in the range of 1 to 1000 L, or 5 to 500 L, or 10 to 100 L can be used. O can be used.

[0058] In the process 206 for supplying molecular oxygen in the embodiment of FIG. 2, O2 is supplied for an oxidation duration (t) of 0.5 seconds (s) to 30 minutes (min). O ) for an oxidation period of 1000 s to 30 min. In other embodiments, O2 may be supplied into the vacuum chamber for an oxidation period of any suitable duration. In some embodiments, O2 may be supplied into the vacuum chamber for an oxidation period of 1000 s to 30 min., for example, t ranging from 0.5 s to 30 min., or 30 s to 15 min., or 1 min to 10 min. O can be used.

[0059] 2, the method 200 further includes an optional process 207 of depositing a dielectric capping layer on the silicon oxide superstructure. Such deposition of the capping layer may be accomplished, at least in part, by atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and / or evaporation, for example.

[0060] In particular, the method 200 of the embodiment of FIG. 2 comprises: subjecting a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate to a maximum processing temperature T max and serves as one particular example of a method for forming. max The lower T allows for the use of such techniques in situations requiring tighter thermal budgets. max Lower T can inhibit the formation of silicon carbide (SiC), which in turn can reduce the density of grain boundaries and / or dislocations at the deposition surface after processing. Additionally or alternatively, certain structures, such as metallization structures, fabricated on the substrate may require the use of lower processing temperatures. In other embodiments, the method for forming a semiconductor structure from a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate can be performed using any suitable T max Tmax is, for example, 1200°C or less, or 500°C or less, or 480°C or less, or 460°C or less, or 450°C or less.

[0061] In one embodiment, a method for forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate includes operations corresponding to processes 201, 205, and 206 of the method 200 of the embodiment of FIG.

[0062] In general, in a method of forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, the steps of performing a process corresponding to any of processes 201, 202, 205, 206, 207 of the embodiment method 200 of Figure 2 need not be performed in a fixed order. Furthermore, the method of forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate may include any number of additional processes or steps not disclosed herein in connection with the embodiment method 200 of Figure 2.

[0063] Some examples are described below.

[0064] In the first example, a 6 mm x 12 mm rectangular Si sample was cut from an n-type Si(100) wafer to serve as a crystalline silicon substrate with a Si(100) deposition surface. The Si sample was mounted on a sample holder made of molybdenum (Mo) via its short edge, allowing for direct current (DC) power to be applied through the Si sample. The sample holder was transferred to a manipulator located inside the vacuum chamber of a multichamber vacuum system, and the Si sample was repeatedly and rapidly heated to cleaning temperatures ranging from 1100 to 1200 °C to remove any native oxide and carbon contaminants from the Si(100) deposition surface. LEED analysis revealed a sharp (2x1) + (1x2) reconstruction resulting from the inherent double-domain surface structure. STM images taken after surface cleaning confirmed the presence of the double-domain reconstruction on large two-dimensional terraces.

[0065] After the cleaning phase, the Si sample with a clean Si(100) deposition surface was oxidized in the same vacuum system using O gas introduced into the vacuum chamber through a leak valve. Before opening the leak valve, the temperature of the Si sample was adjusted to the oxidation temperature (T of approximately 450 °C). O Next, the oxidation pressure in the vacuum chamber (P O ) measured with an ion gauge pressure gauge to 1 × 10 -6 The pressure was raised to 100 mbar and the Si sample was heated to T O The oxidation was carried out at 200 L for 200 seconds to obtain an oxidation dose of 200 L. After that, the leak valve was closed and the Si heating was stopped.

[0066] Following oxidation of the Si samples, XPS was used to confirm that the deposited surface of the Si samples contained silicon oxide. Furthermore, LEED analysis of the Si samples showed a simple (1x1) pattern. Typically, such results indicate the formation of an amorphous silicon oxide layer on top of the Si(100) surface, and the (1x1) LEED diffraction spots are believed to arise from the bulk Si(100) surface underlying such an amorphous layer.

[0067] However, as shown in Figure 3a, STM images taken after oxidation revealed the presence of smooth islands on the Si sample. Consistent with the previous XPS and LEED results, no Si dimer row structures were detected on top of the smooth islands. Instead, high-resolution STM images of the smooth islands, as shown in Figures 3b and 3c, revealed row structures with an inter-row distance of approximately 0.39 nm, which is close to the Si(100) lattice constant. In Figure 3b, the rows extend substantially along the direction indicated by the white double-headed arrow on the surface of the oxidized Si sample.

[0068] Overall, the results demonstrate the formation of an epitaxial crystalline silicon oxide superstructure on the deposition surface of the Si sample, a silicon oxide superstructure that follows the lattice structure of the Si substrate. The crystalline structure of the silicon oxide superstructure follows the Si(100)(1x1) plane periodicity. Thus, the silicon oxide superstructure has a (1x1) planar structure using Wood's notation.

[0069] Furthermore, the (1x1) LEED pattern of the Si sample was stronger than the typical pattern of a Si(100) surface covered with an amorphous silicon oxide layer, especially when the surface-sensitive electron binding energy was about 100 electron volts (eV). Such a high-intensity LEED pattern is consistent with the STM image, indicating the formation of an epitaxial silicon oxide superstructure.

[0070] In the second example, n-type float-zone (FZ) Si wafers and p-type FZ Si wafers with a resistivity of 3 ohm-meters (Ωm) and a diameter of 102 mm (4 inches) served as crystalline silicon substrates with a Si(100) deposition surface. The deposition surfaces of the Si wafers were cleaned with standard RCA cleaning steps, including both RCA-1 and RCA-2, followed by heating at 1050 °C in an oxygen atmosphere. A A pre-annealing step was performed at 200 °C. This resulted in the growth of an amorphous silicon oxide layer, which was etched using a buffered hydrofluoric acid (HF) aqueous solution, after which the wafer was introduced into the vacuum chamber of an industrial ultra-high vacuum (UHV) system. To complete the process of cleaning the deposition surface, the Si wafer was heated at 200 °C until outgassing ceased. A The wafer was subjected to a pre-annealing step at .

[0071] After the cleaning process, the wafer was oxidized by introducing O gas into the vacuum chamber through a leak valve using oxidation parameters similar to those in the first example. This resulted in the formation of a crystalline silicon oxide superstructure on the wafer's deposition surface. Following oxidation, the wafer was cooled and transferred to an ALD system, which was used to grow a capping layer of AlO approximately 20 nm thick on the silicon oxide superstructure using trimethylaluminum (TMA) and water as precursors.

[0072] Finally, the corona discharge oxide characterization of semiconductors (COCOS) technique was employed to evaluate the defect density at the interface between a crystalline silicon wafer and an overlying crystalline silicon oxide superstructure. Based on the results of such COCOS measurements, a reduced interfacial defect density was observed at the interface. The results are consistent with separate carrier lifetime measurements, which showed that the substrate with the overlying crystalline silicon oxide superstructure exhibited an increased minority carrier lifetime.

[0073] In a third example, a 6 mm × 12 mm Si sample was cut from a vicinal, i.e., off-cut, Si(111) wafer to serve as a crystalline silicon substrate. Cleaning and oxidation of the Si sample was performed at a lower T of about 400 °C. O The same procedure and process parameters were used as in the first example, except that HCl was used for the oxidation.

[0074] Scanning tunneling spectroscopy (STS) of a visually cleaved Si(111) surface revealed a surface bandgap of approximately 5 eV after oxidation, indicating the formation of a silicon oxide superstructure on the surface. Furthermore, STM images taken after oxidation revealed the presence of row structures that follow the hexagonal lattice structure of the Si substrate, as shown in Figures 4a and 4b.

[0075] Overall, the results of the STS and STM measurements indicate that a crystalline silicon oxide superstructure forms on the vicinal Si(111) surface of the Si sample. Based on the results, the crystalline structure of the silicon oxide superstructure follows the periodicity of the Si(111)(1x1) surface.

[0076] It is obvious to those skilled in the art that with the advancement of technology, the basic concept of the present invention can be implemented in various ways. Therefore, the present invention and its embodiments are not limited to the above examples, but instead can be modified within the scope of the claims.

[0077] It should be understood that any benefits and advantages described above may relate to one embodiment or to multiple embodiments, and embodiments are not limited to those that solve any or all of the stated problems or that have any or all of the stated benefits and advantages.

[0078] The term "comprising" is used herein to mean including the feature or act that follows it without excluding the presence of one or more additional features or acts. Further, reference to "an" or "an" item should be understood to refer to one or more of those items. [Explanation of symbols]

[0079] 100 Semiconductor Structure 110 Silicon substrate 111 Surface 120 Silicon oxide superstructure 130 Capping Layer 200 ways 201 Provision of silicon substrate 202 Cleaning of deposition surface 203 RCA Cleaning Steps 204 Pre-annealing step 205 Heating of silicon substrate 206 Molecular Oxygen Supply 207 Deposition of Dielectric Capping Layer

Claims

1. A semiconductor structure (100) comprising a crystalline silicon substrate (110) having a surface (111) and a crystalline silicon oxide superstructure (120) on the surface (111) of the silicon substrate (110), the silicon oxide superstructure (120) having a thickness of 3 nm or more and 10 nm or less and a (1x1) planar structure using Wood's notation; The semiconductor structure (100) further comprises a dielectric capping layer (130) on the silicon oxide superstructure.

2. The semiconductor structure (100) of claim 1, wherein the surface (111) is a silicon {100}, silicon {111}, or silicon {110} surface.

3. The semiconductor structure (100) of claim 1, wherein the capping layer (130) comprises a dielectric material having a dielectric constant K of 10 or greater.

4. 1. A method (200) for forming a semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, the method (200) comprising: a process (201) of providing said silicon substrate having a substantially clean deposition surface in a vacuum chamber; The silicon substrate is oxidized at an oxidation temperature T in the range of 100 to 530°C. Ｏ a process (205) of heating to While maintaining the silicon substrate at the oxidation temperature, molecular oxygen O ２ 1 x 10 －８ mbar (millibar) to 1 x 10 －４ Oxidation pressure P in the range of mbar Ｏ and an oxygen dose D in the range of 0.1 to 10,000 L (Langmuir). Ｏ and (206) providing the solution in a vacuum chamber with This results in the silicon oxide superstructure being formed on the deposition surface, the silicon oxide superstructure having a thickness of at least 3 nm and not more than 10 nm, and a (1x1) planar structure using Wood's notation.

5. 5. The method (200) of claim 4, wherein the deposition surface is a silicon {100}, silicon {111}, or silicon {110} surface.

6. The oxidation temperature T Ｏ The method (200) according to claim 4 or 5, wherein is in the range of 150 to 520°C.

7. The oxidation pressure P Ｏ But 1 x 10 －８ mbar to 1 x 10 －５ The method (200) according to any one of claims 4 to 6, wherein the temperature is in the range of 1000 to 10 ...

8. The oxygen dose D Ｏ The method (200) of any one of claims 4 to 7, wherein is in the range of 1 to 1000 L.

9. The molecular oxygen O ２ is the oxidation duration t of 0.5 seconds to 30 minutes. Ｏ The method (200) of any one of claims 4 to 8, wherein the heating element is supplied into the vacuum chamber over a period of time.

10. 10. The method (200) according to any one of claims 4 to 9, wherein the step (201) of providing a silicon substrate comprises a step (202) of cleaning the deposition surface to remove any native oxides and / or other impurities that may be present before the step of supplying molecular oxygen.

11. The process (202) of cleaning the deposition surface includes an RCA cleaning step (203) followed by a pre-annealing temperature T of 200-300° C. Ａ and 1 × 10 －４ Pre-annealing pressure P below mbar Ａ and a pre-annealing duration t of 1 minute or more. Ａ and a pre-annealing step (204) for a pre-annealing period of .

12. The method (200) of any one of claims 4 to 11, further comprising the process (207) of depositing a dielectric capping layer on said silicon oxide superstructure.

13. Maximum processing temperature T ｍａｘ The method (200) of any one of claims 4 to 12, wherein is not more than 500°C.

14. The method (200) of any one of claims 4 to 13, wherein the semiconductor structure is a semiconductor structure (100) of any one of claims 1 to 4.

15. A method for passivating the surface of a crystalline silicon substrate by using a crystalline silicon oxide superstructure having a (1x1) planar structure in Wood's notation in a semiconductor structure.

16. The use according to claim 15, wherein the semiconductor structure is a semiconductor structure (100) according to any one of claims 1 to 3.

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