Photodetectors, photodetector arrays and distance measurement systems

Abstract

A photodetector (1) comprises a single-photon avalanche diode (SPAD) (10) and a first resistor (11) connected in series to the SPAD (10), and during a recharge time in which an electric charge is discharged from the SPAD (10) via the first resistor (11), the electric charge disappears from a multiplication region of the SPAD (10).

Description

[Technical Field]

[0001] The present disclosure relates to a photodetector, and more particularly to a photodetector such as a solid-state imaging device capable of detecting weak light, a photodetector array, and a distance measurement system. [Background technology]

[0002] In recent years, SPADs (Single Photon Avalanche Diodes) have been used in a wide range of fields, including medicine, communications, biology, chemistry, monitoring, automotive applications, and radiation detection. SPADs are photodiodes that have enhanced light detection sensitivity by multiplying signal charges generated by photoelectric conversion using the avalanche breakdown phenomenon (see Patent Document 1 and Non-Patent Documents 1 to 5). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-176782 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure aims to provide a photodetector, a photodetector array, and a distance measurement system that reduce the quenching dead time. [Means for solving the problem]

[0005] In order to achieve the above object, a photodetector according to one embodiment of the present disclosure comprises a single photon avalanche diode (hereinafter referred to as SPAD) and a first resistor connected in series to the SPAD, and during a recharge time when charge is discharged from the SPAD through the first resistor, charge is removed from the multiplication region of the SPAD.

[0006] Here, the excess bias voltage applied to the SPAD may be smaller than the breakdown voltage of the SPAD, and the resistance value R of the first resistor may satisfy the equation (21) described below.

[0007] Furthermore, a photodetector array according to one embodiment of the present disclosure includes N of the above-described photodetectors (N is an integer greater than or equal to 2), the N series circuits included in the N photodetectors are connected in parallel, each of the N series circuits has the SPAD and the first resistor connected in series, one end of the N series circuits that is on the SPAD side is connected to each other, and further includes a second resistor connected to the one end of the N connected photodetectors and connected in series with the N photodetectors, and the resistance value of the second resistor is smaller than 1 / N of the resistance value of the first resistor.

[0008] In addition, a distance measurement system according to one aspect of the present disclosure includes a light receiving unit having a photodetector, a light emitting unit that emits light toward an object to be measured, and a control unit that controls the light receiving unit and the light emitting unit, and the control unit receives a signal corresponding to the reflected light reflected by the object to be measured from the light receiving unit and calculates the distance to the object to be measured. [Effects of the Invention]

[0009] The photodetector, photodetector array, and distance measurement system of the present disclosure can reduce the quenching dead time. [Brief explanation of the drawings]

[0010] [Figure 1A] FIG. 1A is a diagram illustrating an example of a circuit of a photodetector according to an embodiment. [Figure 1B] FIG. 1B is a diagram showing a list of physical quantities used in the simulation of FIG. 1A. [Figure 1C] FIG. 1C is a diagram showing a list of physical constants used in the simulation of FIG. 1A. [Figure 2]FIG. 2 shows the voltage fluctuation and the time change in the number of electrons in the depletion layer calculated from the simulation. [Figure 3] FIG. 3 is a diagram showing the change over time of the reverse bias voltage when avalanche multiplication occurs. [Figure 4] FIG. 4 is a diagram illustrating an example of a circuit of the photodetector according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing a modified example of the photodetector according to the first embodiment. [Figure 6] FIG. 6 is an example of a diagram showing whether quenching occurs or not with respect to the excess bias voltage and the resistance value of the first resistor. [Figure 7] FIG. 7 is an example of a diagram showing whether quenching occurs or not with respect to the capacitance value of the first capacitor and the resistance value of the first resistor. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of a control system including a photodetector according to the second embodiment. [Figure 9] FIG. 9 is a block diagram showing another example of the configuration of a control system including a photodetector according to the second embodiment. [Figure 10] FIG. 10 is a circuit diagram of a photodetector that realizes the control system of FIG. 8 or FIG. [Figure 11] FIG. 11 is a diagram illustrating an example of a circuit of a photodetector array according to the third embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of a circuit of a solid-state imaging device according to the third embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a layout of the solid-state imaging device of FIG. 12 in plan view. [Figure 14] FIG. 14 is a diagram showing a modification of the layout of the solid-state imaging device of FIG. 13 in plan view. [Figure 15] FIG. 15 is a diagram showing an example of a cross-sectional configuration of the solid-state imaging device taken along line XV-XV in FIG. [Figure 16] FIG. 16 is a diagram showing a modification of the cross-sectional configuration of the solid-state imaging device taken along line XV-XV in FIG. [Figure 17]FIG. 17 is a diagram showing another example of the cross-sectional configuration of the solid-state imaging device according to the third embodiment. [Figure 18] FIG. 18 is a schematic layout diagram showing the entire solid-state imaging device of FIG. 17 in plan view. [Figure 19] FIG. 19 is a block diagram illustrating an example of a distance measurement system using a photodetector or photodetector array according to the present disclosure. [Figure 20] FIG. 20 is a diagram showing an example of a timing chart in the distance measurement system of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Findings that formed the basis of this disclosure) The present inventors have found that the following problems occur with the SPAD (Single Photon Avalanche Diode) described in the "Background Art" section.

[0012] Non-Patent Document 1 presents a configuration in which a circuit element (quenching element or quenching resistor) such as a resistor or transistor called a quenching element is connected in series with the SPAD in order to instantly stop (quench) the charge multiplication caused by the avalanche breakdown of the SPAD. Furthermore, the document describes the results of a simulation, and on page 131 it states that the resistance value is 300 kΩ. However, there is no specific information about the device structure of the SPAD or the circuit constants. number No formulas or relationships are disclosed.

[0013] Non-Patent Document 2 discloses a configuration that shortens the quenching dead time by controlling the reverse bias voltage across the SPAD in accordance with the output from the SPAD. Here, the quenching dead time refers to the time from the start of avalanche multiplication until the reverse bias voltage applied to the SPAD changes and returns to a state where multiplication is possible again.

[0014] However, the structure for controlling the quenching resistance of the SPAD is not disclosed, and the resistance value required for the quenching resistance, the structure or characteristic values ​​or bias conditions of the SPAD, specifically the capacitance and breakdown voltage (V BD The relationship between the depletion layer width and excess bias voltage (Vex) is not shown.

[0015] Patent Document 1 presents a configuration for controlling the reverse bias voltage applied to the APD in accordance with the current flowing through the APD, but does not disclose control of the quenching resistance or the capacitance of the APD.

[0016] Here, quenching is one of the operating principles of SPAD, and refers to immediately stopping avalanche multiplication at a certain multiplication factor. SPAD is an avalanche photodiode that is used above the breakdown voltage and can multiply and detect electrons generated from single photons by avalanche multiplication.

[0017] The inventors have found through dynamic simulations of quenching that the requirement for the quenching resistance of a SPAD is that "carriers must disappear from the depletion layer during the quenching recharge process," and have found the resistance condition as shown in equation (21) below.

[0018] Based on this discovery, the quenching resistor can be set lower or actively controlled, shortening the quenching recharge time, or dead time, compared to conventional SPADs, thereby improving the sensitivity and expanding the dynamic range of the SPAD.

[0019] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0020] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0021] (Simulation on which this disclosure is based) First, the simulation on which this disclosure is based will be described.

[0022] 1A is a diagram showing an example circuit of a photodetector 1 according to an embodiment. In addition to the photodetector 1, the diagram also shows a power supply 13. This example circuit is a circuit diagram related to a simulation on which the present disclosure is based.

[0023] The photodetector 1 includes a SPAD 10, a first resistor 11 connected in series to the anode of the SPAD 10, and a first capacitance 12 connected in parallel to the SPAD 10. In FIG. 1A, the first resistor 11 is connected to the cathode of the SPAD 10, but it can also be connected to the anode. A reverse bias voltage equal to or greater than the breakdown voltage is applied to the SPAD 10, at least in an idling state where no charge exists in the depletion layer. The first capacitance 12 is the capacitance of the cathode of the SPAD 10 and includes the parasitic capacitance of the SPAD 10. That is, the first capacitance 12 includes parasitic components such as the junction capacitance and wiring capacitance of the SPAD 10, and is not necessarily an external capacitance, and the type is not limited. In other words, the first capacitance 12 is the parasitic capacitance of the SPAD 10 when there is no external capacitance, or the sum of the parasitic capacitance of the SPAD 10 and the capacitance component in parallel with the SPAD 10 when there is external capacitance.

[0024] The simulation using the circuit in Figure 1A simulates the time evolution of carriers within the SPAD 10. Figure 1B shows the physical quantities used in the simulation. Figure 1C shows the physical constants used in the simulation. Note that the physical constants marked with (*1) in Figure 1C are taken from Non-Patent Document 3. Physical constants marked with (*1) or (*2) can take on different values ​​depending on the material, temperature, etc. Physical constants marked with (*3) are arbitrarily set parameters determined by the externally applied voltage, device structure, impurity concentration, etc. This simulation and the physical constants in Figure 1C assume silicon, but this is not a limitation and the material may be changed. In this case, the physical constants in Figure 1C can be changed accordingly. Other examples of materials include germanium, gallium arsenide, gallium nitride, indium phosphide, and selenium.

[0025] The time change in the number of electrons and holes in the depletion layer of the SPAD 10 when avalanche multiplication occurs due to one photon is described by the differential equations (1) and (2).

[0026]

number

[0027] Here, the impact ionization rate satisfies the following relational expression:

[0028]

number

[0029] The charge generated by avalanche multiplication is temporarily held in the first capacitor 12 and is then discharged to the power supply 13 via the first resistor 11. At this time, the voltage applied across the SPAD 10 and the magnitude of the internal electric field in the multiplication region within the SPAD 10 change according to equations (5) to (7).

[0030]

number

[0031] Moreover, the following equation (8) shows the voltage variation ΔV from the initial state.

[0032]

number

[0033] Figure 2 shows the voltage fluctuations calculated from the above simulation and the voltage fluctuations in the depletion layer. electronic This figure shows the time change in the number of electrons. The vertical axes in Figures 2(a) and (b) represent the absolute value of the voltage fluctuation ΔV occurring in the reverse bias voltage applied to the SPAD 10. The vertical axes in Figures 2(c) and (d) represent the number of electrons n in the depletion layer. The horizontal axes represent time change. Figure 2 shows the simulation results for an initial voltage of V0 = 29 V. The breakdown voltage of the SPAD 10, obtained from the physical constants in Figure 1C, is 27.5 V, and Vex = 1.5 V. t = 0 is the time when avalanche multiplication begins, meaning the time when one electron-hole pair is generated in the multiplication region. Figure 2(a) shows an example of the simulation results when the resistance value of the first resistor 11 is R = 65 kΩ and quenching is not possible. Between 100 and 200 ps, ​​the charge generated by avalanche multiplication accumulates in the capacitance, causing ΔV to swing approximately 2.6 V. After that, ΔV decreases as the charge is discharged (recharged) through the resistor, and after ΔV reaches ΔV ~ 0.9 V at t ~ 730 ns, ΔV increases again. After that, ΔV continues to oscillate at damping, eventually reaching 1.5 V. Since ΔV does not return to 0, the avalanche multiplication has not stopped and quenching has not occurred.

[0034] On the other hand, (b) of FIG. 2 shows an example of a simulation result in which quenching is possible when the resistance value R of the first resistor 11 is 70 kΩ. After the voltage swings to about 2.6 V at t~200 ps, ​​ΔV drops due to recharge, and ΔV becomes 0 at t~2 ns, so that avalanche multiplication stops and quenching is possible. In this way, the maximum voltage swing at quenching in the photodetector of the present disclosure is surplus. biasGreater than voltage Vex.

[0035] According to the change in the number of electrons in the depletion layer over time at R=65k ohms in Figure 2(c), even while ΔV is decreasing due to recharge, the number of electrons in the depletion layer, n(t), is always 1 or more, so avalanche multiplication occurs again based on the electrons remaining in the depletion layer.

[0036] According to the change in the number of electrons in the depletion layer over time for R=70 kΩ in Figure 2(d), the electrons disappear from the depletion layer at t~380 ps during recharge, so avalanche multiplication does not occur again.

[0037] This simulation shows that the condition for achieving quenching in the SPAD10 is that carriers must be removed from the depletion layer during the recharge process, and that quenching can be reliably achieved by setting the resistance value based on this condition. Furthermore, by lowering the resistance value within a range that satisfies this condition, it is possible to shorten the dead time, improve sensitivity, and expand the dynamic range.

[0038] Here, the resistance value R of the first resistor 11 that satisfies the quenching condition that carriers disappear from the depletion layer during the recharge process can be analytically calculated as follows: BD If σ is sufficiently small relative to σ, it can be approximated linearly as in equations (9) and (10).

[0039]

number

[0040] however,

[0041]

number

[0042]

number

[0043] Furthermore, Vex is V BD When Nc(t) is sufficiently small for n(t), Nc(t)>>n(t), so equation (6) becomes

number

[0044]

number

[0045] however,

number

number

number

[0046] Here, the integral on the right side of equation (17) is as follows:

[0047]

number

[0048] The integration in equation (19) is performed approximately using FIG. 3. Specifically, FIG. 3 is a diagram showing the time change of the reverse bias voltage V when avalanche multiplication occurs. The difference between the area of ​​region A and the area of ​​region B is τ q The value divided by Vex is the integral value of the right side of equation (17), and the area A has vertical Vex and horizontal t BD The area B can be approximated as a rectangle with height Vex and base RCln(2).

number

[0049] Since the condition for quenching is that the value of equation (19) is less than 1, the requirement for the resistance value R of the first resistor 11 is as follows:

[0050]

number

[0051] The condition of equation (19) is almost the same as the condition that the time from the start of avalanche multiplication until all the charges are discharged is shorter than the time until the voltage returns due to recharge. The resistance value R calculated by substituting the physical constants in FIG. 1C into the right side of equation (21) is 68 kΩ, which is consistent with the result in FIG. 2. Here, the dead time obtained from equation (21) is RC, which is the recharge time by the first resistor 11,

number

[0052] Up until now, analysis has been based on the value of the impact ionization rate shown in Non-Patent Document 3, but since the value of the impact ionization rate varies depending on the temperature, internal electric field, and device structure of the SPAD 10, different values ​​may be given depending on the document. In this case, the notation of equation (21) may be changed. For example, the impact ionization rate in Non-Patent Document 4 is as shown in the following equation (9-1).

[0053]

number

[0054] However, the subscript i is expressed as e when the carrier is an electron, and as h when the carrier is a hole. In this case, formula (21) can be rewritten as formula (21-1) below.

[0055]

number

number

[0056] (Embodiment 1) Photodetector 1 according to the first embodiment will be described with reference to FIGS.

[0057] 4 is a diagram showing an example circuit of the photodetector 1 according to the first embodiment. The photodetector 1 includes a SPAD 10, a first resistor 11 connected in series to the cathode of the SPAD 10, a first capacitor 12 connected in parallel to the SPAD 10, and an output unit 14 that outputs the cathode voltage of the SPAD 10. One end of the first resistor 11 is connected to a first power supply V1. The anode of the SPAD 10 is connected to a second power supply V2. The first capacitor 12 may be a parasitic capacitance of the SPAD 10, a capacitive element separate from the SPAD 10, or both.

[0058] When light is incident on the SPAD 10, avalanche multiplication causes large fluctuations in the reverse bias voltage, making it possible to output the presence or absence of incident photons and their number. The first capacitance 12 and the first resistor 11 may be formed using an LSI process or may be configured as external circuit elements. Both ends of the first capacitance 12 do not need to be connected to both ends of the SPAD 10; only one end may be connected. In this case, the capacitance C in equation (21) is contributed by the capacitance connected to the end where the first resistor 11 and the SPAD 10 are connected; in FIG. 4, it is the first capacitance 12 connected to the cathode of the SPAD 10.

[0059] Fig. 5 is a diagram showing a modified example of the photodetector 1 according to embodiment 1. The photodetector 1 in Fig. 5 differs from the configuration in Fig. 4 in that the first resistor 11 is a P-channel transistor, that is, a channel resistor of the first transistor 15, and in that it includes a first variable power supply 16. The following description will focus on the differences.

[0060] The first variable power supply 16 supplies a variable voltage as the gate voltage of the first transistor 15. At this time, the channel resistance of the first transistor 15 due to the gate voltage is set to satisfy the quenching resistance requirement, i.e., equation (21). Here, the first transistor 15 is connected to the cathode of the SPAD 10, but the conductivity type is not limited; for example, an N-type conductivity transistor may be connected to the anode of the SPAD 10.

[0061] Next, we will explain how to determine the quenching resistor using Figures 6 and 7. The requirements for quenching are (i) the resistance value of the quenching resistor, (ii) the capacitance C of the SPAD 10, (iii) the excess bias voltage Vex, (iv) the depletion layer width W, and (v) the breakdown voltage V BD , and the above (i) to (v) are set so as to satisfy equation (21). Figure 6 is an example of a diagram showing whether quenching occurs for the excess bias voltage Vex and the resistance value R of the first resistor 11. The dotted line is the calculation result of equation (21), and the conditions in Figure 1C were used for all conditions except for Vex and R. Quenching can occur in the region to the upper right of the dotted line. However, quenching cannot occur in the region to the lower left, and the SPAD 10 continues avalanche multiplication.

[0062] Figure 7 is an example of a diagram showing whether quenching occurs for different capacitance values ​​C of the first capacitor 12 and R of the first resistor 11. The dotted line shows the calculation results of equation (21), where the conditions in Figure 1C were used for all values ​​except C and R. Quenching can occur in the region to the upper right of the dotted line. However, quenching cannot occur in the region to the lower left, and the SPAD 10 continues avalanche multiplication.

[0063] 6 and 7 illustrate the correspondence between the circuit constants required for quenching and the device structure. In particular, by setting the resistance value R of the first resistor 11 so as to approach the dotted lines in Figures 6 and 7, a SPAD 10 and a quenching circuit with a short dead time can be realized.

[0064] As described above, the photodetector 1 of embodiment 1 comprises a SPAD 10 and a first resistor 11 connected in series to the SPAD 10, and during the recharge time when charge is discharged from the SPAD 10 via the first resistor 11, charge disappears from the multiplication region of the SPAD 10.

[0065] Here, the excess bias voltage applied to the SPAD 10 may be smaller than the breakdown voltage of the SPAD 10, and the resistance value R of the first resistor 11 may satisfy the above formula (21). BD is the electric field strength inside the SPAD 10, C is the capacitance including the parasitic capacitance of the SPAD 10, Vex is the excess bias voltage, which is the difference between the reverse bias voltage applied to the SPAD 10 and the breakdown voltage, W is the depletion layer width of the SPAD 10, and α(E BD ) is the electric field strength E BD The impact ionization rate of electrons under BD ) is the electric field strength E BD is the impact ionization rate of the hole under the condition, a is the coefficient of the impact ionization rate of the electron, b is the coefficient of the impact ionization rate of the hole, q is the elementary charge, v s,e denotes the saturation velocity of electrons.

[0066] (Embodiment 2) 8 is a block diagram showing an example of the configuration of a control system including a photodetector 1 according to embodiment 2. This control system includes a power supply 13, a SPAD 10, a quenching resistor 11a, a control reference device 17, and an output unit 14. The SPAD 10 and the quenching resistor 11a correspond to the photodetector 1 in FIG. 5. For example, the quenching resistor 11a corresponds to the first transistor 15 and the first variable power supply 16 in FIG. 5. The first variable power supply 16 outputs a variable voltage to the gate of the first transistor 15 under the control of the control reference device 17.

[0067] The control reference device 17 references the voltage of the power supply 13 and calculates the quenching resistance according to the relational expression (21). 11aThe control reference device 17 controls the resistance value R of the quenching resistor 11a. Specifically, the control reference device 17 is configured with a CPU (Central Processing Unit) or the like, and calculates Vex from the difference between a pre-recorded breakdown voltage and the power supply voltage. The gate voltage of the first transistor 15 is controlled according to the calculated Vex. The gate voltage may be controlled so that the channel resistance of the first transistor 15 is approximately inversely proportional to Vex. This reduces the resistance value R of the quenching resistor 11a and further shortens the dead time even for different reverse bias voltages. In particular, in the SPAD 10, a large Vex increases the photon detection efficiency (PDE), and a small Vex decreases the PDE. Therefore, the reverse bias voltage may be controlled according to the amount of incident light. For example, a photodetector 1 with a wide dynamic range can be realized by setting Vex low under conditions of a large amount of incident light and Vex high under conditions of a small amount of incident light. In this case, using the control system according to the second embodiment can further shorten the dead time and expand the dynamic range.

[0068] Fig. 9 is a block diagram showing another example of the configuration of a control system including the photodetector 1 according to embodiment 2. In the configuration of Fig. 9, compared to the configuration of Fig. 8, the control target of the control reference device 17 is changed from the quenching resistor 11a to the SPAD capacitor 12a.

[0069] 9 reduces the SPAD capacitance 12a when the reverse bias voltage of the SPAD 10 is large, and increases the SPAD capacitance 12a when the reverse bias voltage of the SPAD 10 is small, thereby shortening the dead time for different reverse bias voltage values.

[0070] Figure 10 is a circuit diagram of a photodetector 1 that realizes the control system of Figure 8 or Figure 9. Figure 10 differs from the configuration of Figure 5 in that a second transistor 21, a second variable power supply 22, and a second capacitor 23 are added. The following explanation will focus on these differences.

[0071] A second transistor 21, which is an N-type transistor, is connected to the cathode of the SPAD 10. A second capacitor 23 is connected to the opposite end of the second transistor 21. A second variable power supply 22 is connected to the gate of the second transistor 21.

[0072] When the photodetector 1 of Figure 10 is included in the control system of Figure 8, when the reverse bias voltage of the SPAD 10 is large, the channel resistance is reduced by lowering the gate voltage of the first transistor 15, and when the reverse bias voltage of the SPAD 10 is small, the channel resistance is increased by raising the gate voltage of the first transistor 15.

[0073] When the photodetector 1 of FIG. 10 is included in the control system of FIG. 9, when the reverse bias voltage of the SPAD 10 is large, the second transistor 21 is made non-conductive, thereby capacity When the reverse bias voltage of the SPAD 10 is small, the capacitance of the SPAD 10 is increased by reducing the resistance of the quenching resistor 11a and by turning on the second transistor 21. This minimizes the dead time for different values ​​of Vex. Both the quenching resistor 11a and the SPAD capacitance 12a may be controlled simultaneously. One or more of the following parameters may be referenced to control one or more other different parameters: (i) the resistance value of the quenching resistor, (ii) the capacitance C of the SPAD 10, (iii) the excess bias voltage Vex, (iv) the depletion layer width W, and (v) the breakdown voltage VBD. The above parameters (i) to (v) may also be controlled with respect to temperature. Because the channel resistance of the first transistor 15 changes with temperature, the gate voltage may be controlled in accordance with temperature. In particular, since the dead time remains the same for the same excess bias voltage Vex, it is preferable to control the gate voltage so that the channel resistance of the first transistor 15 does not change with temperature. This reduces the dead time for different temperatures.

[0074] As described above, the photodetector 1 according to the second embodiment is provided with a control reference device 17, which refers to one or more of the following five parameters: (i) the resistance value R of the first resistor 11, (ii) the capacitance C including the parasitic capacitance of the SPAD 10, (iii) the excess bias voltage Vex, (iv) the depletion layer width W of the SPAD 10, and (v) the breakdown voltage, and controls one or more parameters other than the referred parameters.

[0075] Here, the first resistor 11 is a variable resistor, and the control reference device 17 may be configured to decrease the resistance value of the first resistor 11 as the excess bias voltage increases.

[0076] Here, the first resistor 11 includes a first transistor 15 , and the resistance value of the first resistor 11 may correspond to the channel resistance of the first transistor 15 .

[0077] Here, the capacitance C including the parasitic capacitance of the SPAD 10 is variable, and the control reference device 17 may reduce the capacitance value of the capacitance C as the excess bias voltage increases.

[0078] Here, a second transistor 21 is provided at the end where the SPAD 10 and the first transistor 15 are connected, and a second capacitor is provided at the end opposite to the end where the second transistor 21 is connected. 23 The gate voltage of the second transistor 21 may be controlled by referring to the excess bias voltage of the SPAD 10.

[0079] (Embodiment 3) FIG. 11 is a diagram showing an example circuit of a photodetector array according to a third embodiment. This photodetector array includes N (N is a natural number equal to or greater than 2) photodetectors 1 connected in parallel and further includes a second resistor 24. Each of the N photodetectors 1 includes a SPAD 10, a first transistor 15, and a first variable power supply 16. A second resistor 24 is connected between the SPAD 10 and a second power supply V2 at the end connected to the photodetector 1, i.e., the end connected to the SPAD 10. In this case, the second resistor 24 is required to discharge the charges generated in all N SPADs 10 in a time shorter than the recharge time of the SPADs 10. In other words, the time constant rNC defined by the resistance value r of the second resistor 24 is required to be shorter than the recharge time RC of the SPADs 10 defined by the resistance value R of the first resistor 11. In other words, the following equation is required to be satisfied:

[0080]

number

[0081] From equation (21), the resistance value r of the second resistor 24 may be determined according to the following equation:

[0082]

number

[0083] This prevents deterioration of the quenching characteristics even when multiple SPADs 10 are connected in parallel. For example, the SPADs 10 can be used in applications such as image sensors and photon counters in which multiple photodetectors 1 are arranged in an array.

[0084] 11, the output section 14 is omitted, but each photodetector 1 may have the output section 14, or the output section may be shared by N photodetectors 1. When each photodetector 1 has the output section 14, the connection section between the cathode of the SPAD 10 and the first transistor 15 may be used as the output node. When the output section is shared by N photodetectors 1, the connection section between the anode of the SPAD 10 and the second resistor 24 may be used as the output section.

[0085] Fig. 12 is a diagram showing an example circuit of a solid-state imaging device 100 according to embodiment 3. In addition to multiple photodetectors 1, the solid-state imaging device 100 of Fig. 12 includes a control reference device 42, a selection unit 41, a load unit 43, a signal processing unit 44, a signal output line, and an output unit 45. The photodetector 1 of Fig. 12 differs from the photodetector 1 of Fig. 11A in that a third power supply V3, a third transistor 33, and a fourth transistor 34 are added. The following description will focus on these differences.

[0086] The third transistor 33 is an amplifying transistor that outputs a voltage according to the amount of charge to the cathode of the SPAD 10. In detail, when the fourth transistor 34 is on, the third transistor 33 forms a source follower together with the load (for example, a constant current source) of the load unit 43.

[0087] The fourth transistor 34 is a selection switch transistor that is turned on in response to a selection control signal from the selection unit 41 .

[0088] The control reference device 42, the selection unit 41, and the signal processing unit 44 may be formed on a semiconductor substrate and are collectively referred to as a peripheral circuit unit. The cathode of the SPAD 10 is connected to the gate of the third transistor 33, and the amount of current varies depending on the cathode voltage of the SPAD 10. The selection unit 41 is connected to the gate of the fourth transistor 34 and selects at least one photodetector 1 to output a signal. The signal from the selected photodetector 1 is output to the signal processing unit 44 via a signal output line. The signal processed by the signal processing unit 44 is output from the output unit 45 as numerical data or image data. The output unit 45 is, for example, a display. This allows the output from the photodetector 1 to be output in a format such as an image. In FIG. 12, the conductivity types of the third transistor 33 and the fourth transistor 34 are P-type, but they may also be N-type.

[0089] Next, the device structure of the solid-state imaging device shown in FIG. 12 will be described.

[0090] 13 to 15 show the device structures of the photodetector array and solid-state imaging device of the third embodiment. FIG. 13 is a diagram showing a layout example of the solid-state imaging device 100 of FIG. 12 in plan view. FIG. 13 shows a structure for 2×2 pixels. FIG. 13 shows a plurality of photodetectors 1, a SPAD 10 in the photodetector 1, a first well WL1, a first wiring W1, a gate G1 of the first transistor 15, a gate G3 of the third transistor 33, a gate G4 of the fourth transistor 34, a first semiconductor layer L1 of a first conductivity type included in the SPAD 10, and a third semiconductor layer L3 of a second conductivity type included in the SPAD 10. For clarity, wiring other than the first wiring W1 and semiconductor layers other than the first semiconductor layer L1, the third semiconductor layer L3, and the first well WL1 are omitted. The first transistor 15, the third transistor 33, and the fourth transistor 34 are disposed in the first well WL1. The first semiconductor layer L1 is connected by a first wire W1 to the drain of the first transistor 15 and the gate G3 of the third transistor 33. The source of the first transistor 15 is connected to a first power supply V1.

[0091] Fig. 14 is a diagram showing a modified planar layout of solid-state imaging device 100 according to Embodiment 3. In the layout of Fig. 14, the area of ​​gate G1 of first transistor 15 is larger than the area of ​​gate G3 of third transistor 33 and gate G4 of fourth transistor 34, as compared to the layout of Fig. 13.

[0092] In this way, the area of ​​the gate G1 of the first transistor 15 is larger than the gate areas of the other transistors, namely the third transistor 33 and the fourth transistor 34. This reduces the variation in the threshold voltage of the first transistor 15, and reduces the variation in the channel resistance of the first transistor 15. This allows the number of photodetectors 1 arranged in an array to be increased while satisfying the condition of equation (21), thereby widening the dynamic range.

[0093] FIG. 15 is a diagram showing an example of the cross-sectional configuration of the solid-state imaging device 100 taken along line XV-XV in FIG. 13. The solid-state imaging device 100 includes a semiconductor substrate SUB, a wiring layer LM arranged to contact the first main surface S1 side of the semiconductor substrate SUB, an electrode EL arranged to contact the second main surface S2 side, and a lens layer LL arranged to contact the upper part of the wiring layer LM, with the light irradiation surface being the first main surface S1 side. In addition to the cross section shown in FIG. 13, the cross section of FIG. 15 includes a second semiconductor layer L2 of a second conductivity type and a fourth semiconductor layer L4 of a second conductivity type within the semiconductor substrate SUB. The first semiconductor layer L1, the second semiconductor layer L2, the third semiconductor layer L3, and the fourth semiconductor layer L4 form a SPAD 10, and the area around the boundary between the first semiconductor layer L1 and the second semiconductor layer L2 is a multiplication region MP. The second semiconductor layers L2 are connected to each other via the semiconductor substrate SUB or the fourth semiconductor layer L4. The wiring layer LM is omitted except for the first wiring W1. The lens layer LL includes a microlens ML. Here, a voltage may be applied to the anode of the SPAD 10, i.e., to the second semiconductor layer L2, via the electrode EL. In this case, since the second resistor 24 includes the junction between the semiconductor substrate SUB and the electrode EL, it is preferable that the resistance of the junction between the semiconductor substrate SUB and the electrode EL is low. For example, Gashi In the case of silicon, the electrode material may be Ag, Pt, Ti, Au, etc. Value of This reduces the noise and expands the dynamic range.

[0094] Here, the third semiconductor layer L3 functions to separate the first semiconductor layer L1 from the first semiconductor layer L1 and to separate the first semiconductor layer L1 from the first well WL1. At least a portion of the region of the third semiconductor layer L3 that contacts the first major surface S1 may be depleted. This narrows the separation between the first semiconductor layer L1 from the first semiconductor layer L1 or between the first semiconductor layer L1 and the first well WL1, allowing the photodetector 1 to be further miniaturized. Furthermore, no contacts or trenches need to be disposed in the region of the third semiconductor layer L3 that contacts the first major surface S1. This reduces defects in the third semiconductor layer L3 and reduces dark current.

[0095] In Figure 15, the second semiconductor layer L2, the third semiconductor layer L3, and the fourth semiconductor layer L4 are conveniently represented as different semiconductor layers, but they do not necessarily need to be formed with different impurity concentrations or different impurity injections, and may, for example, have the same impurity concentration.

[0096] FIG. 16 is a diagram showing a modified cross-sectional configuration of the solid-state imaging device 100 taken along line XV-XV in FIG. 13. In the modified example of FIG. 16, the light irradiation surface is changed from the first main surface S1 to the second main surface S2 side, as compared to the configuration of FIG. 15. The lens layer LL is disposed so as to be in contact with the upper part of the electrode EL. This prevents light reflection from the wiring and improves sensitivity. In this case, it is preferable that the electrode EL be made of a material with high light transmittance. For example, when the wavelength range to be used is from visible to near-infrared, ITO (Indium Tin Oxide) or the like may be used.

[0097] FIG. 17 is a diagram illustrating another example cross-sectional configuration of a solid-state imaging device 100 according to embodiment 3. This diagram illustrates a wider cross-sectional view than FIG. 16 . The solid-state imaging device 100 includes a light-receiving region 46 in which multiple photodetectors 1 are provided, and a contact region 47 outside the light-receiving region 46. The contact region 47 includes a filter FL, a second wiring W2, and a fifth semiconductor layer L5. A voltage is applied to the anode of the SPAD 10 via the second wiring W2, the fifth semiconductor layer L5, the fourth semiconductor layer L4, and the electrode EL. In FIG. 17 , a filter FL is provided in a region of the contact region 47 adjacent to the second main surface S2 to prevent incident light from passing through, thereby preventing erroneous detection due to light incident on the contact region 47. In FIG. 17 , the second resistor 24 is formed by the second wiring W2, the fifth semiconductor layer L5, the fourth semiconductor layer L4, and the electrode EL. In the example of FIG. 17 , the electrode EL is not necessarily provided. When the electrode EL is not provided, a decrease in photosensitivity due to light reflection and light absorption by the electrode EL can be prevented, thereby improving sensitivity. The fourth semiconductor layer L4 and the fifth semiconductor layer L5 may have higher impurity concentrations to reduce the diffusion resistance, which makes it easier to satisfy the requirement for the second resistor 24, formula (23) or formula (24). In particular, the fourth semiconductor layer L4 may have a gradually increasing impurity concentration from the first main surface S1 toward the second main surface S2. This allows charges generated in the fourth semiconductor layer L4 to be transferred to the multiplication region MP by the built-in potential of the fourth semiconductor layer L4, thereby improving sensitivity. Furthermore, although FIG. 17 shows a configuration in which light is irradiated from the second main surface S2, a configuration in which light is irradiated from the first main surface S1 may also be used.

[0098] FIG. 18 is a schematic plan view of the solid-state imaging device 100 of FIG. 17 . FIG. 18 shows a chip including a light-receiving region 46, a contact region 47, a control reference device 42, a selection unit 41, and a signal processing unit 44. The contact region 47 is disposed adjacent to the light-receiving region 46 and surrounds the light-receiving region 46. The control reference device 42, the selection unit 41, and the signal processing unit 44 are disposed on the outer periphery of the contact region 47. By disposing the contact region 47 and the light-receiving region 46 adjacent to each other, the second resistor 24 can be further reduced, resulting in a photodetector array with a wide dynamic range. The contact region 47 may be disposed outside any of the control reference device 42, the selection unit 41, and the signal processing unit 44, as long as the condition for the second resistor 24, Equation (23) or Equation (24), is satisfied.

[0099] As described above, the photodetector array of embodiment 3 includes N of the above-mentioned photodetectors 1 (N is an integer greater than or equal to 2), the N series circuits included in the N photodetectors 1 are connected in parallel, each of the N series circuits has a SPAD 10 and a first resistor 11 connected in series, one end of the N series circuits that is on the SPAD 10 side are connected to each other, and further includes a second resistor 24 connected to one end of the N connected series circuits and connected in series with the N photodetectors, and the resistance value of the second resistor 24 is smaller than 1 / N of the resistance value of the first resistor 11.

[0100] Here, the N SPADs 10 may be arranged on the same semiconductor substrate, and one end of the N SPADs 10 connected to one another may be connected via the semiconductor substrate.

[0101] Here, a voltage may be applied to one end of the N elements connected to each other via an electrode arranged in contact with a second main surface, which is the main surface of the semiconductor substrate and is the main surface on the side of one end of the N elements connected to each other.

[0102] Here, the device may include a light-receiving region in which N photodetectors are arranged, a contact region arranged outside the light-receiving region, and a second wiring arranged in the contact region so as to contact the first main surface, which is the main surface opposite to the second main surface, and a voltage may be applied to one end of the N photodetectors connected to each other via the second wiring.

[0103] Here, a peripheral circuit section may be provided for controlling the N photodetectors or performing signal processing, and the contact region may be disposed between the light-receiving region and the peripheral circuit section.

[0104] Here, each of the N photodetectors includes at least two transistors including a first transistor, the first resistance 11 is a channel resistance of the first transistor 15, and the gate area of ​​the first transistor 15 may be larger than the gate areas of the other transistors in the photodetector.

[0105] Furthermore, the photodetector array of embodiment 3 includes M (M is an integer greater than or equal to 2) of the above-described photodetectors 1, the photodetectors 1 are connected to one end of the SPAD 10, a third resistor 31 and a third capacitor 32 are connected to the connected end, the first resistor 11 is a first transistor 15, and the resistance value r' of the third resistor 31 satisfies equation (25).

[0106] Here, the first transistor 15 may be in a conductive state during a reset period in which the SPAD 10 is reset, and in a non-conductive state during an exposure period in which light incident on the SPAD 10 is detected.

[0107] Here, the conductivity type of the channel of the first transistor 15 may be the same as the conductivity type of the end of the SPAD 10 to which the first transistor 15 is connected.

[0108] Here, the capacitance value of the third capacitor may be larger than the capacitance of the SPAD 10.

[0109] [Application examples of photodetectors or photodetector arrays] Hereinafter, application examples of photodetectors or photodetector arrays will be described with reference to the drawings.

[0110] FIG. 19 is a block diagram showing an example of an application of a photodetector or a photodetector array, that is, an example of a distance measurement system using the photodetector 1 or photodetector array according to the present disclosure.

[0111] A distance measurement system 500 relating to an application example of the photodetector 1 or the photodetector array has a light emitting unit 510 that emits pulsed light, a light receiving unit 520 that receives the reflected pulsed light, a control unit 530 that controls the light emitting unit 510 and the light receiving unit 520, and an output unit 540 that outputs a signal from the light receiving unit 520.

[0112] The light emitting unit 510 is configured with a light emitting device such as a light emitting diode, and generates pulsed light in response to a control signal from the control unit 530, and irradiates the light toward the measurement object 600. The light emitting unit 510 may be a diffuse light source, and the measurement object 600 may be multiple.

[0113] The light receiving unit 520 is the photodetector 1, photodetector array, or solid-state imaging device 100 according to the above-described embodiments, and receives pulsed light reflected by the measurement object 600. The light receiving unit 520 may include an optical system such as a lens, and may form an image on the surface of the photodetector 1 or photodetector array.

[0114] The control unit 530 is configured with a CPU (Central Processing Unit) and the like, and controls the light-emitting unit 510 and the light-receiving unit 520 so that they operate in synchronization. Furthermore, the control unit 530 calculates the distance to the measurement object 600 by measuring the time it takes for the pulsed light to reflect from the measurement object 600 and return to the light-receiving unit 520, based on a control signal to the light-emitting unit 510 and an output signal from the light-receiving unit 520.

[0115] The output unit 540 outputs the distance to the measurement object 600 calculated by the control unit 530 in a numerical data format or an image format. The output unit 540 is usually configured with a display, for example, a liquid crystal display or an organic EL display.

[0116] The distance measurement system 500 according to this embodiment is a so-called TOF (Time Of Flight) ght ) type distance measurement system.

[0117] FIG. 20 shows an example timing chart for the distance measurement system 500 of FIG. 19. The timing chart includes pulsed light from the light-emitting unit, reflected light 1, reflected light 2, excess bias voltage Vex, gate voltage of the first transistor 15, channel resistance of the first transistor 15, SPAD1 output, and SPAD2 output. The vertical axis represents light intensity for pulsed light from the light-emitting unit, reflected light 1, and reflected light 2, voltage for excess bias voltage, gate voltage of the first transistor 15, SPAD1 output, and SPAD2 output, and resistance for the channel resistance of the first transistor 15. The horizontal axis represents time. SPAD1 and SPAD2 are SPADs 10 within the photodetector array, and their positions are not limited to these. The light-emitting unit is a diffuse light source, and there are at least two measurement targets, including a relatively close measurement target and a relatively distant measurement target. Reflected light 1 is light that is irradiated on a relatively close object and then reflected and enters SPAD1. Reflected light 2 is light that is irradiated on a relatively close object and then reflected and enters SPAD2. Here, as shown in Figure 20, Vex is increased over time. When irradiating a target with diffuse light and receiving diffusely reflected light from the target, the light intensity decreases inversely proportional to the square of the distance. Therefore, reflected light from a close object has high light intensity, while reflected light from a distant object has low light intensity. Therefore, when detecting reflected light from a close object, Vex is lowered and the photon detection efficiency (PDE) is reduced, preventing double counting and reducing the probability of false detection due to dark current. When detecting reflected light from a distant object, Vex is increased and PDE is increased, reducing the possibility of missed detections. At this time, the resistance value may be decreased over time to achieve quenching while minimizing dead time. For example, as shown in Figure 1 2 In the circuit, the quenching resistor is a P-type transistor, so the gate voltage is simply lowered over time.

[0118] In addition, the distance measurement system 500 of embodiment 3 includes a light receiving unit 520 having the above-mentioned photodetector 1, a light emitting unit 510 that emits light toward the object to be measured, and a control unit 530 that controls the light receiving unit 520 and the light emitting unit 510, and the control unit 530 receives a signal corresponding to the reflected light reflected by the object to be measured from the light receiving unit 510 and calculates the distance to the object to be measured.

[0119] Here, after the light emitting unit 510 emits light, the excess bias voltage may be increased over time, and the channel resistance of the first transistor 15 may be decreased over time.

[0120] While the photodetector, photodetector array, and distance measurement system according to one or more aspects have been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments may also be included within the scope of one or more aspects. [Industrial Applicability]

[0121] The present disclosure is applicable to photodetectors, photodetector arrays, and distance measurement systems, and is applicable to, for example, solid-state imaging devices, distance measuring devices, cameras, and the like. [Explanation of symbols]

[0122] 1 Photodetector 10 SPAD 11 1st resistor 11a Quenching resistor 12 1st capacity 12a SPAD capacity 13 Power supply 14 Output section 15, 15a First transistor 16, 16a First variable power supply 17 Control Standard 21 Second transistor 22 Second variable power supply 23 2nd capacity 24 2nd resistor 31 3rd resistor 32 3rd capacity 33 Third transistor 34 4th transistor 35 5th transistor 36 6th transistor 37 4th capacity 41 Selection section 42 Control Standard 43 Load section 44 Signal Processing Section 45 Output section 46 Light receiving area 47 Contact Area 48 Semiconductor Chips 100 Solid-state imaging device 500 Distance Measurement System 510 Light-emitting part 520 Light receiving section 530 Control Unit 540 Output Section CA Contact Area EL electrode FL Filter G1, G2, G3 gates L1 First semiconductor layer L2 Second semiconductor layer L3 Third semiconductor layer L4 Fourth semiconductor layer L5 Fifth semiconductor layer LL Lens Layer LM wiring layer ML Micro Lens MP multiplication area S1 First principal surface S2 2nd main surface SUB Semiconductor substrate V1 1st power supply V2 2nd power supply W1 First wiring W2 Second wiring WL1 First well

Claims

1. A single photon avalanche diode (hereinafter referred to as SPAD), a first resistor connected in series with the SPAD; During a recharge time when charge is discharged from the SPAD through the first resistor, charge is removed from the multiplication region of the SPAD, The capacitance C including the parasitic capacitance of the SPAD is variable, Furthermore, a control reference device is provided which reduces the capacitance value of the capacitor C as the excess bias voltage, which is the difference between the voltage applied to both ends of the SPAD and the breakdown voltage of the SPAD, increases. Photodetector.

2. The maximum value of the voltage amplitude at the end of the SPAD connected to the first resistor is greater than the excess bias voltage.

10. The photodetector of claim 1.

3. A single photon avalanche diode (hereinafter referred to as SPAD), a capacitance connected in parallel with the SPAD; a first resistor connected in series with the SPAD; a readout unit that reads out a voltage at an end of the SPAD that is connected to the first resistor; The capacitance C including the parasitic capacitance of the SPAD is variable, Furthermore, a control reference device is provided which reduces the capacitance value of the capacitor C as the excess bias voltage, which is the difference between the voltage applied to both ends of the SPAD and the breakdown voltage of the SPAD, increases. Photodetector.

4. the excess bias voltage is less than a breakdown voltage of the SPAD; The resistance value R of the first resistor is [Equation 1] Fulfilling In the formula, EBD is the electric field strength inside the SPAD, C is the capacitance including the parasitic capacitance of the SPAD, Vex is the excess bias voltage, and is defined as the difference between the reverse bias voltage applied to the SPAD and the breakdown voltage. W is the depletion layer width of the SPAD, α(EBD) is the impact ionization rate of electrons under the electric field strength EBD, β(EBD) is the impact ionization rate of holes under the electric field strength EBD, a is the coefficient of the electron impact ionization rate, b is the coefficient of the impact ionization rate of holes, q is the elementary charge, vs,e denotes the saturation velocity of electrons, 4. The photodetector according to claim 1 or 3.

5. the first resistor includes a first transistor; a second transistor having one end connected to the SPAD and the first transistor; a second capacitor connected to the other end of the second transistor; controlling the gate voltage of the second transistor by referring to the excess bias voltage of the SPAD; 4. The photodetector according to claim 2 or 3.

6. N photodetectors according to any one of claims 1 to 5 (N is an integer of 2 or more), The N series circuits included in the N photodetectors are connected in parallel, each of the N series circuits has the SPAD and the first resistor connected in series; One ends of the N series circuits on the SPAD side are connected to each other, Further, a second resistor is connected to the one end of the N photodetectors connected to each other and is connected in series with the N photodetectors, The resistance value of the second resistor is smaller than 1 / N of the resistance value of the first resistor. Photodetector array.

7. the N SPADs are arranged on the same semiconductor substrate; the one ends of the N interconnected transistors are connected via the semiconductor substrate; 7. The photodetector array of claim 6.

8. via an electrode arranged in contact with a second main surface which is a main surface of the semiconductor substrate and is a main surface on the side of the one end of the N interconnected elements, A voltage is applied to one end of the N interconnected elements.

8. The photodetector array of claim 7.

9. a light receiving area in which the N photodetectors are arranged; a contact region disposed outside the light receiving region; a second wiring disposed in the contact region so as to contact a first main surface, which is a main surface of the semiconductor substrate and is a main surface opposite to a second main surface, which is a main surface on the side of the one end of the N interconnected elements; a voltage is applied to the one ends of the N interconnected elements via the second wiring; 8. The photodetector array of claim 7.

10. a peripheral circuit unit that controls the N photodetectors or performs signal processing; the contact region is disposed between the light receiving region and the peripheral circuit section.

10. The photodetector array of claim 9.

11. the first resistor includes a first transistor; each of the N photodetectors comprises at least two transistors including the first transistor; the first resistance is a channel resistance of the first transistor, a gate area of ​​the first transistor is larger than a gate area of ​​the other transistors included in the photodetector; The photodetector array according to any one of claims 6 to 10.

12. a photodetector including M photodetectors (M is an integer of 2 or more) according to claim 1; The photodetectors are connected to one another at one end of the SPAD, a third resistor and a third capacitor are connected to the connected end; the first resistor includes a first transistor; the first resistor is the first transistor; The resistance value r' of the third resistor is [Equation 2] fulfill Photodetector array.

13. The first transistor is The SPAD is in a conductive state during a reset period. The SPAD is in a non-conductive state during an exposure period in which light incident on the SPAD is detected.

13. The photodetector array of claim 12.

14. The conductivity type of the channel of the first transistor is The conductivity type of the SPAD is the same as that of the end to which the first transistor is connected.

14. A photodetector array according to claim 12 or 13.

15. The capacitance value of the third capacitor is greater than the capacitance of the SPAD. The photodetector array according to any one of claims 12 to 14.

16. a light receiving section having the photodetector according to any one of claims 1 to 5; a light emitting unit that emits light toward the object to be measured; a control unit that controls the light receiving unit and the light emitting unit, The control unit receives a signal corresponding to the reflected light reflected by the object to be measured from the light receiving unit, and calculates the distance to the object to be measured. Distance measurement system.

17. the first resistor includes a first transistor; After the light emitting unit emits light, the excess bias voltage is increased over time; decreasing a channel resistance of the first transistor over time; 17. A distance measurement system according to claim 16.

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