Substrate bonding in the fabrication of 3D NOR memory circuits.

Abstract

The memory array and single crystal circuitry are provided by substrate bonding (e.g., adhesive bonding or anodic bonding) of the integrated circuit and are interconnected by conductive lines in an interconnect layer. Additional substrate bonding may provide additional circuits or memory arrays and may be electrically connected by interconnect layers at the substrate bonding interface. The memory array includes storage or memory transistors with single crystal epitaxial silicon channel material. [Selected Figure] Figure 1

Description

[Technical Field]

[0001] (Corresponding related application) This application is related to and claims priority to U.S. Provisional Patent Application No. 62 / 735,678, filed September 24, 2018, entitled "Substrate Bonding in Fabrication of 3-Dimensional NOR Memory Circuits" ("Provisional Application I").

[0002] This application is also related to U.S. Patent Application No. 16 / 012,731, filed June 19, 2018 (the "co-pending application"), entitled "3D NOR Memory Array Architecture and Method for Fabricating Same." This application is also related to U.S. Provisional Patent Application No. 62 / 735,662, filed on the same day as this application, entitled "Epitaxial Single Crystal Channel for Storage Transistor in 3D Memory Structures and Method for Fabricating Same" (the "Provisional Application II"). The disclosures of the co-pending application, Provisional Application I, and Provisional Application II are incorporated herein by reference in their entireties. [Background technology]

[0003] FIELD OF THE INVENTION The present invention relates to substrate bonding techniques in the fabrication of integrated circuits, and in particular to substrate bonding techniques applied to high density three-dimensional memory circuits.

[0004] Description of Related Art Substrate bonding is a technique used in the fabrication of many semiconductor devices. In substrate bonding, two substrates of approximately the same or identical area are joined together by, for example, thermocompression bonding, adhesive bonding, anodic bonding, or thermal bonding techniques. After bonding has occurred, often all or substantially all of one or both of the substrates is removed.

[0005] The co-pending application discloses a three-dimensional memory structure configured as an array of NOR memory strings formed on a single crystal semiconductor substrate. The term "NOR memory string" herein refers to a group of thin-film storage transistors sharing a common source region and a common drain region. FIG. 1 shows a cross-sectional view of a memory structure 30 including an array of NOR memory strings formed on top of CMOS circuitry and interconnect layers on a semiconductor substrate. As shown in FIG. 1, the memory structure 30 is formed on a substrate 150. Suitable substrates include, for example, semiconductor substrates used in the fabrication of electrical circuits, as known to those skilled in the art. Non-semiconductor substrates, such as SiO2 substrates, may also be used.

[0006] The semiconductor substrate 150 may be fabricated on and within various circuit elements (e.g., CMOS transistors, such as the CMOS circuit 10 of FIG. 1 ) interconnected through contacts or vias 16 to conductive lines 22 (e.g., copper) in conventional interconnect layers. These circuit elements are initially fabricated on the semiconductor substrate using conventional techniques prior to the formation of the memory structure 30. The interconnect layers (collectively referred to herein as "interconnect layers 20") are typically embedded in a dielectric layer and may also include conductive lines intended to support the operation of a memory array within the memory structure 30 formed above the interconnect layers 20. For example, the interconnect layer 24 provides a conductive line (global word line) connected to conductive lines 32 (e.g., heavily doped polysilicon) that function as word lines supporting the operation of the storage transistors within the memory structure 30. In the detailed description herein, the conductive lines 32 are referred to as "local word lines."

[0007] As shown in FIG. 1, the memory structure 30 includes a stack of multiple "active strips" (e.g., active stacks 101a, 101b, 101c). For example, FIG. 1 shows stacks 101a, 101b, 101c separated from one another by isolation layer 107, with each stack including four active strips. FIG. 1 illustrates a cross-sectional view of an active strip, with the active strip extending lengthwise within and out of the cross-sectional plane. In this embodiment, the active strip includes a drain layer 104, a source layer 103, a body layer 102, and a channel layer 108 (the channel layer 108 is disposed on either side of the body layer 102). In some embodiments, the drain layer 104 and the source layer 103 are both n-type. + Each channel layer 108 is made of polysilicon. - polysilicon, and the body layer 102 is p +The body layer 102 is preferably polysilicon. In some embodiments, a dielectric layer is used instead of the body layer 102. Also shown within the active strips in FIG. 1 are a conductive layer 105c adjacent to the source layer 103 to reduce the resistivity of the source layer 103 along its length, and a conductive layer 105b adjacent to the drain layer 104 to reduce the resistivity of the drain layer 104 along its length. A charge trapping layer 107 and multiple local word lines 32 are provided along each side of the stack of active strips (i.e., along each side of each active strip). In FIG. 1, the local word lines 32 are conductive columns arranged along both sides of the stack of active strips. A storage transistor is composed of a local word line, a portion of the channel layer 108, a portion of the charge trapping layer 107 located therebetween, the source layer 103, and the drain layer 104. The drain layer 104 and the source layer 103 are shared by multiple storage transistors formed along the active strip. Adjacent storage transistors along an active strip, sharing a common source and drain layer, form a NOR memory string (when any storage transistor in the NOR memory string is turned on, transistor current flows between the common source and drain layers). This sequence of fabrication steps imposes constraints on the fabrication of CMOS devices, interconnect layers, and memory devices. For example, fabrication of memory devices requires the deposition of oxide-nitride-oxide (ONO) layers or stacks using low-pressure chemical vapor deposition (LPCVD), typically requiring temperatures above 750°C and a thermal budget of several hours. High-temperature oxide ("HTO," or SiO2) and silicon nitride (SiN) may be suitable for the oxide and nitride in the ONO layers, respectively. Additionally, an aluminum oxide (Al2O3) layer is often preferred as a blocking oxide in the ONO stack. However, annealing temperatures of 900°C or higher are required to crystallize the Al2O3 (i.e., to produce the desired Al2O3 from an electrical perspective).However, fabrication temperatures above 350°C preclude the use of copper for the horizontal interconnect layer 20 embedded in the associated low-κ dielectric film (even if tungsten is used in the vertical interconnect 16 to connect the horizontal interconnect). Similarly, fabrication temperatures above 500°C preclude the use of aluminum for the interconnect. Tungsten is one possible interconnect material when fabrication temperatures exceed 500°C. However, as shown in Table 1 below, tungsten has a relatively high resistivity. This increases the resistance in the interconnect, which increases signal delays and negatively impacts memory device performance.

[0008] [Table 1]

[0009] The underlying CMOS circuitry (e.g., CMOS transistor 10) is constrained by at least two factors by the thermal budget of the memory device. First, to tolerate fabrication temperatures up to 750°C, cobalt silicide or other high-temperature contact materials (e.g., tungsten or tungsten silicide) must be selected for the gate / source / drain metallization 12 within the CMOS transistor 10. While cobalt silicide has a relatively low sheet resistance and contact resistance compared to silicon, the consumption of the underlying silicon during the silicidation step is relatively high, and the resulting roughness of the cobalt silicide-silicon interface necessitates relatively deep dopant junctions in silicon. Meanwhile, short-channel-length transistors require shallow dopant junctions to reduce leakage current. While nickel silicide is often used for source and drain contacts in current-generation, small-sized transistors, cobalt silicide is preferred over nickel silicide because nickel silicide cannot withstand temperatures exceeding 450°C. If the temperature exceeds 450° C., the nickel silicide film will agglomerate on the silicon, which will impair the low sheet resistance and low contact resistance properties of the nickel silicide film.

[0010] Second, for shallow junction and narrow channel devices, temperatures above 600° C. must be avoided after junction formation to prevent dopant diffusion from the source and drain junctions.

[0011] As a result, there is a need for a fabrication method that allows optimal CMOS device and interconnect layers to be integrated into a 3D NOR memory structure (e.g., memory structure 30 of FIG. 1) without the design choices for the CMOS devices and interconnect layers being constrained by the thermal budget of the memory structure. Summary of the Invention

[0012] According to one embodiment of the present invention, the memory array and the single crystal circuit are provided by substrate bonding (eg, adhesive bonding or anodic bonding) the integrated circuit and are interconnected by conductive lines in an interconnect layer.

[0013] Additional circuitry or memory arrays may be provided by additional substrate bonds and electrically connected by interconnect layers at the substrate bond interface.

[0014] According to one embodiment of the present invention, a memory array includes storage or memory transistors having a single crystal epitaxial silicon channel material.

[0015] The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 shows a cross-sectional view of a memory structure 30 including an array of NOR memory strings formed on top of CMOS circuitry and interconnect layers on a semiconductor substrate. [Figure 2A] FIG. 2A shows a semiconductor substrate 100 upon which CMOS devices and interconnect layers are fabricated to support a 3D NOR memory structure. [Figure 2B] FIG. 2B shows a three-dimensional NOR memory structure (ie, memory structure 30) fabricated on an insulating oxide (eg, SiO 2 ) layer 120 above and spaced apart from the semiconductor substrate 110. [Figure 3A] FIG. 3A shows how two devices A' and B' fabricated on substrates A and B are bonded to each other. [Figure 3B] FIG. 3B shows that Device A' and Device B' are electrically connected in a perfectly matched manner after substrate bonding. [Figure 3C] FIG. 3C shows how Device A' and Device B' are electrically connected after substrate bonding with a 250 nm misalignment. [Figure 3D] FIG. 3D shows that an adhesion metal C is used to promote bonding between substrates A and B (ie, at their mutual contact points) in devices A' and B'. [Figure 4] FIG. 4 shows how the substrate 110 of the memory structure 30 is removed, taking the substrate of FIGS. 2A and 2B as an example. [Figure 5] FIG. 5 shows the interconnect layer 40 of the memory structure 30 being formed. [Figure 6-1] 6A-6C show the sequence of steps for fabricating both the CuA and CoA circuits using substrate bonding techniques. [Figure 6-2] 6D-6E show the sequence of steps for fabricating both the CuA and CoA circuits using substrate bonding techniques. [Figure 6-3] FIG. 6F shows the sequence of steps for fabricating both the CuA and CoA circuits using substrate bonding techniques. [Figure 7-1] 7A-7B show how memory blocks 310, 360 are bonded to substrates 300, 350 using substrate bonding techniques. [Figure 7-2] FIG. 7C shows the bonding of memory blocks 310, 360 to substrates 300, 350 using substrate bonding techniques. [Figure 8-1] 8A-8C illustrate a process in which CuAs CMOS transistors are provided below memory blocks having epitaxial single crystal silicon channels in the memory cells according to one embodiment of the present invention. [Figure 8-2] 8D-8E illustrate a process in which CuAs CMOS transistors are provided below memory blocks having epitaxial single crystal silicon channels in the memory cells according to one embodiment of the present invention.

[0017] For clarity of presentation and to enable cross-referencing between the figures, like elements in the figures have been given like reference numerals. DETAILED DESCRIPTION OF THE INVENTION

[0018] According to one embodiment of the present invention, CMOS devices (e.g., CMOS transistor 10) and interconnect layers (e.g., interconnect layer 20) are fabricated on separate semiconductor substrates rather than on the same silicon substrate on which memory structure 30 is fabricated. FIG. 2A shows semiconductor substrate 100 on which CMOS device 10 and interconnect layer 20 are fabricated to support a 3D NOR memory structure. As shown in FIG. 2B, the 3D NOR memory structure (i.e., memory structure 30) is fabricated on an insulating oxide (e.g., SiO2) layer 120 on and spaced apart from semiconductor substrate 110. As known to those of ordinary skill in the art, both substrates 100, 110 may be provided from silicon wafers.

[0019] After both semiconductor substrates 100, 110 have undergone the appropriate fabrication steps, the two substrates are bonded together using "flip-chip" technology, bonding the surface of semiconductor substrate 100 having interconnect layer 20 to the surface of semiconductor substrate 110 having memory structure 30. In this manner, interconnect layer 20 and CMOS device 10 can be fabricated without being constrained by the high temperatures optimal for fabricating memory structure 30.

[0020] The two substrates are bonded together so that contact points on the interconnect layer 20 are electrically connected to corresponding contact points on the memory structure 30. Each substrate is provided with lithographic alignment marks, which allow for alignment of the target bond points with minimal misalignment. Figures 3A-3D illustrate exemplary substrate bonding of substrates A and B at designated substrate bonding points. Figure 3A illustrates two devices A' and B' fabricated on substrates A and B, respectively, being bonded together. Devices A' and B' are, for example, 300 nm wide conductive lines in an interconnect system. Figure 3B illustrates devices A' and B' electrically connected with perfect alignment after substrate bonding. Figure 3C illustrates devices A' and B' electrically connected with a 250 nm misalignment after substrate bonding. (Alignment accuracy of ±250 nm or better is achievable with current substrate bonding technology.) Substrates A and B can be bonded using any suitable substrate bonding technique, such as thermocompression bonding, anodic bonding, plasma activated bonding, eutectic bonding, or surface activated bonding. Among these techniques, anodic bonding is preferred. Anodic bonding allows the two substrates to be electrically and physically connected by contacting them and applying an electrostatic field.

[0021] According to one embodiment of the present invention, as shown in Figure 3D, an adhesion metal C may be used to promote bonding between substrate A and substrate B at their mutual contact points (i.e., devices A', B'). The adhesion metal C may be, for example, chromium, titanium, indium, or alloys thereof, or any suitable material. The principles and mechanisms of substrate bonding are known to those skilled in the art and will not be described in detail herein.

[0022] After bonding, one of the substrates may be removed. FIG. 4 illustrates the removal of substrate 110 of memory structure 30 using the substrate of FIGS. 2A and 2B as an example. Substrate 110 can be removed by any suitable substrate thinning technique, such as laser lift-off, mechanical polishing, or chemical etching. In one embodiment, mechanical polishing and chemical etching are used in combination to remove substrate 110. The combined use of mechanical polishing and chemical etching allows for the removal of substrate 110 at a lower cost and with greater precision (i.e., without damaging memory structure 30) than either technique used alone. For example, if substrate 110 is 500 μm thick, an initial step involves removing approximately 480 μm of the substrate by mechanical polishing, followed by the remaining approximately 20 μm by chemical etching.

[0023] Substrate thinning by mechanical polishing is performed by rotating the substrate around its center relative to the polishing surface. Substrate thinning by mechanical force is sometimes called "grinding" if the thinned substrate surface is rough, or "polishing" if the thinned substrate surface is smooth. Either grinding or polishing methods may be used, or a combination of grinding and polishing may be used. After the mechanical grinding or polishing process is complete, the remaining 20 μm of memory structure 30 is removed by chemical etching.

[0024] Any suitable chemical may be used in chemically etching the substrate 110. Suitable chemical reagents for the silicon substrate 110 include, for example, KOH, TMAH, and HF. + , HNO3, or HF +4, the etch stop layer 120 ensures that the memory structure 30 remains intact and undamaged from the chemical etching of the substrate 110. When an oxide layer (e.g., a SiO2 layer) is used as the etch stop layer, KOH may be used because silicon etches at a rate approximately 500 times faster than SiO2. Therefore, the SiO2 layer functions as an efficient etch stop layer for silicon etching.

[0025] After substrate 110 is removed, further fabrication can proceed on the bonded substrate. For example, Figure 5 illustrates the formation of interconnect layer 40 of memory structure 30. The formation of memory structure 30 is separate from the formation of interconnect layer 40, which may be selected from either aluminum or copper. Such interconnects may be formed at lower temperatures (e.g., below 450°C).

[0026] According to another embodiment of the present invention, substrate bonding may be used to fabricate single crystal transistors below the memory array (known as a CMOS under-array structure ("CuA")) or above the memory array (known as a CMOS over-array structure ("CoA")). Figures 6A-6F show a series of steps in which substrate bonding techniques are used to fabricate both CuA and CoA circuits.

[0027] As shown in Figure 6A, CMOS transistors 210 are fabricated on substrate 200, while memory array 140 is fabricated on substrate 130. Then, as shown in Figure 6B, substrate 130 is flipped over and substrate-bonded to substrate 200, electrically connecting memory array 140 to CMOS transistors 210 on substrate 200 through interconnect layer 220. Substrate 130 is then removed to expose memory array 140. Then, interconnect layer 150 is fabricated over the exposed side of memory array 140, as shown in Figure 6C.

[0028] As shown in Figure 6D, a second group of CMOS transistors 290 are fabricated on substrate 260. Substrate 260 is most preferably a silicon-on-insulator ("SOI") substrate, with two single-crystal silicon layers on opposite sides of an oxide (SiO2) layer from substrate 260. As shown in Figure 6D, CMOS transistors 290 and an overlying interconnect layer 300 are formed on silicon layer 280 and above silicon layer 280, respectively, and spaced from substrate 260 by SiO2 layer 270. Substrate 260 is then flipped and substrate-bonded, as shown in Figure 6E, to electrically connect CMOS transistors 290 to memory array 140 via interconnect layer 150.

[0029] As shown in FIG. 6F, the substrate 260 is then removed to expose the SiO2 layer 270, above which the interconnect layer 310 is fabricated and to which the CMOS transistor 290 is electrically connected. The result is a CuA-type CMOS transistor 210 fabricated in a single-crystal silicon substrate 200, a memory array 140 disposed at least partially above the interconnect layer 220, a CoA-type CMOS transistor 290 disposed at least partially above the memory array 140, and multiple layers of interconnect layers 150, 300, and 310 disposed at least partially above and below the memory array 140. By providing CMOS transistors below and above the memory array, as shown in FIGS. 6A-6F, a highly efficient memory array is achieved. A highly efficient memory array refers to a memory array fabricated on a semiconductor die in which substantially all of the area is occupied by memory cells. For example, in Figures 6A-6F, CMOS transistors 210 below memory array 140 may be high voltage or analog transistors, while CMOS transistors 290 above memory array 140 may be low voltage, short channel, high performance logic CMOS transistors that are preferably as physically close as possible to the chip's input / output pads.

[0030] According to yet another embodiment of the present invention, substrate bonding may be used to bond one memory block to another. This method simplifies fabrication by minimizing the aspect ratio of the fabricated memory structures, while enabling high areal density memory structures to be fabricated on a single chip. FIGS. 7A-7C illustrate the bonding of memory blocks 310 and 360 to substrates 300 and 350 using substrate bonding techniques. As shown in FIG. 7A, the CMOS transistors 210 and interconnect layer 220, as well as memory block 310, are fabricated on substrate 300, while memory block 360 is fabricated on substrate 350. Then, as shown in FIG. 7B, substrate 350 is flipped over and substrate-bonded to substrate 360 ​​to electrically connect memory block 310 and memory block 350. Then, as shown in FIG. 7C, substrate 350 is removed and interconnect layer 370 is fabricated.

[0031] According to yet another embodiment of the present invention, a single-crystal silicon channel for a memory cell transistor can be formed by depositing an epitaxial silicon layer indexed off a single-crystal substrate. Such a process is difficult to use for memory blocks containing CuAlCMOS transistors because a "clear" path from the substrate to the source / drain layers of the memory array may not be available. Examples of fabricating single-crystal epitaxial silicon for thin-film storage transistors are disclosed, for example, in Provisional Application No. 2002 / 002622, incorporated herein by reference. Specifically, Provisional Application No. 2002 / 002622 discloses a type of thin-film storage transistor (referred to herein as a "quasi-volatile memory circuit (QVM circuit)") that has a data retention time (e.g., 100 milliseconds to one year) longer than conventional dynamic random access memory (DRAM) circuits and shorter than conventional non-volatile memory circuits. A QVM circuit may be configured, for example, as a three-dimensional array of NOR memory strings. When only memory blocks are constructed on a silicon substrate (i.e., without CuAlCMOS transistors underneath), a clear path for depositing epitaxial silicon is provided. The substrate with the resulting memory blocks may then be bonded using substrate bonding to another substrate on which CMOS transistors have been fabricated. Figures 8A-8E illustrate a process in which CuA CMOS transistors are provided beneath memory blocks with epitaxial single crystal silicon channels in the memory cells, according to one embodiment of the present invention.

[0032] First, as shown in FIG. 8A, a stack of active strips (each having a source and drain layer 420) is formed on a substrate 400, with adjacent stacks separated by trenches that extend down to the substrate 400. Next, as shown in FIG. 8B, epitaxial silicon 430 is grown from the surface 402 of the silicon substrate 400, indexing off the silicon substrate 400. Next, as shown in FIG. 8C, an anisotropic etch removes substantially all of the epitaxial silicon 430 from the trenches, except for an epitaxial silicon channel 440 that remains in the recess between the source and drain layers of the active strips. Thereafter, as shown in FIG. 8D, fabrication of the memory block 810 proceeds to completion (an exemplary fabrication process is disclosed, for example, in the co-pending application incorporated herein by reference). Thereafter, as shown in FIGS. 8D-8E, the substrate 400 is flipped over and bonded to a substrate 450 containing the CMOS transistor 210 and the interconnect layer 220 formed thereon. As explained above, the substrate 400 may be removed and an interconnect layer may be fabricated above the memory blocks.

[0033] The above detailed description is provided to illustrate particular embodiments of the present invention and is not intended to be limiting. Various modifications and variations are possible within the scope of the present invention. The gist of the present invention is set forth in the appended claims.

Claims

1. a single-crystal semiconductor substrate, the semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate; a first set of circuits including single crystal transistors formed on the first semiconductor substrate; a first interconnect layer including a plurality of conductive lines formed on top of the circuitry; a first memory block electrically connected to the first set of circuits via the conductive lines in the first interconnect layer, the first memory block including a memory transistor having an epitaxial single crystal silicon channel region, the conductive lines in the first interconnect layer and the first memory block being joined by a substrate bond; a second interconnect layer formed above the first memory block, the second interconnect layer including a plurality of conductive lines, the first interconnect layer and the second interconnect layer being disposed on opposite sides of the first memory block; a second set of circuits including single crystal transistors formed on or in the second semiconductor substrate, the second set of circuits electrically connected to the first memory block via the conductive lines in the second interconnect layer, the second set of circuits and the conductive lines in the second interconnect layer joined by a substrate bond; and An integrated circuit comprising:

2. 10. The integrated circuit of claim 1, The integrated circuit, wherein the substrate bonding is any one of thermocompression bonding, adhesive bonding, anodic bonding, and thermal bonding.

3. 10. The integrated circuit of claim 1, The integrated circuit wherein the second set of circuits is formed in a silicon layer disposed above an insulating layer of a silicon-on-insulator substrate.

4. 4. An integrated circuit according to claim 3, the integrated circuit further includes a third interconnect layer; The third interconnect layer includes a plurality of conductive lines and is disposed on the insulating layer on an opposite side of the silicon layer on which the second set of circuits is formed.

5. 10. The integrated circuit of claim 1, An integrated circuit wherein the first set of circuits includes high voltage transistors or analog transistors.

6. 10. The integrated circuit of claim 1, The integrated circuit wherein the second set of circuits is formed from low voltage, short channel, high performance logic CMOS transistors.

7. 10. The integrated circuit of claim 1, further comprising a second memory block; the second memory block is electrically connected to the first memory block; the first memory block and the second memory block are bonded by substrate bonding; The second interconnect layer is formed on top of the second memory block opposite the first memory block.

8. 10. The integrated circuit of claim 1, The integrated circuit, wherein the first memory block includes one or more of a non-volatile memory string array and a semi-volatile memory string array.

9. 9. An integrated circuit according to claim 8, The integrated circuit wherein the first memory block is configured as a three-dimensional memory array.

10. 10. The integrated circuit of claim 9, An integrated circuit in which the three-dimensional memory array includes NOR type memory strings.

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