Method for fabricating high performance three-dimensional semiconductor structures and structures produced therefrom

Abstract

A method for interconnecting metal structures in the manufacturing of 3D semiconductors is provided. This method includes the steps of: providing bonding layers on a first upper surface of a first substrate and a second upper surface of a second substrate; bonding the first upper surface to the second upper surface to form a bonding portion; etching vias through the lower surface of the first substrate, through the first substrate around a first metal structure embedded in the first substrate, through the bonding portion, and up to a second metal structure embedded in the second substrate; and filling the vias with a conductive material to form a via structure, thereby electrically connecting the metal structures. [Selection Diagram] Figure 11

Description

[Technical Field]

[0001] This invention claims the benefit of U.S. Patent Application Publication No. 62,620,893, entitled "APPARATUS AND METHOD FOR INTERCONNECTION OF LAYERS IN ADVANCED 3D SEMICONDUCTOR STRUCTURES," filed January 23, 2018, the entire contents of which, including tables, figures, and claims, are incorporated herein.

[0002] The present technology is directed to methods for interconnecting layers during the fabrication of three-dimensional (3D) semiconductor structures. More specifically, the present technology is a novel application of existing techniques to simplify the fabrication of interconnections between bonded device layers, to provide high-precision alignment, to provide very high microelectronic element to connection ratios, and to transfer and interconnect multiple layers. [Background technology]

[0003] For the 3D integration of multiple layers on a separate silicon substrate, semiconductor manufacturing processes can use various techniques for integrating and interconnecting layers between substrates, such as bump bonding and through-silicon vias (TSVs). These techniques require highly reliable methods for interconnecting between metal layers in a stack of semiconductor layers. Additionally, these metal layers reside at different depths in the stack, complicating the interconnection. Many semiconductor processes are planar processes, typically involving only the most recently applied layer.

[0004] One approach is disclosed at https: / / ieeexplore.ieee.org / document / 6251571, where it is disclosed that Cu-Cu bonding has been identified as a possible option to enable 3D-IC integration at a reasonable cost. For 3D stacking, TSVs can be exposed (nailed) on the backside of the wafer and directly bonded to Cu landing pads. This is a promising approach for small pitch IOs.S This approach can reduce the cost of additional processing steps, such as RDL (redistribution layer) and bumping. In this work, we present the results achieved by developing a process for TSV nail exposure to enable electrical contact during thermal compression bonding (TCB) of Cu-Cu. Therefore, the impact of various TSV nail structures under various TCB conditions for a minimum TSV pitch of 10 μm is investigated. Three different TSV nail structures are defined: no nail exposure, flat TSVs, and dome-shaped TSVs (see Figure 1). TSVs with different heights (2 μm and 5 μm) are also fabricated in the dome-shaped case. The results achieved with different structures under different bonding conditions are first reported. We then focused on the best-performing structure and demonstrated the need for the use of underfill (UF) to ensure good die-to-die adhesion. The backside of a donor wafer is attached to the frontside of a mount wafer. The TSVs are large, ranging in size from 5 to 100 μm, and the wafers are thick. The pixels are about 1 to about 10 μm. The interconnects block light and cannot be used in pixel arrays. Backside milling is also a problematic process because milling through a roughly 700 μm wafer is expensive and using a Cu nail as a milling stop inevitably involves mixing of Si and Cu. Cu is a contaminant of Si and has high solid-state fluidity and solubility.

[0005] U.S. Patent Application Publication No. 2018 / 0102251 discloses directly bonded native interconnects and an active base die. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths without the overhead of standard interfaces. Because the native interconnects are pre-connected, the system saves redistribution routing. The base die can contain custom logic, allowing attached dies to provide storage functions. This architecture can connect various interconnect types and chiplets from various process nodes and operate at different voltages. The base die can have state elements for driving. Functional blocks on the base die receive native signals from various chiplets and communicate with all attached chiplets. Chiplets can share the processing and storage resources of the base die. Routing interruptions are minimal, improving signal quality and timing. The system can operate at double or quadruple data rates. This architecture facilitates the assembly of ASIC, ASSP, and FPGA ICs, as well as neural networks, reducing footprint and power requirements. It translates to the assembly of individual die on a single parent die, similar to early hybrid modules. Simply put, it is the adaptation of the direct-bond interconnect concept to multiple, heterogeneous mixes of die on top of a (larger) base die. This system inherently limits the number of layers that can be layered in succession to only two. This system does not provide interconnects through the donor die to the next connection and layer. While smaller than typical die-level to substrate level, the interconnects are still at least about 10 μm thick due to the manner in which these interconnects are placed between the base die and the chiplets.

[0006] U.S. Patent Application Publication No. 2017 / 0194291 discloses a semiconductor structure and a method for forming the semiconductor structure. The method includes the steps of: preparing a first semiconductor workpiece; bonding a second semiconductor workpiece to a first surface of the first semiconductor workpiece; forming a first conductive via through the second semiconductor workpiece in the first semiconductor workpiece; bonding a third semiconductor workpiece to a second surface of the first semiconductor workpiece opposite the first surface; and forming a second conductive via through the first semiconductor workpiece and the third semiconductor workpiece in the second semiconductor workpiece so that the first conductive via and the second conductive via are electrically connected. This method requires forming metal pads on the surface of the semiconductors to electrically connect the conductive vias to each semiconductor. This is not self-aligned. It also lacks flexibility in terms of via structures that selectively interconnect contact structures on different wafers. There is no direct wafer bonding, especially with an air gap between the wafer and the die and a filler layer. This is a technique for "stacking" dies to take advantage of the smaller interconnect volume and greater die density. This applies to TSV and bump bonding, and therefore to thicker dies and interconnect structures larger than about 10-100 μm.

[0007] U.S. Patent Application Publication No. 2017 / 0316971 discloses a method for three-dimensionally integrating elements, such as singulated dies or wafers, and an integrated structure having connected elements, such as singulated dies or wafers. Either or both of the dies and wafers may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. The first and second contact structures are exposed during bonding and may be electrically interconnected as a result of bonding. Vias may be etched and filled after bonding to expose and form electrical interconnects between the interconnected first and second contact structures and provide electrical access to the interconnects from the surface. The via structures are large. They are not self-aligned. There is also no flexibility in terms of via structures selectively interconnecting contact structures on different wafers.

[0008] U.S. Patent Application Publication No. 2017 / 0062366 discloses a method for forming a direct hybrid bond and a device resulting from the direct hybrid bond. The direct hybrid bond includes a first substrate having a first set of metallic bond pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bond pads on the first substrate; a second substrate having a second set of metallic bond pads capped by the first conductive barrier, the second substrate being aligned with the first set of metallic bond pads and preferably connected to the device or circuit, and having a second non-metallic region adjacent to the metallic bond pads on the second substrate; and a contact-bonded interface between the first and second sets of metallic bond pads capped by a conductive barrier formed by contact-bonding the first non-metallic region to the second non-metallic region. Interconnects penetrate the attachment interface prior to bonding. Via structures are limited in size to about 0 to 1 μm and are limited in number for yield reasons. There is one connection per four microelectronic elements. The process is limited to bonding two wafers and does not allow for subsequent wafer bonding.

[0009] U.S. Patent Application Publication No. 2016 / 0204084 discloses a method for forming a semiconductor device structure. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed on the front side of the first semiconductor wafer, and no devices are formed on the second semiconductor wafer. The method further includes bonding the front side of the first semiconductor wafer to the back side of the second semiconductor wafer and thinning the front side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed on the front side of the second semiconductor wafer. At least one first TSV is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer. This process is limited to bonding two wafers and does not allow for subsequent wafer bonding.

[0010] As can be seen from the above, current 3D integration methods often involve processing individual device layers separately and then assembling them. This can lead to differences in tolerances between the individual layers, as well as alignment tolerances between these layers during the assembly process. The overall process is complicated by the need for connections between two different metal wire layers buried beneath the device layers. Further complications can arise when making those buried signals available at the top surface of the assembly. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] US Patent Application Publication No. 2018 / 0102251 [Patent Document 2] US Patent Application Publication No. 2017 / 0194291 [Patent Document 3] US Patent Application Publication No. 2017 / 0316971 [Patent Document 4] US Patent Application Publication No. 2017 / 0062366 [Patent Document 5] US Patent Application Publication No. 2016 / 0204084 [Non-patent literature]

[0012] [Non-Patent Document 1] https: / / ieeexplore.ieee.org / document / 6251571 Summary of the Invention [Problem to be solved by the invention]

[0013] New manufacturing methods are needed that allow device layers to be assembled with high alignment accuracy. It is preferable to adapt known techniques with new methods to make the method more suitable. It is desirable that the via structures be 0.22 μm or less and not limited in number. It is even more advantageous that there is one connection per microelectronic element. It is even more advantageous that the connections penetrate the attachment interface after bonding. It is even more advantageous that the method provides self-alignment. It is even more advantageous that the via structures selectively interconnect with contact structures on different wafers. [Means for solving the problem]

[0014] This technology provides a new manufacturing method that allows device layers to be assembled with high-precision alignment. This method increases yield and reliability. Via structures can be 0.22 μm or smaller and are not limited in number. Very high interconnection density is possible, resulting in semiconductor devices suitable for use in imaging, since there can be more than one connection per pixel. The connections penetrate the attachment interface after bonding. This method is self-aligned. Via structures can be selectively interconnected to via structures on different wafers. For example, one via structure can interconnect a via structure on a first wafer to a via structure on a second wafer, while an adjacent via structure can interconnect a third via structure on a third wafer to both the via structure on the first wafer and the via structure on the second wafer.

[0015] In one embodiment, a method for interconnecting metal structures in 3D semiconductor manufacturing is provided, the method including the steps of providing a bonding layer on a first top surface of a first substrate and a second top surface of a second substrate; bonding the first top surface to the second top surface to provide a bond; etching a via through the bottom surface of the first substrate, through the first substrate around a first metal structure embedded in the first substrate, through the bond, and to a second metal structure embedded in the second substrate; and filling the via with a conductive material to provide a via structure, thereby electrically connecting the metal structures.

[0016] The method may further include an etch stop in the first metal structure to protect the conductive layer in the first metal structure from etching.

[0017] The method may further include an etch stop in the second metal structure to stop the etch at the second substrate.

[0018] In this method, the etching step can result in the via having a diameter of less than about 500 nanometers. The method can further include bonding a third substrate to the underside of the first substrate to provide a second bond.

[0019] The method may further include etching a second via through the third substrate around a third metal structure embedded in the third substrate, through the second junction, and down to the via structure.

[0020] The method may further include filling the second via with a conductive material to expand the via structure, thereby electrically connecting the metal structure.

[0021] The method may further include sequentially bonding, etching, and filling the vias in fourth and subsequent substrates, thereby providing a three-dimensional semiconductor n-th order substrate.

[0022] The method may be carried out at room temperature.

[0023] In this method, the bond may be an oxide bond.

[0024] In another embodiment, a method for connecting substrates in three-dimensional semiconductor manufacturing is provided, the method including the steps of: selecting a first substrate with a first top surface and a first metal structure below the first top surface; selecting a second substrate with a second top surface and a second metal structure below the second top surface, the first and second metal structures having a conductive layer proximate the top surface and an etch stop distal from the top surface; providing a bonding layer on the first top surface and the second top surface; bonding the bonding layer to provide a bond; etching a via through the bottom surface of the first substrate, through the first substrate around the first metal structure, through the bond, and to the second metal structure; and filling the via with a conductive material to provide a via structure.

[0025] In this method, the etching step can produce vias with diameters of less than about 750 nm.

[0026] In this method, the etching step can produce vias with diameters of less than about 250 nm.

[0027] The method may further include bonding a third substrate to the underside of the first substrate to provide a second bond.

[0028] The method may further include etching a second via through the third substrate around a third metal structure embedded in the third substrate, through the second junction, and down to the via structure.

[0029] The method may further include filling the second via with a conductive material to expand the via structure, thereby electrically connecting the metal structure.

[0030] The method may further include etching a plurality of vias into the substrate and filling the plurality of vias with a conductive material.

[0031] In this method, the etching step may produce a plurality of vias at a density of about one via per microelectronic element.

[0032] In another embodiment, a method for forming a three-dimensional semiconductor structure is provided, the method including: selecting a first silicon wafer including a first device layer and a back-end (BEOL) layer, the BEOL layer including a first top surface and a first metal stack, the first metal stack including a conductive layer proximate the first top surface and an etch stop distal from the first top surface, the first top surface being provided with an acidifying layer; selecting a transfer layer including a second device layer and a second BEOL layer, the second BEOL layer including a second top surface and a second metal stack, the second metal stack including a second top surface and an etch stop distal from the first top surface; the first BEOL layer includes a conductive layer proximate the surface and an etch stop distal to the second top surface, the second top surface being provided with an oxide layer; bonding a first silicon wafer to the transfer layer using the oxide layer such that the first top surface faces the second top surface; etching a plurality of vias through the transfer layer and into the first BEOL layer to a depth of the first metal stack; and filling the vias with a conductive material to provide electrical connections between the first metal stack and the second metal stack, thereby forming a three-dimensional semiconductor structure.

[0033] In this method, the first silicon wafer can be selected to have a first metal stack about 5 nm from its first top surface, and the transfer layer can be selected to have a second metal stack about 5 nm from its second top surface.

[0034] The method may further include etching a plurality of vias into the substrate and filling the plurality of vias with a conductive material.

[0035] In this method, the etching step may produce a plurality of vias at a density of about one via per microelectronic element.

[0036] In this method, the etching step can produce vias with diameters of less than about 250 nanometers. [Brief explanation of the drawings]

[0037] [Figure 1A] FIG. 1 is a side view of a mount wafer and a transfer layer wafer according to the present technique. [Figure 1B] FIG. 1 is a side view of a mount wafer and a transfer layer wafer bonded together to provide a semiconductor structure. [Figure 2] FIG. 1C is a side view of the metal stack of the transfer wafer and the transfer layer wafer of FIGS. 1A and 1B. [Figure 3] 1 is a side view of a semiconductor structure in preparation for etching. [Figure 4A] FIG. 2 is a side view of the semiconductor structure after etching to provide vias. [Figure 4B] FIG. 10 is a detailed side view of the via and metal stack. [Figure 5] 1 is a side view of a semiconductor structure with vias filled to provide a via structure. [Figure 6] FIG. 1 is a side view of a preferred embodiment with vias lined with an insulating layer. [Figure 7A] FIG. 10 is a side view of the second transfer wafer. [Figure 7B] FIG. 10 shows a second transfer wafer bonded to the first transfer wafer to provide a second carrier structure. [Figure 8] FIG. 2 is a side view of a second semiconductor structure in preparation for etching. [Figure 9] FIG. 10 is a side view of the second semiconductor structure after etching to provide a second via structure. [Figure 10] FIG. 10 is a side view of a second semiconductor structure with a second via filled. [Figure 11] 1 is a diagram of a semiconductor with vias extending through different transfer wafers. DETAILED DESCRIPTION OF THE INVENTION

[0038] Unless expressly stated otherwise, the following rules of interpretation apply to this specification (the written description and the claims): (a) words used in this specification shall be construed as to gender or number (singular or plural) as the context requires; (b) the singular terms "a," "an," and "the" used in this specification and the appended claims shall include the plural unless the context clearly dictates otherwise; (c) the inferential term "about" applied to a recited range or value represents an approximation within a deviation within the range or value known or expected in the art from measurement methods; (d) the word "herein" (e) the terms "hereby," "hereof," "hereinbefore," "hereinafter," and words of similar import refer to this specification as a whole and not to any particular paragraph, claim, or other portion unless otherwise expressly stated; (e) recited details are for convenience only and do not control or affect the meaning or construction of any portion of this specification; (f) "or" and "any" are not exclusive, and "include" and "including" are not limiting. Furthermore, the terms "comprising," "having," "including," and "containing" should be construed as open-ended terms (i.e., meaning "including but not limited to") unless otherwise specified.

[0039] The recitation of ranges of values ​​herein is intended merely as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein. Each separate value is incorporated herein as if individually recited herein. When a specific range of values ​​is provided, it is understood that intervening values ​​between the upper and lower limits of that range are included therein, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, and any other stated or intervening value in the stated range. All smaller subranges are also included. The limits of these smaller ranges are also included therein, subject to any specifically excluded limit in the stated range.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the relevant art. Although any methods and materials similar or equivalent to those described herein can also be used, the acceptable methods and materials are described below.

[0041] As shown in FIG. 1A, a silicon mount wafer, generally designated 6, includes a first device transfer layer 10. The first device transfer layer 10 includes front-end (FEOL) structures 12 (microelectronic elements), such as, but not limited to, transistors, photodiodes (pixels), microelectronic mechanical systems (MEMS), diodes, resistors, capacitors, inductors, silicon photonic devices, or other suitable elements, and a first back-end (BEOL) layer 14 having a first metal stack 16, which may be, but is not limited to, metal wiring embedded in a dielectric. A first dielectric layer 18, which in a preferred embodiment is a high-density oxide layer, more preferably a high-quality silicon dioxide layer (e.g., but not limited to, silicon nitride, silicon oxynitride (SiON), or tantalum oxide), is deposited on a first side 20 of the silicon mount wafer 6. Typically, the silicon mount wafer 6 is an all-layer complementary oxide semiconductor (CMOS) wafer and provides mechanical support for final assembly of the transferred layers. The silicon transfer layer wafer, generally designated 8, includes a second device layer 22. The second device layer 22 includes second front-end (FEOL) structures 24 (microelectronic elements), such as, but not limited to, transistors, diodes, resistors, capacitors, inductors, or other suitable elements, and a second back-end (BEOL) layer 26 having a second metal stack 28, which may be, but is not limited to, metal wiring. A second dielectric layer 30, preferably a high-density oxide layer that matches the first dielectric layer 18 in density and porosity, and in preferred embodiments, a high-density oxide layer or more preferably a high-quality silicon dioxide layer (e.g., but not limited to, silicon nitride, silicon oxynitride (SiON), or tantalum oxide), is deposited on a first side 32 of the silicon transfer layer wafer 8. The first and second dielectric layers 18, 30 are silicon dioxide layers. Both the mount wafer 6 and the transfer layer wafer 8 have a high degree of flatness and a low level of roughness on their surfaces 20, 32. The first and second dielectric layers 18, 30 should also have flat surfaces 34, 36 with little or no roughness.The first and second dielectric layers 18, 30 are processed to ensure flatness and roughness to achieve good bonding. This is not essential for the first and second dielectric layers 18, 30. Exemplary values ​​for wafer bow are less than 70 μm across a 200 mm wafer, with a local surface roughness of approximately 0.2 nm. As can be seen, the first and second metal stacks 16, 28 are embedded within the first and second BEOL layers 14, 26. They may be at different depths. As shown in FIG. 1B , in a first manufacturing step, the silicon mount wafer 6 and the silicon transfer layer wafer 8 are bonded together by the dielectric layers 18, 30. The dielectric layers 18, 30 are covalently bonded to form a first bonding interface 38. Alternatively, bonding can be fusion bonding, hybrid bonding, eutectic bonding, adhesive bonding, thermocompression bonding, or plasma-activated bonding. Bonding can be performed at room temperature or at a temperature that does not exceed the breakdown limits of the BEOL stack of the transferred layers. Once the mount wafer 6 and transfer layer wafer 8 are bonded, the mount wafer 6 is thinned using the method of U.S. Patent No. 7,166,520, which is incorporated herein by reference in its entirety. Briefly, the silicon mount wafer 6 contains hydrogen platelet regions that are parallel to the surface of the wafer. This is a cohesive plane, and when force is applied, the wafer breaks along the plane, reducing the wafer thickness to a highly controlled thickness using known techniques such as polishing and tungsten chemical mechanical planarization (CMP).

[0042] Details of the metal stacks 16, 28, 108 and their orientation are shown in Figure 2. The metal stacks 16, 28, 108 are comprised of a conductive layer 40, 42, 142, which may be, for example, but not limited to, aluminum or copper, and an etch stop 44, 46, 148, which may be, for example, but not limited to, a stack of titanium, titanium nitride, and tungsten. The conductive layer 40, 42, 142 is proximate the first surface 20, 32, and the etch stop 44, 46, 146 is distal from the first surface 20, 32. In a preferred embodiment, the conductive layer 40, 42, 142 is about 500 to less than about 100 nm, preferably about 5 nm from the first surface 20, 32. The silicon mount wafer 6 and silicon transfer layer wafer 8 are stacked together with the silicon transfer layer wafer 8 inverted so that the etch stop 46 is above the conductive layer 42 on the silicon transfer layer wafer 8 and below the conductive layer 40 on the silicon wafer 6. The etch stops 44, 46, 146 are also known as protective layers. If a second transfer layer wafer is added, it is placed on top of the first transfer layer wafer 8 in the same orientation as the first transfer layer wafer 8.

[0043] 3, a third dielectric layer 50, preferably a high-quality oxide layer, more preferably silicon dioxide, but which could be another dielectric layer as described above, is applied to the second side 52 of the transfer layer wafer 8 in a second fabrication step. A patterned photoresist 54 having apertures 52 is placed over the third dielectric layer 50. The patterned photoresist 54 ensures that the third dielectric layer 50 is etched only where the apertures 56 are located.

[0044] As shown in FIG. 4A , a via 60 is etched, extending through the third dielectric layer 50, through the transfer layer wafer 8, through the first bonding interface 38, and into the first BEOL layer 14 of the silicon mount wafer 6. As shown in FIG. 4B , the etch stop 46 of the second metal stack 28 acts as a barrier to the etching of the conductive layer 42, thereby allowing the conductive layer 42 to maintain its integrity. The etch proceeds beyond the second metal stack 28 to the first metal stack 16, exposing the conductive layers 40, 42 to each other. This thus self-aligns the conductive layers 40, 42 in a single etching step. Any suitable etching method may be used, including, for example, plasma etching, reactive ion plasma etching (RIE), chemical wet etching, laser drilling, and / or other processes known in the art. The etching process may result in a via with a vertical or tapered sidewall profile, or an irregular profile, such as a foot. The vias 60 have a high aspect ratio, which may be about 5 to about 10 or greater.

[0045] 5 illustrates the next step in the method. A conductive material is deposited within the via 60 to form a via structure 62, or interconnect, thereby electrically interconnecting the conductive layers 40, 42, and 142 to one another. The conductive material may be formed of tungsten, a tungsten-based alloy, titanium, copper or a copper-based alloy, aluminum, gold, silver, molybdenum (Mo), titanium nitride (TiN), or the like. In a preferred embodiment, titanium, titanium nitride, and tungsten are used, and the via structure 62 is processed using a tungsten chemical mechanical planarization (CMP) process. Those skilled in the art will appreciate that once the via structure 62 is established, electrical contact is made through the second metal stack 28 to the silicon in the second device layer 22. This contact may be desirable or may require electrical isolation.

[0046] 6, a dielectric insulating layer 70 is present on the sidewalls 72 of the vias 60. During preparation of the silicon transfer layer wafer 8, trenches are cut through the second device layer 22 and these trenches are filled with a dielectric, such as oxygen. The vias 60 are smaller than the trenches that are filled with the dielectric, resulting in the dielectric insulating layer 70.

[0047] In a further step, shown in FIG. 7A, a second transfer layer wafer, generally referenced 80, is added. The second transfer layer wafer 80 includes a third device layer 82. The third device layer 82 includes a third front-end (FEOL) structure 84 (microelectronic element), such as, but not limited to, a transistor, diode, resistor, capacitor, inductor, or other suitable element, and a third back-end (BEOL) layer 86 having a third metal stack 88, which may be, but is not limited to, a metal wiring. A fourth dielectric layer 90 is grown on a first surface 92 of the second transfer layer wafer 80. The fourth dielectric layer 90 is preferably a high-quality oxide layer, most preferably silicon dioxide, but may be any of the other dielectric layers described above. As shown in FIG. 7B, the fourth dielectric layer 90 bonds with the dielectric layer 50 to form a second bonding interface 91. As described above and shown in FIG. 8, a fifth dielectric layer 100 is applied to the second side 102 of the second transfer layer wafer 80, and a photoresist 104 with apertures 106 is placed on top of the second dielectric layer 100. The photoresist 104 ensures that the apertures 106 are only etched where they are located. The third metal stack 88 is as described above and shown in FIG. 2.

[0048] 9 , a via 110 is etched through the fifth dielectric layer 100, through the second transfer layer wafer 80, through the second bonding interface 91, and to the top surface 112 of the first via structure 62. The etch stop 146 of the third metal stack 108 acts as a barrier to the etching of the conductive layer 142, thereby allowing the conductive layer 142 to maintain its integrity. The etch proceeds beyond the third metal stack 108 to the first via structure 62, exposing the conductive layer 142 to the first via structure 62. This therefore self-aligns the conductive layers 40, 42.

[0049] As shown in FIG. 10 , a conductive material is deposited within the via 110 to form a via structure 120, or interconnect, thereby electrically interconnecting the conductive layers 40, 42, and 142. The conductive material may be formed of tungsten, a tungsten-based alloy, titanium, copper or a copper-based alloy, aluminum, gold, silver, molybdenum (Mo), titanium nitride (TiN), or the like. In a preferred embodiment, titanium, titanium nitride, and tungsten are used, and the via structure 120 is processed using a tungsten chemical mechanical planarization (CMP) process and an etching process. Those skilled in the art will understand that once the via structure 120 is established, electrical contact is made to the silicon through the third metal stack 108 in the third device layer 82. This contact may be desirable or may require electrical isolation.

[0050] 11 , a first via, generally referenced 198, is created by a first etching step that self-aligns the conductive layers 40 and 42. The via 198 is lined with an insulating layer 200 between the via structure 202 and the via wall 204. A second via, generally referenced 210, is created by a second etching step that self-aligns the conductive layers 40, 42, and 142. This via 210 may or may not be lined with an insulating layer. Via structure 212 allows the second via 210 to self-align all three conductive layers 40, 42, and 142 in a single step.

[0051] Regardless of the number of transfer layers added, the finishing step of the fabrication involves passivating the surface using various oxides and nitrides in several layers. These layers are each in the 1 μm range. Without being bound by theory, this passivation protects the semiconductor from environmental influences. This is followed by patterning with a "pad-open" mask and etching the passivation through the metal stack 22, 108. After etching, the metal stack 22, 108 is ready for wire bonding, bump bonding, or any other standard die / packaging level connection technology, including, but not limited to, redistribution layer (RDL) and other lamination techniques.

[0052] As known to those skilled in the art, additional transfer layers can be added as described for the addition of a second transfer layer. All processes used are room temperature processes. The vias and via structures are about 250 to about 750 nanometers in diameter, with all ranges therebetween. The vias and via structures are very dense, with as few as one microelectronic element per via.

[0053] While the example embodiments have been described with what are presently considered to be examples of the most practical and / or preferred embodiments possible, it should be understood that the description is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the example embodiments. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific example embodiments described in detail herein. Such equivalents are intended to be encompassed by the claims appended hereto or as later filed.

Claims

1. 1. A method of interconnecting metal structures in the fabrication of a 3D semiconductor structure, comprising: providing a first substrate (8) including a first front end (FEOL) structure (24), a first back end (BEOL) layer (26), and a first top surface (32); providing a second substrate (6) including a second FEOL structure (12), a second BEOL layer (14), and a second top surface (20); depositing a first dielectric layer (30) on the first upper surface (32); depositing a second dielectric layer (18) on the second upper surface (20); bonding the first dielectric layer (30) to the second dielectric layer (18) to form a bond; disposing a patterned photoresist (54) having openings (56) on the lower surface (52) of the first substrate (8); etching a via (60) having a dielectric insulating layer (70) along its sidewalls (72) through the bottom surface (52) of the first substrate (8), adjacent to and in contact with a first metal structure (28) embedded in the first BEOL layer (26), through the first substrate (8), through the junction, and down to a second metal structure (16) embedded in the second BEOL layer (14); filling the vias (60) with a conductive material to provide a via structure (62) thereby electrically connecting the first metal structure (28) and the second metal structure (16); A method comprising:

2. 10. The method of claim 1, further comprising: an etch stop in said first metal structure for protecting a conductive layer in said first metal structure from etching.

3. 3. The method of claim 2 further comprising an etch stop in said second metal structure.

4. The method of claim 3 , wherein the etching step provides vias with diameters of less than about 500 nanometers.

5. 5. The method of claim 4, further comprising bonding a third substrate including a third FEOL structure, a third dielectric layer, and a third BEOL layer therebetween to the bottom surface of the first substrate to provide a second bond.

6. 6. The method of claim 5, further comprising etching a second via adjacent to and in contact with a third metal structure embedded in the third BEOL layer, through the third substrate, through the second junction, and down to the via structure.

7. 7. The method of claim 6, further comprising filling the second via with a conductive material and expanding the via structure, thereby electrically connecting the first metal structure, the second metal structure, and the third metal structure.

8. 8. The method of claim 7, further comprising the steps of sequentially bonding and etching vias and filling said vias in fourth and subsequent additional substrates, thereby providing a three-dimensional semiconductor structure of n substrates, where n is a total number of substrates.

9. 3. The method of claim 2, wherein all steps are carried out at room temperature.

10. The method described in claim 9, wherein the bond in the step of providing the bond is an oxide bond.

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