Semiconductor Module

Abstract

To provide a semiconductor module that has both surfaces of a plurality of multi-gate type semiconductor devices mounted.SOLUTION: A semiconductor module according to an embodiment comprises: a first conductor; a second conductor; a third conductor; a fourth conductor; a plurality of conductive bonding materials; and a plurality of multi-gate type semiconductor devices. The multi-gate type semiconductor device comprises: a semiconductor layer; a collector electrode; an emitter electrode; a first gate electrode; and a second gate electrode that is bonded through the fourth conductor and the conductive bonding material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor module. [Background technology]

[0002] For example, semiconductor devices such as IGBTs (insulated gate bipolar transistors) are used in power conversion circuits. Multi-gate IGBTs can reduce losses in semiconductor devices, but when modularizing them, it is desirable to achieve both a configuration that prevents interference between multiple gate wirings and miniaturization. For semiconductor devices, double-sided mounting semiconductor modules are desirable, which can reduce parasitic inductance, improve heat dissipation, and improve packaging density. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-161720 A Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a semiconductor module in which a plurality of multi-gate type semiconductor devices are mounted on both sides. [Means for solving the problem]

[0005] The semiconductor module of the embodiment includes a first conductor, a second conductor, a third conductor, a fourth conductor, a plurality of conductive bonding materials, and a plurality of multi-gate semiconductor devices. The multi-gate semiconductor device includes a semiconductor layer, a collector electrode, an emitter electrode, a first gate electrode, and the fourth conductor bonded via the conductive bonding material. The and two gate electrodes. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a schematic view illustrating a semiconductor module according to the first embodiment. [Figure 2] 2(a) and 2(b) are schematic views illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the first embodiment. [Figure 3] 3A and 3B are schematic views illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the second embodiment. [Figure 4] 4(a) and 4(b) are schematic views illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the third embodiment. [Figure 5] 5(a) and 5(b) are schematic views illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the fourth embodiment. [Figure 6] 6(a) and 6(b) are schematic views illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the fifth embodiment. [Figure 7] 7(a) and 7(b) are schematic views illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the sixth embodiment. [Figure 8] FIG. 8 is a schematic diagram illustrating a multi-gate IGBT, a diode, and a conductor included in a semiconductor module according to a reference example. [Figure 9] FIG. 9 is a cross-sectional view showing an example of the configuration of a multi-gate IGBT. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0008] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0009] In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0010] (First embodiment) FIG. 1 is a schematic diagram illustrating a semiconductor module according to a first embodiment. The semiconductor module 10 includes multiple semiconductor devices connected in parallel. The semiconductor device is a switching element that switches electrical connection between two electrodes in response to gate electrode input and has at least four types of electrodes. This specification describes an example in which the semiconductor device is a multi-gate IGBT semiconductor chip having two types of gate electrodes. FIG. 1(a) shows a perspective view of the semiconductor module according to the first embodiment, FIG. 1(b) shows an exploded perspective view of the semiconductor module according to the first embodiment, FIG. 1(c) shows a perspective view of a first substrate on which the semiconductor module according to the first embodiment can be mounted, and FIG. 1(d) shows a perspective view of a second substrate on which the semiconductor module according to the first embodiment can be mounted. In FIGS. 1(a) and 1(b), the first substrate 80 and the second substrate 81 are omitted. In FIG. 1(d), the Z direction is inverted.

[0011] As shown in FIG. 1, the semiconductor module 10 according to the embodiment includes a first conductor 100, a second conductor 110, a third conductor 120, a fourth conductor 121, multi-gate IGBTs 200 and 210, and metal bonding materials 300, 310, 320, 321, 330, 340, 350, and 351.

[0012] The direction from one multi-gate IGBT 200 to another multi-gate IGBT 200 is defined as a first direction D1. The first direction D1 is defined as the X direction. The direction intersecting with the first direction D1 is defined as a second direction D2. The direction intersecting with the first direction D1 and the second direction D2 is defined as a D3 direction. The second direction D2 is, for example, the Y direction, and the third direction D3 is, for example, the Z direction. The X direction, Y direction, and Z direction are directions independent of each other. The X direction, Y direction, and Z direction intersect, for example, perpendicularly to each other.

[0013] The multi-gate IGBT 200 includes a collector electrode 201, an emitter electrode 202, a first gate electrode 203, and a second gate electrode 204. The multi-gate IGBT 210 includes a collector electrode 211, an emitter electrode 212, a first gate electrode 213, and a second gate electrode 214. The multi-gate IGBTs 200 and 210 have the same electrode arrangement and the same type of semiconductor structure.

[0014] The multi-gate IGBTs 200 and 210 have a first surface and a second surface opposite the first surface. Collector electrodes 201 and 211 are provided on the first surface. Because the collector electrodes 201 and 211 are the only electrodes provided on the first surface, the collector electrodes 201 and 211 can be made larger, thereby suppressing heat generation in the multi-gate IGBTs 200 and 210. Emitter electrodes 202 and 212, first gate electrodes 203 and 213, and second gate electrodes 204 and 214 are provided on the second surface. When wiring is routed using wire bonding or the like instead of mounting with a metal bonding material, the emitter electrodes 202 and 212, first gate electrodes 203 and 213, and second gate electrodes 204 and 214 provided on the second surface can be arranged at any position on the multi-gate IGBTs 200 and 210 while remaining electrically independent. However, when the emitter electrodes 202, 212, first gate electrodes 203, 213, and second gate electrodes 204, 214 provided on the second surface are mounted using a metal bonding material while the second conductor 110, third conductor 120, and fourth conductor 121 are located at the same height, the arrangement of the emitter electrodes 202, 212, first gate electrodes 203, 213, and second gate electrodes 204, 214 is limited.

[0015] The first and second gate electrodes are electrically independent and can be controlled electrically and temporally independently of each other.

[0016] The emitter electrode may be divided into a plurality of parts as shown in FIG. 1, or may not be divided.

[0017] The semiconductor module 10 has multiple multi-gate IGBTs, including multi-gate IGBTs 200 and 210. A multi-gate IGBT is a switching element having at least two types of gate electrodes provided on a common semiconductor substrate of a semiconductor element. Electrodes of the same type in the multiple multi-gate IGBTs are connected to each other by metal bonding members. While FIG. 1 shows two parallel-connected multi-gate IGBTs, this embodiment can be applied to any parallel-connected number greater than two.

[0018] The collector electrode 201, the metal bonding material 300, and the first conductor 100 overlap in order in the third direction D3 and are connected to each other. The collector electrode 211, the metal bonding material 330, and the first conductor 100 overlap in order in the third direction D3 and are connected to each other. The first conductor 100, the metal bonding material 300, and the collector electrode 201 overlap in order in the third direction D3 and are connected to each other. The first conductor 100, the metal bonding material 330, and the collector electrode 211 overlap in order in the third direction D3 and are connected to each other. The emitter electrode 202, the metal bonding material 310, and the second conductor 110 overlap in order in the third direction D3 and are connected to each other. The emitter electrode 212, the metal bonding material 340, and the second conductor 110 overlap in order in the third direction D3 and are connected to each other. The first gate electrode 203, the metal bonding material 320, and the third conductor 120 overlap in order in the third direction D3 and are connected to each other. The first gate electrode 213, the metal bonding material 350, and the third conductor 120 overlap in order in the third direction D3 and are connected to each other. The second gate electrode 204, the metal bonding material 321, and the fourth conductor 121 overlap in order in the third direction D3 and are connected to each other. The second gate electrode 214, the metal bonding material 351, and the fourth conductor 121 overlap in order in the third direction D3 and are connected to each other.

[0019] The first conductor 100 is a conductor extending in the first direction D1 and the second direction D2, and may be, for example, a metal wiring of a DBC (Direct Bonded Copper) substrate or a metal-based substrate. In this case, the first conductor 100 may be part of the first substrate 80. The first substrate 80 includes a base layer 90, an insulating layer 91, and the first conductor 100. The base layer 90 is a substrate on which the insulating layer 91 and the first conductor 100 are mounted, and extends in the first direction D1 and the second direction D2, and may be made of, for example, copper or aluminum. The insulating layer 91 is provided between the base layer 90 and the first conductor 100, and insulates the base layer 90 from the first conductor 100, and may be made of, for example, resin or ceramic.

[0020] The second conductor 110, the third conductor 120, and the fourth conductor 121 are conductors extending in the first direction D1. The second conductor 110, the third conductor 120, and the fourth conductor 121 can also be formed using metal wiring, such as a DBC (Direct Bonded Copper) substrate or a metal-based substrate. In this case, the second conductor 110, the third conductor 120, and the fourth conductor 121 may be part of the second substrate 81. The second substrate 81 includes a base layer 92, an insulating layer 93, the second conductor 110, the third conductor 120, and the fourth conductor 121. The base layer 92 is a substrate on which the insulating layer 92 and the second conductor 110, the third conductor 120, and the fourth conductor 121 are mounted, and extends in the first direction D1 and the second direction D2. For example, copper or aluminum can be used. The insulating layer 93 is provided between the base layer 92 and the second conductor 110, the third conductor 120, and the fourth conductor 121. The insulating layer 93 insulates the base layer 90 from the multiple conductors, and may be made of, for example, resin or ceramic. The second conductor 110, the third conductor 120, and the fourth conductor 121 are wiring on the second substrate 81, and therefore are located at the same position in the third direction D3. In other words, the second conductor 110, the third conductor 120, and the fourth conductor 121 are equally spaced from the base layer 92 and are equally spaced from the first conductor 100. In the third direction D3, the first conductor 100, the second conductor 110, the third conductor 121, the fourth conductor 121, and the multiple multi-gate IGBTs are located between the first substrate 80 and the second substrate 81.

[0021] For example, a solder material or a sintered bonding material can be used for the metal bonding materials 300, 310, 320, 321, 330, 340, 350, and 351. The metal bonding materials are conductive bonding materials.

[0022] As shown in FIG. 1 , the semiconductor module 10 may further include diodes 500 and 510. The diode 500 includes an anode electrode 502 and a cathode electrode 501. The diode 501 includes an anode electrode 512 and a cathode electrode 511. The diodes 500 and 510 extend in a first direction D1 and a second direction D2 and have a first surface and a second surface opposite the first surface. The cathode electrodes 501 and 511 are provided on the first surfaces of the diodes 500 and 510, respectively. The anode electrodes 502 and 512 are provided on the second surfaces of the diodes 500 and 510, respectively. The anode electrode 502, the metal bonding material 370, and the second conductor 110 overlap in order in the third direction D3 and are connected to each other. The anode electrode 512, the metal bonding material 390, and the second conductor 110 overlap in order in the third direction D3 and are connected to each other. The cathode electrode 501, the metal bonding material 360, and the first conductor 100 overlap in order in the third direction D3 and are connected to each other. The cathode electrode 511, the metal bonding material 380, and the first conductor 100 overlap in order in the third direction D3 and are connected to each other. The diodes 500 and 510 are provided as needed and may be omitted.

[0023] The semiconductor module 10 can drive multiple semiconductor devices with the same control signal by electrically connecting the same type of electrodes of the multiple semiconductor devices. The semiconductor module 10 can control a larger current and power than a single semiconductor device.

[0024] 2(a) and 2(b) are schematic diagrams illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the first embodiment. Fig. 2(a) is a plan view showing the multi-gate IGBT and diodes according to the first embodiment, and Fig. 2(b) is a plan view showing the positional relationship between the multi-gate IGBT and diodes according to the first embodiment and the conductors.

[0025] In the embodiment, the first gate electrode 203 and the second gate electrode 204 are arranged at an interval in the second direction D2. The first gate electrode 203 and the second gate electrode 204 and the collector electrode 202 are arranged at an interval in the second direction D2. The first gate electrode 213 and the second gate electrode 214 are also arranged at an interval in the second direction D2. The first gate electrode 213 and the second gate electrode 214 and the collector electrode 212 are also arranged at an interval in the second direction D2. As a result, the second conductor 110, the third conductor 120, and the fourth conductor 121 are located at the same position in the third direction D3, but are spaced apart in the second direction D2 and electrically isolated from each other.

[0026] The second conductor 110, the third conductor 120, and the fourth conductor 121 can be electrically separated while remaining in the same position in the third direction D3 without changing their dimensions in the third direction D3, thereby reducing the size of the semiconductor module 10 in the third direction D3. In other words, the second conductor 110, the third conductor 120, and the fourth conductor 121 are connected to the same electrode groups of multiple semiconductor devices arranged in a predetermined direction without intersecting three-dimensionally in the third direction D3. In the semiconductor module 10, the area of ​​the circuit loop is reduced, resulting in reduced parasitic inductance. Furthermore, because the semiconductor devices included in the semiconductor module 10 have shapes extending in the first direction D1 and the second direction D2, heat is dissipated from both ends in the third direction D3. Therefore, the small size of the semiconductor module 10 in the third direction D3 reduces thermal resistance and improves heat dissipation. Furthermore, the small size of the semiconductor module 10 in the third direction D3 reduces the overall size of the semiconductor module 10, improving packaging density.

[0027] An example of the configuration of a multi-gate IGBT will be described with reference to FIG. 9. FIG. 9 is a cross-sectional view showing an example of the configuration of a multi-gate IGBT. Below, an example is shown in which two IGBTs controlled by two gates are formed on a single chip. However, as long as at least one gate operates as an IGBT or simply as a switch, the other gate may be a switching diode or have some other configuration. The electrodes in the trenches are connected to various conductors, but this is not shown here.

[0028] In the semiconductor layer 11, a first gate trench 21, a second gate trench 22, a first gate electrode 51 (first gate conductor), a second gate electrode 52 (second gate conductor), a p-type collector region 28, an n-type buffer region 30, an n-type drift region 32, a p-type base region 34, a first n-type emitter region 36, a second n-type emitter region 37, a first gate insulating film 41, a second gate insulating film 42, a resistive trench 61, a first resistive layer 71, and an insulating film 63 are provided.

[0029] The semiconductor layer 11 has a first surface P1 and a second surface P2 facing the first surface P1. The semiconductor layer 11 is, for example, single crystal silicon.

[0030] The emitter electrode 12 is provided on the first face P1 side of the semiconductor layer 1. The emitter electrode 12 covers, for example, the entire surface of the IGBT cell region 101. At least a portion of the emitter electrode 12 contacts the first face P1 of the semiconductor layer 11. The emitter electrode 12 is, for example, a metal. An emitter voltage is applied to the emitter electrode 12. The emitter voltage is, for example, 0 V.

[0031] The collector electrode 14 is provided on the second face P2 side of the semiconductor layer 11. At least a portion of the collector electrode 14 contacts the second face P2 of the semiconductor layer 11. The collector electrode 14 is made of, for example, a metal. A collector voltage is applied to the collector electrode 14. The collector voltage is, for example, not less than 200 V and not more than 6500 V.

[0032] The p-type collector region 28 is a p+ type semiconductor region. The p-type collector region 28 is electrically connected to the collector electrode 14. The p-type collector region 28 is in contact with the collector electrode 14.

[0033] The p-type collector region 28 serves as a source of holes when the IGBT 200 is in the on state.

[0034] The n-type buffer region 30 is an n-type semiconductor region. The n-type buffer region 30 is provided between the first face P1 and the p-type collector region 28. The n-type buffer region 30 has the function of suppressing the extension of a depletion layer when the IGBT 200 is in an off state. It is also possible to configure the IGBT 200 without providing the n-type buffer region 30.

[0035] The n-type drift region 32 is an n-type semiconductor region. The n-type drift region 32 is provided between the first face P1 and the n-type buffer region 30. The n-type impurity concentration of the n-type drift region 32 is lower than the n-type impurity concentration of the n-type buffer region 30.

[0036] The n-type drift region 32 serves as a path for an on-current when the IGBT 200 is in an on-state. The n-type drift region 32 is depleted when the IGBT 200 is in an off-state, and has the function of maintaining the breakdown voltage of the IGBT 200.

[0037] The p-type base region 34 is a p-type semiconductor region. The p-type base region 34 is provided between the first face P1 and the n-type drift region 32. The depth of the p-type base region 34 from the first face P1 toward the second face P2 is, for example, 6 μm or less. When the IGBT 200 is in the on state, an inversion layer is formed in the p-type base region 34, and the p-type base region 34 functions as a channel region of the transistor.

[0038] An n-barrier layer (not shown) may be provided between the n-type drift region 32 and the p-type base region 34. The n-type impurity concentration of the n-barrier layer is higher than the n-type impurity concentration of the n-type drift region 32. The n-barrier layer is provided closer to the p-type base region 34 than the lower end of the first gate trench 21. In other words, the n-barrier layer is shallower than the lower end of the first gate trench 21.

[0039] The first n-type emitter region 36 is an n+ type semiconductor region. The first n-type emitter region 36 is provided between the first face P1 and the p-type base region 34. The n-type impurity concentration of the first n-type emitter region 36 is higher than the n-type impurity concentration of the n-type drift region 32.

[0040] The first n-type emitter region 36 is electrically connected to the emitter electrode 12. The first n-type emitter region 36 is in contact with the emitter electrode 12. The first n-type emitter region 36 serves as a supply source of electrons when the transistor having the first gate electrode 51 is in an on-state.

[0041] The second n-type emitter region 37 is an n+ type semiconductor region. The second n-type emitter region 37 is provided between the first face P1 and the p-type base region 34. The n-type impurity concentration of the second n-type emitter region 37 is higher than the n-type impurity concentration of the n-type drift region 32.

[0042] The second n-type emitter region 37 is electrically connected to the emitter electrode 12. The second n-type emitter region 37 is in contact with the emitter electrode 12. The second n-type emitter region 37 serves as a source of electrons when the transistor having the second gate electrode 52 is in an on-state.

[0043] The first gate trench 21 is provided in the IGBT cell region 101. The first gate trench 21 extends in a first direction parallel to the first plane P1 in a first plane P1. The first gate trench 21 has a stripe shape. A plurality of the first gate trenches 21 are repeatedly arranged in a second direction perpendicular to the first direction.

[0044] The first gate trench 21 penetrates the first n-type emitter region 36 and the p-type base region 34. The depth of the first gate trench 21 is, for example, 6 μm or less.

[0045] The first gate electrode 51 is provided in the first gate trench 21. The first gate electrode 51 is, for example, a semiconductor or a metal. The first gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. A first gate insulating film 41 is provided between the first gate electrode 51 and the p-type base region 34. The first gate insulating film 41 is, for example, a silicon oxide film.

[0046] The second gate trenches 22 are provided in the IGBT cell region 101. The second gate trenches 22 extend in a first direction parallel to the first plane P1 in the first plane P1. The second gate trenches 22 have a stripe shape. The second gate trenches 22 are repeatedly arranged in a second direction perpendicular to the first direction.

[0047] The second gate trench 22 penetrates the p-type base region 34. The depth of the second gate trench 22 is, for example, not less than 4 μm and not more than 6 μm.

[0048] The second gate trench 22 has, for example, the same shape as the first gate trench 21.

[0049] The second gate electrode 52 is provided in the second gate trench 22. The second gate electrode 52 is, for example, a semiconductor or a metal. The second gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The second gate electrode 52 is electrically connected to the gate electrode pad 111.

[0050] A second gate insulating film 42 is provided between the second gate electrode 52 and the p-type base region 34. The second gate insulating film 42 is, for example, a silicon oxide film.

[0051] The resistor trench 61 is provided in the IGBT cell region 101. The resistor trench 61 is provided between the first gate trench 21 and the second gate trench 22. The resistor trench 61 extends in a first direction parallel to the first plane P1 on the first plane P1. The resistor trench 61 has a stripe shape. The resistor trenches 61 are repeatedly arranged in a second direction perpendicular to the first direction.

[0052] The resistive trench 61 penetrates the p-type base region 34. The resistive trench 61 has a depth of, for example, 6 μm or less.

[0053] The resistor trench 61 has, for example, the same shape as the first gate trench 21 and the second gate trench 22.

[0054] The first resistive layer 71 is provided in the resistive trench 61. The first resistive layer 71 is, for example, a semiconductor or a metal. The first resistive layer 71 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The first resistive layer 71 is electrically connected to the gate electrode.

[0055] The electrical resistivity of the first resistance layer 71 is higher than, for example, the electrical resistivity of the first gate electrode 51 and the electrical resistivity of the second gate electrode 52. For example, the first resistance layer 71, the first gate electrode 51, and the second gate electrode 52 are made of amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The conductive impurity concentration of the first resistance layer 71 is lower than the conductive impurity concentration of the first gate electrode 51 and the conductive impurity concentration of the second gate electrode 52.

[0056] An insulating film 63 is provided between the first resistance layer 71 and the p-type base region 34. The insulating film 63 is, for example, a silicon oxide film.

[0057] Next, the operation of the multi-gate IGBT 200 will be described.

[0058] Although the transistor having the first gate electrode 51 and the transistor having the second gate electrode 52 do not have clearly separated structures, for the sake of convenience in explaining their operation, they will be referred to as a transistor having the first gate electrode 51 and a transistor having the second gate electrode 52.

[0059] When the IGBT 200 is in an off state, for example, an emitter voltage is applied to the emitter electrode 12. The emitter voltage is, for example, 0 V. A collector voltage is applied to the collector electrode 14. The collector voltage is, for example, 200 V or more and 6500 V or less.

[0060] When the IGBT 200 is in the off state, a turn-off voltage is applied to the gate electrode pad 111. Therefore, the turn-off voltage is also applied to the first gate electrode 51 and the second gate electrode 52. The turn-off voltage is a voltage below the threshold value at which the transistor in the cell region 101 does not turn on, and is, for example, 0 V.

[0061] When the IGBT 200 is turned on, a turn-on voltage is applied to the gate electrode pad 111. The turn-on voltage is also applied to the first gate electrode 51 and the second gate electrode 52.

[0062] The turn-on voltage is a voltage that exceeds the threshold voltage of the transistor in the cell region 101. The turn-on voltage is, for example, 15 V. Both the transistor having the first gate electrode 51 and the transistor having the second gate electrode 52 in the cell region 101 are turned on.

[0063] When turning off the IGBT 200, a turn-off voltage is applied to the gate electrode pad. At this time, the first gate electrode 51 has a higher gate resistance than the second gate electrode 52 because the first resistive layer 71 is connected to the gate electrode pad. Therefore, the change in potential of the first gate electrode 51 is delayed relative to the change in potential of the second gate electrode 52. Therefore, the transistor having the second gate electrode 52 turns off before the transistor having the first gate electrode 51.

[0064] When the transistor having the second gate electrode 52 is turned off, the number of electrons injected from the emitter electrode 12 side into the n-type drift region 32 decreases. Therefore, the amount of carriers accumulated in the n-type drift region 32 decreases.

[0065] Thereafter, the transistor having the delayed first gate electrode 51 also turns off, turning off the IGBT 200. At this time, the amount of carriers stored in the n-type drift region 32 has already decreased, so the turn-off time is shortened and switching loss is suppressed.

[0066] FIG. 8 is a schematic diagram illustrating a multi-gate IGBT, diodes, and conductors included in a semiconductor module according to a reference example. FIG. 8(a) is a plan view showing the multi-gate IGBT and diode according to the reference example, and FIG. 8(b) is a plan view showing the positional relationship between the multi-gate IGBT and diode according to the reference example and the conductors. As shown in FIG. 8(a), in the reference example, the multi-gate IGBT has a large emitter electrode on which heat concentrates. The first gate electrode 203 and the second gate electrode 204 are spaced apart from the emitter electrode 202 in the first direction D1. The first gate electrode 203 and the second gate electrode 204 are spaced apart from the emitter electrode 202 in the second direction D2. The first gate electrode 213 and the second gate electrode 214 are spaced apart from the emitter electrode 212 in the first direction D1. The first gate electrode 213 and the second gate electrode 214 are spaced apart from the emitter electrode 212 in the second direction D2.

[0067] 8(b), the third conductor 120 electrically connecting the first gate electrode 203 of the multi-gate IGBT 200 and the first gate electrode 213 of the multi-gate IGBT 210, the fourth conductor 121 electrically connecting the second gate electrode 204 of the multi-gate IGBT 200 and the first gate electrode 214 of the multi-gate IGBT 210, and the second conductor 110 cannot all be electrically separated. In the embodiment, the third conductor 120 electrically connecting the first gate electrode 203 of the multi-gate IGBT 200 and the first gate electrode 213 of the multi-gate IGBT 210, the fourth conductor 121 electrically connecting the second gate electrode 204 of the multi-gate IGBT 200 and the first gate electrode 214 of the multi-gate IGBT 210, and the second conductor 110 are electrically separated.

[0068] For example, in the second reference example, the first gate electrodes 203 and 213 and the second gate electrodes 204 and 214 can be wired while being electrically isolated by using wire bonding.

[0069] However, in order to wire bond the first gate electrodes 203, 213 and the second gate electrodes 204, 214, a space of, for example, 1 mm or more is required between the emitter electrodes 202, 212 and the second conductor 110 in the direction D3. This space can be secured by inserting a metal block of 1 mm or more between the emitter electrodes 202, 212 and the second conductor 110, or by changing the metal bonding materials 310, 340 to ones with a thickness of 1 mm or more. For example, solder balls or solder with a diameter of 1 mm or more or solder with a metal core ball is used as the metal bonding material, and copper is used as the metal for the solder with a metal core ball. However, inserting a space of 1 mm or more between the emitter electrodes 202, 212 and the second conductor 110 is expected to increase parasitic inductance, size, and thermal resistance. In the embodiment, the third conductor 120 electrically connecting the first gate electrode 203 of the multi-gate IGBT 200 and the first gate electrode 213 of the multi-gate IGBT 210, and the fourth conductor 121 electrically connecting the second gate electrode 204 of the multi-gate IGBT 200 and the first gate electrode 214 of the multi-gate IGBT 210 are electrically separated while existing at the same height as the second conductor 110, thereby reducing parasitic inductance, size, and thermal resistance compared to the second reference example.

[0070] The distance between the first gate electrode 203 and the second gate electrode 204 of the multi-gate IGBT 200 is defined as a first distance d1. The first distance d1 is preferably, for example, 50 μm or more and 500 μm or less. When the first distance d1 is 50 μm or more, it becomes easy to ensure, for example, a dielectric strength voltage between the first gate electrode 203 and the second gate electrode 204. When the first distance d1 is 500 μm or less, it becomes easy, for example, to miniaturize the multi-gate IGBT 200.

[0071] The distance between the first gate electrode 203 and the emitter electrode 202 of the multi-gate IGBT 200 is defined as a second distance d2. The second distance d2 is preferably, for example, 50 μm or more and 500 μm or less. When the second distance d2 is 50 μm or more, it becomes easy to ensure, for example, a dielectric strength voltage between the first gate electrode 203 and the emitter electrode 202. When the second distance d2 is 500 μm or less, it becomes easy, for example, to miniaturize the multi-gate IGBT 200.

[0072] The distance between the third conductor 120 and the fourth conductor 121 is defined as a third distance d3. The third distance d3 is preferably, for example, 50 μm or more and 1000 μm or less. When the third distance d3 is 50 μm or more, it becomes easy to ensure, for example, a dielectric strength voltage between the third conductor 120 and the fourth conductor 121.

[0073] The distance between the third conductor 120 and the second conductor 110 is defined as a fourth distance d4. The fourth distance d4 is preferably, for example, 50 μm or more and 1000 μm or less. When the fourth distance d4 is 50 μm or more, it becomes easier to ensure, for example, a sufficient dielectric strength voltage between the third conductor 120 and the second conductor 110.

[0074] (Second embodiment) The second embodiment relates to an electrode arrangement of a multi-gate IGBT and a method of connecting the multi-gate IGBT to a conductor. Figures 3(a) and 3(b) are schematic diagrams illustrating a multi-gate IGBT, a diode, and a conductor included in the semiconductor module according to the first embodiment. Figure 3(a) is a plan view showing a multi-gate IGBT and a diode according to the second embodiment, and Figure 3(b) is a plan view showing the positional relationship between the multi-gate IGBT and the diode according to the second embodiment and the conductor.

[0075] As shown in Fig. 3(a), the second embodiment differs from the first embodiment in that the positions of the first gate electrodes 203, 213 and the second gate electrodes 204, 214 are displaced in the first direction D1. The first gate electrodes 203, 213 and the second gate electrodes 204, 214 do not overlap with each other in the first direction but are spaced apart. Even when the gate electrodes are displaced in the first direction D1 in this manner, the second conductor 110, the third conductor 120, and the fourth conductor 121 are electrically isolated from each other while being at the same height, as shown in Fig. 3(b).

[0076] (Third embodiment) The third embodiment relates to an electrode arrangement of a multi-gate IGBT and a method of connecting the multi-gate IGBT to a conductor. Figures 4(a) and 4(b) are schematic diagrams illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the first embodiment. Figure 4(a) is a plan view showing the multi-gate IGBT and diodes according to the third embodiment, and Figure 4(b) is a plan view showing the positional relationship between the multi-gate IGBT and diodes according to the third embodiment and the conductors.

[0077] As shown in FIG. 4A, in the third embodiment, the emitter electrode is located between the first gate electrode 203 and the second gate electrode 204 of the multi-gate IGBT 200 in the second direction D2. Also, the emitter electrode is located between the first gate electrode 213 and the second gate electrode 214 of the multi-gate IGBT 210 in the second direction D2. In this case, as shown in FIG. 4B, the second conductor 110, the third conductor 120, and the fourth conductor 121 are electrically isolated from each other while being at the same height. Similarly to the second embodiment, the first gate electrode 203 and the second gate electrode 204 of the multi-gate IGBT 200 may be displaced in the first direction D1, and the first gate electrode 213 and the second gate electrode 214 of the multi-gate IGBT 210 may also be displaced in the first direction D1.

[0078] In the third embodiment, the preferred ranges of the second distance d2 and the fourth distance d4 are the same as those in the first embodiment, but the first distance d1 and the third distance d3 do not need to be within specific ranges.

[0079] The distance between the second gate electrode 204 and the emitter electrode 202 of the multi-gate IGBT 200 is defined as a fifth distance d5. The fifth distance d5 is preferably, for example, 50 μm or more and 500 μm or less. When the fifth distance d5 is 50 μm or more, it becomes easy to ensure, for example, a dielectric strength voltage between the second gate electrode 204 and the emitter electrode 202. When the fifth distance d5 is 500 μm or less, it becomes easy, for example, to miniaturize the multi-gate IGBT 200.

[0080] The distance between the fourth conductor 121 and the second conductor 110 is defined as a sixth distance d6. The sixth distance d6 is preferably, for example, 50 μm or more and 1000 μm or less. When the sixth distance d6 is 50 μm or more, it becomes easy to ensure, for example, a dielectric strength voltage between the fourth conductor 121 and the second conductor 110.

[0081] (Fourth embodiment) The fourth embodiment relates to an electrode arrangement of a multi-gate IGBT and a method of connecting the multi-gate IGBT to a conductor. Figures 5(a) and 5(b) are schematic diagrams illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the first embodiment. Figure 5(a) is a plan view showing the multi-gate IGBT and diodes according to the fourth embodiment, and Figure 5(b) is a plan view showing the positional relationship between the multi-gate IGBT and diodes according to the fourth embodiment and the conductors.

[0082] As shown in FIG. 5( a), in the fourth embodiment, a portion of a first gate electrode 203 of a multi-gate IGBT 200 is surrounded by an emitter electrode 202. Also, a portion of a first gate electrode 213 of a multi-gate IGBT 210 is surrounded by an emitter electrode 212. In the first direction, the first gate electrodes 203, 213 are located between a portion of the emitter electrodes 202, 212. In such a case, too, by wiring the third conductor 120 so that it passes between the first gate electrode 203 and the second gate electrode 204, as shown in FIG. 5( b), the second conductor 110, the third conductor 120, and the fourth conductor 121 are electrically isolated from each other while being at the same height. The first gate electrode 203 and the second gate electrode 204 of the multi-gate IGBT 200 may be displaced in the first direction D1, as in the second embodiment, and the first gate electrode 213 and the second gate electrode 214 of the multi-gate IGBT 210 may also be displaced in the first direction D1, as in the second embodiment. The third conductor 120 has a portion extending in the second direction D2, and by contacting the first gate electrode at this portion, the portion extending in the first direction D1 can be narrowed and the contact area can be increased. Because the portion extending in the first direction D1 is narrow, the first distance d1 can be reduced. The first distance d1 is preferably, for example, 5000 μm or less.

[0083] In the fourth embodiment, the first distance d1 is preferably, for example, 500 μm or more. When the first distance d1 is 500 μm or more, for example, it becomes easy to wire the conductor 120 between the first gate electrode 203 and the second gate electrode 204.

[0084] (Fifth embodiment) The fifth embodiment relates to an electrode arrangement of a multi-gate IGBT and a method of connecting the multi-gate IGBT to a conductor. Figures 6(a) and 6(b) are schematic diagrams illustrating the multi-gate IGBT, diodes, and conductors included in the semiconductor module according to the first embodiment. Figure 6(a) is a plan view showing the multi-gate IGBT and diodes according to the fifth embodiment, and Figure 6(b) is a plan view showing the positional relationship between the multi-gate IGBT and diodes according to the fifth embodiment and the conductors.

[0085] As shown in FIG. 6(a), in the fifth embodiment, a portion of the first gate electrode 203 and a portion of the second gate electrode 204 of a multi-gate IGBT 200 have the same D2 coordinate. The position of a portion of the first gate electrode 203 and a portion of the second gate electrode 204 are the same in the second direction D2. Furthermore, a portion of the first gate electrode 213 and a portion of the second gate electrode 214 of a multi-gate IGBT 210 have the same D2 coordinate. Even in this case, as shown in FIG. 6(b), by wiring the third conductor 120 so that it is not directly above the second gate electrodes 204 and 214 and wiring the fourth conductor 121 so that it is not directly above the first gate electrodes 203 and 213, the second conductor 110, the third conductor 120, and the fourth conductor 121 are electrically isolated from each other while being at the same height. In the second direction, the third conductor 120 is located between the second gate electrodes 204 and 214 and the emitter electrodes 202 and 212. The first gate electrode 203 and the second gate electrode 204 of the multi-gate IGBT 200 may be displaced in the first direction D1 as in the second embodiment, and the first gate electrode 213 and the second gate electrode 214 of the multi-gate IGBT 210 may also be displaced in the first direction D1 as in the second embodiment. By arranging the first gate electrode 203 and the second gate electrode 204 so that a part of them overlaps in the second direction, the first gate electrode 203 and the second gate electrode 204 can be formed large.

[0086] The distance between the bottom end of the first gate electrode 203 and the bottom end of the second gate electrode 204 of the multi-gate IGBT 200 is defined as a seventh distance d7. The distance between the emitter electrode side end of the first gate electrode and the emitter electrode side end of the second gate electrode is the seventh distance d7. The seventh distance d7 is preferably, for example, 500 μm or more. When the seventh distance d7 is 500 μm or more, it becomes easy to wire the conductor 120 between the second gate electrode 204 and the emitter electrode 202, for example.

[0087] (Sixth embodiment) The sixth embodiment relates to an electrode arrangement of a multi-gate IGBT and a method of connecting the multi-gate IGBT to a conductor. Figures 7(a) and 7(b) are schematic diagrams illustrating a multi-gate IGBT, a diode, and a conductor included in the semiconductor module according to the first embodiment. Figure 7(a) is a plan view showing a multi-gate IGBT and a diode according to the sixth embodiment, and Figure 7(b) is a plan view showing the positional relationship between the multi-gate IGBT and the diode according to the sixth embodiment and the conductor.

[0088] 7(a), in the sixth embodiment, a first gate electrode 203 and a second gate electrode 204 of a multi-gate IGBT 200 are arranged at an interval only in a first direction D1, and the first gate electrode 203 and the second gate electrode 204 are arranged at an interval in a second direction from an emitter electrode 202. Also, a first gate electrode 213 and a second gate electrode 214 of a multi-gate IGBT 210 are arranged at an interval only in the first direction D1, and the first gate electrode 213 and the second gate electrode 214 are arranged at an interval in a second direction D2 from an emitter electrode 212. 7(b), by wiring the third conductor 120 so that it passes between the first gate electrodes 203, 213 and the second gate electrodes 204, 214 and the emitter electrodes 202, 212, and by wiring the fourth conductor 121 on the terminal side as seen from the first gate electrodes 203, 213 and the second gate electrodes 204, 214, the second conductor 110, the third conductor 120, and the fourth conductor 121 are electrically separated while existing at the same height. Furthermore, the first gate electrode 203 and the second gate electrode 204 of the multi-gate IGBT 200 may be displaced in the first direction D1 as in the second embodiment, and the first gate electrode 213 and the second gate electrode 214 of the multi-gate IGBT 210 may also be displaced in the first direction D1 as in the second embodiment.

[0089] In the sixth embodiment, the second distance d2 and the fifth distance d5 are preferably, for example, 500 μm or more. When the second distance d2 and the fifth distance d5 are 500 μm or more, for example, it becomes easy to wire the conductor 120 between the first gate electrode 203 and the emitter electrode 202 and between the second gate electrode 204 and the emitter electrode 202.

[0090] In the above example, a case where one multi-gate IGBT has a first gate electrode and a second gate electrode has been described, but one embodiment or a combination of multiple embodiments can be applied to a case where the multi-gate IGBT has any number of gate electrodes, two or more, such as a first gate electrode, a second gate electrode, a third gate electrode, ..., an Nth gate electrode.

[0091] The embodiment may include the following configurations (e.g., technical solutions).

[0092] (Configuration 1) a first conductor extending in a first direction and a second direction intersecting the first direction; a second conductor extending in the first direction and spaced apart from the first conductor in a third direction intersecting the first direction and the second direction; a third conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; a fourth conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; A plurality of conductive bonding materials; A plurality of multi-gate semiconductor devices, the multi-gate semiconductor devices comprising: a semiconductor layer having a first surface and a second surface; a collector electrode located on the first surface and joined to the first conductor via a conductive bonding material; an emitter electrode located on the second surface and joined to the second conductor via a conductive bonding material; a first gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the third conductor via a conductive joining material; a second gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the fourth conductor via a conductive joining material; a plurality of multi-gate type semiconductor devices including a plurality of multi-gate type semiconductor devices each comprising: A semiconductor module having:

[0093] (Configuration 2) 2. The semiconductor module according to claim 1, wherein the first gate electrode and the second gate electrode are spaced apart in the second direction.

[0094] (Configuration 3) a first distance between the first gate electrode and the second gate electrode is not less than 50 μm and not more than 500 μm; a second distance between the first gate electrode and the emitter electrode is not less than 50 μm and not more than 500 μm; a third distance between the third conductor and the fourth conductor is 50 μm or more; 3. The semiconductor module according to claim 1, wherein a fourth distance between the second conductor and the third conductor is 50 μm or more.

[0095] (Configuration 4) 2. The semiconductor module according to claim 1, wherein the emitter electrode is located between the first gate electrode and the second gate electrode in the second direction.

[0096] (Configuration 5) a second distance between the first gate electrode and the emitter electrode is not less than 50 μm and not more than 500 μm; a fifth distance between the second gate electrode and the emitter electrode is not less than 50 μm and not more than 500 μm; a fourth distance between the second conductor and the third conductor is 50 μm or more; 5. The semiconductor module according to claim 1, wherein a sixth distance between the second conductor and the fourth conductor is 50 μm or more.

[0097] (Configuration 6) a portion of the first gate electrode is located between a portion and another portion of the emitter in the first direction; 2. The semiconductor module of claim 1, wherein the third conductor is located between the first gate electrode and the second gate electrode in the second direction.

[0098] (Configuration 7) a position of a part of the first gate electrode and a position of a part of the second gate electrode are the same in the second direction; 2. The semiconductor module according to claim 1, wherein the third conductor is located between the second gate electrode and the emitter electrode in the second direction.

[0099] (Configuration 8) 2. The semiconductor module according to claim 1, wherein a seventh distance between the emitter electrode side end of the first gate electrode and the emitter electrode side end of the second gate electrode is 500 μm or more.

[0100] (Configuration 9) the first gate electrode and the second gate electrode are arranged in the first direction with an interval therebetween and are at the same position in the second direction; 2. The semiconductor module according to claim 1, wherein the third conductor is located between the first gate electrode and the second gate electrode and the emitter electrode in the second direction.

[0101] (Configuration 10) a first distance between the first gate electrode and the second gate electrode is not less than 50 μm and not more than 500 μm; a second distance between the first gate electrode and the emitter electrode is not less than 50 μm and not more than 500 μm; a third distance between the third conductor and the fourth conductor is 50 μm or more; 10. The semiconductor module of claim 9, wherein a fourth distance between the second conductor and the third conductor is 50 μm or more.

[0102] (Configuration 11) The multi-gate semiconductor device comprises: a first semiconductor region of a first conductivity type located between the collector electrode and the emitter electrode; a second semiconductor region of a second conductivity type located between the first semiconductor region and the emitter electrode; a third semiconductor region of the first conductivity type located between the second semiconductor region and the emitter electrode and in contact with the emitter electrode; a fourth semiconductor region of the second conductivity type located between the first semiconductor region and the emitter electrode; a fifth semiconductor region of the first conductivity type located between the second semiconductor region and the emitter electrode and in contact with the emitter electrode; a first gate conductor that faces the second semiconductor region and the third semiconductor region via an insulating film and is connected to the first gate electrode; 2. The semiconductor module according to configuration 1, further comprising: a second gate conductor that faces the fourth semiconductor region and the fifth semiconductor region via an insulating film and is connected to the second gate electrode.

[0103] (Configuration 12) 12. The semiconductor module according to claim 11, wherein the multi-gate semiconductor device has a sixth semiconductor region of a second conductivity type located between the collector electrode and the first semiconductor.

[0104] (Configuration 13) 2. The semiconductor module according to claim 1, wherein the multi-gate semiconductor device is an IGBT.

[0105] (Configuration 14) a plurality of switching elements, each including a first surface and a second surface extending in a first direction and a second direction intersecting the first direction, a collector electrode located on the first surface and connected to the first conductive plate, an emitter electrode located on the second surface, a first gate electrode located on the second surface, and a second gate electrode located on the second surface; a plurality of conductive bonding materials respectively connected to the plurality of emitter electrodes, the plurality of first gate electrodes, and the plurality of third gate electrodes; a first conductive plate extending in a first direction and electrically connected to a plurality of collector electrodes of the plurality of switching elements; a second conductive plate extending in a first direction and electrically connected to the emitter electrodes of the switching elements via the conductive bonding materials; a third conductive plate extending in a first direction and electrically connected to the first gate electrodes of the switching elements via the conductive bonding materials; a conductive fourth conductive plate extending in a first direction and electrically connected to the second gate electrodes of the switching elements via the bonding materials; A semiconductor module having:

[0106] According to the embodiment, it is possible to provide a semiconductor module that enables a plurality of multi-gate IGBTs that suppress loss to be mounted on both sides, including the gate portions.

[0107] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in the semiconductor module, such as the semiconductor device, metal bonding material, conductor, heat dissipation fin, and control unit, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0108] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0109] In addition, all semiconductor modules that can be implemented by a person skilled in the art by making appropriate design modifications based on the semiconductor module described above as an embodiment of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0110] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of the present invention.

[0111] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0112] 10...semiconductor module, 80...first substrate, 81...second substrate, 90, 92...base layer, 91, 93...insulating layer, 100...first conductor, 110...second conductor, 120...third conductor, 121...fourth conductor, 200, 210...multi-gate IGBT, 200A...left end of multi-gate IGBT 200, 200B...right end of multi-gate IGBT 200, 201, 211...collector electrode, 202, 212...emitter electrode, 203, 213...first gate electrode, 204, 214...second gate electrode, 300-390...metallic bonding material, 500, 510...diode, 501, 511...cathode electrode, 502, 512...anode electrode, D1~D3...1st~3rd direction, d1~d7...1st~7th distance

Claims

1. a first conductor extending in a first direction and a second direction intersecting the first direction; a second conductor extending in the first direction and spaced apart from the first conductor in a third direction intersecting the first direction and the second direction; a third conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; a fourth conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; A plurality of conductive bonding materials; A plurality of multi-gate semiconductor devices, the multi-gate semiconductor devices comprising: a semiconductor layer having a first surface and a second surface; a collector electrode located on the first surface and joined to the first conductor via a conductive bonding material; an emitter electrode located on the second surface and joined to the second conductor via a conductive bonding material; a first gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the third conductor via a conductive joining material; a second gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the fourth conductor via a conductive joining material; a plurality of multi-gate semiconductor devices, A semiconductor module having: the first gate electrode and the second gate electrode are spaced apart in the second direction, the first gate electrode is located between the second gate electrode and the emitter electrode in the second direction.

2. a first conductor extending in a first direction and a second direction intersecting the first direction; a second conductor extending in the first direction and spaced apart from the first conductor in a third direction intersecting the first direction and the second direction; a third conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; a fourth conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; A plurality of conductive bonding materials; A plurality of multi-gate semiconductor devices, the multi-gate semiconductor devices comprising: a semiconductor layer having a first surface and a second surface; a collector electrode located on the first surface and joined to the first conductor via a conductive bonding material; an emitter electrode located on the second surface and joined to the second conductor via a conductive bonding material; a first gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the third conductor via a conductive joining material; a second gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the fourth conductor via a conductive joining material; a plurality of multi-gate semiconductor devices, A semiconductor module having: a portion of the first gate electrode is located between a portion and another portion of the emitter electrode in the first direction; the third conductor is located between the first gate electrode and the second gate electrode in the second direction.

3. a first conductor extending in a first direction and a second direction intersecting the first direction; a second conductor extending in the first direction and spaced apart from the first conductor in a third direction intersecting the first direction and the second direction; a third conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; a fourth conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; A plurality of conductive bonding materials; A plurality of multi-gate semiconductor devices, the multi-gate semiconductor devices comprising: a semiconductor layer having a first surface and a second surface; a collector electrode located on the first surface and joined to the first conductor via a conductive bonding material; an emitter electrode located on the second surface and joined to the second conductor via a conductive bonding material; a first gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the third conductor via a conductive joining material; a second gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the fourth conductor via a conductive joining material; a plurality of multi-gate semiconductor devices, A semiconductor module having: a position of a part of the first gate electrode and a position of a part of the second gate electrode are the same in the second direction; a semiconductor module in which the third conductor is located between the second gate electrode and the emitter electrode in the second direction;

4. a first conductor extending in a first direction and a second direction intersecting the first direction; a second conductor extending in the first direction and spaced apart from the first conductor in a third direction intersecting the first direction and the second direction; a third conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; a fourth conductor extending in the first direction and positioned in the third direction at the same position as the second conductor; A plurality of conductive bonding materials; A plurality of multi-gate semiconductor devices, the multi-gate semiconductor devices comprising: a semiconductor layer having a first surface and a second surface; a collector electrode located on the first surface and joined to the first conductor via a conductive bonding material; an emitter electrode located on the second surface and joined to the second conductor via a conductive bonding material; a first gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the third conductor via a conductive joining material; a second gate electrode located on the second surface, spaced apart from the emitter electrode in the second direction, and joined to the fourth conductor via a conductive joining material; a plurality of multi-gate semiconductor devices, A semiconductor module having: the first gate electrode and the second gate electrode are arranged in the first direction with an interval therebetween, and the first gate electrode and the second gate electrode are positioned at the same position in the second direction; the third conductor is located between the first gate electrode and the second gate electrode and the emitter electrode in the second direction.

5. 3. The semiconductor module according to claim 1, wherein the first gate electrode and the second gate electrode are spaced apart in the second direction.

6. a first distance between the first gate electrode and the second gate electrode is not less than 50 μm and not more than 500 μm; a second distance between the first gate electrode and the emitter electrode is not less than 50 μm and not more than 500 μm; a third distance between the third conductor and the fourth conductor is 50 μm or more; The semiconductor module according to claim 5 , wherein a fourth distance between the second conductor and the third conductor is equal to or greater than 50 μm.

7. 4. The semiconductor module according to claim 1, wherein a seventh distance between the end of the first gate electrode on the emitter electrode side and the end of the second gate electrode on the emitter electrode side is 500 [mu]m or more.

8. a first distance between the first gate electrode and the second gate electrode is not less than 50 μm and not more than 500 μm; a second distance between the first gate electrode and the emitter electrode is not less than 50 μm and not more than 500 μm; a third distance between the third conductor and the fourth conductor is 50 μm or more; The semiconductor module according to claim 7 , wherein a fourth distance between the second conductor and the third conductor is equal to or greater than 50 μm.

9. The multi-gate semiconductor device comprises: a first semiconductor region of a first conductivity type located between the collector electrode and the emitter electrode; a second semiconductor region of a second conductivity type located between the first semiconductor region and the emitter electrode; a third semiconductor region of the first conductivity type located between the second semiconductor region and the emitter electrode and in contact with the emitter electrode; a fourth semiconductor region of the second conductivity type located between the first semiconductor region and the emitter electrode; a fifth semiconductor region of the first conductivity type located between the second semiconductor region and the emitter electrode and in contact with the emitter electrode; a first gate conductor that faces the second semiconductor region and the third semiconductor region via an insulating film and is connected to the first gate electrode; 5. The semiconductor module according to claim 1, further comprising: a second gate conductor that faces the fourth semiconductor region and the fifth semiconductor region via an insulating film and is connected to the second gate electrode.

10. The multi-gate semiconductor device is located between the collector electrode and the first semiconductor region.

10. The semiconductor module according to claim 9, further comprising a sixth semiconductor region of the second conductivity type.

11. 5. The semiconductor module according to claim 1, wherein the multi-gate semiconductor device is an IGBT.

12. a plurality of switching elements each including a first surface and a second surface extending in a first direction and a second direction intersecting the first direction, a collector electrode located on the first surface, an emitter electrode located on the second surface, a first gate electrode located on the second surface, and a second gate electrode located on the second surface; a plurality of conductive bonding materials respectively connected to the plurality of emitter electrodes, the plurality of first gate electrodes, and the plurality of second gate electrodes; a first conductor extending in a first direction and electrically connected to a plurality of collector electrodes of the plurality of switching elements; a second conductor extending in a first direction and electrically connected to the emitter electrodes of the switching elements via the conductive bonding materials; a third conductor extending in a first direction and electrically connected to the first gate electrodes of the switching elements via the conductive bonding materials; a fourth conductor extending in a first direction and electrically connected to the second gate electrodes of the switching elements via the conductive bonding materials; the third conductor and the fourth conductor are located at the same positions as the second conductor in a third direction intersecting the first direction and the second direction, the first gate electrode and the second gate electrode are spaced apart in the second direction, the first gate electrode is located between the second gate electrode and the emitter electrode in the second direction; Semiconductor module.

13. a plurality of switching elements each including a first surface and a second surface extending in a first direction and a second direction intersecting the first direction, a collector electrode located on the first surface, an emitter electrode located on the second surface, a first gate electrode located on the second surface, and a second gate electrode located on the second surface; a plurality of conductive bonding materials respectively connected to the plurality of emitter electrodes, the plurality of first gate electrodes, and the plurality of second gate electrodes; a first conductor extending in a first direction and electrically connected to a plurality of collector electrodes of the plurality of switching elements; a second conductor extending in a first direction and electrically connected to the emitter electrodes of the switching elements via the conductive bonding materials; a third conductor extending in a first direction and electrically connected to the first gate electrodes of the switching elements via the conductive bonding materials; a fourth conductor extending in a first direction and electrically connected to the second gate electrodes of the switching elements via the conductive bonding materials; the third conductor and the fourth conductor are located at the same positions as the second conductor in a third direction intersecting the first direction and the second direction, a portion of the first gate electrode is located between a portion and another portion of the emitter electrode in the first direction; the third conductor is located between the first gate electrode and the second gate electrode in the second direction. Semiconductor module.

14. a plurality of switching elements each including a first surface and a second surface extending in a first direction and a second direction intersecting the first direction, a collector electrode located on the first surface, an emitter electrode located on the second surface, a first gate electrode located on the second surface, and a second gate electrode located on the second surface; a plurality of conductive bonding materials respectively connected to the plurality of emitter electrodes, the plurality of first gate electrodes, and the plurality of second gate electrodes; a first conductor extending in a first direction and electrically connected to a plurality of collector electrodes of the plurality of switching elements; a second conductor extending in a first direction and electrically connected to the emitter electrodes of the switching elements via the conductive bonding materials; a third conductor extending in a first direction and electrically connected to the first gate electrodes of the switching elements via the conductive bonding materials; a fourth conductor extending in a first direction and electrically connected to the second gate electrodes of the switching elements via the conductive bonding materials; the third conductor and the fourth conductor are located at the same positions as the second conductor in a third direction intersecting the first direction and the second direction, a position of a part of the first gate electrode and a position of a part of the second gate electrode are the same in the second direction; a semiconductor module in which the third conductor is located between the second gate electrode and the emitter electrode in the second direction;

15. a plurality of switching elements each including a first surface and a second surface extending in a first direction and a second direction intersecting the first direction, a collector electrode located on the first surface, an emitter electrode located on the second surface, a first gate electrode located on the second surface, and a second gate electrode located on the second surface; a plurality of conductive bonding materials respectively connected to the plurality of emitter electrodes, the plurality of first gate electrodes, and the plurality of second gate electrodes; a first conductor extending in a first direction and electrically connected to a plurality of collector electrodes of the plurality of switching elements; a second conductor extending in a first direction and electrically connected to the emitter electrodes of the switching elements via the conductive bonding materials; a third conductor extending in a first direction and electrically connected to the first gate electrodes of the switching elements via the conductive bonding materials; a fourth conductor extending in a first direction and electrically connected to the second gate electrodes of the switching elements via the conductive bonding materials; the third conductor and the fourth conductor are located at the same positions as the second conductor in a third direction intersecting the first direction and the second direction, the first gate electrode and the second gate electrode are arranged in the first direction with an interval therebetween, and the first gate electrode and the second gate electrode are positioned at the same position in the second direction; the third conductor is located between the first gate electrode and the second gate electrode and the emitter electrode in the second direction.

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