Thyristor rectifier control system

Abstract

To provide a thyristor rectifier control system that can appropriately and easily perform a gate pulse test.SOLUTION: A monitoring operation panel 21 includes a breaker control circuit 81 in which a breaker closing ready signal is asserted, a monitoring operation panel acquires the authority to operate a circuit breaker using the circuit breaker operation selector switch, and the circuit breaker is closed when the circuit breaker is instructed to close by the circuit breaker operation switch. A control panel 20 includes a second current setting controller 23 that sets the magnitude of the current output from a thyristor rectifier as the magnitude of the second current, a second current generator 24 that generates the second current having a magnitude set by the second current setting controller 23, and a third arithmetic circuit 103 that negates the breaker closing ready signal when the condition that the gate start signal is asserted is satisfied.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a control system for a thyristor rectifier. [Background technology]

[0002] Test equipment for power conversion devices equipped with rectifiers has been known for some time. For example, the test equipment described in Patent Document 1 includes a transformer, a test device, a test reactor, a control device, a current detector, a monitoring device, a current detector, a voltage detector, a first reactor, a second reactor, and a capacitor. The monitoring device performs a functional test of the inverter. In the inverter functional test, for example, the monitoring device acquires values ​​of the inverter's output current and output voltage from the current detector and determines whether they comply with specified test conditions to perform a functional test to determine whether the inverter is operating normally. The test equipment performs power conversion operation simulating load operation by being PWM-controlled by a second PWM control unit of the control device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-145909 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there are cases where the operating equipment is installed in a remote monitoring operation panel, and the control board is installed in a control panel adjacent to the thyristor rectifier body. In such cases, the following problems arise: The tester performing the gate pulse test must move to the monitoring operation panel to set the current, which is inconvenient; and during a gate pulse test using the control panel, the circuit breaker may be closed at the remote monitoring operation panel, making it impossible to perform the gate pulse test properly.

[0005] Therefore, an object of the present disclosure is to provide a control system for a thyristor rectifier that can properly and easily perform a gate pulse test. [Means for solving the problem]

[0006] The thyristor rectifier control system of the present disclosure includes a control panel and a monitoring operation panel. The monitoring operation panel includes a circuit breaker operation changeover switch for acquiring operation authority for the circuit breaker, a circuit breaker operation switch for instructing circuit breaker closing or opening, a circuit breaker control circuit for closing the circuit breaker when a circuit breaker closing preparation completion signal is asserted and the circuit breaker operation changeover switch acquires operation authority for the circuit breaker and the circuit breaker operation switch instructs closing the circuit breaker, a first current setting operator for setting the magnitude of a current output from the thyristor rectifier as the magnitude of a first current, and a first current generator for generating the first current having the magnitude set by the first current setting operator. The control panel includes a control board, a test instruction switch for issuing a test instruction, a first arithmetic circuit for asserting a first test mode signal when the test instruction switch is turned on and a circuit breaker tripping confirmation signal confirming that the circuit breaker is in an tripped state is asserted, a second arithmetic circuit for asserting a gate start signal and supplying it to the control board when the condition for the first test mode signal is asserted, a third arithmetic circuit for negating a circuit breaker closing preparation completion signal when the condition for the gate start signal is asserted, a second current setting operator for setting the magnitude of a current output from the thyristor rectifier as the magnitude of a second current, and a second current generator for generating the second current of the magnitude set by the second current setting operator. The control board includes a gate pulse generator for generating a gate pulse signal and supplying it to the thyristor rectifier when the gate start signal is asserted, and a current controller for setting the phase angle of the gate pulse signal based on the first current or the second current. [Effects of the Invention]

[0007] According to the present disclosure, the control panel includes a second current setting controller that sets the magnitude of the current output from the thyristor rectifier as the magnitude of the second current, a second current generator that generates the second current having the magnitude set by the second current setting controller, and a third arithmetic circuit that negates a circuit breaker closing preparation completion signal when a condition that the gate start signal is asserted is satisfied. The monitoring operation panel includes a circuit breaker control circuit that closes the circuit breaker when the circuit breaker closing preparation completion signal is asserted, the monitoring operation panel acquires control authority for the circuit breaker via the circuit breaker operation changeover switch, and the circuit breaker closing command is instructed by the circuit breaker operation switch. This eliminates the need for a tester performing a gate pulse test to travel to the monitoring operation panel to set the current, and prevents the circuit breaker from being closed at a remote monitoring operation panel during a gate pulse test using the control panel. As a result, the gate pulse test can be performed appropriately and easily. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram showing the configuration of a control and monitoring panel 10 of a reference example. [Figure 2] 1 is a diagram showing a control board 14, an AC power supply 32, a circuit breaker 33, a thyristor rectifier 31, and a load LD. [Figure 3] 1 is a diagram illustrating an example of a control system for a thyristor rectifier according to an embodiment; [Figure 4] 2 is a diagram showing a first current setting controller 84 and a first current generator 80. FIG. [Figure 5] 2 is a diagram showing a second current setting controller 23 and a second current generator 24. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, identical or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0010] [Reference example] Fig. 1 is a diagram showing the configuration of a control and monitoring panel 10 of a reference example. Fig. 2 is a diagram showing a control board 14, an AC power supply 32, a circuit breaker 33, a thyristor rectifier 31, and a load LD.

[0011] In the reference example, the control and monitoring operation functions of the thyristor rectifier are concentrated in a control and monitoring panel 10 installed remotely from the thyristor rectifier itself. Gate pulse tests and light load tests are performed using the operating devices and control board 14 installed in the control and monitoring panel 10. In the gate pulse test, a gate start signal is supplied to the control board without closing the circuit breaker, causing the control board to send a gate pulse signal to the thyristor rectifier. In the light load test, a gate start signal is supplied to the control board after closing the circuit breaker, causing the control board to send a gate pulse signal to the thyristor rectifier.

[0012] The control and monitoring panel 10 includes a test instruction switch 51, a circuit breaker operation authority acquisition switch 52, a current setting operation authority acquisition switch 53, a current setting operation device 54, a PLC (Programmable Logic Controller) 12, and a control board 14.

[0013] The PLC 12 includes an AND circuit 55 , a NAND circuit 57 , a flip-flop 56 , a current generator 60 , a lower limit determination circuit 59 , and an AND circuit 58 .

[0014] When the test instruction switch 51 is set to ON, the test instruction signal X1 is asserted to a high level. When the test instruction switch 51 is set to OFF, the test instruction signal X1 is negated to a low level.

[0015] The circuit breaker tripping confirmation signal X2 is sent from another control panel. When the circuit breaker 33 is tripped, the circuit breaker tripping confirmation signal X2 is asserted to a high level. When the circuit breaker 33 is closed, the circuit breaker tripping confirmation signal X2 is negated to a low level.

[0016] The circuit breaker operation authority acquisition switch 52 is a switch for acquiring the operation authority of the circuit breaker 33 in the control monitoring panel 10. When the circuit breaker operation authority acquisition switch 52 is set to ON, the circuit breaker operation authority acquisition signal X3 is asserted to a high level. When the circuit breaker operation authority acquisition switch 52 is set to OFF, the circuit breaker operation authority acquisition signal X3 is negated to a low level.

[0017] The current setting operation authority acquisition switch 53 is a switch for acquiring authority to set the output current of the thyristor rectifier 31 in the control monitoring panel 10. When the current setting operation authority acquisition switch 53 is set to on, the current setting operation authority acquisition signal X4 is asserted to a high level. When the current setting operation authority acquisition switch 53 is set to off, the current setting operation authority acquisition signal X4 is negated to a low level.

[0018] The AND circuit 55 outputs a signal Y1 representing the logical product of the test instruction signal X1, the circuit breaker tripping confirmation signal X2, the circuit breaker operation authority acquisition signal X3, and the current setting operation authority acquisition signal X4.

[0019] The NAND circuit 57 outputs a signal Y2 representing the NAND of the test instruction signal X1, the circuit breaker operation authority acquisition signal X3, and the current setting operation authority acquisition signal X4.

[0020] The flip-flop 56 has a set terminal S that receives the output signal Y1 of the AND circuit 55, a reset terminal R that receives the output signal Y2 of the NAND circuit 57, and an output terminal that outputs the test mode signal TM.

[0021] The current setting controller 54 sets the magnitude of the current output from the thyristor rectifier 31. The current generator 60 generates a current I0 of the magnitude set by the current setting controller 54 and supplies it to the control board 14.

[0022] The lower limit determination circuit 59 asserts a lower limit signal IL when the magnitude of the current set by the current setting operator 54 is at the lower limit, and negates the lower limit signal IL when the magnitude is greater than the lower limit.

[0023] The AND circuit 58 outputs the logical product of the test mode signal TM and the lower limit signal IL as a gate start signal GS. The gate start signal GS is supplied to the control board 14.

[0024] The AC power supply 32 is connected to the thyristor rectifier 31 via a circuit breaker 33. When the circuit breaker 33 is closed, the AC current from the AC power supply 32 is supplied to the thyristor rectifier 31. When the circuit breaker 33 is shut off, the AC current from the AC power supply 32 is not supplied to the thyristor rectifier 31.

[0025] The thyristor rectifier 31 includes U-phase thyristors (thyristor elements) 5U and 5X, V-phase thyristors 5V and 5Y, and W-phase thyristors 5W and 5Z. The anode of thyristor 5U is connected to the cathode of thyristor 5X, the anode of thyristor 5V is connected to the cathode of thyristor 5Y, and the anode of thyristor 5W is connected to the cathode of thyristor 5Z. The anodes of thyristors 5X, 5Y, and 5Z are common, and the cathodes of thyristors 5U, 5V, and 5W are common. A load LD is connected in parallel between the cathode of thyristor 5W and the anode of thyristor 5Z.

[0026] The control board 14 includes a reference phase detector 16 , a current controller 15 , and a gate pulse generator 17 .

[0027] The reference phase detector 16 uses the point where the line voltage of the rectifier AC voltages VU, VV, VW changes from a negative voltage to a positive voltage as a reference point (reference phase), and outputs reference phases SU, SV, SW of the UVW phases to the gate pulse generator 17.

[0028] The current controller 15 follows the current I0 output from the PLC 12, and outputs a voltage according to a thyristor control angle signal α that indicates the control angle of the thyristor rectifier 31 (the phase angle of the gate pulse signal).

[0029] The gate pulse generator 17 outputs gate pulse signals PU, PX, PV, PY, PW, and PZ for firing the thyristor rectifier 31 when the gate start signal GS is asserted. The gate pulse signal PU is a signal for firing the thyristor 5U. The gate pulse signal PX is a signal for firing the thyristor 5X. The gate pulse signal PV is a signal for firing the thyristor 5V. The gate pulse signal PY is a signal for firing the thyristor 5Y. The gate pulse signal PW is a signal for firing the thyristor 5W. The gate pulse signal PZ is a signal for firing the thyristor 5Z.

[0030] When the gate start signal GS is asserted, the gate pulse generator 17 outputs gate pulse signals PU, PX, PV, PY, PW, and PZ for firing the thyristors 5U, 5X, 5V, 5Y, 5W, and 5Z based on the reference phases SU, SV, and SW and the thyristor control angle signal α, thereby performing a rectification operation.

[0031] The thyristor rectifier 31 supplies a DC voltage to the load LD in accordance with the timing of the gate pulse signals PU, PX, PV, PY, PW, and PZ.

[0032] In the reference example, the control function and monitoring operation function of the thyristor rectifier 31 are concentrated in a control and monitoring panel 10 installed at a location far away from the main body of the thyristor rectifier 31. In the reference example, when a thyristor rectifier having a constant current control function is used to perform a gate pulse test and a light load test, the tester must move to the control and monitoring panel 10 installed at a distance to set the current, which is inconvenient.

[0033] [Embodiment Mode] FIG. 3 is a diagram illustrating an example of a control system for a thyristor rectifier according to an embodiment.

[0034] The control system for the thyristor rectifier includes a control panel 20 and a monitoring operation panel 21.

[0035] The control panel 20 is installed adjacent to the thyristor rectifier 31. The monitoring operation panel 21 is installed at a position far away from the thyristor rectifier 31.

[0036] The monitoring operation panel 21 includes a circuit breaker operation authority acquisition switch 82, a circuit breaker operation switch 83, a first current setting operation device 84, and the PLC 22. The PLC 22 includes a circuit breaker control circuit 81 and a first current generator 80.

[0037] The circuit breaker operation authority acquisition switch 82 is a switch for acquiring the operation authority of the circuit breaker 33 .

[0038] The circuit breaker operation switch 83 is a switch for instructing the circuit breaker 33 to be turned on or off.

[0039] The circuit breaker control circuit 81 closes the circuit breaker 33 when the circuit breaker closing preparation completion signal CBP is asserted, the monitoring operation panel 21 acquires the operation authority for the circuit breaker 33 by the circuit breaker operation authority acquisition switch 82, and the circuit breaker operation switch 83 instructs closing the circuit breaker 33.

[0040] The first current setting controller 84 sets the magnitude of the current output from the thyristor rectifier 31 as the magnitude of the first current. The first current generator 80 generates a first current Ix having the magnitude set by the first current setting controller 84. The first current setting controller 84 is operated by a supervisor when the thyristor rectifier 31 is actually operating.

[0041] 4 is a diagram showing a first current setting controller 84 and a first current generator 80. The first current setting controller 84 is a twist switch. The first current generator 80 generates a first current Ix having a magnitude corresponding to the amount of operation of the twist switch.

[0042] The control panel 20 includes a test instruction switch 11, a first arithmetic circuit 101, a second arithmetic circuit 102, a third arithmetic circuit 103, a fourth arithmetic circuit 104, a second current setting controller 23, a second current generator 24, a lower limit judgment circuit 59, a selector switch ST, and a control board 14.

[0043] The test instruction switch 11 issues a test instruction. When the test instruction switch 11 is set to ON, the test instruction signal X1 is asserted to a high level. When the test instruction switch 11 is set to OFF, the test instruction signal X1 is negated to a low level.

[0044] When the circuit breaker 33 is in the off state, the circuit breaker tripping confirmation signal X2 is asserted to a high level. When the circuit breaker 33 is in the on state, the circuit breaker tripping confirmation signal X2 is negated to a low level.

[0045] The second current setting controller 23 sets the magnitude of the current output from the thyristor rectifier 31 as the magnitude of the second current. The second current generator 24 generates a second current Iy having the magnitude set by the second current setting controller 23. The second current setting controller 23 is operated by a tester when the thyristor rectifier 31 is subjected to a test operation.

[0046] FIG. 5 is a diagram showing the second current setting controller 23 and the second current generator 24. As shown in FIG.

[0047] The second current setting controller 23 includes a limit switch (a switch whose contact state changes at the lower limit of the current setting). The second current generator 24 includes a voltage divider circuit. The voltage divider circuit includes resistors R1, VR2, and R3 connected in series between a power supply Vcc and a ground Vss. The resistor VR2 is a variable resistor. The resistance value of the resistor VR2 changes depending on the limit switch. The voltage divider circuit generates a second current Iy according to the resistance value of the resistor VR2.

[0048] The lower limit determination circuit 59 asserts the lower limit signal IL when the magnitude of the second current is at the lower limit value, and negates the lower limit signal IL when the magnitude of the second current is greater than the lower limit value.

[0049] The first arithmetic circuit 101 asserts the first test mode signal TM1 when the test command switch 11 is turned on and the circuit breaker tripping confirmation signal X2 is asserted. The first arithmetic circuit 101 may assert the first test mode signal TM1 when the following conditions are met: the test command switch 11 is turned off, or a signal X5 is asserted, indicating that a major fault has occurred anywhere in the rectifier equipment, including the thyristor rectifier 31 and the rectifier transformer.

[0050] The first arithmetic circuit 101 includes, for example, an AND circuit 62, an OR circuit 61, and a flip-flop 63.

[0051] The AND circuit 62 outputs the logical AND of the test instruction signal X1, the circuit breaker tripping confirmation signal X2, and the lower limit signal IL.

[0052] The OR circuit 61 outputs the logical sum of a signal X5 indicating that a serious fault has occurred at any point in the rectifier equipment including the thyristor rectifier 31 and the rectifier transformer, and an inverted signal of the test instruction signal X1.

[0053] The flip-flop 63 has a set terminal S that receives the output of the AND circuit 62, a reset terminal R that receives the output of the OR circuit 61, and an output terminal that outputs the first test mode signal TM1.

[0054] When the condition that the first test mode signal TM1 is asserted is satisfied, the second arithmetic circuit 102 asserts the gate start signal GS and supplies it to the control board 14. When the condition that the lower limit signal IL indicating that the magnitude of the second current is at the lower limit is also satisfied, the second arithmetic circuit 102 may assert the gate start signal GS and supply it to the control board 14.

[0055] The second arithmetic circuit 102 includes, for example, an AND circuit 65.

[0056] The AND circuit 65 outputs the logical product of the first test mode signal TM1 and the inverted signal of the lower limit signal IL as the gate start signal GS.

[0057] The third arithmetic circuit 103 negates the breaker closing preparation completion signal CBP when the condition that the gate start signal GS is asserted is satisfied.

[0058] The third arithmetic circuit 103 may be configured to assert the circuit breaker closing preparation completion signal CBP when the conditions that the gate start signal GS is negated or the circuit breaker tripping confirmation signal X2 is asserted are satisfied. The third arithmetic circuit 103 may be configured to assert the circuit breaker closing preparation completion signal CBP when the conditions that the signal X3 indicating that the main body of the thyristor rectifier 31 has failed is negated and the signal X4 indicating that the DC power supply for operating the control panel 20 is on are further satisfied.

[0059] The third arithmetic circuit 103 includes, for example, an OR circuit 67 and an AND circuit 66.

[0060] The OR circuit 67 outputs the logical sum of the inverted signal of the gate start signal GS and the circuit breaker tripping confirmation signal X2.

[0061] The AND circuit 66 outputs the logical product of the inverted signal of the signal X3 indicating that the main body of the thyristor rectifier 31 has failed, the signal X4 indicating that the DC power supply for operating the control panel 20 is on, and the output signal of the OR circuit 67 as the circuit breaker closing preparation completion signal CBP.

[0062] The fourth arithmetic circuit 104 supplies the second test mode signal TM2 to the monitoring operation panel 21. The fourth arithmetic circuit 104 asserts the second test mode signal TM2 when the test instruction switch 11 is turned on and the conditions for asserting the first test mode signal TM1 are met.

[0063] The fourth arithmetic circuit 104 includes, for example, an AND circuit 64.

[0064] The AND circuit 64 outputs the logical product of the test instruction signal X1 and the first test mode signal TM1 to the monitoring operation panel 21 as a second test mode signal TM2.

[0065] The changeover switch ST supplies either the first current Ix or the second current Iy to the control board 14. When the first test mode signal TM1 is asserted, the changeover switch ST supplies the second current Iy to the control board 14, and when the first test mode signal TM1 is negated, the changeover switch ST supplies the first current Ix to the control board 14.

[0066] As described above, according to this embodiment, by providing the control panel 20 installed adjacent to the thyristor rectifier 31 with a current setting function during testing (second current setting controller 23 and second current generator 24), the test personnel do not need to travel to the monitoring control panel 21 installed at a distance, which is convenient.

[0067] The condition for closing the circuit breaker 33 in the monitoring operation panel 21 includes that a gate pulse test is not being performed (the gate start signal GS is negated). This prevents the circuit breaker 33 from being closed in the remote monitoring operation panel 21 during the gate pulse test, enabling safe testing.

[0068] By using a limit switch as the second current setting operating device 23 in the control panel 20 and a voltage dividing circuit using a variable resistor as the second current generator 24, the control panel 20 can be made smaller, which allows for cost reduction.

[0069] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The present invention is defined by the claims rather than the above description, and it is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0070] 5U, 5V, 5W, 5X, 5Y, 5Z thyristor, LD load, 10 control monitoring panel, 11, 51 test instruction switch, 14 control board, 15 current controller, 16 reference phase detector, 17 gate pulse generator, 20 control panel, 21 monitoring operation panel, 23 second current setting operation device, 24 second current generator, 31 thyristor rectifier, 32 AC power source, 33 circuit breaker, 52, 82 circuit breaker operation authority acquisition switch, 53 current setting operation authority acquisition switch, 54 current setting operation device, 56, 63 flip-flop, 59 lower limit judgment circuit, 60 current generator, 80 first current generator, 81 circuit breaker control circuit, 83 circuit breaker operation switch, 84 first current setting operation device, 101 first calculation circuit, 102 second calculation circuit, 103 Third calculation circuit, 104, fourth calculation circuit, R1, VR, VR2 resistors, ST selector switch.

Claims

1. The control panel and A monitoring control panel is provided. The monitoring operation panel includes: a circuit breaker operation changeover switch for acquiring the operation authority of the circuit breaker; a circuit breaker operation switch for instructing the circuit breaker to be turned on or off; a circuit breaker control circuit that closes the circuit breaker when a circuit breaker closing preparation completion signal is asserted, the circuit breaker operation changeover switch is used to allow the monitoring operation panel to acquire the operation authority for the circuit breaker, and the circuit breaker operation switch is used to instruct closing of the circuit breaker; a first current setting controller that sets the magnitude of a current output from the thyristor rectifier as the magnitude of a first current; a first current generator that generates a first current having a magnitude set by the first current setting controller; The control panel includes: A control board; a test instruction switch for instructing a test; a first arithmetic circuit that asserts a first test mode signal when the test instruction switch is turned on and a circuit breaker tripping confirmation signal that confirms that the circuit breaker is in a tripped state is asserted; a second arithmetic circuit that asserts a gate start signal and supplies it to the control board when the condition that the first test mode signal is asserted is satisfied; a third arithmetic circuit that negates the breaker closing preparation completion signal when the condition that the gate start signal is asserted is satisfied; a second current setting controller that sets the magnitude of the current output from the thyristor rectifier as the magnitude of a second current; a second current generator that generates a second current having a magnitude set by the second current setting controller; The control board a gate pulse generator that generates a gate pulse signal and supplies it to the thyristor rectifier when the gate start signal is asserted; a current controller that sets a phase angle of the gate pulse signal based on the first current or the second current.

2. 2. The thyristor rectifier control system according to claim 1, wherein said first calculation circuit asserts said first test mode signal when a condition that the magnitude of said second current is a lower limit is further satisfied.

3. 3. The thyristor rectifier control system according to claim 2, wherein the first arithmetic circuit negates the first test mode signal when the test instruction switch is turned off or when a condition is met that a serious fault has occurred at any point in the rectifier equipment.

4. 2. The thyristor rectifier control system according to claim 1, wherein the second arithmetic circuit asserts the gate start signal and supplies it to the control board when the condition that the magnitude of the second current is not a lower limit is further satisfied.

5. the second current setting operator includes a limit switch, the second current generator includes a variable resistor whose resistance value is changed by the limit switch; 2. The thyristor rectifier control system according to claim 1, wherein said second current generator generates said second current according to a resistance value of said variable resistor.

6. a selector switch that supplies either the first current or the second current to the control board; 2. The thyristor rectifier control system according to claim 1, wherein the changeover switch supplies the second current to the control board when the first test mode signal is asserted, and supplies the first current to the control board when the first test mode signal is negated.

7. a fourth arithmetic circuit for supplying a second test mode signal to the monitoring operation panel; 2. The thyristor rectifier control system according to claim 1, wherein the fourth arithmetic circuit asserts the second test mode signal when the test instruction switch is turned on and the condition that the first test mode signal is asserted is satisfied.

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