Display device

Abstract

To provide a display device suitable for enlargement.SOLUTION: A display device includes first to third wires, a first transistor, first to third conductive layers, and a first pixel electrode. The first wire extends in a first direction and intersects with the second and third wires. The second and third wires extend in a second direction intersecting with the first direction. A gate of the first transistor is electrically connected to the first wire. One of a source and a drain of the first transistor is electrically connected to the second wire through the first to third conductive layers. The second conductive layer includes a region overlapping with the third wire. The first conductive layer, the third conductive layer, and the first pixel electrode include the same material. The first wire and the second conductive layer include the same material. A selection signal is supplied to the first wire. Different signals are supplied to the second and third wires.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, Electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, or manufacturing methods thereof The law can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Transistors, semiconductor circuits, arithmetic units, memory devices, etc. are examples of semiconductor devices. In addition, it is also used in imaging devices, electro-optical devices, power generation devices (thin film solar cells, organic thin film solar cells, etc.) ), and electronic devices may have semiconductor devices. [Background technology]

[0004] In recent years, there has been a demand for high-resolution display devices. For example, in home television sets (TV , or television receiver), the resolution is full high definition (192 pixels) 0×1080) is the mainstream, but 4K (pixel count 3840×2160) The development of high-resolution display devices such as 8K (7680 x 4320 pixels) is progressing. There are.

[0005] A liquid crystal display device is known as one of the display devices. By using the optical modulation effect of the It represents the image and displays it as an image.

[0006] Also, as a type of field effect transistor, a semiconductor formed on a substrate having an insulating surface A thin film transistor in which a channel forming region is formed using a film is known. In this case, amorphous silicon is used in the semiconductor film used in the channel formation region of the thin film transistor. For example, in the case of a liquid crystal display device, a thin film transistor is used for each pixel. Used as a switching transistor. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-053283 Summary of the Invention [Problem to be solved by the invention]

[0008] In the case of display devices such as televisions and monitors, the higher the resolution or the larger the screen size, the better. The larger the difference, the more significant the increase in load on the transistors and the like included in the display device. This allows transistors to be operated at high drive frequencies, especially when the field-effect mobility of the transistor is low. It can sometimes be difficult.

[0009] An object of one embodiment of the present invention is to provide a high-resolution display device and a manufacturing method thereof. Another object is to provide a display device suitable for large size and a manufacturing method thereof. Another object is to provide a low-cost display device and a manufacturing method thereof. Another object is to provide a display device with high productivity and a manufacturing method thereof. Another object is to provide a highly reliable display device and a manufacturing method thereof. One of the objects of the present invention is to provide a display device using amorphous silicon or the like and a manufacturing method thereof. Alternatively, the present invention aims to provide a display device using a metal oxide or the like and a manufacturing method thereof. Another object is to provide a novel display device and a manufacturing method thereof. do.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a first wiring, a second wiring, a third wiring, and a first transistor. a first conductive layer, a second conductive layer, a third conductive layer, and a first pixel electrode; A display device, wherein a first wiring extends in a first direction and a second wiring and a third wiring extend in a second direction. The second wiring and the third wiring are respectively in a second direction intersecting the first direction. The gate of the first transistor is electrically connected to the first wiring. One of the source and drain of the transistor is formed by the first conductive layer, the second conductive layer, and the third conductive layer. The second conductive layer is electrically connected to the second wiring through the conductive layer, and the second conductive layer overlaps with the third wiring. a first conductive layer, a third conductive layer, and a first pixel electrode, the first conductive layer, and the third conductive layer comprising the same material; The first wiring and the second conductive layer include the same material, and the first wiring is provided with a selection signal. The first wiring is supplied with a signal, and the second wiring and the third wiring are supplied with different signals. do.

[0012] Alternatively, in the above aspect, the second wiring and the third wiring are connected to the first source driver and The first source driver may be electrically connected to the second source driver.

[0013] Alternatively, in the above embodiment, the fourth wiring, the fifth wiring, the sixth wiring, and the second transistor a transistor, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, and a second pixel electrode; The fourth wiring extends in the first direction, and the second wiring, the third wiring, and the fifth wiring The fifth wiring and the sixth wiring are connected in the first direction and the sixth direction, respectively. The gate of the second transistor extends in a second direction intersecting the first wiring, and the gate of the second transistor is electrically connected to the fourth wiring. The source or drain of the second transistor is connected to the fourth conductive layer, the fifth conductive layer, The fifth conductive layer is electrically connected to the fifth wiring via the sixth conductive layer. The fourth conductive layer, the sixth conductive layer, and the second pixel electrode have an area overlapping with the sixth wiring. The fourth wiring and the fifth conductive layer include the same material, and the fourth wiring and the fifth conductive layer include the same material. The same selection signal as that of the first wiring is supplied to the second wiring, the third wiring, the fifth wiring, and the The first and sixth wirings may be supplied with different signals.

[0014] Alternatively, in the above-mentioned aspect, the fifth wiring and the sixth wiring are connected to the first source driver and The first source driver may be electrically connected to the second source driver.

[0015] Alternatively, in the above embodiment, the first transistor has a first semiconductor layer and the second transistor The transistor has a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are each It may have a portion located between the third wiring and the sixth wiring.

[0016] Alternatively, in the above embodiment, the first semiconductor layer and the second semiconductor layer are each an amorphous silicon. It may also contain a recombinant.

[0017] Alternatively, in the above embodiment, the first semiconductor layer and the second semiconductor layer are each a microcrystalline silicon. It may also comprise silicon or polycrystalline silicon.

[0018] Alternatively, in the above embodiment, the first semiconductor layer and the second semiconductor layer are each made of a metal oxide. It may contain things.

[0019] Alternatively, in the above embodiment, the metal oxide may be selected from indium, zinc, and M (where M is aluminum). Smoke, titanium, gallium, germanium, yttrium, zirconium, lanthanum, and celery The alloy may contain chromium, tin, neodymium, or hafnium.

[0020] Another embodiment of the present invention is a method for manufacturing a display device, the method including: forming a gate line and A step of forming a first conductive layer, a step of forming a first insulating layer, and a step of forming a semiconductor layer. a second conductive layer having a region in contact with the semiconductor layer; a first source line; a second source line; and forming a second insulating layer; and forming a third conductive layer. The insulating layer has a first opening reaching the second conductive layer, a second opening reaching the third conductive layer, and a third opening portion is formed in the first insulating layer and the second insulating layer, the third opening portion reaching the second source line; A fourth opening and a fifth opening reaching the first conductive layer are formed so as to sandwich the first source line. forming a pixel electrode so as to be electrically connected to the second conductive layer through the first opening; An electrode is formed, electrically connected to the third conductive layer through the second opening, and a fourth opening is formed. A fourth conductive layer is formed so as to be electrically connected to the first conductive layer through the third opening. the second source line through the fifth opening and the first conductive layer through the fifth opening. and forming a fifth conductive layer so as to be connected to the . [Effects of the Invention]

[0021] According to one embodiment of the present invention, a high-resolution display device and a manufacturing method thereof can be provided. Alternatively, a display device suitable for large size and a manufacturing method thereof can be provided. Therefore, it is possible to provide a low-cost display device and a manufacturing method thereof. A display device and a manufacturing method thereof can be provided. A display device using amorphous silicon or the like and a manufacturing method thereof can be provided. Also, a display device using a metal oxide or the like and a manufacturing method thereof can be provided. A novel display device and a manufacturing method thereof can be provided. can be provided.

[0022] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. It can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0023] [Figure 1] 1 shows an example of the configuration of a display device. [Figure 2] 1 shows an example of the configuration of a display device. [Figure 3] 1 shows an example of the configuration of a display device. [Figure 4] 1 shows an example of the configuration of a display device. [Figure 5] 1 shows an example of the configuration of a display device. [Figure 6] 1 shows an example of the configuration of a display device. [Figure 7] 1 shows an example of the configuration of a display device. [Figure 8] 1 shows an example of the configuration of a display device. [Figure 9] 1 shows an example of the configuration of a display device. [Figure 10] 1 shows an example of the configuration of a display device. [Figure 11] 1 shows an example of the configuration of a display device. [Figure 12] 1 shows an example of the configuration of a display device. [Figure 13] 1 shows an example of the configuration of a display device. [Figure 14] 1 shows an example of the configuration of a display device. [Figure 15] 1 shows an example of the configuration of a display device. [Figure 16] 1 shows an example of the configuration of a display device. [Figure 17] 1 shows an example of a method for manufacturing a display device. [Figure 18] 1 shows an example of a method for manufacturing a display device. [Figure 19] 1 shows an example of a method for manufacturing a display device. [Figure 20] 1 shows an example of a method for manufacturing a display device. [Figure 21] 1 shows an example of a method for manufacturing a display device. [Figure 22] 1 shows an example of a method for manufacturing a display device. [Figure 23] 1 shows an example of the configuration of a display device. [Figure 24] An example of a transistor configuration. [Figure 25] An example of a transistor configuration. [Figure 26] An example of a transistor configuration. [Figure 27] An example of a transistor configuration. [Figure 28] An example of a transistor configuration. [Figure 29] An example of a transistor configuration. [Figure 30] 1 shows an example of a laser irradiation method and a laser crystallization apparatus. [Figure 31] An example of a laser irradiation method. [Figure 32] An example of the display panel configuration. [Figure 33] An example of the configuration of electronic devices. [Figure 34] 1A and 1B are a block diagram showing a display module according to a first embodiment and a circuit diagram showing a pixel according to the first embodiment. [Figure 35] FIG. 2 is a top view showing a pixel layout according to the first embodiment. [Figure 36] 10 shows an approximate result of data writing time in Example 1. [Figure 37] 10 shows an approximate result of data writing time in Example 1. [Figure 38] 1A and 1B are a block diagram showing a display module according to a first embodiment and a circuit diagram showing a pixel according to the first embodiment. [Figure 39] FIG. 2 is a top view showing a pixel layout according to the first embodiment. [Figure 40] 10 shows an approximate result of data writing time in Example 1. [Figure 41] 10 shows an approximate result of the data writing time in Example 1. [Figure 42] 10 shows an approximate result of data writing time in Example 1. [Figure 43] 10 shows an approximate result of the data writing time in Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. It should not be construed as being limited to the contents of the description of the state.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0026] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limit.

[0028] A transistor is a type of semiconductor device that amplifies current and voltage and controls conduction or non-conduction. In this specification, the transistor is a GFET(Insulated Gate Field Effect Transis) transistors (TFTs) and thin film transistors (TFTs) include.

[0029] Also, the functions of "source" and "drain" may differ depending on whether transistors of different polarities are used or not. , and may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. This shall be the case.

[0030] In addition, in this specification, the terms "source," "drain," and "gate" are used interchangeably. These can be rephrased as "source electrode," "drain electrode," and "gate electrode," respectively. There is.

[0031] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. Switching elements, resistive elements, coils, capacitive elements, and other elements with various functions Includes:

[0032] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image on a display surface. ) Therefore, the display panel is one aspect of an output device.

[0033] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Switched Circuit) or TCP (Tape Carrier Packet e) or COG (Chip On Glass) on the board. The IC is mounted using the assembly method, etc., and is called a display panel module or display module. , or simply referred to as a display panel, etc.

[0034] In this specification, a touch sensor is a sensor that detects a touch or pressure of a detection object such as a finger or a stylus. It has the function of detecting when something moves or approaches. It also detects the location information. Therefore, the touch sensor is one aspect of the input device. For example, the touch sensor may have one or more sensor elements.

[0035] In this specification and the like, a substrate having a touch sensor is referred to as a touch sensor panel, or simply In this specification, the substrate of the touch sensor panel is For example, those with FPC or TCP connectors attached, or those with CO The IC mounted by the G method is called a touch sensor panel module or touch sensor It may be called a module, a sensor module, or simply a touch sensor.

[0036] In this specification, a touch panel, which is one aspect of a display device, is a device that displays an image or the like on a display surface. The function of the display is to display (output) the information when a finger, stylus, or other object touches, presses, or The touch panel has a function as a touch sensor that detects approaching objects. A panel is one aspect of an input / output device.

[0037] The touch panel is, for example, a display panel (or display device) with a touch sensor, a touch sensor It can also be called a functional display panel (or display device).

[0038] The touch panel may also have a configuration including a display panel and a touch sensor panel. Alternatively, the display panel may be configured to have a touch sensor function inside or on its surface. It can also be done as follows.

[0039] In this specification, a connector such as an FPC or TCP is attached to the substrate of the touch panel. or a board with an IC mounted on it using the COG method, It may be called a touch panel module, display module, or simply a touch panel. .

[0040] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0041] One embodiment of the present invention is a display device having a display portion in which a plurality of pixels are arranged in a matrix. The display section has wiring (also called gate lines or scanning lines) to which selection signals are supplied, and pixel Wiring (source line, signal line, data line) through which signals (also called video signals) are written Here, the gate lines and the source lines are connected to each other. The gate lines and source lines are arranged parallel to each other, and cross each other.

[0042] One pixel has at least one transistor and one display element. The transistor has a conductive layer that functions as a pixel electrode. The gate of the transistor is electrically connected to the gate line or the drain. The other of the source and the drain is electrically connected to a source line.

[0043] Here, the direction in which the gate lines extend is defined as a row direction or a first direction, and the direction in which the source lines extend is defined as a column direction. We will call this the first direction or second direction.

[0044] Here, it is preferable that the same selection signal is supplied to three or more adjacent gate lines. In other words, it is preferable that the selection periods of these gate lines are the same. It is preferable to use one set of these because it simplifies the configuration of the drive circuit.

[0045] When the same selection signal is supplied to four gate lines, four adjacent pixels in the column direction are simultaneously Therefore, these four pixels are connected to different source lines. In other words, four source lines are arranged for each column.

[0046] By arranging four source lines per column, one horizontal period is made longer than before. For example, when the same selection signal is supplied to four gate lines, Furthermore, the parasitic capacitance between the source lines can be reduced, allowing the This reduces the load on the source lines, making it possible to Even high-resolution display devices are operated using transistors with low field-effect mobility. Of course, resolutions above 8K (for example, 10K, 12K or 1 Even a display device (such as a display device with a resolution of 6K) can be operated by using a structure according to one embodiment of the present invention. In addition, the screen size must be 50 inches or more diagonally, 60 inches or more diagonally, or The above-described configuration can also be applied to large display devices of 70 inches or more.

[0047] When four source lines are arranged per column, two source lines are arranged on the left side of the pixel. In other words, two source lines can be arranged on the left outer and left inner sides of the pixel. In this configuration, the source lines can be arranged on the left side, the right inner side, and the right outer side of the pixel. The source of the transistor electrically connected to the left outer source line is the source of the left inner source line of the pixel. In this configuration, the transistor electrically connected to the source line on the right outer side of the pixel intersects with the line. The source of the transistor crosses the source line on the right inside of the pixel. The conductive layer can be formed in the same process as the electrode, and the conductive layer can be formed in the same process as the transistor gate. and a conductive layer that can be formed on the left side of the pixel, and electrically connected to the source line on the left side of the pixel. This prevents the source of the transistor and the source line on the left inside of the pixel from shorting out. In one embodiment of the present invention, a conductive layer that can be formed in the same process as a pixel electrode and a transistor are provided. A conductive layer that can be formed in the same process as the gate of the transistor is used to form the right outer the source of the transistor electrically connected to the source line on the right side of the pixel; This prevents short-circuiting of the source lines. Even if the source lines are arranged in one or two rows, the Therefore, the number of steps, specifically the number of steps in the photolithography process, is prevented from increasing. In other words, it is possible to prevent the number of photomasks from increasing. This makes it possible to suppress an increase in the manufacturing cost of the display device.

[0048] A more specific example of the display device will be described below with reference to the drawings.

[0049] [Example of display device configuration] FIG. 1 is a block diagram of a display device 10 according to one embodiment of the present invention. A display unit 17, a gate driver 12a, a gate driver 12b, and a source driver 13a The display section 17 has a pixel 11 arranged in a matrix. In this specification, the pixel 11 in the i-th row and j-th column is referred to as pixel 11(i,j). Posted.

[0050] In FIG. 1, the gate driver 12a and the gate driver 12b are arranged opposite each other with the display unit 17 interposed therebetween. 1 shows an example in which the gate driver 12a and the gate driver 1 A plurality of wirings GL0 are connected to 2b. In FIG. 1, wirings GL0(i) are shown. Wire GL0(i) consists of four wires (wire GL(i), wire GL(i+1), wire GL(i +2), and wiring GL(i+3). Therefore, these four wirings The same selection signal is given to the lines GL0 and GL. It has the following functions.

[0051] The gate driver 12a and the gate driver 12b transmit the same selection signal to the same wiring GL0. This allows the display device 10 to be configured with only one gate driver. This allows the charge / discharge time of the wiring GL0 to be shorter than when the wiring GL1 is used. Even in extremely high-resolution displays such as 1080p and 8K, transistors with low field-effect mobility It is possible to operate it using a register. Also, the screen size is 50 inches or more diagonally, The present invention can also be applied to large display devices with a diagonal of 60 inches or more, or 70 inches or more. It is possible to apply the display device.

[0052] In FIG. 1, a source driver 13a and a source driver 13b are arranged with a display unit 17 sandwiched between them. The source driver 13a and the source driver 13b are provided with a plurality of Four wires are provided for one pixel column. In Figure 1, the j-th Four wirings corresponding to pixel columns (wiring SL1(j), wiring SL2(j), wiring SL3(j) , wiring SL4(j)) and four wirings corresponding to the j+1th pixel column (wiring SL1(j+ 1), wiring SL2(j+1), wiring SL3(j+1), wiring SL4(j+1)) Different signals can be supplied to different wires. For example, wire SL 1(j), wiring SL2(j), wiring SL3(j), and wiring SL4(j) each have It is possible to supply different signals to the wirings SL (wirings SL1, SL2, and SL3 and wiring SL4) function as source lines.

[0053] The source driver 13a and the source driver 13b supply the same signal to the same line SL. This allows the display device 10 to operate in a manner similar to that described above, even if the display device 10 has only one source driver. This allows the charging and discharging time of the wiring SL to be shortened. Even in extremely high-resolution display devices such as LCDs, transistors with low field-effect mobility are used. It is also possible to operate it using a screen size of 50 inches or more diagonally, 60 inches or more diagonally. The display device according to one embodiment of the present invention can also be used for large display devices with a diagonal of 70 inches or more. It becomes possible to apply

[0054] One pixel 11 corresponds to one color. When color display is performed using color mixing, the pixel 11 can also be called a sub-pixel.

[0055] In addition, the plurality of pixels arranged in a row in the column direction are pixels that exhibit the same color. When a liquid crystal element is used as a display element, the pixels arranged in a row in the column direction are preferably A colored layer that transmits light of the same color as the liquid crystal element is provided so as to overlap the liquid crystal element.

[0056] Here, when a transistor with low field effect mobility is used, the display portion of the display device is divided into a plurality of display areas. However, in the above method, the characteristics of the driving circuit may vary. The boundaries between the divided display areas are visible due to the In addition, image processing etc. is required to divide the input image data in advance. This requires high-speed, large-scale image processing equipment.

[0057] On the other hand, the display device of one embodiment of the present invention uses a transistor with relatively low field-effect mobility. Even in this case, it is possible to drive the display unit without dividing it into multiple display areas. .

[0058] The display device 10 may be provided with a protection circuit. When the protection circuits 18a, 18b, 19a, and 19b are provided, 1 shows a block diagram of the display device 10 in this case. The protection circuit 18a and the protection circuit 18b are connected to the wiring G. The protection circuit 19a and the protection circuit 19b are electrically connected to the wiring SL1, It is electrically connected to the wiring SL2, the wiring SL3, and the wiring SL4.

[0059] The protection circuit 18a can be provided on the side of the gate driver 12a, and the protection circuit 18b can be provided on the side of the gate driver 12a. The protection circuit 18a and the protection circuit 18b can be provided on the side of the gate driver 12b. The protection circuit 19 can be provided at a position opposite to the display unit 17. a can be provided on the source driver 13a side, and the protection circuit 19b can be provided on the source driver 13b side. In other words, the protection circuit 19a and the protection circuit 19b can be provided on the side of the front The indicator 17 can be provided at opposing positions.

[0060] By providing a protection circuit in the display device 10, the image can be protected from noise, surges, electrostatic discharge, etc. This can protect the element 11, thereby improving the reliability of the display device 10. do.

[0061] Although four source lines are provided for each pixel column in FIG. 1, one embodiment of the present invention is not limited to this. In FIG. 3, three source lines (line SL1, line SL2, line SL 3) shows the configuration to be provided. In the display device 10 having this configuration, the wiring GL0(i) is composed of three Electrically connected to the wiring (wiring GL(i), wiring GL(i+1), wiring GL(i+2)) The same selection signal is applied to these three wirings. Five or more source lines may be provided per pixel column.

[0062] In Figure 1, an example is shown in which two gate drivers and two source drivers are arranged. A configuration in which only one gate driver or one source driver or both are provided may also be used. .

[0063] In FIG. 4, the source driver 13a and the source driver 13b are each connected to one pixel column. In other words, the same number of source drivers 13a as the number of pixel columns are arranged in the example shown. The source driver 13a is provided along one side of the rectangular display unit 17, and the display unit 17 is sandwiched between the source driver 13a and the In the opposite position, source drivers 13b are provided in the same number as the pixel columns. One gate driver 12a and one gate driver 12b are connected to each wiring GL0. In other words, the number of gate drivers 12a is equal to the number of pixel rows divided by 4. The gate driver 12a is disposed along one side of the rectangular display unit 17, and the display unit 17 is sandwiched between the gate driver 12a and the display unit 17. The number of gate drivers 12b is equal to the number of pixel rows divided by four, and they are provided at positions opposite to each other. By adopting such a configuration, it is possible to prevent the display from being affected by the potential drop caused by the wiring resistance even in a large display device. This can reduce display unevenness.

[0064] The display device 10 may be provided with a reference voltage generating circuit. The reference voltage generation circuit has the function of generating a reference voltage for the signal supplied by the switch driver. For example, it can be a gamma reference generation circuit. The display device 10 includes a reference voltage generating circuit having a function of supplying a reference voltage to the source driver 13a. a reference voltage generating circuit having a function of supplying a reference voltage to the source driver 13b; 16b and 16c are provided. By configuring the display device 10 as shown in FIG. Therefore, the accuracy of the voltage of the signal generated from each source driver 13a and the This can improve the accuracy of the voltage of the signal generated from the inverter 13b.

[0065] FIG. 6 shows a display device 10 having the configuration shown in FIG. 4, with a source driver 13a and a source driver 13b is provided with a reference voltage generating circuit 16 having a function of supplying a reference voltage. Even when the display device 10 has the configuration shown in FIG. and the accuracy of the voltage of the signal generated from each source driver 13b. The voltage accuracy can be improved.

[0066] [Pixel configuration example] An example of the configuration of pixels arranged in the display unit 17 of the display device 10 will be described below.

[0067] FIG. 7 shows four pixels arranged in a row in the column direction, namely, pixel 11(i,j), pixel 11(i 11(i+1,j), pixel 11(i+2,j), and pixel 11(i+3,j). is doing.

[0068] Each pixel 11 includes a transistor 30, a liquid crystal element 20, and a capacitor 60.

[0069] The wirings S1 to S4 correspond to source lines, and the wirings G1 to G4 correspond to source lines. For example, in the case shown in FIG. 7, the line S1 corresponds to the line SL1(j). Accordingly, the wiring S2 corresponds to the wiring SL2(j), the wiring S3 corresponds to the wiring SL3(j), and The line S4 corresponds to the wiring SL4(j). In the case shown in FIG. 7, the wiring G1 corresponds to the wiring GL (i), wiring G2 corresponds to wiring GL(i+1), and wiring G3 corresponds to wiring GL(i+2 ), and the wiring G4 corresponds to the wiring GL(i+3).

[0070] The pixel 11(i, j) has a transistor 30 connected to either the source or the drain of a wiring. S1 is electrically connected, and the gate of the transistor 30 of the pixel 11(i, j) is The wiring G1 is electrically connected to the transistor 30 of the pixel 11(i+1, j). A wiring S2 is electrically connected to either the source or the drain of the pixel 11(i+1, j). The gate of the transistor 30 in the pixel 11 (i +2, j) has a source or a drain of the transistor 30, and the wiring S3 is connected to the source or the drain of the transistor 30. The gate of the transistor 30 of the pixel 11(i+2, j) is electrically connected to the wiring G3 is electrically connected to the source of the transistor 30 in the pixel 11(i+3,j). Alternatively, a wiring S4 is electrically connected to one of the drains, and the pixel 11(i+3, j) is enabled. The gate of the transistor 30 is electrically connected to a wiring G4.

[0071] The other of the source and drain of the transistor 30 is connected to one electrode of the capacitor 60. and is electrically connected to one electrode (pixel electrode) of the liquid crystal element 20. A wiring CS is electrically connected to one of the electrodes, and a common potential is supplied to the wiring CS.

[0072] The transistor 30 switches between an on state and an off state to receive the voltage supplied from the source line. The transistor 11 has a function of controlling the writing of the signal to the pixel 11. By turning on the transistor 30, the charge corresponding to the signal supplied from the source line is transferred to the corresponding transistor. It is possible to write data to the capacitor 60 electrically connected to the transistor 30. By turning off the transistor 30, the charge written in the capacitance element 60 is held. It is possible.

[0073] Here, the transistor 30 may be a transistor using amorphous silicon. It is difficult to increase the field-effect mobility of amorphous silicon transistors. Although it is difficult to achieve this, a display device according to one embodiment of the present invention can be realized by using such a transistor. Even if the screen size is large, it can be made to have extremely high resolution such as 4K or 8K. Large display devices with a diagonal of 50 inches or more, 60 inches or more, or 70 inches or more It is possible.

[0074] Alternatively, the transistor 30 may have a metal oxide (metal oxide) in the channel forming region. A transistor including an OS transistor (hereinafter also referred to as an OS transistor) can be used. Metal oxides have a larger energy gap than semiconductors such as silicon, making them suitable for use in OS transistors. The transistor can reduce the minority carrier density. When Therefore, the use of an OS transistor as the transistor 30 This allows the capacitance element 60 to hold charge for a long period of time. The frequency of writing charge to 0, i.e., the frequency of refresh operations, can be reduced, The power consumption of the device 10 can be reduced.

[0075] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. , oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors Semiconductor or simply called OS). When a metal oxide is used in the semiconductor layer of a transistor, the metal oxide is called an oxide semiconductor. In other words, metal oxides may have some amplification, rectification, and switching properties. When the metal oxide has at least one of the above, the metal oxide is called a metal oxide semiconductor. de semiconductor), or OS for short. ET refers to a transistor having a metal oxide or oxide semiconductor.

[0076] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. In addition, metal oxides containing nitrogen are called metal oxynitrides. ) may also be referred to as

[0077] In this specification, CAAC (c-axis aligned crystal ), and when written as CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Represents an example.

[0078] In this specification and the like, CAC-OS or CAC-metal oxide means A part of the material has a conductive function, and a part of the material has an insulating function, and the whole material It functions as a semiconductor. When e is used in the active layer of a transistor, the conductive function is to transfer electrons (or The insulating function is the function of preventing the flow of electrons, which are carriers. By making the conductive function and insulating function work in a complementary manner, The function to turn the sync on / off can be set to CAC-OS or CAC-metal. CAC-OS or CAC-metal oxide By separating the functions in e, it is possible to maximize the functionality of both. Cut.

[0079] In this specification and the like, CAC-OS or CAC-metal oxide is a The conductive region has the above-mentioned conductive function and the insulating region. The conductive region has the insulating function described above. The regions may be separated at the nanoparticle level. The conductive areas may be unevenly distributed in the material. They may be observed connected in a dot-like pattern.

[0080] In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be dispersed in the material:

[0081] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxidized de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, when carriers flow, In the narrow gap component, carriers mainly flow. The component having a wide gap acts complementary to the component having a narrow gap. Carriers also flow into the wide-gap component in conjunction with the component with a wide gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, the transistor has a high current driving force in the on state, i.e., a large on-current. Furthermore, high field-effect mobility can be obtained.

[0082] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a matrix composite.

[0083] FIG. 8A shows the layout of pixel 11(i+2,j) and pixel 11(i+3,j). An example is shown.

[0084] In FIG. 8(A) and other figures, components provided on the same layer are indicated by the same hatching. In the following figures, the same hardware is used for components on the same layer. Sometimes etched.

[0085] As shown in FIG. 8(A), the wiring G3, the wiring G4, and the wiring CS are extended in the row direction (horizontal direction). Wirings S1 to S4 extend in the column direction (vertical direction).

[0086] An example of the configuration of the pixel 11(i+2,j) will be described. In the transistor 30, a semiconductor layer 32 is provided on the wiring G3, and a part of the wiring G3 is In addition, a part of the wiring S3 functions as either a source or a drain. The semiconductor layer 32 has a region located between the wiring S2 and the wiring S3.

[0087] The other of the source and drain of the transistor 30 and one of the electrodes of the capacitance element 60 A conductive layer 33a having a function as an electrode is provided so as to be electrically connected to the semiconductor layer 32. In addition, a conductive layer 21 having a function as a pixel electrode is provided, and is connected to the pixel electrode through an opening 38. Thus, the conductive layer 33a and the conductive layer 21 are electrically connected to each other.

[0088] An example of the configuration of pixel 11(i+3,j) will be described. In the transistor 30, a semiconductor layer 32 is provided on the wiring G4, and a part of the wiring G4 is The semiconductor layer 32 has a function as a gate. do.

[0089] The other of the source and drain of the transistor 30 and one of the electrodes of the capacitance element 60 A conductive layer 33a having a function as an electrode is provided so as to be electrically connected to the semiconductor layer 32. In addition, a conductive layer 21 having a function as a pixel electrode is provided, and is connected to the pixel electrode through an opening 38. Thus, the conductive layer 33a and the conductive layer 21 are electrically connected to each other.

[0090] In addition, the conductive layer 51 which functions as one of the source and drain of the transistor 30 is provided so as to be electrically connected to the semiconductor layer 32. The conductive layer 51 is The conductive layer 52 is electrically connected to the conductive layer 52 formed in the same layer through the opening 71. The conductive layer 52 is connected to a conductive layer 53 formed on the same layer as the wiring G4 through an opening 72. The conductive layer 53 is formed in the same layer as the conductive layer 21. The conductive layer 54 is electrically connected to the wiring S4 through the opening 73. , are electrically connected through openings 74.

[0091] That is, in the pixel 11(i+3,j), the source or drain of the transistor 30 The conductive layer 51 having the function of one of the conductive layers 52, 53, and 54 is The pixel 11(i+3, j) is electrically connected to the wiring S4 via the In this configuration, the conductive layer 51, the wiring S3, and the wiring S4 are provided in the same layer, The conductive layer 53 has an area overlapping with the wiring S3, but does not overlap with the source or drain of the transistor 30. In addition, the conductive layer 52 and the conductive The conductive layer 54 can be formed in the same process as the conductive layer 21 having the function as a pixel electrode. In this case, the conductive layer 53 can be formed in the same process as the wiring G4. Even if four source lines are arranged in a row, one or two source lines are arranged in each row. Compared to a configuration in which the wires are arranged, the number of steps, specifically the photolithography process, is reduced. It is possible to suppress an increase in the number of steps. This can suppress an increase in the manufacturing cost of the display device. can.

[0092] FIG. 8B shows an example of the layout of pixel 11(i, j) and pixel 11(i+1, j). As shown in FIG. 8B, the wiring G1 and the wiring G2 extend in the row direction. .

[0093] In pixel 11(i,j), as either the source or drain of transistor 30 The conductive layer 51 having a function is connected to the wiring S via the conductive layer 52, the conductive layer 53, and the conductive layer 54. 1. Other than that, the configuration of pixel 11(i,j) and pixel 11( The configuration of i+3,j) is similar.

[0094] In the pixel 11(i+1, j), a part of the wiring S2 is connected to the source of the transistor 30 or The other points are the same as those of the pixel 11(i+1, j). The configuration of pixel 11(i+2,j) is similar to that of pixel 11(i+2,j).

[0095] The above is a description of an example of the pixel configuration.

[0096] [Cross-section example] An example of the cross-sectional configuration of the display device will be described below.

[0097] [Cross-sectional configuration example 1] FIG. 9 shows an example of a cross section corresponding to the cutting line A1-A2 in FIG. 9 shows an example in which a transmissive liquid crystal element 20 is used as the element. The 15 side is the display side.

[0098] The display device 10 has a configuration in which a liquid crystal 22 is sandwiched between a substrate 14 and a substrate 15. The liquid crystal element 20 has a conductive layer 21 provided on the substrate 14 side and a conductive layer 22 provided on the substrate 15 side. 23 and a liquid crystal 22 sandwiched therebetween. An alignment film 24a is provided between the liquid crystal 22 and the conductive layer 23, and an alignment film 24b is provided between the liquid crystal 22 and the conductive layer 23. do.

[0099] The conductive layer 21 functions as a pixel electrode, and the conductive layer 23 functions as a common electrode, etc. In addition, both the conductive layer 21 and the conductive layer 23 have the function of transmitting visible light. Therefore, the liquid crystal element 20 is a transmissive liquid crystal element.

[0100] A colored layer 41 and a light-shielding layer 42 are provided on the surface of the substrate 15 facing the substrate 14. An insulating layer 26 is provided to cover the light-shielding layer 42 and the insulating layer 26, and a conductive layer 23 is provided to cover the insulating layer 26. The colored layer 41 is provided in an area overlapping the conductive layer 21. The light-shielding layer 42 is , and is provided to cover the transistor 30 and the opening 38, etc.

[0101] A polarizing plate 39a is disposed outside the substrate 14, and a polarizing plate 39b is disposed outside the substrate 15. Furthermore, a backlight unit 90 is provided outside the polarizing plate 39a. It is being used.

[0102] The transistor 30, the capacitance element 60, etc. are provided on the substrate 14. The transistor 30 is , which functions as a selection transistor for the pixel 11. The transistor 30 is The liquid crystal display panel 20 is electrically connected to the liquid crystal element 20 via the LED.

[0103] The transistor 30 shown in FIG. 9 is a transistor of the so-called bottom gate channel etch structure. The transistor 30 includes a conductive layer 31 that functions as a gate and a gate insulating layer 32. The insulating layer 34, which functions as an insulating layer, the semiconductor layer 32, and the source and drain regions are A pair of impurity semiconductor layers 35 functioning as a source and a drain. The semiconductor layer 32 has a pair of conductive layers 33a and 33b having a conductive function. The portion overlapping with the layer 31 functions as a channel formation region. is provided in contact with the semiconductor layer 32, and the conductive layer 33a and the conductive layer 33b are formed on the impurity semiconductor layer 3 It is placed adjacent to 5.

[0104] In this specification and the like, the impurity semiconductor layer may be simply referred to as a semiconductor layer.

[0105] The conductive layer 31 corresponds to a part of the wiring G3 in FIG. 8(A), and the conductive layer 33b corresponds to the wiring G3. The conductive layer 31a and the conductive layer 33c correspond to a part of the wiring S3. It corresponds to a part of CS and a part of wiring S4.

[0106] The semiconductor layer 32 is preferably made of a semiconductor containing silicon. For example, amorphous silicon is used. Silicon, microcrystalline silicon, polycrystalline silicon, etc. can be used. Amorphous silicon is preferable because it can be formed on a large substrate with good yield. The display device according to one embodiment of the present invention uses amorphous silicon having a relatively low field effect mobility. Even when a transistor having a high resistance is used, a good display is possible.

[0107] The impurity semiconductor layer 35 is formed from a semiconductor doped with an impurity element that imparts one conductivity type. If the transistor is n-type, it is made of a semiconductor doped with an impurity element that gives it one conductivity type. Examples of the semiconductor include silicon doped with P or As. When the semiconductor is p-type, for example, B is added as an impurity element to give one conductivity type. However, it is preferable that the transistor is an n-type. may be formed of an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor. You may do so.

[0108] The capacitance element 60 is composed of a conductive layer 31a, an insulating layer 34, and a conductive layer 33a. Furthermore, a conductive layer 33c is provided on the conductive layer 31 with an insulating layer 34 interposed therebetween.

[0109] In addition, insulating layers 82 and 81 are laminated to cover the transistor 30 and the like. The conductive layer 21, which functions as a pixel electrode, is provided on the insulating layer 81. The conductive layer 21 and the conductive layer 33a are electrically connected to each other through the opening 38 formed in the edge layer 81 and the insulating layer 82. The insulating layer 81 preferably functions as a planarizing layer. The insulating layer 82 also serves as a protective film that prevents impurities from diffusing into the transistor 30 and other components. For example, the insulating layer 82 may be made of an inorganic insulating material. Layer 81 can be made of an organic insulating material.

[0110] In this specification, when the insulating layer 82 and the insulating layer 81 are collectively regarded as one insulating layer, There is.

[0111] [Cross-sectional configuration example 2] FIG. 10 shows an example of a cross section corresponding to the section line B1-B2 in FIG. 8(A). The transistor 30 has a conductive layer 31 functioning as a gate and a gate insulating layer. The insulating layer 34 has a function as a source region and a drain region. The semiconductor layer 32 has a function as a source region and a drain region. a pair of impurity semiconductor layers 35 having a function as a source and a drain; The semiconductor layer 32 has a pair of conductive layers 33a and 51. The impurity semiconductor layer 35 functions as a channel formation region. The conductive layer 33a and the conductive layer 51 are provided in contact with the impurity semiconductor layer 35. can be.

[0112] The conductive layer 31 corresponds to a part of the wiring G4 in FIG. As in the case of the first embodiment, the conductive layer 31a, the conductive layer 33b, and the conductive layer 33c are each a part of the wiring CS. , a part of the wiring S3, and a part of the wiring S4. 4 and has an area overlapping with the conductive layer 53.

[0113] As described above, the conductive layer 81 and the conductive layer 82 are formed through the openings 71 formed in the insulating layers 81 and 82. The conductive layer 51 and the conductive layer 52 are electrically connected. The conductive layer 52 and the conductive layer 53 are electrically connected through an opening 72 provided in the layer 34. The conductive layer 81 is electrically connected to the insulating layer 82 through an opening 73 formed in the insulating layer 34. The conductive layer 53 and the conductive layer 54 are electrically connected to each other. The conductive layer 54 and the conductive layer 33c are electrically connected through the opening 74. As described above, the transistor 3 is connected to the conductive layer 52, the conductive layer 53, and the conductive layer 54. A conductive layer 51 having a function as either the source or drain of the semiconductor device 10 and a part of the wiring S4 The openings 72 and 73 are electrically connected to the corresponding conductive layers 33c. , and the conductive layer 33b are sandwiched between them. The conductive layer 51 having the function of one of the drains is connected to the conductive layer 3 corresponding to a part of the wiring S3. 10, the conductive layer 52 and the conductive layer 3b are prevented from short-circuiting. The conductive layer 54 is formed in the same layer as the conductive layer 21, and the conductive layer 53 is formed in the same layer as the conductive layer 31. and is formed in the same layer as the conductive layer 31a.

[0114] It should be noted that components formed on the same layer may have the same material. For example, the conductive layer 21, the conductive layer 52, and the conductive layer 54 each have the same material. In addition, for example, the conductive layer 31, the conductive layer 31a, and the conductive layer 53 can be respectively They may have the same material.

[0115] [Cross-sectional configuration example 3] Fig. 11 shows a modified example of the configuration shown in Fig. 10. In Fig. 11, the colored layer 41 is provided on the substrate 14 side. This simplifies the configuration on the substrate 15 side.

[0116] When the colored layer 41 is used as a planarizing film, the insulating layer 81 may be omitted. This reduces the number of steps for manufacturing the display device 10. This can reduce manufacturing costs.

[0117] [Cross-sectional configuration example 4] Fig. 12 shows a modification of the configuration shown in Fig. 10. In Fig. 12, conductive layer 52, conductive layer 53, and conductive 1 shows an example in which the conductive layer 54, the opening 72, and the opening 73 are omitted. The conductive layer 51 and the conductive layer 33c are connected via a conductive layer 55 formed in the same layer as the conductive layer 21. Specifically, the conductive layer 51 and the conductive layer 55 are electrically connected to each other through the opening 71. are electrically connected, and the conductive layer 33c and the conductive layer 55 are electrically connected through the opening 74. Even when the configuration shown in FIG. 12 is used, the conductive layer 51 and the conductive layer 33b are not short-circuited. can be suppressed.

[0118] [Cross-sectional configuration example 5] FIG. 13 shows a modified example of the configuration shown in FIG. 9, FIG. 14 shows a modified example of the configuration shown in FIG. 10, and FIG. 15 shows a modified example of the configuration shown in FIG. 11 shows a modified example of the configuration shown in FIG. 11, and FIG. 16 shows a modified example of the configuration shown in FIG. 12. 13 to 16 differ from those shown in FIGS. 9 to 12 in that they do not have the impurity semiconductor layer 35. This differs from the configuration shown in .

[0119] In the configurations shown in FIGS. 13 to 16, the semiconductor layer 32 uses a semiconductor containing a metal oxide. It is preferable to use a semiconductor containing a metal oxide for the semiconductor layer 32, that is, a transistor. By using an OS transistor as the 30, as described above, the The charge corresponding to the charge can be held in the capacitor 60 for a long period of time. This reduces the frequency of writing charge to the display, i.e., the frequency of refresh operations. The power consumption of the device 10 can be reduced.

[0120] The above is a description of the cross-sectional configuration example.

[0121] [About each component] Each of the above components will be described below.

[0122] 〔substrate〕 A material having a flat surface can be used for the substrate of the display panel. The substrate from which the light is extracted is made of a material that transmits the light. For example, glass, quartz, ceramic Materials such as black, sapphire, and organic resin can be used.

[0123] By using a thin substrate, it is possible to reduce the weight and thickness of the display panel. By using a substrate with a thickness that allows flexibility, a flexible display panel can be realized. Alternatively, a thin glass substrate that is flexible can be used. Alternatively, a composite material in which glass and a resin material are bonded together with an adhesive layer may be used.

[0124] [Transistor] A transistor is made up of a conductive layer that functions as a gate, a semiconductor layer, and a gate electrode that functions as a source. a conductive layer having a function as a drain; a conductive layer having a function as a gate insulating layer; and an insulating layer having a function.

[0125] Note that the structure of a transistor included in a display device of one embodiment of the present invention is not particularly limited. For example, a planar type transistor or a staggered type transistor may be used. Alternatively, a top-gate or bottom-gate transistor may be used. Alternatively, gates may be provided above and below the channel. It may be possible.

[0126] [Semiconductor layer] The crystallinity of the semiconductor layer used in the transistor is not particularly limited. Semiconductors (microcrystalline semiconductors, polycrystalline semiconductors, single-crystal semiconductors, or semiconductors having crystalline regions in part) When a crystalline semiconductor is used, transistor characteristics are improved. This is preferable because it can suppress deterioration of the film.

[0127] The semiconductor layer of the transistor contains, for example, elements of Group 14 (silicon, germanium, etc.). When silicon is used as the semiconductor layer of a transistor, It is particularly preferable to use amorphous silicon. By this method, transistors can be formed over a large substrate with high yield. This makes it possible to improve the mass productivity of the display device.

[0128] In addition, silicon having crystallinity such as microcrystalline silicon, polycrystalline silicon, and single crystal silicon can be used. In particular, polycrystalline silicon can be formed at a lower temperature than single-crystalline silicon. It also has higher field-effect mobility and higher reliability than amorphous silicon.

[0129] The bottom-gate transistor exemplified in this embodiment can reduce the manufacturing process. In this case, the use of amorphous silicon is preferable because it is lower than polycrystalline silicon. Because it can be formed at low temperatures, it is suitable for use as a material for wiring and electrodes below the semiconductor layer, as well as for substrates. This allows for the use of materials with low thermal conductivity, which broadens the range of material choices. On the other hand, a top gate type transistor can be suitably used. Since the impurity region of the transistor is easily formed in a self-aligned manner, it is possible to reduce the variation in characteristics. In this case, it is particularly preferable to use polycrystalline silicon or single crystal silicon. This may be appropriate when:

[0130] The semiconductor layer of the transistor can be made of a metal oxide. semiconductors containing gallium arsenide, or metal oxides containing indium, etc. Cut.

[0131] In particular, it is preferable to use a metal oxide having a band gap larger than that of silicon. If a semiconductor material with a wider band gap and lower carrier density than that of a capacitor is used, This is preferable because it can reduce the current when the transistor is in the off state.

[0132] Transistors using metal oxides with a larger bandgap than silicon are The charge stored in the capacitor connected in series with the transistor is maintained for a long period of time by the current. By applying such transistors to pixels, it is possible to It is also possible to stop the driving circuit while maintaining the gradation of the displayed image. Thus, a display device with reduced power consumption can be realized.

[0133] The semiconductor layer may be, for example, at least indium, zinc, and M (aluminum, titanium, gallium). Sm, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium It includes a film expressed as In-M-Zn oxide containing metals such as aluminum or hafnium. In addition, in order to reduce variations in the electrical characteristics of transistors using the semiconductor layer, , and preferably includes a stabilizer therewith.

[0134] The stabilizer includes the metals listed above under M, such as gallium, tin, hafnium, etc. Other stabilizers include sulphur, aluminium or zirconium. , the lanthanides lanthanum, cerium, praseodymium, neodymium, samarium, Uropium, gadolinium, terbium, dysprosium, holmium, erbium, Examples include rhenium, ytterbium, and lutetium.

[0135] Examples of metal oxides that form the semiconductor layer include In-Ga-Zn oxides and In-Al -Zn-based oxides, In-Sn-Zn-based oxides, In-Hf-Zn-based oxides, In-La- Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Z n-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides Oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In-Hf-Ga -Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn oxide and In-Hf-Al-Zn oxide can be used. do.

[0136] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The atomic ratio of In, Ga, and Zn does not matter. For example, The numerical ratio may be In:Ga:Zn=1:1:1 or In:Ga:Zn=2:2:1. Alternatively, In:Ga:Zn=3:1:2, or In:Ga:Zn=4: It may be 2:3, or In:Ga:Zn=5:1:6, or a value close to these values. In addition, metal elements other than In, Ga, and Zn may be contained.

[0137] The semiconductor layer and the conductive layer may contain the same metal element from the oxides. By using the same metal element for the dielectric layer and the conductive layer, manufacturing costs can be reduced. For example, by using a metal oxide target of the same metal composition, the manufacturing cost can be reduced. In addition, the etching gas or etching solution used in processing the semiconductor layer and the conductive layer can be However, the semiconductor layer and the conductive layer do not have to contain the same metal element. For example, during the manufacturing process of a transistor or a capacitor, In this case, metal elements in the film may be released, resulting in a different metal composition.

[0138] The metal oxide constituting the semiconductor layer has an energy gap of 2 eV or more, preferably 2.5 eV or more. It is preferable that the energy gap is 3 eV or more, and more preferably 3 eV or more. By using a metal oxide with a wide gap, the off-state current of a transistor can be reduced. do.

[0139] When the metal oxide constituting the semiconductor layer is In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used for film formation satisfies In≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is , In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3 :1:2, 4:2:4.1, In:M:Zn=2:1:3, In:M:Zn=3:1:2 , In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1 :8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. are preferred. The atomic ratio of the metal elements contained in the semiconductor layer to be formed is determined by the above-mentioned sputtering method. The atomic ratio of metal elements contained in the target varies by ±40%. .

[0140] The metal oxide constituting the semiconductor layer is CAC-OS or CAC-metal o This can increase the field-effect mobility of the transistor. This can be done.

[0141] It is preferable to use a metal oxide having a low carrier density for the semiconductor layer. The layer has a carrier density of 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 below , and more preferably 1 × 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below or less, more preferably 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than Such a semiconductor layer has a low impurity concentration and a low defect level density. When the semiconductor layer is made of a metal oxide, it has stable properties due to its low impurity content. Examples of suitable oxygen include water and hydrogen.

[0142] In this specification and the like, a metal oxide having a low impurity concentration and a low defect level density is referred to as a high-purity intrinsic metal oxide. These metal oxides may be referred to as pure metal oxides or substantially high-purity intrinsic metal oxides.

[0143] High-purity intrinsic or substantially high-purity intrinsic metal oxides have fewer carrier sources, making them less likely to generate carriers. Therefore, the carrier density can be reduced. The threshold voltage rarely becomes negative (also known as normally-on) Furthermore, highly pure intrinsic or substantially highly pure intrinsic metal oxides have a low density of defect states. In addition, the trap level density may be low due to the high purity intrinsic or substantially high purity. The transistors having highly intrinsic metal oxides have significantly smaller off-state currents and wider channel widths. W is 1 x 10 6 Even if the device has a channel length L of 10 μm, the In the voltage (drain voltage) range of 1V to 10V, the off-state current is Below the measurement limit of the analyzer, i.e., 1 × 10 -13 A characteristic of A or less can be obtained. do.

[0144] Note that a semiconductor layer applicable to one embodiment of the present invention is not limited to the above, and may be any other suitable semiconductor layer. The appropriate composition is selected according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the In order to obtain the required semiconductor characteristics of the transistor, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density It is preferable to set the degree etc. to an appropriate value.

[0145] The metal oxides that make up the semiconductor layer contain silicon and carbon, which are elements of Group 14. If the semiconductor layer is filled with oxygen, oxygen vacancies may increase, causing the semiconductor layer to become n-type. , the concentration of silicon and carbon in the semiconductor layer (concentrations obtained by secondary ion mass spectrometry) , 2 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 It is preferable to do the following:

[0146] In addition, alkali metals and alkaline earth metals generate carriers when bonded with metal oxides. This may increase the off-state current of the transistor. of alkali metals or alkaline earth metals obtained by secondary ion mass spectrometry in the layer The concentration is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / c m 3 It is preferable to do the following:

[0147] The semiconductor layer may have a non-single crystal structure, for example. In non-single crystalline structures, the amorphous structure is the most defective. The level density is high.

[0148] Amorphous metal oxides, for example, have disordered atomic arrangements and do not have crystalline components. Alternatively, an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not have any crystalline portions.

[0149] The semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a single crystalline structure region, or the like. The mixed film may be a film having two or more of the above-mentioned regions. It may have a single layer structure containing two or more of the above regions, or a laminated structure. .

[0150] [Conductive Layer] In addition to the gate, source, and drain of the transistor, various wiring and Materials that can be used for the conductive layers such as electrodes include aluminum, titanium, chromium, Nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tung Examples include metals such as stainless steel, or alloys that contain these as their main components. The film containing silicon can be used as a single layer or as a laminate structure. Single layer structure of aluminum film, double layer structure with aluminum film laminated on titanium film, tungsten Two-layer structure with aluminum film laminated on top of copper-magnesium-aluminum alloy film Two-layer structure with copper film laminated, two-layer structure with copper film laminated on titanium film, copper film laminated on tungsten film Two-layer structure with laminated films: titanium film or titanium nitride film and aluminum film on top of it Or a three-layer structure in which a copper film is laminated and a titanium film or titanium nitride film is further formed thereon. Molybdenum film or molybdenum nitride film is laminated on top of which aluminum film or copper film is stacked. There are three-layer structures, such as a layer of silicon dioxide and a molybdenum film or molybdenum nitride film formed on top of that. It is to be noted that oxides such as indium oxide, tin oxide, or zinc oxide may also be used. The use of copper containing gun is preferred because it improves the controllability of the shape by etching.

[0151] In addition to the gate, source, and drain of a transistor, various wirings that make up a display device are also Examples of conductive materials having light-transmitting properties that can be used for conductive layers such as wires and electrodes include oxides. Indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, gallium doped Conductive oxides such as zinc oxide or graphene can be used. , platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, Use of metal materials such as copper, palladium, or titanium, or alloy materials containing such metal materials. Alternatively, nitrides of the metal materials (for example, titanium nitride) may be used. When a metal material or an alloy material (or a nitride thereof) is used, the material has a light-transmitting property. The thickness can be as thin as possible. Also, a laminated film of the above materials can be used as the conductive layer. For example, if a laminated film of an alloy of silver and magnesium and indium tin oxide is used, the conductivity can be improved. These are preferable because they can enhance the electrical conductivity of the display device. and a conductive layer of a display element (a conductive layer having a function as a pixel electrode or a common electrode). ) can also be used.

[0152] [Insulating layer] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic and epoxy. In addition to resins with siloxane bonds, silicon oxide, silicon oxynitride, silicon nitride oxide, Inorganic insulating materials such as silicon, silicon nitride, and aluminum oxide can also be used.

[0153] In addition, when the semiconductor layer contains a metal oxide, the insulating layer having a region in contact with the semiconductor layer is It is preferable to have a region (excess oxygen region) containing oxygen in excess of the stoichiometric composition. For example, the insulating layer 34 and the insulating layer 82 having a region in contact with the semiconductor layer 32 may be formed by adding excess oxygen. It is preferable that the insulating layer 34 and the insulating layer 82 have a semiconductor layer. When the semiconductor layer 32 contains a metal oxide, oxygen can be supplied to the semiconductor layer 32. When oxygen vacancies are formed in the oxide, impurities such as hydrogen enter the oxygen vacancies, resulting in the formation of oxygen vacancies. This may cause the generation of carrier electrons, which can degrade the electrical characteristics of the transistor. When an insulating layer having a region in contact with a semiconductor layer has an excess oxygen region, the insulating layer may Oxygen can be supplied from the insulating layer to the semiconductor layer, and oxygen vacancies can be compensated for. This can suppress deterioration of the electrical characteristics of the transistor. To provide the element region, for example, an insulating layer may be formed in an oxygen atmosphere. The insulating layer may be heat-treated in an oxygen atmosphere.

[0154] [Liquid Crystal Element] As the liquid crystal element, for example, a vertical alignment (VA) model A liquid crystal element to which a vertical alignment mode is applied can be used. ulti-Domain Vertical Alignment) mode, PVA(P atterned Vertical Alignment) mode, ASV (Adva nced Super View mode, etc. can be used.

[0155] In addition, the liquid crystal element may be one that employs various modes. In addition to the VA mode, there are also TN (Twisted Nematic) and IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optically Compensated) d Birefringence mode, FLC (Ferroelectric Li quid Crystal) mode, AFLC(AntiFerroelectric) mode Liquid Crystal mode, ECB (Electrically Controlled Blue) Rolled Birefringence mode, guest host mode, etc. are applied. A liquid crystal element having such a configuration can be used.

[0156] The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of the liquid crystal is due to the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal used in the liquid crystal element is Thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC) Polymer Dispersed Liquid Crystal), polymer net Work type liquid crystal (PNLC: Polymer Network Liquid Crystal al), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials include Depending on the conditions, it can be in a cholesteric phase, smectic phase, cubic phase, or chiral nematic phase. phase, isotropic phase, etc.

[0157] The liquid crystal material may be either a positive type liquid crystal or a negative type liquid crystal. The optimum liquid crystal material may be used depending on the mode and design to be applied.

[0158] In addition, an alignment film can be provided to control the alignment of the liquid crystal. When using a liquid crystal, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of a cholesteric liquid crystal is increased, the phase transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range. To improve this, a liquid crystal composition containing several weight percent or more of a chiral agent is used in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time and optically isotropic In addition, the liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent does not require alignment treatment. The viewing angle dependency is small. Also, no alignment film is required, so rubbing treatment is not required. Therefore, electrostatic breakdown caused by the rubbing treatment can be prevented. This reduces defects and damage to the liquid crystal display device during the manufacturing process.

[0159] The liquid crystal element may be a transmissive liquid crystal element, a reflective liquid crystal element, or a semi-transmissive liquid crystal element. There are children.

[0160] In one embodiment of the present invention, a transmissive liquid crystal element can be particularly suitably used.

[0161] When using a transmissive or semi-transmissive liquid crystal element, two polarizing plates are placed between a pair of substrates. A backlight is provided outside the polarizing plate. The backlight may be a bottom-type backlight or an edge-light type backlight. Direct backlight with LED (Light Emitting Diode) This is preferred because it makes local dimming easier and increases contrast. In addition, when an edge-light type backlight is used, the module including the backlight can be This is preferable because it allows the thickness of the foil to be reduced.

[0162] In addition, by turning off the edge-lit backlight, a see-through display can be achieved. This can be done.

[0163] [Colored layer] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. Examples of such materials include resin materials.

[0164] [Light blocking layer] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. The light-shielding layer may be a laminated film of a film containing the material of the colored layer. A film containing a material used for a colored layer that transmits light of a different color and a film containing a material used for a colored layer that transmits light of a different color are used. By forming the colored layer and the light-shielding layer from the same material, This is preferable because the same equipment can be used and the process can be simplified.

[0165] This concludes the explanation of each component.

[0166] [Example of pixel manufacturing method] An example of a method for manufacturing the display device 10 will be described below.

[0167] The thin films (insulating films, semiconductor films, conductive films, etc.) that make up the display device are each formed by sputtering. method, chemical vapor deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be, for example, plasma-enhanced chemical vapor deposition (PE Examples of thermal CVD include metal organic chemical vapor deposition (MOCVD) and thermal CVD. deposition (MOCVD: Metal Organic CVD) method.

[0168] The thin films (insulating films, semiconductor films, conductive films, etc.) that make up the display device are formed by spin coating, Dip, spray application, inkjet printing, dispensing, screen printing, offset Printing methods such as inkjet printing, or doctor knife, slit coating, roll coating, curtain coating It can be formed by coating or knife coating.

[0169] The thin film constituting the display device can be processed using a lithography method or the like. Alternatively, an island-shaped thin film may be formed by a film formation method using a shielding mask. The thin film may be processed by a lint method, a sandblasting method, a lift-off method, or the like.

[0170] When processing using photolithography, the light used for exposure is, for example, i-line (wavelength ray (wavelength 365nm), g-ray (wavelength 436nm), h-ray (wavelength 405nm), and a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. The exposure may also be performed by immersion exposure. Extreme Ultra-Violet (EUV) and X For exposure, electron beams can be used instead of light. Ultraviolet light, X-rays, or electron beams are preferred because they allow extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is used. is not necessary.

[0171] For etching thin films, there are dry etching, wet etching, and sandblasting methods. etc. can be used.

[0172] [Example of manufacturing method 1] An example of a method for manufacturing the pixel 11(i+3, j) etc. having the configuration shown in FIG. 10 is shown in FIGS. 17 to 19. When manufacturing the display device 10, first, a conductive layer is formed on the substrate 14. Next, Patterning is performed by lithography or the like, and the conductive layer is processed by etching or the like. By this, the conductive layer 31, the conductive layer 31a, and the conductive layer 53 are formed (FIG. 17(A)). As described above, the conductive layer 31 corresponds to a part of the wiring G3, and the conductive layer 31a corresponds to a part of the wiring CS. Corresponds to the part.

[0173] Next, the insulating layer 34 is formed. As described above, the insulating layer 34 is formed on the substrate 11 provided in the display device 10. It functions as a gate insulating layer for the transistor.

[0174] Thereafter, a semiconductor layer is formed on the insulating layer 34. For example, amorphous silicon is used as the semiconductor layer. When using silane, the film can be formed by a CVD method using monosilane or the like as a raw material. This allows the dangling bonds of silicon contained in the semiconductor layer to be bonded by hydrogen. In this way, the amorphous structure containing hydrogen can be stabilized thermodynamically. The silicon is called hydrogenated amorphous silicon.

[0175] Next, an impurity semiconductor layer, which is a semiconductor layer containing impurities, is formed on the semiconductor layer. When hydrogenated amorphous silicon is used as the pure semiconductor layer, the transistor is When making a mold, phosphine or arsine is added to the raw material such as monosilane, and CVD is performed. When the transistor is to be p-type, the film can be formed by a method such as monosilane. By adding diborane or the like to the raw material, an impurity semiconductor layer can be formed by CVD or other methods. Cut.

[0176] Thereafter, patterning is performed by photolithography or the like, and the formed semiconductor layer is etched. The semiconductor layer 32 and the impurity semiconductor layer 35 are formed by processing the semiconductor layer 32 by a bonding method or the like. (Figure 17(B)).

[0177] Next, a conductive layer is formed on the insulating layer 34 and the impurity semiconductor layer 35. Patterning is performed by a lithography method or the like, and the conductive layer is processed by an etching method or the like. By this, the conductive layer 51, the conductive layer 33a, the conductive layer 33b, and the conductive layer 33c are formed. (FIG. 17(C)). As described above, the conductive layer 51 is the source or drain of the transistor 30. The conductive layer 33a serves as one of the source and drain of the transistor 30. and functions as one electrode of the capacitor element 60. The conductive layer 33b is connected to the wiring S The conductive layer 33b corresponds to a part of the wiring S3, and the conductive layer 33c corresponds to a part of the wiring S4. It is formed to have an area overlapping with the conductive layer 53 .

[0178] Next, the insulating layer 82 is formed, and then the insulating layer 81 is formed. After the insulating layer 81 is formed, Mechanical polishing (CMP) The insulating layer 81 is subjected to a planarization process by a method or the like.

[0179] Next, patterning is performed by photolithography or the like, and then etching or the like is performed. By processing the insulating layer 81 and the insulating layer 82, openings 71 and 82 reaching the conductive layer 51 are formed. An opening 38 reaching the conductive layer 33a and an opening 74 reaching the conductive layer 33c are formed. In addition, the insulating layer 81, the insulating layer 82, and the insulating layer 34 are processed by etching or the like. As a result, the openings 72 and 73 reaching the conductive layer 53 are formed so as to sandwich the conductive layer 33b. As a result, the opening 38 and the openings 71 to 74 are formed (FIG. 18(A)). is formed.

[0180] Next, a conductive layer is formed on the insulating layer 81, the opening 38, and the openings 71 to 74. Then, patterning is performed using a photolithography method or the like, and the corresponding The conductive layer is processed to form conductive layer 21, conductive layer 52, and conductive layer 54. (FIG. 18(B)). The conductive layer 21 is electrically connected to the conductive layer 33a through the opening 38. The conductive layer 52 is electrically connected to the conductive layer 51 through the opening 71 and is electrically connected to the conductive layer 52 through the opening 72. The conductive layer 54 is electrically connected to the conductive layer 53 through the opening 73. The conductive layer 33c is electrically connected to the conductive layer 33a through the opening 74. The conductive layer 21 functions as a pixel electrode of a liquid crystal element provided in the display device 10. In addition, the conductive layer 5 having a function as either the source or the drain of the transistor 30 1 is a conductive layer 33c corresponding to a part of the wiring S4, a conductive layer 52, a conductive layer 53, and a conductive Electrical connection is made via layer 54 .

[0181] Next, an alignment film 24a is formed (FIG. 19(A)). A colored layer 41, an insulating layer 26, a conductive layer 23, and an alignment film 24b are formed (FIG. 19(B)). The colored layer 41 is formed by using a photolithography method, a printing method, or an inkjet method. For example, the colored layer 41 can be formed at room temperature by using an inkjet method. It can be fabricated in a low vacuum or on a large substrate. The colored layer 41 can also be formed on extremely high resolution display devices such as 4K and 8K. In addition, the screen size must be 50 inches or more, 60 inches or more, or 70 inches or more. The colored layer 41 can be formed on a large display device of 1000 or more. Since the colored layer 41 can be formed without using a This can reduce the number of layers, thereby reducing the manufacturing cost.

[0182] Next, an adhesive layer ( The liquid crystal 22 is sealed using a polarizing plate 39a, a polarizing plate 39b, and The backlight unit 90 is formed. As a result, the display device 10 having the configuration shown in FIG. It can be made.

[0183] Here, when manufacturing a display device, the fewer photolithography steps in the manufacturing process, the better. That is, the fewer the number of photomasks, the lower the manufacturing cost. .

[0184] For example, in the steps shown in FIGS. 17 and 18 (steps on the substrate 14 side), the shape of the conductive layer 31, etc. 17(A)), a step of forming the semiconductor layer 32 and the like (FIG. 17(B)), a step of forming the conductive layer 33a (FIG. 17C), a process of forming openings 38, etc. (FIG. 18A), and a conductive By going through a total of five photolithography steps, such as the step of forming the layer 21 (FIG. 18(B)), The display device 10 can be manufactured. That is, the backplane substrate is manufactured using five photomasks. can be produced.

[0185] When the display device is configured to have one or two source lines per pixel column, as shown in FIG. 9. For example, the pixel 11 may not have the configuration shown in FIG. Even in this case, when manufacturing the backplane substrate, A total of five photolithography processes are required, meaning five photomasks are required. From the above, even in the case where four source lines are provided per pixel column, , the same number of photomasks are used as when one or two source lines are provided per pixel column. This allows the manufacture of a display device with four source lines per pixel column. The manufacturing cost of a display device having such a configuration is reduced by providing one or two source lines per pixel column. Therefore, it is possible to suppress an increase in the manufacturing cost of the display device having such a configuration.

[0186] [Example of manufacturing method 2] An example of a method for manufacturing the pixel 11(i+3, j) etc. having the configuration shown in FIG. 14 is shown in FIGS. 20 to 22. 20(A), (B), (C), 21(A), (B), and 22(A), ( B) are respectively Fig. 17(A), (B), (C), Fig. 18(A), (B), and Fig. 19 The manufacturing method shown in FIGS. 20 to 22 corresponds to (A) and (B). This method differs from the previously described manufacturing method in that the impurity semiconductor layer 35 is not formed during this process.

[0187] In the manufacturing method shown in FIGS. 20 to 22, the semiconductor layer formed on the insulating layer 34 is, for example, Metal oxide can be used. In this case, the semiconductor layer can be formed by sputtering. When an In-Ga-Zn oxide is used as the semiconductor layer, for example, The semiconductor layer is formed by sputtering using an In-Ga-Zn oxide target. The other steps can be performed in the same manner as in the manufacturing method shown in FIGS. can be done.

[0188] The above is an explanation of an example of a method for manufacturing pixels and the like.

[0189] [Shape of the conductive layer] The conductive layer that can be used for wiring such as gate lines and source lines is made of a low-resistance material such as a metal or alloy. The use of such a material is preferable because it can reduce wiring resistance. In the case of fabricating a semiconductor device, it is also effective to increase the width of the wiring. Since the conductive layer does not transmit visible light, the width of the wiring itself is As the size of the wiring increases and the number of wirings increases, the aperture ratio may decrease.

[0190] Therefore, by devising the shape of the edge of the conductive layer, it is possible to efficiently transmit light from the backlight unit. can be taken out.

[0191] FIG. 23A shows a cross-sectional view of a conductive layer 33 constituting a source line and the like and its vicinity. The conductive layer 33 has an inversely tapered end. a, conductive layer 33b, and conductive layer 33c. Alternatively, the conductive layer 33 may be, for example, It can be considered as a conductive layer 51 .

[0192] Here, the taper angle is the angle between the bottom surface (the surface in contact with the surface on which the film is formed) and the side surface at the end of the thin film. The taper angle is the angle between the surface and the surface. The taper angle is greater than 0 degrees and less than 180 degrees. When the angle is less than 90 degrees, it is called a forward taper, and when it is greater than 90 degrees, it is called a reverse taper.

[0193] As shown in FIG. 23(A), the conductive layer 33 has an inverse tapered shape, so that the backlight unit A part of the light 50 incident from the unit is reflected by the side surface of the conductive layer 33 and reaches the liquid crystal 22. As a result, compared with when the side surface of the conductive layer 33 is vertical or has a forward tapered shape, This can increase the light extraction efficiency.

[0194] Here, the taper angle of the conductive layer 33 is greater than 90 degrees and less than 135 degrees, preferably 91 degrees or less. It is preferable that the angle is 120 degrees or less, and more preferably 95 degrees or more and 110 degrees or less.

[0195] In addition, in FIG. 23(B), when the conductive layer 31 constituting the gate line etc. has an inverse tapered shape, By forming the conductive layer 31 in an inverse tapered shape in addition to the conductive layer 33, the The light extraction efficiency can be effectively increased.

[0196] The above is the description of the shape of the conductive layer.

[0197] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0198] (Embodiment 2) In this embodiment mode, a transistor which can be used for a display device or the like shown in the above embodiment mode will be described. An example of the data will be described with reference to the drawings.

[0199] [Transistor configuration example 1] Modified examples of the transistors shown in FIGS. 9 to 12 will be described below.

[0200] The transistor shown in FIG. 24A has a semiconductor layer 32 and an impurity semiconductor layer 35 between them. It has a layer 37.

[0201] The semiconductor layer 37 may be formed of a semiconductor film similar to the semiconductor layer 32. 37 indicates that the semiconductor layer 32 is etched away during etching of the impurity semiconductor layer 35. It has a function as an etching stopper to prevent the In the example shown, the semiconductor layer 37 is separated into left and right halves. It may cover the channel forming region of the conductor layer 32 .

[0202] The semiconductor layer 37 may contain impurities at a lower concentration than the impurity semiconductor layer 35. This allows the semiconductor layer 37 to be an LDD (Lightly Doped Drain) region. This can function as a gate driver, suppressing the hot channel effect when the transistor is driven. It can be controlled.

[0203] The transistor shown in FIG. 24B has an insulating layer 84 on the channel forming region of the semiconductor layer 32. The insulating layer 84 is provided to prevent etching when the impurity semiconductor layer 35 is etched. It functions as a topper.

[0204] The transistor shown in FIG. 24C includes a semiconductor layer 32p instead of the semiconductor layer 32. The semiconductor layer 32p includes a semiconductor film with high crystallinity. For example, the semiconductor layer 32p is a polycrystalline semiconductor. This allows the transistor to have high field-effect mobility. This can be done.

[0205] The transistor shown in FIG. 24(D) has a semiconductor layer 32p in the channel forming region of the semiconductor layer 32. For example, the transistor shown in FIG. 24D has a semiconductor film that becomes the semiconductor layer 32. It can be formed by irradiating the area with laser light or the like to crystallize it locally. This makes it possible to realize a transistor with high field-effect mobility.

[0206] The transistor shown in FIG. 24(E) is the same as the transistor shown in FIG. 24(A) except for the semiconductor layer 32 The channel formation region of the semiconductor device includes a crystalline semiconductor layer 32p.

[0207] The transistor shown in FIG. 24(F) is the same as the transistor shown in FIG. 24(B), except that the semiconductor layer 32 The channel formation region of the semiconductor device includes a crystalline semiconductor layer 32p.

[0208] [Transistor configuration example 2] Modified examples of the transistors shown in FIGS. 13 to 16 will be described below.

[0209] As an example of the structure of a transistor, a transistor 200a is shown in FIGS. 25A is a top view of the transistor 200a. 25(B) corresponds to a cross-sectional view of the cut surface between the dashed line X1-X2 shown in FIG. 25(A). 25(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 25(A). In FIG. 25(A), in order to avoid complication, the transistor Some of the components of 200a (such as an insulating layer that functions as a gate insulating layer) are omitted in the figure. In the following description, the direction of the dashed dotted line X1-X2 is the channel length direction, and the dashed dotted line The Y1-Y2 direction is sometimes called the channel width direction. In the following drawings, some of the components are omitted in the same manner as in FIG. 25(A). This may occur.

[0210] The transistor 200a includes a conductive layer 221 on an insulating layer 224 and a conductive layer 222 on the insulating layer 224 and a conductive layer 223 on the insulating layer 224. The insulating layer 211 on the layer 221, the semiconductor layer 231 on the insulating layer 211, and the semiconductor layer 231 on the and a conductive layer 222a on the insulating layer 211, and a conductive layer 222b on the semiconductor layer 231 and the insulating layer 211. layer 222b, and an insulating layer on the semiconductor layer 231, the conductive layer 222a, and the conductive layer 222b. 212 and a conductive layer 223 on the insulating layer 212.

[0211] It should be noted that the insulating layer 224 may be a substrate instead of an insulating layer. In this case, the substrate should contain the same material as the substrate 14 shown in the first embodiment. can be done.

[0212] The conductive layer 221 and the conductive layer 223 are the same as the conductive layer 31 shown in the first embodiment, for example. The insulating layer 211 may contain the same material as the insulating layer 34 shown in the first embodiment, for example. The conductive layer 222a and the conductive layer 222b may include, for example, a material similar to that of The insulating layer may include the same materials as the conductive layer 33 and the conductive layer 51 shown in the first embodiment. The insulating layer 212 may contain the same material as the insulating layer 82 shown in the first embodiment.

[0213] The semiconductor layer 231 is made of a metal oxide, similar to the semiconductor layer 32 shown in the first embodiment. In this embodiment, the semiconductor layer 231 can be a semiconductor layer containing a metal oxide The following description will be given assuming that the semiconductor layer includes:

[0214] The insulating layer 211 and the insulating layer 212 have an opening 235. The conductive layer 223 has an opening 235. It is electrically connected to the conductive layer 221 via 35 .

[0215] Here, the insulating layer 211 functions as a first gate insulating layer of the transistor 200a. The insulating layer 212 functions as a second gate insulating layer of the transistor 200a. In the transistor 200a, the conductive layer 221 functions as a first gate. The conductive layer 222a functions as either a source or a drain. 2b functions as the other of the source and drain. In a, the conductive layer 223 functions as a second gate.

[0216] The transistor 200a is a so-called channel-etched transistor. It has an algate structure.

[0217] The transistor 200a may also be configured without the conductive layer 223. In this case, the transistor 200a is a so-called channel-etched transistor, and the bottom It has a gate structure.

[0218] As shown in FIGS. 25(B) and 25(C), the semiconductor layer 231 is formed by the conductive layer 221 and the conductive layer 2 23 and is sandwiched between two conductive layers that function as gates. The length of the conductive layer 223 in the channel length direction and the length of the conductive layer 223 in the channel width direction are The length of the semiconductor layer 231 in the channel length direction and the length of the semiconductor layer 231 in the channel width direction are The entire semiconductor layer 231 is covered with the conductive layer 223 via the insulating layer 212. are.

[0219] In other words, the conductive layer 221 and the conductive layer 223 are provided on the insulating layer 211 and the insulating layer 212. The semiconductor layer 231 is connected to the opening 235 formed in the opening 235 and is positioned outside the side edge of the semiconductor layer 231. It has an area where

[0220] With this configuration, the semiconductor layer 231 included in the transistor 200a is The transistor can be electrically surrounded by the electric field of the conductive layer 221 and the conductive layer 223. As shown in 200a, the electric field of the first gate and the second gate forms a channel forming region. The device structure of the transistor that electrically surrounds the semiconductor layer on which the This can be called an ed channel (s-channel) structure.

[0221] The transistor 200a has an s-channel structure, and therefore functions as a first gate. The conductive layer 221 has an electric field for inducing a channel, which is effectively applied to the semiconductor layer 231. Therefore, the current driving capability of the transistor 200a is improved, and a high on-state current can be obtained. It is also possible to increase the on-current, which allows The transistor 200a can be miniaturized. The conductive layer 231 functions as a first gate and the conductive layer 221 functions as a second gate. Since the transistor 200a has a structure surrounded by the conductive layer 223, Strength can be increased.

[0222] The transistor 200a has an s-channel structure and has high field-effect mobility. Because of its high performance, transistor 200a is used in drive circuits, typically gate drivers. This makes it possible to provide a display device with a narrow frame width (also called a narrow frame).

[0223] Next, as an example of the structure of a transistor, a transistor 200b will be described with reference to FIG. 26A is a top view of the transistor 200b. FIG. 26(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 26(A). 26(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 26(A). This corresponds to a cross-sectional view.

[0224] The transistor 200b includes a semiconductor layer 231, a conductive layer 222a, a conductive layer 222b, and an insulating layer. The transistor 200 differs from the transistor 200a in that the edge layer 212 has a laminated structure.

[0225] The insulating layer 212 is an insulating layer on the semiconductor layer 231, the conductive layer 222a, and the conductive layer 222b. The insulating layer 212 has a semiconductor layer 212a and an insulating layer 212b on the insulating layer 212a. The insulating layer 212 has a function of supplying oxygen to the insulating layer 231. That is, the insulating layer 212 contains oxygen. The insulating layer 212a is an insulating layer that can transmit oxygen. This serves as a film for reducing damage to the semiconductor layer 231 when forming the insulating layer 212b to be formed later. It still works.

[0226] The insulating layer 212a has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 1 nm or less can be used.

[0227] Furthermore, it is preferable that the insulating layer 212a has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3 x 10 17 spins / cm 3 This is because the insulating layer 212a If the density of defects contained in the insulating layer 212a is high, oxygen will bond to the defects, This is because the oxygen permeability decreases.

[0228] In the insulating layer 212a, all of the oxygen that has entered the insulating layer 212a from the outside is absorbed by the insulating layer 212a. In some cases, oxygen may remain in the insulating layer 212a without moving out of the insulating layer 212a. As oxygen enters the insulating layer 212a, the oxygen contained in the insulating layer 212a flows out of the insulating layer 212a. The migration may cause oxygen migration in the insulating layer 212a. When an oxide insulating layer that can transmit oxygen is formed as insulating layer 212a, the insulating layer 212b is provided on the insulating layer 212a. The oxygen desorbed from the insulating layer 212b is transported to the semiconductor layer 231 via the insulating layer 212a. can be moved to

[0229] In addition, an oxide insulating layer with a low density of states due to nitrogen oxides is used as the insulating layer 212a. The density of levels due to the nitrogen oxides can be calculated by the valence band of the metal oxide. can be formed between the energy of the upper edge of the conduction band of the metal oxide and the energy of the lower edge of the conduction band of the metal oxide. The oxide insulating layer may be a silicon oxynitride film which emits less nitrogen oxide, or For example, an aluminum oxynitride film which releases less nitrogen oxides can be used.

[0230] The silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectroscopy (TDS). In Thermal Desorption Spectroscopy (TDS), nitrogen This is a film that releases more ammonia than oxide, and typically releases ammonia is 1×10 18 / cm 3 5x10 or more 19 / cm 3 The following is a list of ammonia release rates. The amount is set so that the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by heat treatment.

[0231] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO or NO forms a level in the insulating layer 212a, etc. The level Therefore, the nitroxide is located within the energy gap of the insulating layer 212a and When the electrons diffuse to the interface of the semiconductor layer 231, the level traps electrons on the insulating layer 212a side. As a result, the trapped electrons may be trapped in the insulating layer 212a and the semiconductor layer 2 31 Because they remain near the interface, they shift the threshold voltage of the transistor in the positive direction. Wow.

[0232] Nitrogen oxides also react with ammonia and oxygen during the heat treatment. The nitrogen oxide contained in a reacts with the ammonia contained in the insulating layer 212b during the heat treatment. As a result, the nitrogen oxides contained in the insulating layer 212a are reduced. At the interface between 12a and the semiconductor layer 231, electrons are less likely to be trapped.

[0233] By using the oxide insulating layer as the insulating layer 212a, the threshold voltage of the transistor It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0234] The oxide insulating layer has a nitrogen concentration of 6×10 as measured by SIMS. 20 atoms / cm 3 The following is the result.

[0235] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating layer using the VD method, a dense and hard film can be obtained. It can be formed.

[0236] The insulating layer 212b is an oxide insulating layer containing more oxygen than the oxygen required for the stoichiometric composition. In the oxide insulating layer, part of the oxygen is released by heating. , the oxide insulating layer has an oxygen release rate of 1.0 × 10 19 atoms / cm 3 That's all good Preferably 3.0 x 10 20 atoms / cm 3 The above region is also The amount of release is determined when the temperature of the heat treatment in TDS is between 50°C and 650°C, or between 50°C and 650°C. The total amount of oxygen released is in the range of 550℃ or less. This is the total amount converted into atoms.

[0237] The insulating layer 212b has a thickness of 30 nm to 500 nm, preferably 50 nm or more. A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 400 nm or less can be used.

[0238] Furthermore, it is preferable that the insulating layer 212b has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating layer 212b is a semiconductor compared to the insulating layer 212a. Since it is farther away from layer 231, it can have a higher defect density than insulating layer 212a.

[0239] In addition, the insulating layers 212a and 212b can be made of the same material. Therefore, the interface between the insulating layer 212a and the insulating layer 212b may not be clearly visible. In this embodiment, the interface between the insulating layer 212a and the insulating layer 212b is shown by a broken line. In this embodiment, the insulating layer 212a and the insulating layer 212b are provided in a two-layer structure. However, the present invention is not limited to this. For example, the insulating layer 212a may have a single layer structure or a three-layer structure. A laminated structure of more than one layer may also be used.

[0240] In the transistor 200b, the semiconductor layer 231 is a semiconductor layer 231_ on the insulating layer 211. 1 and a semiconductor layer 231_2 on the semiconductor layer 231_1. The semiconductor layer 231_1 and the semiconductor layer 231_2 each contain the same element. The semiconductor layer 231_1 and the semiconductor layer 231_2 preferably contain the elements contained in the semiconductor layer 231. I wish.

[0241] In addition, the semiconductor layer 231_1 and the semiconductor layer 231_2 have an atomic ratio of In to the element M of As an example, the semiconductor layer 231_1 and the semiconductor layer 231_2 preferably have a region where the The ratio of the number of In, M, and Zn atoms in 31_2 is In:M:Zn=4:2:3 or Here, "nearby" means that when In is 4, M is 1.5 or more and 2.5 or less. The semiconductor layer 231_1 is a layer having a thickness of 1000 nm or less, and Zn is 2 or more and 4 or less. The ratio of the number of atoms of In, M, and Zn in the semiconductor layer 231_2 is In:M:Zn=5 :1:6 or its vicinity. By making the composition of the layer 231_2 approximately the same, the same sputtering target can be used to form the layer 231_2. This allows for the reduction of manufacturing costs. When a target is used, the semiconductor layer 231_1 and the semiconductor layer 231_2 are successively formed in a vacuum in the same chamber. Since the conductor layer 231_2 can be formed, the semiconductor layer 231_1 and the semiconductor layer 231_ This can prevent impurities from being introduced into the interface with 2.

[0242] Here, the semiconductor layer 231_1 has a region with lower crystallinity than the semiconductor layer 231_2. The crystallinity of the semiconductor layer 231_1 and the semiconductor layer 231_2 may be, for example, X Analyze using X-ray diffraction (XRD), or Transmission Electron Microscope (TEM) This can be analyzed by analyzing using a scope.

[0243] The low-crystallinity region of the semiconductor layer 231_1 becomes a diffusion path for excess oxygen, and the semiconductor layer 231_ The excess oxygen can be diffused into the semiconductor layer 231_2, which has higher crystallinity than the semiconductor layer 231_1. In this way, the semiconductor layer has a stacked structure with different crystal structures, and the region with low crystallinity is formed by the diffusion of excess oxygen. By using this as a path, a highly reliable transistor can be provided.

[0244] In addition, the semiconductor layer 231_2 has a region with higher crystallinity than the semiconductor layer 231_1. This can suppress impurities that may be mixed into the semiconductor layer 231. By increasing the crystallinity of the conductive layer 222a and the conductive layer 222b, The surface of the semiconductor layer 231, that is, the surface of the semiconductor layer 231_2, can be suppressed. The surface is etched by the etchant or etchant used in forming the conductive layer 222a and the conductive layer 222b. However, the semiconductor layer 231_2 has a region with high crystallinity. In this case, the semiconductor layer 231_1 has better etching resistance than the semiconductor layer 231_1 having low crystallinity. The semiconductor layer 231_2 functions as an etching stopper.

[0245] The semiconductor layer 231_1 has a region with lower crystallinity than the semiconductor layer 231_2. This can result in a high carrier density.

[0246] In addition, when the carrier density of the semiconductor layer 231_1 increases, the conduction band of the semiconductor layer 231_1 The Fermi level may become relatively high in the semiconductor layer 231_1. The lower end of the conduction band is lowered, and the lower end of the conduction band of the semiconductor layer 231_1 and the gate insulating layer (here Therefore, the energy difference between the trap level that can be formed in the insulating layer 211 may become large. The larger the energy difference, the less charge is trapped in the gate insulating layer. This may reduce the fluctuation in the threshold voltage of the transistor. When the carrier density of the layer 231_1 is increased, the field effect mobility of the semiconductor layer 231 is increased. This can be done.

[0247] In the transistor 200b, an example in which the semiconductor layer 231 has a stacked structure of two layers is shown. However, the present invention is not limited to this, and a configuration in which three or more layers are laminated may also be used.

[0248] The conductive layer 222a included in the transistor 200b includes a conductive layer 222a_1 and a conductive layer 222 a_1 and a conductive layer 222a_3 on the conductive layer 222a_2. The conductive layer 222b included in the transistor 200b includes a conductive layer 222b_1 and The conductive layer 222b_2 on the conductive layer 222b_1 and the conductive layer 222b_2 on the conductive layer 222b_2 _3 and,.

[0249] For example, the conductive layer 222a_1, the conductive layer 222b_1, the conductive layer 222a_3, and the conductive layer 222b_3 includes titanium, tungsten, tantalum, molybdenum, indium, and gallium. It is preferable that the alloy contains one or more selected from the group consisting of sodium, tin, and zinc. The conductive layer 222a_2 and the conductive layer 222b_2 may be made of copper, aluminum, and silver.

[0250] More specifically, the conductive layer 222a_1, the conductive layer 222b_1, the conductive layer 222a_3, and and conductive layer 222b_3 is made of In—Sn oxide or In—Zn oxide, and conductive layer 222 Copper can be used for the a_2 and conductive layer 222b_2.

[0251] The end of the conductive layer 222a_1 is located outside the end of the conductive layer 222a_2. The conductive layer 222a_3 covers the upper and side surfaces of the conductive layer 222a_2 and has a conductive The conductive layer 222b_1 has an area in contact with the conductive layer 222a_1. The conductive layer 222b_3 has an area located outside the end of the conductive layer 22 The conductive layer 222b_1 covers the upper and side surfaces of the conductive layer 222b_2 and has a region in contact with the conductive layer 222b_1.

[0252] By adopting the above-mentioned structure, the wiring resistance of the conductive layer 222a and the conductive layer 222b is reduced, and This is preferable because it can suppress the diffusion of copper into the semiconductor layer 231 .

[0253] Next, as an example of the structure of a transistor, a transistor 200c will be described with reference to FIG. 27A is a top view of a transistor 200c. FIG. 27(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 27(A). 27(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 27(A). This corresponds to a cross-sectional view.

[0254] The transistor 200c has a conductive layer 221 on an insulating layer 224 and a conductive layer 221 on an insulating layer 224. The insulating layer 211 on the layer 224, the semiconductor layer 231 on the insulating layer 211, and the semiconductor layer 231 and and an insulating layer 216 on the insulating layer 211, and a conductive layer on the semiconductor layer 231 and the insulating layer 216. 222a, a conductive layer 222b on the semiconductor layer 231 and on the insulating layer 216, and the insulating layer 216 , the insulating layer 212 on the conductive layer 222a and the conductive layer 222b, and the conductive layer 223 and has.

[0255] The insulating layer 211, the insulating layer 216, and the insulating layer 212 have an opening 235. The conductive layer 221, which functions as the first gate of the gate electrode 200c, is exposed through an opening 235. The conductive layer 223 serving as the second gate of the transistor 200c is electrically connected to the conductive layer 223. The insulating layer 216 also has an opening 238a and an opening 238b. A conductive layer 222a that functions as either the source or the drain of the transistor 200c. The transistor 20 is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source and drain of the Oc is formed in the opening 23. It is electrically connected to the semiconductor layer 231 via 8b.

[0256] The insulating layer 216 functions as a channel protection layer of the transistor 200c. When the conductive layer 216 is not provided, the conductive layer 222a and the conductive layer 222b are formed by etching or the like. When forming the semiconductor layer 231, the channel forming region of the semiconductor layer 231 may be damaged. This may cause the electrical characteristics of the transistor to become unstable. After the openings 238a and 238b are formed, a conductive layer is formed and then etched. The conductive layer 222a and the conductive layer 222b are formed by processing the semiconductor substrate 100 by a semiconductor processing method or the like. Damage to the channel forming region of the conductor layer 231 can be suppressed. This stabilizes the electrical characteristics of the transistor, enabling the realization of a highly reliable transistor.

[0257] Insulating layer 216 can include, for example, similar materials to insulating layer 212 .

[0258] The insulating layer 216 preferably has an excess oxygen region. By having the above structure, oxygen can be supplied to the channel formation region of the semiconductor layer 231. Therefore, oxygen vacancies formed in the channel formation region can be compensated for by excess oxygen. Therefore, a highly reliable display device can be provided.

[0259] After the openings 238a and 238b are formed, an impurity element is added to the semiconductor layer 231. Specifically, it is preferable to add an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. As a result, the conductive property of the semiconductor layer 231 is improved, as will be described in detail later. The region overlapping with the layer 222a (either the source region or the drain region), and the conductive layer 222 The conductivity of the region overlapping with b (the other of the source region and the drain region) can be increased. This improves the current driving capability of the transistor 200c, and high on-current characteristics are obtained. This makes it possible to

[0260] The transistor 200c is a so-called channel protection type transistor, and It has a rugate structure.

[0261] The transistor 200c is s By having such a configuration, the transistor 200c has a -channel structure. The semiconductor layer 231 included therein is electrically connected by the electric field of the conductive layer 221 and the conductive layer 223. It can be surrounded.

[0262] The transistor 200c has an s-channel structure, and therefore the conductive layer 221 The electric field for inducing a channel is effectively applied to the semiconductor layer 231 by the electric layer 223. This improves the current driving capability of the transistor 200c, resulting in a high on-state current. It is also possible to increase the on-current, which allows The transistor 200c can be miniaturized. The conductor layer 231 has a structure surrounded by the conductive layer 221 and the conductive layer 223. Therefore, the mechanical strength of the transistor 200c can be increased.

[0263] Note that the transistor 200c may not include the conductive layer 223. In this case, the transistor 200c is a so-called channel protection type transistor, and It has a gate structure.

[0264] Next, an example of the structure of a transistor will be described using FIGS. 28(A), (B), (C), and (D). and explain.

[0265] 28(A) and (B) are cross-sectional views of the transistor 200d, and FIGS. 28(C) and (D) are cross-sectional views of the transistor 200d. 1 is a cross-sectional view of a transistor 200e. Transistor 200e is a variation of transistor 200b shown above. Therefore, in Fig. 28(A), (B), (C), and (D), The parts having the same functions as the transistors 200b and 200c are the same. The same reference numerals are used and detailed explanations are omitted.

[0266] 28(A) is a cross-sectional view of the transistor 200d in the channel length direction, and FIG. FIG. 28B is a cross-sectional view of the transistor 200d in the channel width direction. 28(D) is a cross-sectional view of the transistor 200e in the channel length direction. FIG. 10 is a cross-sectional view of 0e in the channel width direction.

[0267] The transistor 200d shown in FIGS. 28A and 28B has the following characteristics compared to the transistor 200b: The conductive layer 223 and the opening 235 are not provided. Compared to transistor 200b, the insulating layer 212, the conductive layer 222a, and the conductive layer 222b The configuration is different.

[0268] In the transistor 200d, the insulating layer 212 is formed by an insulating layer 212c and a thin film transistor 212b. The insulating layer 212c is made of a material that supplies oxygen to the semiconductor layer 231. and a function of preventing the intrusion of impurities (typically, water, hydrogen, etc.). The insulating layer 212c may be an aluminum oxide film, an aluminum oxynitride film, or an aluminum nitride film. In particular, the insulating layer 212c may be a reactive sputtering film. It is preferable that the aluminum oxide film be formed by a deposition method. An example of a method for forming an aluminum oxide film by sputtering is the following method. Examples include:

[0269] First, inert gas (typically Ar gas) and oxygen gas are introduced into the sputtering chamber. Then, a gas mixture of the above is introduced. By applying a voltage to the aluminum target, an aluminum oxide film can be formed. The power source for applying voltage to the aluminum target can be a DC power source, an AC power source, Alternatively, an RF power source may be used. In particular, a DC power source is preferred because it improves productivity. .

[0270] The insulating layer 212d has a function of suppressing the intrusion of impurities (typically water, hydrogen, etc.). The insulating layer 212d may be a silicon nitride film, a silicon nitride oxide film, or a silicon oxynitride film. In particular, the insulating layer 212d can be formed by the PECVD method. It is preferable to use a silicon nitride film. Silicon nitride formed by the PECVD method The film formed by the PECVD method is preferred because it is easy to obtain a high film density. The silicon nitride film may have a high hydrogen concentration in the film.

[0271] In the transistor 200d, an insulating layer 212c is disposed below the insulating layer 212d. Therefore, hydrogen contained in the insulating layer 212d does not diffuse to the semiconductor layer 231 side, or Hard to spread.

[0272] Unlike the transistor 200b, the transistor 200d has a single gate structure. By using a transistor having a single gate structure, The number of masks can be reduced, thereby increasing productivity.

[0273] The transistor 200e shown in FIGS. 28(C) and 28(D) has the following characteristics compared to the transistor 200c: The configurations of the insulating layer 216 and the insulating layer 212 are different. has insulating layer 216a instead of insulating layer 216, and insulating layer 212 instead of insulating layer 213. 2d. In the transistor 200e, the semiconductor layer 231 has a semiconductor layer 23 1_1 and a semiconductor layer 231_2.

[0274] The insulating layer 216a has the same function as the insulating layer 212c.

[0275] The structure of the transistor 200d and the transistor 200e reduces the need for large capital investment. It can be produced using existing production lines without the need for additional capital investment. Fast silicon production lines can be easily replaced with oxide semiconductor production lines. It becomes possible.

[0276] Next, as an example of the structure of a transistor, a transistor 200f will be described with reference to FIG. 29A is a top view of a transistor 200f. FIG. 29(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 29(A). 29(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 29(A). This corresponds to a cross-sectional view.

[0277] The transistor 200f shown in FIGS. 29A, 29B, and 29C has a conductive layer 224 on an insulating layer 224. 221, an insulating layer 211 on the conductive layer 221 and the insulating layer 224, and a semiconductor layer on the insulating layer 211. A conductor layer 231, an insulating layer 212 on the semiconductor layer 231, and a conductive layer 223 on the insulating layer 212. , an insulating layer 215 on the insulating layer 211 , on the semiconductor layer 231 , and on the conductive layer 223 . The semiconductor layer 231 has a channel forming region 231i overlapping with the conductive layer 223 and an insulating layer 2 a source region 231s in contact with the insulating layer 215, and a drain region 231d in contact with the insulating layer 215. Has.

[0278] The insulating layer 215 contains nitrogen or hydrogen. and the drain region 231d, the nitrogen or hydrogen in the insulating layer 215 is sorbed. The source region 231s and the drain region 231d are doped with ions. The carrier density of the drain region 231d is increased by adding nitrogen or hydrogen. do.

[0279] The transistor 200f is connected to the source via an opening 236a provided in the insulating layer 215. The transistor region 231s may have a conductive layer 222a electrically connected to the conductive layer 222a. The capacitor 200f is connected to the drain region 231d through an opening 236b provided in the insulating layer 215. The conductive layer 222b may be electrically connected to the

[0280] The insulating layer 211 functions as a first gate insulating layer, and the insulating layer 212 functions as a second gate insulating layer. The insulating layer 215 also functions as a protective insulating layer. .

[0281] Furthermore, the insulating layer 212 has an excess oxygen region. As a result, excess oxygen can be supplied into the channel formation region 231i of the semiconductor layer 231. Therefore, oxygen vacancies that may be formed in the channel formation region 231i can be compensated for by excess oxygen. Since the liquid crystal display device can be filled with the liquid crystal, a highly reliable display device can be provided.

[0282] In order to supply excess oxygen into the semiconductor layer 231, a layer formed below the semiconductor layer 231 is In this case, excess oxygen may be supplied to the insulating layer 211. The excess oxygen is contained in the source region 231s and the drain region 231d of the semiconductor layer 231. Excess oxygen can also be supplied to the source region 231s and the drain region 231d. When the voltage is supplied, the resistance of the source region 231s and the drain region 231d may become high. be.

[0283] On the other hand, the insulating layer 212 formed above the semiconductor layer 231 has excess oxygen. This makes it possible to selectively supply excess oxygen only to the channel formation region 231i. Alternatively, the channel forming region 231i, the source region 231s, and the drain region 231s may be formed by After supplying excess oxygen to the source region 231s and the drain region 231d, By selectively increasing the carrier density, the source region 231s and the drain region 231 It is possible to prevent the resistance of d from increasing.

[0284] The source region 231s and the drain region 231d of the semiconductor layer 231 are Each of them preferably has an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative examples of the element that forms the oxygen vacancy or the element that bonds to the oxygen vacancy include hydrogen, Examples include boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gas elements. Representative examples of rare gas elements include helium, neon, argon, krypton, and Xenon, etc. The elements that form the oxygen vacancies or the elements that bond with the oxygen vacancies are insulating. If one or more of the insulating layer 215 is included, the source region 231s and and drain region 231d, and / or by impurity doping process 231s and the drain region 231d.

[0285] When an impurity element is added to a metal oxide, the bond between the metal element and oxygen in the metal oxide is broken. When impurity elements are added to a metal oxide, oxygen vacancies are formed. The oxygen that was bonded to the metal element in the substance bonds with the impurity element, and the oxygen is released from the metal element. As a result, the carrier density in the metal oxide increases, and the The electrical conductivity increases.

[0286] The conductive layer 221 functions as a first gate, and the conductive layer 223 functions as a second gate. The conductive layer 222a functions as a gate, the conductive layer 222b functions as a source, and the conductive layer 222c functions as a gate. has a function as a drain.

[0287] As shown in FIG. 29(C), an opening 237 is formed in the insulating layer 211 and the insulating layer 212. The conductive layer 221 is electrically connected to the conductive layer 223 through the opening 237. Therefore, the same potential is applied to the conductive layer 221 and the conductive layer 223. The opening 237 may not be provided, and different potentials may be applied to the conductive layer 221 and the conductive layer 223. Alternatively, the conductive layer 221 may be used as a light-shielding film without providing the opening 237. For example, By forming the conductive layer 221 from a light-shielding material, the channel forming region 231i is This can suppress light from below that is projected.

[0288] As shown in FIGS. 29(B) and 29(C), the semiconductor layer 231 functions as a first gate. and a conductive layer 223 having a function as a second gate. and is sandwiched between two conductive layers that function as gates.

[0289] The transistor 200f is also connected to the transistors 200a, 200b, and The transistor 200c has an s-channel structure. As a result, the semiconductor layer 231 included in the transistor 200f functions as a first gate. The conductive layer 221 having the function of the second gate and the conductive layer 223 having the function of the second gate are electrically connected. It can be electrically surrounded by

[0290] The transistor 200f has an s-channel structure, and therefore the conductive layer 221 The electric field for inducing a channel is effectively applied to the semiconductor layer 231 by the electric layer 223. This improves the current driving capability of the transistor 200f, resulting in a high on-state current. It is also possible to increase the on-current, which allows The transistor 200f can be miniaturized. The conductor layer 231 has a structure surrounded by the conductive layer 221 and the conductive layer 223. Therefore, the mechanical strength of the transistor 200f can be increased.

[0291] The transistor 200f can be determined by the position of the conductive layer 223 relative to the semiconductor layer 231 or the The method of forming the conductive layer 223 is TGSA (Top Gate Self Aligned). It may also be called a type FET.

[0292] In the transistor 200f, similarly to the transistor 200b, the semiconductor layer 231 It may be configured by laminating two or more layers.

[0293] In the transistor 200f, the insulating layer 212 is formed only in a portion overlapping with the conductive layer 223. However, the present invention is not limited to this, and the insulating layer 212 may have a configuration in which the semiconductor layer 231 is covered. Alternatively, the conductive layer 221 may not be provided.

[0294] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh.

[0295] (Embodiment 3) In this embodiment, a polycrystalline silicon film that can be used for a semiconductor layer of a transistor is An example of a crystallization method and a laser crystallization apparatus will be described.

[0296] To form a polycrystalline silicon layer with good crystallinity, an amorphous silicon layer is provided on a substrate. It is preferable to crystallize the amorphous silicon layer by irradiating it with laser light. is used as a linear beam, and the substrate is moved while the linear beam is irradiated onto the amorphous silicon layer. In this way, a polycrystalline silicon layer can be formed in a desired region on the substrate.

[0297] The linear beam method has a relatively good throughput. Since the laser beam is irradiated multiple times while moving relatively, the output of the laser beam is The resulting beam profile changes are likely to cause variations in crystallinity. For example, the semiconductor layer crystallized by this method can be used for a transistor in a pixel of a display device. When the image is displayed, random stripes caused by variations in crystallinity may be visible. There is.

[0298] In addition, the length of the linear beam is ideally equal to or greater than the length of one side of the substrate. The length of the system is limited by the output of the laser oscillator and the configuration of the optical system. In substrate processing, it is practical to irradiate the laser by folding it back within the substrate surface. The crystallinity of this region is different from that of the other regions. Since the crystallinity is easily different, display irregularities may occur in this region.

[0299] In order to prevent the above problems, a laser is locally applied to an amorphous silicon layer formed on a substrate. Local laser irradiation can be used to crystallize the material. A polycrystalline silicon layer can be easily formed.

[0300] FIG. 30(A) shows a method of locally irradiating an amorphous silicon layer formed on a substrate with laser. FIG.

[0301] The laser beam 826 emitted from the optical system unit 821 is reflected by the mirror 822. The laser light 826 is incident on the microlens array 823. The light is focused to form a plurality of laser beams 827 .

[0302] A substrate 830 on which an amorphous silicon layer 840 is formed is fixed to the stage 815. By irradiating the polycrystalline silicon layer 840 with a plurality of laser beams 827, a plurality of polycrystalline silicon The insulating layer 841 can be formed at the same time.

[0303] The individual microlenses of the microlens array 823 are arranged at the same pitch as the pixels of the display device. Alternatively, they may be provided at intervals that are an integral multiple of the pixel pitch. In any case, laser irradiation and movement of the stage 815 in the X or Y direction are repeated. By returning the polycrystalline silicon layer to the substrate, it is possible to form a polycrystalline silicon layer in the area corresponding to all the pixels.

[0304] For example, if the microlens array 823 has a pixel pitch of M rows and N columns (M and N are natural numbers), When a lens is used, laser light is first irradiated at a predetermined starting position, and a polycrystalline silicon with M rows and N columns is formed. Then, the layer 841 is moved in the row direction by a distance of N columns. Laser light is irradiated to form polycrystalline silicon layers 841 of M rows and N columns. N columns of polycrystalline silicon layers 841 can be formed. By repeating this process, A plurality of polycrystalline silicon layers 841 can be formed in desired areas. When performing the laser irradiation process, the laser is irradiated by moving the wafer by a distance of N columns in the row direction. Furthermore, the movement in the column direction by a distance of M rows and the irradiation of the laser light may be repeated.

[0305] If the oscillation frequency of the laser light and the moving speed of the stage 815 are adjusted appropriately, Even if the laser irradiation is performed while moving the 815 in one direction, the polycrystalline silicon A thin film layer can be formed.

[0306] The size of the laser beam 827 is set to, for example, the size of the laser beam 827 that includes the entire semiconductor layer of one transistor. Alternatively, the entire channel formation region of one transistor can be formed in an area of ​​about 1000 μm. Alternatively, the area can be set to a value that includes the channel forming region of one transistor. These can be made to have an area that includes a part of the required transistor. The appropriate one can be selected depending on the electrical characteristics of the device.

[0307] In the case of a display device having a plurality of transistors in one pixel, The size of the module 827 is large enough to include the entire semiconductor layer of each transistor in one pixel. The size of the laser beam 827 can be determined by the number of pixels. The area may be large enough to include the entire semiconductor layer of the transistor.

[0308] As shown in FIG. 31(A), between the mirror 822 and the microlens array 823 A mask 824 may be provided. The mask 824 has a plurality of apertures corresponding to the respective microlenses. The shape of the opening can be reflected in the shape of the laser beam 827. When the mask 824 has a circular opening as shown in FIG. 31(A), a circular laser beam is In addition, when the mask 824 has a rectangular opening, a rectangular The mask 824 can be, for example, a mask of a transistor. This is effective when it is desired to crystallize only the channel forming region. As shown in FIG. 31(B), it may be provided between the optical system unit 821 and the mirror 822.

[0309] FIG. 30(B) shows a laser crystal that can be used in the local laser irradiation process described above. FIG. 1 is a perspective view illustrating the main configuration of the laser crystallization device. The components include a moving mechanism 812, a moving mechanism 813, and a stage 815. A laser oscillator 820 for shaping a laser beam 827, an optical system unit 821, a mirror 822 and a microlens array 823.

[0310] The moving mechanism 812 and the moving mechanism 813 have the function of performing a reciprocating linear motion in the horizontal direction. The mechanism for powering the moving mechanism 812 and the moving mechanism 813 may be, for example, a motor-driven mechanism. A ball screw mechanism 816 that moves the moving mechanism 812 can be used. Since the movement directions of the stages 813 are perpendicular to each other, the stages fixed to the movement mechanism 813 815 can be freely moved in the X and Y directions.

[0311] The stage 815 has a fixing mechanism such as a vacuum suction mechanism, and can fix the substrate 830 etc. The stage 815 may also have a heating mechanism as needed. Although not shown, the stage 815 has a pusher pin and its up / down mechanism, and When carrying in or out the substrate 830, the substrate 830 can be moved up or down.

[0312] The laser oscillator 820 is only required to output light of a wavelength and intensity suitable for the purpose of processing. A CW laser is preferred, but a CW laser is also acceptable. Excimer lasers capable of emitting ultraviolet light such as 3 nm (XeF) and 308 nm (XeCl) Alternatively, a solid-state laser (YAG laser, fiber laser, etc.) can be used. Uses double waves (515nm, 532nm, etc.) or triple waves (343nm, 355nm, etc.) There may be a plurality of laser oscillators 820.

[0313] The optical system unit 821 includes, for example, a mirror, a beam expander, a beam homogenizer, etc. The laser oscillator 820 outputs a laser beam 825 having a uniform energy distribution in the plane. It can be unified and stretched.

[0314] The mirror 822 may be, for example, a dielectric multilayer mirror, and the incident angle of the laser beam may be adjusted. The microlens array 823 is installed so that the angle is approximately 45°. The shape may be such that a plurality of convex lenses are provided on the top surface or on the upper and lower surfaces.

[0315] By using the above laser crystallization apparatus, polycrystalline silicon with little variation in crystallinity can be produced. A layer can be formed.

[0316] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0317] (Fourth embodiment) Below, a CAC-OS transistor that can be used in a transistor disclosed in one embodiment of the present invention will be described. The configuration will be explained.

[0318] CAC-OS is, for example, a metal oxide in which the elements constituting the metal oxide are 0.5 nm or more and 10 nm or less. Preferably, a material unevenly distributed in a size of 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, we will consider the case where one or more metal elements are unevenly distributed in a metal oxide. The region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more. The mixed state of particles with sizes of 2 nm or less or close to that size is also called a mosaic or patch state. say.

[0319] The metal oxide preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Sodium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, gel Al, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, It contains one or more selected from the group consisting of tantalum, tungsten, and magnesium. It may be possible.

[0320] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) ), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z1 and Z2 are real numbers greater than 0.) The material is separated into mosaics. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0321] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite metal oxide having a mixed structure with a region in which In this specification, for example, when the atomic ratio of In to the element M in the first region is , the atomic ratio of In to the element M in the second region is greater than the atomic ratio of In in the first region. The concentration of In is higher than in the region

[0322] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0323] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0324] On the other hand, CAC-OS is a material structure of metal oxide. In a material composition containing Zn and O, nanoparticles with Ga as the main component were observed in some areas. The region where In is observed as a nanoparticle and the region where In is observed as a nanoparticle are the main component are shown in the model. Therefore, in CAC-OS, the crystal structure Construction is a secondary element.

[0325] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0326] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0327] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements from the group consisting of sodium, etc. are included, CAC-OS will The region observed is a nanoparticle with the metal element as the main component, and a nanoparticle with In as the main component in part. The structure is such that the areas observed as particles and the areas observed as particles are randomly dispersed in a mosaic pattern. cormorant.

[0328] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0329] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction, the measurement region It can be seen that no orientation in the ab plane direction or the c axis direction is observed.

[0330] In addition, the CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the Therefore, the electron diffraction pattern indicates that CAC-OS The crystal structure is nc (nano-c) which has no orientation in the plane direction and cross-sectional direction. It can be seen that it has a crystal structure.

[0331] For example, in the case of CAC-OS, an In-Ga-Zn oxide, energy dispersive X-ray Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using a copy of the GaO X3 The region where is the principal component and , In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed. It can be confirmed that it has the structure shown in the figure.

[0332] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main components are In X2 Zn Y2 O Z2 , or InO X1 The area where is the principal component and It has a phase-separated structure with a mosaic of regions each consisting mainly of one element.

[0333] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This is a region with high conductivity compared to the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The carriers flow through the area where the main component is the metal oxide. Therefore, the conductivity of In is expressed as a crystalline oxide. X2 Zn Y2 O Z2 , or InO X1 but The main component is distributed in a cloud-like pattern in the metal oxide, resulting in high field-effect mobility. (μ) can be realized.

[0334] On the other hand, GaO X3 The region where In etc. are the main components is X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 etc. are the main components The distribution of these regions in the metal oxide suppresses leakage current and provides good switching performance. This allows for realizing a smoothing operation.

[0335] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 and insulation due to I n X2 Zn Y2 OZ2 , or InO X1 The conductivity caused by the This allows for a high on-state current (I on ) and high field-effect mobility (μ). Cut.

[0336] Furthermore, semiconductor devices using CAC-OS are highly reliable. It is ideal for a variety of semiconductor devices, including displays.

[0337] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0338] (Embodiment 5) In this embodiment mode, another structural example of the display device described in the above embodiment mode will be described.

[0339] 32 shows an example of the configuration of the display device 10. The display device 10 is a display device provided on a substrate 14. The display unit 17 includes a plurality of pixels 11 connected to the wiring GL and the wiring SL. Has.

[0340] The display device 10 also includes a plurality of TABs (Tape Automated Bonding g) A tape 121a and a plurality of TAB tapes 121b are provided. The TAB tape 121a and the TAB tape 121b are provided at positions facing each other with the display unit 17 in between. An integrated circuit including a gate driver 12a and the like is mounted on the TAB tape 121a. The TAB tape 121b has an integrated circuit formed with a gate driver 12b and the like. The gate driver 12a and the gate driver 12b are connected to a plurality of wirings GL. The line GL is connected to the gate electrode GL and has a function of supplying a selection signal to the line GL.

[0341] The display device 10 also includes a plurality of printed circuit boards 131a and a plurality of TAB tapes 132. a, and a plurality of printed circuit boards 131b and a plurality of TAB tapes 132b are provided. The printed circuit board 131a and the TAB tape 132a are provided. The TAB tape 132b and the display unit 17 are disposed opposite each other. There are.

[0342] The printed circuit boards 131a are connected to a plurality of TAB tapes 132a, and receive input from the outside. The printed circuit board 131b has the function of distributing the received signal to the TAB tape 132a. Each of them is connected to a plurality of TAB tapes 132b, and the externally input signal is transmitted to the TAB tape The TAB tape 132a has a function of distributing the signals to the source driver 132b. The TAB tape 132b is provided with an integrated circuit having a source driver 3a and the like. The integrated circuit on which the source driver 13a and the source driver 13b are formed is mounted. The switch driver 13b is connected to a plurality of wirings SL and has the function of supplying signals to the wirings SL. Has.

[0343] When manufacturing a large-screen display panel that can handle 2K, 4K, and 8K broadcasts, etc., In this way, a plurality of printed circuit boards 131a and a plurality of printed circuit boards 131b can be provided. This is preferable. This makes it possible to easily input image data to the display device 10.

[0344] The gate driver 12a, the gate driver 12b, the source driver 13a, and the The base driver 13b is a COG (Chip On Glass) type, COF (Chip It can also be provided on the substrate 14 by a method such as an On Film method.

[0345] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0346] (Embodiment 6) In this embodiment, an electronic device of one embodiment of the present invention will be described with reference to drawings.

[0347] The electronic devices exemplified below have a display device according to one embodiment of the present invention in their display portions. Therefore, it is an electronic device that has achieved high resolution. The electronic device may be a stand-alone electronic device.

[0348] The display unit of the electronic device according to one embodiment of the present invention may include, for example, full high-definition, 4K2K, 8K4K , 16K, 8K, or higher resolution images can be displayed. The display screen size must be 20 inches or more diagonally, or 30 inches or more diagonally, or It can be 50 inches or more diagonal, 60 inches or more diagonal, or 70 inches or more diagonal. do.

[0349] Examples of electronic devices include television sets, desktop or notebook PCs, etc. Personal computers, computer monitors, digital signage Signage: Digital signage, large game machines such as pachinko machines, etc. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, Examples of such devices include mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0350] The electronic device or lighting device according to one embodiment of the present invention can be applied to an interior or exterior wall of a house or building, or Alternatively, it can be incorporated along the curved surfaces of the interior or exterior of the automobile.

[0351] The electronic device according to one embodiment of the present invention may include an antenna. This allows the display of images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0352] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.). , distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared radiation) It may be possible.

[0353] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar - Functions to display date or time, etc., and functions to run various software (programs) functions, wireless communication functions, functions to read programs or data recorded on recording media, etc. can have:

[0354] An example of a television device is shown in FIG. 33A. The television device 7100 includes a housing 71 The display unit 7000 is built into the housing 71. This shows a configuration that supports 01.

[0355] The display device of one embodiment of the present invention can be applied to the display portion 7000. The revision device 7100 can display high-resolution images. The mobile device 7100 can display high-resolution images on a large screen.

[0356] The television set 7100 shown in FIG. 33A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or the display unit 700. The display unit 7000 may be provided with a touch sensor, and the operation may be performed by touching the display unit 7000 with a finger or the like. The remote control unit 7111 displays the information output from the remote control unit 7111. The remote control 7111 may have a display unit for displaying the operation keys or touch screen. The panel allows you to operate the channel and volume, and the information displayed on the display unit 7000 You can control the video that is displayed.

[0357] The television device 7100 includes a receiver, a modem, and the like. It is also possible to receive general television broadcasts via wired or wireless connection via a modem. By connecting to a wired communication network, it can be transmitted in one direction (sender to receiver) or two directions. It is also possible to communicate information in two directions (between a sender and a receiver, or between receivers, etc.). .

[0358] FIG. 33B shows a notebook personal computer 7200. The computer 7200 includes a housing 7211, a keyboard 7212, a pointing device The housing 7211 has a display unit 7000 and an external connection port 7213. It is included.

[0359] The display device of one embodiment of the present invention can be applied to the display portion 7000. The portable personal computer 7200 is capable of displaying high-resolution images. The notebook personal computer 7200 can display high-resolution images on a large screen. This can be done.

[0360] Figure 33(C) and (D) show the digital signage. An example of a sign is shown below.

[0361] The digital signage 7300 shown in FIG. 33C includes a housing 7301, a display unit 7000, and and speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0362] FIG. 33(D) shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit 7 provided along the curved surface of a pillar 7401. 000.

[0363] 33C and 33D, the display device of one embodiment of the present invention is applied to the display portion 7000. This allows the Digital Signage 7300 and Digital Signage 7 The 400 is capable of displaying high-resolution images. The 7300 is also capable of displaying high-resolution images. The Digital Signage 7400 can display high-resolution images on a large screen. .

[0364] The larger the display unit 7000, the more information can be displayed at once. The wider the part 7000, the more noticeable it is, and for example, the more effective the advertisement. Cut.

[0365] By applying a touch panel to the display unit 7000, images or videos can be displayed on the display unit 7000. It is also preferable because it not only shows route information but also allows users to operate it intuitively. When used to provide information such as traffic information, the user can operate the device intuitively. This can improve accessibility.

[0366] Also, as shown in Figures 33(C) and (D), Digital Signage 7300 or Digital The signage 7400 is an information terminal 7311 such as a smartphone carried by a user or It is preferable that the display unit 7411 can be connected to the information terminal 7411 by wireless communication. The advertisement information displayed on 000 is displayed on the screen of the information terminal 7311 or the information terminal 7411. In addition, the information terminal 7311 or the information terminal 7411 can be operated. By doing so, the display on the display unit 7000 can be switched.

[0367] In addition, the digital signage 7300 or the digital signage 7400 is equipped with an information terminal 7 311 or the screen of the information terminal 7411 is used as a control means (controller) to play games. This allows an unspecified number of users to participate in the game at the same time and enjoy it. It is possible.

[0368] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination. [Example]

[0369] In this embodiment, an 8K4K liquid crystal display having a pixel area of ​​65 inches diagonal is used. Explains the results of an estimate of the data writing time for LCD display modules. do.

[0370] In particular, in this embodiment, hydrogenated amorphous silicon (a-Si) is used as the semiconductor layer of the transistor. :H) by applying one embodiment of the present invention, a large-scale and high-resolution display I checked to see if I could get it to work.

[0371] The resolution of an 8K4K display is 7680 horizontally and 4320 vertically. , which is an extremely high resolution. In addition, Rec There is a recommendation ITU-R BT.2020-2. In this standard, The driving method is progressive, and the frame frequency is said to be up to 120Hz.

[0372] High-resolution, large-sized display modules using low field-effect mobility transistors In this case, the image rewriting operation may not be completed in time during the frame period, making it impossible to drive the device. At this time, the pixel area is divided into a plurality of areas (for example, four areas), and each area is provided with a scanning line driving circuit (gate A signal line driver circuit (also called a source driver) and a signal line driver circuit (also called a source driver) are arranged in the This configuration allows images to be rewritten simultaneously in multiple pixel regions. Therefore, even when a transistor with low field effect mobility is used, This allows for image rewriting.

[0373] However, in a configuration in which the pixel area is divided, I Increased costs due to the increase in C and associated materials, and a decrease in aperture ratio due to an increase in the number of wiring Below: Increased frame area due to IC implementation, and a circuit for synchronizing the divided pixel areas and the boundary between the divided pixel regions is visible. There are concerns about the deterioration of image quality. This raises concerns that a high-speed, large-scale image processing circuit will be required.

[0374] Therefore, in this embodiment, a selection signal is supplied to each gate line, and pixels are selected one by one. In addition to this configuration, a selection signal is simultaneously supplied to two or four gate lines, and adjacent gate lines in the column direction are We investigated a configuration in which two or four pixels are selected simultaneously. In each column, four pixels are connected to different source lines. In this embodiment, the pixel layout in this configuration is used. We then estimated the data writing time.

[0375] In this embodiment, hydrogenated amorphous silicon is used for the semiconductor layer of the transistor. The cases of using a metal oxide and a metal oxide were investigated.

[0376] When hydrogenated amorphous silicon is used for the semiconductor layer, microcrystalline silicon is used. The field-effect mobility, which is a design parameter, was changed based on the actual measurement values ​​of the transistors fabricated by this method. The data write time was estimated using the pseudo parameters.

[0377] Regarding the semiconductor layer using metal oxide, the following two types of structures were investigated. The first type is an In-Ga-Zn oxide, which is composed of In, Ga, and Zn atoms. A single layer of metal oxide with a numerical ratio of In:Ga:Zn=1:1:1 or close to it is used as a semiconductor layer. The second type is when the atomic ratio of In, Ga, and Zn is In:Ga:Z. This is the case when metal oxides with n=4:2:3 or close thereto are used in a laminated semiconductor layer. Specifically, the first metal oxide layer is formed of CAC-OS (Cloud-Aligned Co- A second metal oxide semiconductor (MOX) film was used. CAAC-OS (c-axis-aligned crystalline o The case where a silicon oxide semiconductor film is used is assumed.

[0378] The parameters of each layer used in this example are shown in Table 1. These are the parameters for the semiconductor layer made of metal oxide. These are parameters assuming a transistor with a hydrogenated amorphous silicon. Similar parameters were used when using a con for the semiconductor layer.

[0379] [Table 1]

[0380] <When pixels are selected one by one> FIG. 34(A) is a block diagram showing the configuration of the display module used in this example. In this configuration, a selection signal is supplied to each gate line, and pixels are selected one by one. The gate driver and source driver are both external. The same signal is sent from the Gate Driver IC (External) The source line is connected to one source driver IC (Source Driver The signal is supplied from an IC (External). The pixel area is not divided. The size of the element area is 65 inches diagonally, and the number of effective pixels is 7680 x RGB(H) x 432 0(V).

[0381] FIG. 34(B) shows a circuit diagram of pixel PIX(i,j). The gate of the transistor M1 is connected to a capacitor C1 and a liquid crystal element LC. is connected to the gate line GL(i). One of them is connected to the source line SL(j), and the other is connected to one electrode of the capacitance element C1, and The other electrode of the capacitance element C1 is connected to the wiring CS The other electrode of the liquid crystal element LC is connected to the wiring TCOM. .

[0382] Figures 35(A) and (B) show the image of the display module when the pixels are selected one by one. FIG. 35(A) shows the stacked structure from the gate line GL(i) to the pixel electrode. 35(B) is a top view of the pixel electrode (P This is a top view excluding the tungsten ion beam electrode.

[0383] The pixel size is 62.5 μm × 187.5 μm. The transistor M1 is a bottom gate It is a channel-etched transistor with a top contact structure. The channel length L is 4 μm, the channel width W is 8 μm, and the LDD region overlapping the gate (hereinafter referred to as the over -Lap LDD area L ov The width of the gate line GL(i) is 10 μm, and the wiring The width of the CSCOM is 3.5 μm. The width of the source line SL(j) is 10 μm. At the crossing points with the wiring (gate line GL(i) and wiring CSCOM), the opening is 4 μm. The rate is 45.6%.

[0384] First, using Figure 36, we will roughly estimate the data write time when metal oxide is used for the semiconductor layer. This article explains:

[0385] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 35(A) and the field effect of the transistor is calculated. By varying only the parameter of the effective mobility, the charging time of the gate line and the source line of the pixel can be In this example, the data writing time is the time required for the gate line This corresponds to the total charging time of the source line and the pixel. The gate line charging time is the time when the gate line potential reaches 75% of the maximum input voltage. The charging time of the source line and the pixel is the time until the potential of the source line reaches the maximum of the input voltage. The time it takes to reach 99% of the value.

[0386] In addition, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=4:2:3. The field-effect mobility when a metal oxide or a metal oxide in the vicinity is used as a semiconductor layer in a stacked configuration is taken as 1. The normalized value (normalized mobility) was used. The size of the transistor was not changed. The load of the entire area is as follows: The parasitic resistance Rgl of the gate line is 3.60 kΩ ,The parasitic capacitance Cgl of the gate line is 255pF, and the parasitic resistance Rsl of the source line is 5.80kΩ. The parasitic capacitance Csl of the source line is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF. In this embodiment, the parasitic capacitance Cpix of the pixel is the storage capacitance of the capacitive element, the capacitance of the liquid crystal element, The capacitance of the node A includes the capacitance of the node B and the parasitic capacitance of the node A. In each pixel, a source or a drain of a transistor, one electrode of a capacitor, and This is a node to which one electrode of the liquid crystal element is connected.

[0387] In FIG. 36, the normalized mobility is 1 when the atomic ratio of In, Ga, and Zn is In When a metal oxide having a ratio of Ga:Zn=4:2:3 or a similar ratio is used as a semiconductor layer, This corresponds to the case where the data is written (indicated as "CAC\CAAC" in Figure 36). The horizontal period is 3.55 μs, which is shorter than the 3.85 μs of one horizontal period at 60 Hz. It was estimated that the data writing time was 120 Hz drive, one horizontal period is longer than 1.93 μs, so it is difficult to operate at 120 Hz drive. was estimated.

[0388] In FIG. 36, the normalized mobility of 0.5 is obtained when the atomic ratio of In, Ga, and Zn is A single layer of metal oxide with In:Ga:Zn=1:1:1 or a similar ratio is used as the semiconductor layer. This corresponds to the case where data is written to the IGZO (111) (shown as "IGZO (111)" in Figure 36). The loading time is 4.17 μs, which is longer than one horizontal period of 3.85 μs at 60 Hz. It was estimated that it would be difficult to operate at not only 120Hz but also 60Hz.

[0389] Next, using FIG. 37, data for hydrogenated amorphous silicon used in the semiconductor layer will be described. The following explains the rough calculation of the writing time.

[0390] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 35(A) and the microcrystalline silicon is used. The field-effect mobility, which is a design parameter, was changed based on the actual measurement values ​​of the transistors fabricated by this method. By doing so, we were able to roughly calculate the charging time of the gate line of the pixel and the charging time of the source line and pixel. The size of the transistor and the magnitude of the storage capacitance were not changed. When silicon is used for the semiconductor layer, larger transistor size and storage capacitance are required. Therefore, the data writing time must be longer than that in this example. The load of the entire area is as follows: The parasitic resistance Rgl of the gate line is 3.60 kΩ, The parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, The parasitic capacitance of the source line Csl is 147 pF, and the parasitic capacitance of the pixel Cpix is ​​216.6 fF. .

[0391] In FIG. 37, the field-effect mobility is 0.6, 0.7, and 0.8 cm 2 / Vs] results are This corresponds to the case where hydrogenated amorphous silicon is used for the semiconductor layer. The loading times are 19.66 μs, 16.19 μs, and 13.81 μs, respectively. 1 horizontal period is 1.93 μs at Hz driving and 3.85 μs at 60 Hz driving. It was estimated that it would be difficult to operate at 60Hz as well as 120Hz. .

[0392] <When two pixels are selected at the same time> FIG. 38(A) is a block diagram showing the configuration of the display module used in this example. In this configuration, a selection signal is supplied to two gate lines at the same time, and adjacent pixels in the column direction are selected. are selected simultaneously. Both the gate driver and source driver are external. The same signal is supplied to the gate lines from two gate driver ICs. i) is electrically connected to the gate line GL(i) and the gate line GL(i+1), The pixels in the i-th and (i+1)-th rows are driven simultaneously. The signal is supplied from the driver IC. The pixel area is not divided. The size of the pixel area is It is 65 inches square and has an effective pixel count of 7680 x RGB (H) x 4320 (V).

[0393] FIG. 38B shows a circuit diagram of pixel PIX(i,j) and pixel PIX(i+1,j). .

[0394] First, the configuration of pixel PIX(i,j) will be described. The gate of transistor M1 is connected to , connected to the gate line GL(i). One of them is connected to the source line SL1(j), and the other is connected to one electrode of the capacitance element C1, and The other electrode of the capacitance element C1 is connected to the wiring CS The other electrode of the liquid crystal element LC is connected to the wiring TCOM. .

[0395] Next, the configuration of pixel PIX(i+1,j) will be described. , a transistor M2, a capacitance element C2, and a liquid crystal element LC. The gate of the transistor M2 is connected to the gate line GL(i+1). One of the drains is connected to the source line SL2(j), and the other is connected to one of the capacitance elements C2. The other electrode of the capacitance element C2 is connected to the electrode of the capacitance element C1 and one of the electrodes of the liquid crystal element LC. The other electrode of the liquid crystal element LC is connected to the wiring TCOM. It continues.

[0396] Figures 39(A) and (B) show the display module when two pixels are selected simultaneously. The pixel layout is shown in FIG. 39(A). The stacked structure from the gate line GL(i) to the pixel electrode is shown in FIG. FIG. 39(B) is a top view of the structure seen from the pixel electrode side. FIG.

[0397] The pixel size is 62.5 μm × 187.5 μm. The transistor M1 is a bottom gate It is a channel-etched transistor with a top contact structure. The channel length L is 4 μm, the channel width W is 8 μm, and the overlap LDD region L ov is 2 μm The width of the gate line GL(i) is 10 μm, and the width of the wiring CSCOM is 3.5 μm. The width of the source line SL1(j) and the source line SL2(j) is both 10 μm. The cross section with the gate line is 4 μm in both cases, and the aperture ratio is 37.3%.

[0398] First, using Figure 40, we will roughly estimate the data write time when metal oxide is used for the semiconductor layer. This article explains:

[0399] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 39(A) and the field effect of the transistor is calculated. By varying only the parameter of the effective mobility, the charging time of the gate line and the source line of the pixel can be The charge time of the pixel was estimated. Here, the atomic ratio of In, Ga, and Zn was In: When metal oxides with Ga:Zn=4:2:3 or similar are used as the semiconductor layer The field-effect mobility of the transistor was normalized to 1 (normalized mobility). The load on the entire pixel area is as follows: Gate line parasitic The resistance Rgl is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 364 pF, and the parasitic resistance of the source line is Resistance Rsl is 4.83kΩ, parasitic capacitance Csl of the source line is 182pF, and parasitic capacitance Cp ix is ​​191fF.

[0400] In FIG. 40, the normalized mobility is 1.0 when the atomic ratio of In, Ga, and Zn is In When a metal oxide having a ratio of Ga:Zn=4:2:3 or a similar ratio is used as a semiconductor layer, This corresponds to the case where the data is written (indicated as "CAC\CAAC" in Figure 40). The horizontal period is 3.49 μs, which is shorter than the 3.83 μs of one horizontal period at 120 Hz. It was estimated that it could operate at 0Hz.

[0401] In FIG. 40, the normalized mobility of 0.5 is obtained when the atomic ratio of In, Ga, and Zn is A single layer of metal oxide with In:Ga:Zn=1:1:1 or a similar ratio is used as the semiconductor layer. This corresponds to the case where data is written to the IGZO (111) (shown as "IGZO (111)" in Figure 40). The loading time is 4.02 μs, which is shorter than the horizontal period of 7.66 μs at 60 Hz. It is estimated that it can operate at 60Hz. The data writing time is One horizontal period is longer than 3.83 μs at 120 Hz, making it difficult to operate at 120 Hz. It was estimated that.

[0402] In FIG. 40, the same selection signal is supplied to two gate lines, so the length of one horizontal period is This allows for a double increase in the field-effect mobility compared to 36. This makes it easier to operate high resolution displays.

[0403] From the results of Figures 36 and 40, when CAC\CAAC is used in the semiconductor layer, Operation at 120Hz, which was difficult with a configuration that writes to two pixels simultaneously, can now be achieved. It was shown that this can be achieved by configuring it to be written.

[0404] 36 and 40, when IGZO(111) is used as the semiconductor layer, Operation at 60Hz, which was difficult with a configuration that writes to each pixel individually, can now be achieved with two pixels. It was shown that this can be achieved by configuring simultaneous writing.

[0405] Next, using Figure 41, we will explain the data when hydrogenated amorphous silicon is used for the semiconductor layer. The following explains the rough calculation of the writing time.

[0406] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 39(A) and the microcrystalline silicon is used. The field-effect mobility, which is a design parameter, was changed based on the actual measurement values ​​of the transistors fabricated by this method. By doing so, we were able to roughly calculate the charging time of the gate line of the pixel and the charging time of the source line and pixel. The size of the transistor and the size of the storage capacitor have not changed. The parasitic resistance of the gate line Rgl is 3.60 kΩ, and the parasitic capacitance of the gate line C gl is 364pF, the parasitic resistance of the source line Rsl is 4.83kΩ, and the parasitic capacitance of the source line Cs l is 182 pF, and the parasitic capacitance of the pixel Cpix is ​​191 fF.

[0407] In FIG. 41, the field effect mobility is 0.6, 0.7, and 0.8 cm 2 / Vs] results are This corresponds to the case where hydrogenated amorphous silicon is used for the semiconductor layer. The loading times are 17.98μs, 14.89μs, and 12.78μs, respectively. Hz drive, one horizontal period is 3.83 μs, and 60 Hz drive, one horizontal period is 7.66 μs. It was estimated that it would be difficult to operate at 60Hz as well as 120Hz. .

[0408] From the results of Figure 41, when hydrogenated amorphous silicon is used for the semiconductor layer, Unlike the case where a semiconductor layer is used (see the results in Figure 40), two pixels are written simultaneously. Even with the configuration, it was estimated that it would be difficult to operate at 60Hz.

[0409] <When four pixels are selected at the same time> The block diagram showing the configuration of the display module used in this embodiment is a source driver 1. The size of the pixel area is 65mm diagonally. The effective pixel count is 7680 x RGB (H) x 4320 (V). The circuit diagram of the pixel provided in the element area is the same as that of FIG. 7, and the pixel layout is as shown in FIG. 8(A), ( Same as B).

[0410] The pixel size is 62.5 μm × 187.5 μm. The transistors provided in the pixel are: Each is a channel-etched transistor with a bottom-gate top-contact structure. Specifically, the channel length L of each transistor in the pixel is Both are 4 μm, the channel width W is 8 μm, and the overlap LDD region L ov is 3 μm The width of each gate line is 10 μm, the width of each CS line is 5 μm, and the width of each source line is 4 μm. The aperture ratio is 29%.

[0411] First, using Figure 42, we will roughly estimate the data write time when metal oxide is used for the semiconductor layer. This article explains:

[0412] The parasitic resistance and parasitic capacitance are extracted from the pixel layout in Figure 8, and only the mobility parameter is changed. By doing so, the charging time of the gate line of the pixel and the charging time of the source line and pixel were roughly calculated. Here, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=4:2:3 or The field-effect mobility when a metal oxide in the vicinity of the The size of the transistor was not changed. The load on the gate line is as follows: the parasitic resistance Rgl is 3.53 kΩ; The parasitic capacitance Cgl of the source line is 518 pF, the parasitic resistance Rsl of the source line is 10.28 kΩ, The parasitic capacitance Csl of the line is 170 pF, and the parasitic capacitance Cpix of the pixel is 99.7 fF.

[0413] In FIG. 42, the normalized mobility is 1.0 when the atomic ratio of In, Ga, and Zn is In When a metal oxide having a ratio of Ga:Zn=4:2:3 or a similar ratio is used as a semiconductor layer, This corresponds to the case where the data is written (indicated as "CAC\CAAC" in Figure 42). The horizontal period is 5.05 μs, which is shorter than the 7.61 μs of one horizontal period at 120 Hz. It was estimated that it could operate at 0Hz.

[0414] In FIG. 42, the normalized mobility of 0.5 is obtained when the atomic ratio of In, Ga, and Zn is A single layer of metal oxide with In:Ga:Zn=1:1:1 or a similar ratio is used as the semiconductor layer. This corresponds to the case where data is written to the IGZO (111) (shown as "IGZO (111)" in Figure 42). The loading time is 5.22 μs, which is shorter than the horizontal period of 7.61 μs at 120 Hz. It was estimated that it would be possible to operate at 120Hz.

[0415] In FIG. 42, the same selection signal is supplied to four gate lines, so the length of one horizontal period is This allows for a four-fold increase compared to 36. Therefore, it is possible to use transistors with low field-effect mobility. This makes it easier to operate high resolution displays.

[0416] From the results in Figure 42, by using a configuration in which four pixels are written simultaneously, it is possible to achieve a higher performance than CAC\CAAC. Even when IGZO(111), which has a lower mobility than IGZO(111), is used as the semiconductor layer, the It was shown that drive operation can be achieved.

[0417] Next, using Figure 43, we will write data for when hydrogenated amorphous silicon is used for the semiconductor layer. The following explains the approximate writing time.

[0418] The parasitic resistance and parasitic capacitance were extracted from the pixel layout in Figure 8, and the device was fabricated using microcrystalline silicon. By changing the field-effect mobility, which is a design parameter, we were able to obtain the The charging time of the gate line of the pixel and the charging time of the source line and pixel were estimated. The size of the pixel area and the size of the storage capacitor have not been changed. The parasitic resistance Rgl of the gate line is 3.53 kΩ, and the parasitic capacitance Cgl of the gate line is 5 18pF, the parasitic resistance Rsl of the source line is 10.28kΩ, and the parasitic capacitance Csl of the source line is 1 70pF, and the parasitic capacitance of the pixel Cpix is ​​99.7fF.

[0419] In Figure 43, the field effect mobility is 0.6, 0.7, and 0.8 cm 2 / Vs] results are This corresponds to the case where hydrogenated amorphous silicon is used for the semiconductor layer. The loading times are 11.66μs, 10.06μs, and 9.01μs, respectively, and It is estimated that one horizontal period during driving is shorter than 15.3 μs and that it can operate at 60 Hz. The data write time is 7.61μs per horizontal period when driven at 120Hz. It was estimated that it would be difficult to operate at 120Hz for a period longer than 10ms.

[0420] From the results of Figures 37, 41, and 43, it can be seen that hydrogenated amorphous silicon is used for the semiconductor layer. When using a 60Hz drive, applying a configuration that writes to four pixels simultaneously can achieve 60Hz drive. It has been shown that this can be achieved.

[0421] As described above, by applying one embodiment of the present invention, a semiconductor layer of a transistor can be formed using hydrogenated ammonia. Even if we use rufus silicon, we can achieve a 65-inch diagonal display with a resolution of 8K / 4K. , and was estimated to be capable of driving large, high-resolution displays. [Explanation of symbols]

[0422] 10 Display device 11 pixels 12a Gate Driver 12b Gate Driver 13 Source Driver 13a Source Driver 13b Source Driver 14 PCB 15 PCB 16 Reference voltage generation circuit 16a Reference voltage generation circuit 16b Reference voltage generation circuit 17 Display 18a protection circuit 18b Protection circuit 19a protection circuit 19b Protection circuit 20 Liquid crystal element 21 Conductive layer 22 LCD 23 Conductive layer 24a Alignment film 24b Alignment film 26 Insulating layer 30 transistors 31 Conductive layer 31a conductive layer 32 Semiconductor layer 32p semiconductor layer 33 Conductive layer 33a conductive layer 33b Conductive layer 33c conductive layer 34 Insulating layer 35 Impurity semiconductor layer 37 Semiconductor layer 38 Opening 39a Polarizing plate 39b Polarizing plate 41 Colored layer 42 Light blocking layer 50 light 51 Conductive layer 52 Conductive layer 53 Conductive layer 54 Conductive layer 55 Conductive layer 60 Capacitor element 71 Opening 72 Opening 73 Opening 74 Opening 81 Insulating layer 82 Insulating layer 84 Insulating layer 90 Backlight unit 121a TAB tape 121b TAB tape 131a Printed circuit board 131b Printed circuit board 132a TAB tape 132b TAB tape 200a transistor 200b transistor 200c transistor 200d transistor 200e transistor 200f transistor 211 Insulating layer 212 Insulating layer 212a Insulating layer 212b insulating layer 212c Insulating layer 212d Insulating layer 215 Insulating Layer 216 Insulating Layer 216a Insulating layer 221 Conductive layer 222a conductive layer 222a_1 Conductive layer 222a_2 Conductive layer 222a_3 Conductive layer 222b Conductive layer 222b_1 Conductive layer 222b_2 Conductive layer 222b_3 Conductive layer 223 Conductive Layer 224 Insulating Layer 231 Semiconductor layer 231_1 Semiconductor layer 231_2 Semiconductor layer 231d Drain region 231i Channel formation region 231s Source Region 235 Opening 236a opening 236b opening 237 Opening 238a opening 238b opening 812 Moving mechanism 813 Moving mechanism 815 Stage 816 Ball screw mechanism 820 Laser Oscillator 821 Optical Unit 822 Mirror 823 Microlens Array 824 Mask 825 Laser light 826 Laser light 827 Laser Beam 830 board 840 amorphous silicon layer 841 Polycrystalline silicon layer 7000 Display 7100 Television equipment 7101 Housing 7103 Stand 7111 Remote control device 7200 Notebook Personal Computer 7211 Case 7212 keyboard 7213 Pointing Device 7214 External connection port 7300 Digital Signage 7301 Housing 7303 Speaker 7311 Information terminals 7400 Digital Signage 7401 Pillar 7411 Information terminals

Claims

1. A display device comprising a first pixel having a first wiring, a second wiring, and a third wiring, a first transistor, a first conductive layer, a second conductive layer, and a third conductive layer, and a first pixel electrode above a substrate, the first wiring extends in a first direction and intersects with the second wiring and the third wiring; the second wiring and the third wiring each extend in a second direction intersecting the first direction; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring via the first conductive layer, the second conductive layer, and the third conductive layer; the second conductive layer has a region overlapping with the third wiring, the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material and have a region in contact with an upper surface of a first insulating film; the first wiring and the second conductive layer include the same material and have a region in contact with the upper surface of the substrate; a selection signal is supplied to the first wiring; The display device, wherein different signals are supplied to the second wiring and the third wiring.

2. A display device comprising a first pixel having a first wiring, a second wiring, and a third wiring, a first transistor, a first conductive layer, a second conductive layer, and a third conductive layer, and a first pixel electrode above a substrate, the first wiring extends in a first direction and intersects with the second wiring and the third wiring; the second wiring and the third wiring each extend in a second direction intersecting the first direction; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring via the first conductive layer, the second conductive layer, and the third conductive layer; the second conductive layer has a region overlapping with the third wiring, the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material and have a region in contact with an upper surface of a first insulating film; the first wiring and the second conductive layer include the same material and have a region in contact with the upper surface of the substrate; a selection signal is supplied to the first wiring; different signals are supplied to the second wiring and the third wiring, a third wiring having a region located between the first pixel electrode and the second wiring when viewed in a plan view of the first pixel;

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