Flip chip stacking structure and method for forming same - Patents.com

Abstract

To provide a flip chip stacking structure and a method for forming the same.SOLUTION: The present disclosure includes a semiconductor package. The semiconductor package includes a redistribution layer (RDL) having a first surface in contact with an input / output (I / O) contact and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure. The staircase interconnect structure is formed on the second surface of the RDL, and is electrically connected to the RDL. The staircase interconnect structure includes a staircase layer, the staircase layer including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. An integrated circuit (IC) chip is electrically connected to the RDL through the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to the field of semiconductor technology, and more particularly to methods for multi-chip packaging. [Background technology]

[0002] Chip packaging is an important aspect of modern semiconductor miniaturization. Multiple integrated circuits (ICs) are packaged into a single package to achieve homogeneous or heterogeneous chip integration. For example, memory chips and control logic can be integrated into a single package to achieve lower fabrication costs, reduced device footprints, and improved device performance. To address the density limitations in planar memory cells, three-dimensional (3D) memory architectures have been developed. However, as device feature sizes and package sizes approach their lower limits, it becomes increasingly difficult to create a sufficient number of input / output (I / O) contacts, especially for planar or 3D memory chips that address memory bits through arrays of word lines and bit lines. Summary of the Invention [Means for solving the problem]

[0003] The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with an input / output (I / O) contact and a second surface opposite the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected to the RDL. The staircase interconnect structure includes a staircase layer including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer, leaving a remaining portion of the top surface of the first staircase layer exposed. Integrated circuit (IC) chips are electrically connected to the RDL through the staircase interconnect structure. A first of the IC chips is electrically connected to the RDL through a remaining portion of the top surface of the first staircase layer.

[0004] The present disclosure also includes a method for forming a semiconductor packaging structure. The method includes providing a carrier substrate and forming a staircase interconnect structure on the carrier substrate. The step of forming the staircase interconnect structure includes forming a first staircase layer and forming a second staircase layer on an upper surface of the first staircase layer. The second staircase layer covers a portion of the upper surface of the first staircase layer, leaving a remaining portion of the upper surface of the first staircase layer exposed. The method also includes flip-mounting integrated circuit (IC) chips on the carrier substrate and on the staircase interconnect structure. The flip-mounting of the IC chips includes electrically connecting a first IC chip of the IC chips to the first staircase layer through the remaining portion of the upper surface of the first staircase layer. The method also includes replacing the carrier substrate with a redistribution layer (RDL). The method further includes electrically connecting the IC chip to the RDL through the staircase interconnect structure by electrically connecting the first IC chip to the RDL through the remaining portion of the upper surface of the first staircase layer.

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, according to common practice in the industry, various features have not been drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of illustration and discussion. [Brief explanation of the drawings]

[0006] [Figure 1] 1A-1C illustrate an exemplary fabrication process for forming stacked flip chip packages according to some embodiments of the present disclosure. [Figure 2] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 3] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 4] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 5] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 6] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 7] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 8]1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 9] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 10] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 11] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 12] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed at one end of the stacked chips according to some embodiments of the present disclosure. [Figure 13] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed on both ends of the stacked chips according to some embodiments of the present disclosure. [Figure 14] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating stepped interconnect structures formed on both ends of the stacked chips according to some embodiments of the present disclosure. [Figure 15] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating contact pads formed between stepped interconnect structures according to some embodiments of the present disclosure. [Figure 16] 1A-1C are cross-sectional views of stacked flip-chip packages incorporating contact pads formed between stepped interconnect structures according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0007] Illustrative embodiments will now be described with reference to the accompanying drawings, in which like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements.

[0008] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in a variety of other applications.

[0009] It is noted that references herein to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but that not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it will be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0010] Generally, terminology can be understood, at least in part, from usage in context. For example, the term "one or more," as used herein, can be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the," etc., can be understood to convey singular usage or to convey plural usage, again depending, at least in part, on the context.

[0011] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" something, but can also include meaning "on" something with intermediate features or layers between them, and that "above" or "over" can not only mean "above" or "over" something, but can also include meaning it is "above" or "over" something (i.e., directly on) with no intermediate features or layers between them.

[0012] Additionally, spatially relative terms such as "below," "below," "lower," "bottom," "above," "over," "upper," and "top" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures for ease of description. For example, top and bottom surfaces can refer to first and second major surfaces, respectively, formed on opposite sides of an element. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate includes a top surface and a bottom surface. The top surface of the substrate is where semiconductor devices are formed, and thus the semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. Materials added onto the substrate can be patterned or can remain unpatterned. Moreover, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0014] As used herein, the term "layer" refers to a portion of material that includes a region having a predetermined thickness. A layer can extend throughout an underlying or overlying structure, or can have an extension that is less than the extension of the underlying or overlying structure. Furthermore, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal planes between the top and bottom surfaces of a continuous structure (or at the top and bottom surfaces). A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (with contacts, interconnect lines, and / or via contacts formed therein) and one or more dielectric layers.

[0015] As used herein, the term "nominal" refers to a desired (or target) value of a characteristic or parameter for a component or process operation that is established during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of interest. Based on a particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0016] As used herein, the term "3D NAND memory device" (referred to herein as "memory device") refers to a semiconductor device that includes vertically oriented strings of 3D NAND memory cell transistors (referred to herein as "memory strings", e.g., NAND strings or 3D NAND strings, etc.) on a laterally oriented substrate, such that the memory strings extend perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of the substrate.

[0017] As used herein, the term "disposed" refers to being formed or otherwise produced or positioned by a process (e.g., depositing, attaching, or placing, etc.).

[0018] In this disclosure, the term "horizontal / horizontally" means nominally parallel to the lateral surfaces of the substrate.

[0019] Integrated circuit packaging is often the final stage of semiconductor device fabrication. Multiple integrated circuits (e.g., chips) are packaged into a single package to achieve homogeneous or heterogeneous chip integration. Packaging provides protection for the contents enclosed within the package and allows access for power and signals to and from external circuitry. Fan-out packaging technologies, such as Fan-Out Wafer Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP), have been developed to achieve lower manufacturing costs, reduced device footprints, and improved device performance. In the FOWLP process, individual chips are disposed on a wafer-shaped substrate with allocated space between each die for additional input / output (I / O) connection points. The chips are then embedded in a molding compound. A redistribution layer (RDL) is formed to reroute I / O connections on the chip from the molding compound area at the periphery. A dicing saw can separate the chips from the array of completed packages formed on the wafer-shaped substrate to form individual semiconductor packages. However, because a typical large wafer is approximately 300 mm, the amount of semiconductor devices that can be fabricated and packaged on the wafer is limited. The FOPLP process has been developed to provide increased packaging capacity compared to the FOWLP process. In the FOPLP process, chips are arranged on a substrate-level panel rather than a wafer-shaped substrate, increasing packaging capacity. For example, the substrate-level panel can be a square-shaped panel with sides measuring 500 mm or 600 mm.

[0020] For both FOWLP and FOPLP processes, it is becoming increasingly difficult to support the amount of I / O connections for stacked memory devices (e.g., 3D NAND memory chips). As the demand for higher storage capacity continues to increase, the number of vertical levels of memory cells and staircase structures also increases. For example, a 64-level 3D NAND memory device may include two 32-level staircase structures, one formed on top of the other. Similarly, a 128-level 3D NAND memory device may include two 64-level staircase structures. As device critical dimensions continue to shrink, it is becoming increasingly difficult to provide a sufficient amount of I / O connections for memory chips in fan-out packaging.

[0021] Various embodiments described in this disclosure incorporate a stacked staircase interconnect structure for memory chips in fan-out packaging. The stacked staircase interconnect structure can provide electrical connections to each IC chip of the stacked IC chips through pillar bumps formed on each level of the stacked staircase interconnect structure, which increases the number of I / O connection points. The embodiments described herein use fan-out packaging as an example and may also be applied to other packaging technologies.

[0022] FIG. 1 is a flow diagram of a method 100 for fabricating multi-chip packaging incorporating a stepped interconnect structure, according to some embodiments. For illustrative purposes, the operations shown in FIG. 1 will be described with reference to an exemplary fabrication process for fabricating a packaging structure 200 as shown in FIGS. 2-12 and a packaging structure 1300 in FIGS. 13 and 14. The operations may be performed in a different order, or not at all, depending on the particular application. It should be noted that method 100 may not produce a complete semiconductor device. Thus, it is understood that additional processes may be provided before, during, and after method 100, and that some other processes are merely briefly described herein.

[0023] Referring to FIG. 1 , in operation 105, according to some embodiments, contact pads are formed on a carrier substrate. For example, as described with reference to the packaging structure 200 shown in FIG. 2 , contact pads 208 are formed on a carrier substrate 202. For clarity of illustration, FIG. 2 includes various views of the packaging structure 200. For example, FIG. 2 includes a side view 210 and a corresponding top view 220 showing the contact pads 208 and the substrate 202. The contact pads 208 may be disposed in a first package 204 and a second package 206 of the packaging structure 200. The first and second packages 204 and 206 may be separated at a package boundary 205. Additional IC chips may be disposed on the packaging structure 200, which are not shown in FIG. 2 for simplicity. In some embodiments, the IC chips included in the first and second packages 204 and 206 can be the same or different, depending on the device design and desired functionality.

[0024] The carrier substrate 202 can include any suitable material for semiconductor packaging. For example, the substrate carrier can include glass, gallium nitride, gallium arsenide, III-V compounds, glass, plastic sheets, silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), any other suitable material, and / or combinations thereof.

[0025] The contact pads 208 may be formed using a conductive material and may be formed on the top surface of the carrier substrate 202. The contact pads 208 may be subsequently used to form I / O connections. In some embodiments, one or more rows of contact pads 208 may be formed. By way of example, as shown in the plan view 200 of FIG. 2, the first package 204 includes at least three rows of contact pads 208a, 208b, and 208c, while the second package 206 includes at least two rows of contact pads 208c and 208d. In some embodiments, the contact pads 208 may be embedded in the carrier substrate 202, such that the top surfaces of the contact pads 208 and the top surface of the carrier substrate 202 are substantially coplanar. In some embodiments, the contact pads 208 may be formed from tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silver (Ag), gold (Au), doped silicon, silicide, titanium nitride (TiN), tantalum nitride (TaN), any suitable material, and / or combinations thereof. In some embodiments, the contact pads 208 may be disposed by a blanket deposition process, followed by a patterning process. In some embodiments, the contact pads 208 may be disposed from peripheral regions extending toward the center of the first and second packages 204 and 206, as shown in FIG. 2. In some embodiments (not shown in FIG. 2), the contact pads 208 may be formed in central regions of the first and second packages 204 and 206. In some embodiments, the contact pads 208 may be formed in the peripheral region of the first package 204 and in the central region of the second package 206. In some embodiments, the contact pads 208 may be disposed using deposition techniques, including, but not limited to, chemical vapor deposition (CVD), flowable CVD (FCVD), sputtering, metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), high density plasma (HDP), any suitable deposition technique, and / or combinations thereof.

[0026] 1 , in operation 110, according to some embodiments, a dielectric layer and a blocking layer are formed on a carrier substrate 202. For example, as shown in FIG. 3 , a dielectric layer 310 and a blocking layer 314 may be formed on a carrier substrate 202 in the first package 204 and the second package 206 of the packaging structure 200.

[0027] The dielectric layer 310 may be disposed by blanket depositing a dielectric material over the carrier substrate 202 (including over the top surface of the carrier substrate 202 and over the exposed surfaces of the contact pads 208). A patterning process may be used to remove portions of the blanket-deposited dielectric material so that the remaining portions of the dielectric material can form the dielectric layer 310. In some embodiments, the dielectric layer 310 may be formed from an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, any suitable insulating material, and / or combinations thereof, etc.). In some embodiments, disposing the dielectric layer 310 may include any suitable deposition technique, including, but not limited to, CVD, FCVD, sputtering, MOCVD, PECVD, LPCVD, PVD, HDP, any suitable deposition technique, and / or combinations thereof.

[0028] The blocking layer 314 may be disposed on the top surfaces of the carrier substrate 202 and the contact pads 208 between the dielectric layers 310. In some embodiments, the blocking layer 314 may be disposed by blanket depositing a dielectric material over the dielectric layer 310, the top surface of the carrier substrate 202, and the exposed surfaces (e.g., top surface and sidewalls) of the contact pads 208. A patterning or polishing process may be performed such that the deposited material remains between adjacent dielectric layers 310, and the top surfaces of the blocking layer 314 and the dielectric layer 310 are substantially planar. For example, a chemical mechanical polishing (CMP) process may be used. In some embodiments, the blocking layer 314 and the dielectric layer 310 are formed of different materials. For example, the blocking layer 314 and the dielectric layer 310 may be disposed using materials that have high etch selectivities (e.g., greater than about 10) relative to one another. For example, the blocking layer 314 may be formed using silicon oxide, and the dielectric layer 310 may be formed using silicon oxynitride. In some embodiments, the blocking layer 314 may be formed from an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, any suitable insulating material, and / or combinations thereof, etc.). In some embodiments, the deposition process of the blocking layer 314 may include any suitable deposition technique, including, but not limited to, CVD, FCVD, sputtering, MOCVD, PECVD, LPCVD, PVD, HDP, any suitable deposition technique, and / or combinations thereof. In some embodiments, the blocking layer 314 may be formed from a photoresist material and deposited by a spin-on process. In some embodiments, an annealing process may be applied to the deposited photoresist material to enhance its physical durability.

[0029] 1, in operation 115, according to some embodiments, a first stepped layer of vertical interconnects are formed in a dielectric layer. For example, as shown in FIG. 4, vertical interconnects 418 may be disposed in dielectric layer 310 in first package 204 and second package 206 of packaging structure 200.

[0030] The vertical interconnects 418 can be conductive lines that are disposed by etching openings in the dielectric layer 310 and depositing a conductive material in the openings. In some embodiments, the vertical interconnects 418 can be disposed by a damascene process or a dual damascene process. In some embodiments, the vertical interconnects 418 can be formed from a conductive material (e.g., copper, cobalt, tungsten, aluminum, gold, silver, any suitable conductive material, combinations thereof, etc.). In some embodiments, the conductive material can be blanket deposited until the openings are filled. A planarization process (e.g., a CMP process) can be used so that the remaining conductive material and the top surface of the dielectric layer 310 are substantially coplanar.

[0031] Referring again to FIG. 1 , in operation 120, according to some embodiments, horizontal interconnects for a first staircase layer are formed in a dielectric layer. For example, as shown in FIG. 5 , horizontal interconnects 518 may be disposed in dielectric layer 514 in first package 204 and second package 206 of packaging structure 200. Horizontal interconnects 418 and vertical interconnects 518 may form the lowest interconnect level of the staircase interconnect structure. The staircase interconnect structure may be formed from multiple interconnect levels, where each interconnect level is also referred to in this disclosure as a “staircase layer” (or “SC layer”) of the staircase interconnect structure. For example, first staircase layer 502 may be formed including vertical interconnects 418 and horizontal interconnects 518 according to some embodiments.

[0032] Dielectric layer 510 and blocking layer 514 may be disposed on dielectric layer 310 and blocking layer 314, respectively. In some embodiments, dielectric layer 510 may be disposed using a deposition method and material composition similar to that of dielectric layer 310. For example, dielectric layers 310 and 510 may be formed from silicon oxide, silicon nitride, or silicon oxynitride. Similarly, blocking layer 514 may be disposed using a deposition method and material composition similar to that of blocking layer 314. For example, blocking layers 314 and 514 may be formed from a photoresist material.

[0033] The horizontal interconnects 518 can be conductive lines that are disposed by etching openings in the dielectric layer 510 and depositing a conductive material in the openings. In some embodiments, the horizontal interconnects 518 can be disposed by a damascene process or a dual damascene process. In some embodiments, the horizontal interconnects 518 and the vertical interconnects 418 can be formed using similar conductive materials (e.g., copper, cobalt, tungsten, aluminum, gold, silver, etc.). In some embodiments, the width of the horizontal interconnects 518 can be larger than the width of the vertical interconnects 418 to provide horizontal electrical connection and to provide greater alignment tolerance for electrically connecting subsequent interconnect structures to the vertical interconnects 418. In some embodiments, a planarization process can be used to make the top surfaces of the horizontal interconnects 518, the dielectric layer 510, and the blocking layer 514 substantially coplanar.

[0034] Referring again to FIG. 1 , in operation 125, according to some embodiments, vertical interconnects and horizontal interconnects for a second staircase layer are formed in the dielectric layers. For example, as shown in FIG. 6 , second staircase layer 504 is formed on first staircase layer 502. The width of second staircase layer 504 is smaller than the width of first staircase layer 502, such that one or more interconnect structures from first staircase layer 502 are exposed and then covered by blocking layers 610 and 612. In some embodiments, the material composition and deposition method for dielectric layers 602 and 604 can be similar to that of dielectric layers 310 and 510, respectively. In some embodiments, the material composition and deposition method of blocking layers 610 and 612 can be similar to that of blocking layers 314 and 514, respectively. Vertical interconnects 618 and horizontal interconnects 620 can be disposed in dielectric layers 602 and 604, respectively.

[0035] Referring again to FIG. 1 , in operation 130, additional staircase layers are formed according to some embodiments. As shown in FIG. 7 , additional staircase layers (e.g., third staircase layer 506 and fourth staircase layer 508) are subsequently formed on second staircase layer 504. Third staircase layer 506 may include vertical interconnects 718 and horizontal interconnects 720 formed in dielectric layers 702 and 714, respectively. Similarly, fourth staircase layer 508 may include vertical interconnects 758 and horizontal interconnects 760 formed in dielectric layers 732 and 754, respectively. Blocking layers 710, 712, 740, and 742 may be similar to blocking layers 314 and 514 and are not described in detail herein for simplicity. Each subsequent staircase layer has a smaller width than the preceding staircase layer below it, such that at least one or more interconnects from the underlying staircase layer are exposed and then covered by a blocking layer. For example, blocking layer 710 contacts horizontal interconnect 620 of second staircase layer 504. Similarly, blocking layer 740 from fourth staircase layer 508 contacts horizontal interconnect 720 of third staircase layer 504.

[0036] Referring again to FIG. 1 , in operation 135, according to some embodiments, the blocking layers are removed. As shown in FIG. 8 , the blocking layers from all staircase layers are removed to expose the dielectric layers and horizontal interconnects not covered by subsequent staircase layers. Specifically, blocking layers (e.g., blocking layers 314, 514, 610, 612, 710, 712, 740, and 742, etc.) may be removed to expose horizontal interconnects formed near the ends of the respective staircase layers. In some embodiments, not all blocking layers are removed. The exposed horizontal interconnects and portions of the dielectric layers may be collectively referred to as the “step” or “stair” of the staircase interconnect structure. For example, the top surface of the portion of the first staircase layer 502 exposed by removing the blocking layers may be referred to as step 519, as shown in FIG. 8 . Thus, adjacent staircase layers are offset by the steps formed at the ends of the staircase layers. Specifically, a pair of offset adjacent staircase layers can include a first staircase layer and a subsequently formed second staircase layer, where the second staircase layer covers a portion (but not the entirety) of the top surface of the first staircase layer. For example, the steps 519 of the first staircase layer 502 are exposed and are not covered by the dielectric layer 602 of the second staircase layer 504. In some embodiments, the blocking layer can be removed using an appropriate etching process (e.g., a plasma etching process or a wet etching process, etc.). In some embodiments, the blocking layer is formed using a photoresist material, and the removal process can include a photoresist stripping process or a plasma ashing process.

[0037] Referring again to FIG. 1 , in operation 140, according to some embodiments, the inverted chip is disposed in the second staircase layer 504. As shown in FIG. 9 , pillar bumps 916, 936, and 956 may be disposed in the packaging structure 200. The pillar bump 916 may be disposed at the same horizontal level as the second staircase layer 504. As such, the pillar bump 916 is above the first staircase layer 502 and is electrically coupled to the horizontal interconnects 518 of the first staircase layer 502. The pillar bump 916 may include a pillar base 918 and a pillar body 920. In some embodiments, the pillar base 918 and the pillar body 920 may be formed using similar conductive materials. For example, the pillar base 918 and the pillar body 920 may be formed using copper. In some embodiments, the pillar base 918 and the pillar body 920 may be formed using electroplating, electroless plating, sputtering, PVD, any suitable deposition process, and combinations thereof. In some embodiments, the pillar base 918 and the pillar body 920 may be formed using different conductive materials. In some embodiments, the pillar base 918 and the pillar body 920 may be formed using any suitable conductive material (e.g., tungsten, cobalt, silver, gold, combinations thereof, etc.). The pillar bump 936 may include a pillar base 938 in contact with the contact pad 208 and a pillar body 940 formed on the pillar base 938. In some embodiments, the pillar base 938 and the pillar body 940 may be formed using materials and deposition processes similar to those of the pillar base 918 and the pillar body 920, which will not be described in detail herein for simplicity. The pillar bumps 936 can be used to provide electrical connection to an inverted chip disposed at the same horizontal level as the second staircase layer 504. In some embodiments, the second staircase layer 504 can be the lowest chip mounting level that is directly connected to the contact pads 208.The pillar bump 956 can include a pillar base 958 in contact with the contact pad 208 and a pillar body 960 formed on the pillar base 958. In some embodiments, the pillar base 958 and the pillar body 960 can be formed using materials and deposition processes similar to those of the pillar base 918 and the pillar body 920, which are not described in detail herein for simplicity. In some embodiments, a single pillar body 960 can be physically and electrically connected to two or more pillar bases 958. The pillar body 960 can be connected to a terminal of the chip, which is disposed in the packaging structure 200 but is not shown in FIG. 9 .

[0038] The chip 946 may be flip-mounted onto the contact pads 208 via the pillar bumps 936. In some embodiments, the chip 946 is mounted horizontally at the same level as the second stair layer 504. The chip 946 may include an integrated circuit 948 attached to a carrier 950. The chip 946 may be inverted and mounted onto the pillar bumps 936 so that terminals (not shown in FIG. 9 ) from the integrated circuit 948 are in contact with the top surface of the pillar body 940. This mounting configuration may allow power and signals to be transmitted between the pillar bumps 936 and the chip 946, allowing the integrated circuit 948 to be controlled by external circuitry. In some embodiments, the chip 946 may include various suitable integrated circuits (e.g., control circuits including transistors arranged into CMOS circuits, RF circuits, etc.). In some embodiments, active and passive devices (e.g., transistors, diodes, capacitors, resistors, inductors, etc.) may be disposed on and / or within the chip 946. The incorporation of pillar bumps (e.g., pillar bumps 916, 936, and 956) can reduce the need for wirebond connections, which reduces parasitic capacitance and inductance. While FIG. 9 shows a single row of pillar bumps 916, 936, and 956, multiple rows / columns of pillar bumps can be arranged to provide electrical connections. For example, pillar bumps 916, 936, and 956 are formed in rows extending in the x-direction. Additional pillar bumps can be arranged in columns extending in the y-direction, which are not shown in FIG. 9 for simplicity. For example, pillar bumps can be formed on multiple rows of contact pads 208a-208d shown with reference to plan view 200 of FIG. 2.Incorporating an array of pillar bumps into a packaging structure can improve product yield and performance, and can increase the number of available I / O connects, which can alleviate the need to use wire connections (e.g., wire bonding) to form high-yield multiple row / column I / O connects.

[0039] Referring again to FIG. 1 , in operation 145, according to some embodiments, an inverted chip is disposed in the third staircase layer. As shown in FIG. 10 , the chip 1046 can include an integrated circuit 1048 attached to a carrier 1050. The chip 1046, disposed at the same horizontal level as the third staircase layer 506, is directly connected to a lower staircase layer (e.g., the second staircase layer 504). The chip 1046 can be mounted on the inverted pillar bump 916 such that terminals (not shown in FIG. 9 ) from the integrated circuit 1048 face toward the step 519 and can be in contact with the top surface of the pillar body 920. This mounting configuration can allow power and signals to be transmitted between the pillar bump 916 and the chip 1046, such that the integrated circuit 1048 can be controlled by external circuitry through the horizontal and vertical interconnects of the first staircase layer 502.

[0040] The chip 1046 may include various integrated circuits (e.g., memory circuits, etc.). For example, the chip 1046 may include a three-dimensional (3D) memory circuit such as a 3D NAND flash memory chip. The 3D NAND flash memory chip may include an array of flash memory cells, which includes a stack of gate electrodes disposed on a substrate with word lines through which semiconductor channels extend into the substrate and intersect the word lines. The detailed structure of the 3D NAND flash memory chip is not shown in FIG. 10 for simplicity. The detailed structure may include a bottom / lower gate electrode that functions as a bottom / lower selective gate. The top / upper gate electrode functions as a top / upper selective gate. A word line / gate electrode between the top / upper selective gate electrode and the bottom / lower gate electrode functions as a word line. The intersection of the word line and the semiconductor channel forms a memory cell. The top / upper selective gate is connected to a word line for row selection, and the bottom / lower selective gate is connected to a bit line for column selection. A 3D NAND memory chip can include an array of contact structures for providing electrical connection from external connections to word lines, selective gates, or any suitable terminals. The contact structures can be electrically coupled to external connections on the semiconductor packaging that will be accessed by a flash memory controller or system. Examples of 3D NAND flash memory devices and methods for forming same can be found in U.S. Patent No. 10,559,592, entitled "Memory Device and Forming Method Thereof," which is incorporated herein by reference in its entirety.

[0041] Referring again to FIG. 1 , in operation 150, according to some embodiments, additional inverted chips are disposed in the various staircase layers. The inverted chips may include integrated circuits mounted on carriers. For example, chip 1146 may include integrated circuit 1048 attached to carrier 1050. In some embodiments, the chips may be disposed without a carrier (e.g., chip 1346 including an integrated circuit). As shown in FIG. 11 , similar to chip 1046, each of chips 1146, 1246, and 1168 may then be disposed on a staircase layer and directly and electrically connected to another staircase layer directly below it. Additionally, chips 1146, 1246, and 1168 may be electrically connected to other staircase layers through horizontal and vertical interconnects. For example, the chip 1146 may be inverted and mounted on the pillar bumps 926 so that terminals (not shown in FIG. 11 ) from the integrated circuit 1148 face (e.g., directly above) the portion of the second stair layer 504 that is not covered by the third stair layer 506, and come into contact with the top surface of the pillar body 930. This mounting configuration may allow power and signals to be transmitted between the pillar bumps 926 and the chip 1146, such that the integrated circuit 1148 may be controlled by external circuitry through the horizontal and vertical interconnects of the first and second stair layers 502 and 504.

[0042] A molding compound may be formed over the carrier substrate to encapsulate the stacked interconnect structure and the disposed chips. As shown in FIG. 11, molding compound 1180 may be disposed such that step layers 502-508 and chips 946-1346 are embedded within molding compound 1180. In some embodiments, molding compound 1180 may be formed from a resin compound, an epoxy molding compound, any suitable molding compound, and / or a combination thereof.

[0043] Referring again to FIG. 1 , in operation 155, according to some embodiments, a redistribution layer (RDL) and metal bumps are formed. As shown in FIG. 12 , the packaging structure 200 is inverted, and an RDL 1202 and metal bumps 1204 may be disposed on the backside of the packaging structure 200. The metal bumps 1204 may be used as I / O contacts or any suitable electrical contacts. In some embodiments, the carrier substrate 202 may be replaced by an RDL 1202. For example, the carrier substrate 202 may be removed to expose the surfaces of the dielectric layer 310, the vertical interconnects 418, the contact pads 208, and the molding compound 1180. An RDL 1202 may then be formed on the exposed surfaces. The RDL 1202 may include horizontal and vertical conductive lines to fan out the vertical interconnects formed in the first staircase layer 502 to a larger footprint. In some embodiments, the RDL 1202 may include one or more dielectric layers with conductive wires (not shown in FIG. 12 for simplicity) embedded therein. The conductive wires may be formed using any suitable material (e.g., aluminum, aluminum alloys, or other metals, etc.). In some embodiments, the RDL 1202 may further include a fuse.

[0044] The metal bumps 1204 may be disposed on and electrically connected to the RDL 1202. The metal bumps 1204 may include solder bumps (e.g., eutectic solder bumps, etc.). Alternatively, the metal bumps 1204 may be formed from copper bumps or other metal bumps formed from gold, silver, nickel, tungsten, aluminum, other metals, and / or alloys thereof. The metal bumps 1204 may also include Controlled Collapse Chip Connection (C4) bumps used in semiconductor interconnection techniques (e.g., flip-chip interconnections, etc.). In some embodiments, the metal bumps 1204 may protrude from the surface of the RDL 1202, as shown in FIG. 12. A solder mask (not shown) may be disposed prior to the formation of the metal bumps 1204 to protect the bump material from forming in unwanted areas. The metal bumps 1204 may be formed through any number of suitable techniques, including PVD, CVD, electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and electroplating.

[0045] 13 and 14 illustrate a packaging structure 1300 incorporating stepped interconnect structures formed on both ends of stacked chips, according to some embodiments. Like reference numbers in FIGS. 2-14 generally indicate identical, functionally similar, and / or structurally similar elements.

[0046] FIG. 13 illustrates a packaging structure 1300 prior to the formation of RDLs and metal bumps. The packaging structure 1300 includes a first package 1304 and a second package 1306. In some embodiments, the first and second packages 1304 and 1306 can be mirror-symmetrical, as shown in FIG. 13. The stacked chips, including chips 946, 1046, 1146, and 1246, are similar to those in FIGS. 2-12 and are not described in detail herein for simplicity. In contrast to the staircase interconnect structure described in FIGS. 2-12, the staircase interconnect structure illustrated in FIGS. 13 and 14 connects to both ends of the stacked chips. For example, as shown in FIG. 13, pillar bumps 916 and 926 connect to one end of chips 1046 and 1146, while pillar bumps 1316 and 1326 connect to the opposing ends of chips 1246 and 1346.

[0047] 14 shows the packaging structure 1300 after the formation of the RDL and metal bumps. As shown in FIG. 14, the RDL 1402 may be disposed on the back side of the packaging structure 1300, and the metal bumps 1404 may be disposed on the RDL 1402. The RDL 1402 and the metal bumps 1404 may be similar to the RDL 1202 and the metal bumps 1204 and will not be described in detail herein for simplicity.

[0048] After the metal bumps are disposed in the packaging structures shown in FIGS. 12 and 14, additional processes may be performed. For example, panel-level testing may be performed through the metal bumps to determine packaging characteristics (e.g., fabrication yield and device performance, etc.). A dicing process may be used to separate adjacent packages. For example, packages 204 and 206 in FIG. 12 may be separated by dicing along package boundary 205. Packages 1304 and 1306 may be separated by dicing along package boundary 1305.

[0049] 15 and 16 illustrate a packaging structure 1500 prior to the formation of RDLs and metal bumps, according to some embodiments. FIGS. 15 and 16 are cross-sectional and plan views, respectively, of the packaging structure 1500. Contact pads 208 are formed over a central region of the substrate between staircase layers 1502 and 1504. Similar to the staircase layers shown in FIGS. 6-14, the staircase layers 1502 and 1504 can have steps formed in the x-direction. Additionally, the staircase layer 1504 can have steps formed in the y-direction by an appropriate method (e.g., stacking chips having lengths that incrementally decrease in the y-direction, as shown in FIG. 16). For example, chip 1346 having length L1 can be formed on chip 1160 having a shorter length L2. In some embodiments, mounting chips having similar lengths can also have steps in the y-direction by mounting subsequent chips with incremental offsets. RDLs and metal bumps similar to those described in Figures 12 and 14 may be formed on the packaging structure 1500, which will not be discussed in detail herein for simplicity.

[0050] This disclosure describes a stacked staircase interconnect structure for memory chips in fan-out packaging. The stacked staircase interconnect structure can provide electrical connection to each chip of the stacked chips through pillar bumps formed on each level of the stacked staircase interconnect structure, which increases the number of I / O connection points.

[0051] In some embodiments, the semiconductor package includes a redistribution layer (RDL) and metal bumps formed on a first surface of the RDL. The semiconductor package also includes a staircase interconnect structure formed on a second surface of the RDL. The staircase interconnect structure includes staircase layers, each staircase layer being offset from an adjacent staircase layer. The semiconductor package further includes an integrated circuit (IC) chip electrically connected to the staircase interconnect structure.

[0052] In some embodiments, the semiconductor package includes a redistribution layer (RDL) and contact pads in contact with the RDL. The semiconductor package also includes a first plurality of pillar bumps in contact with the contact pads. The semiconductor package further includes a staircase interconnect structure in contact with the RDL. The staircase interconnect structure includes a first staircase layer having a first plurality of interconnects in contact with the RDL and a second staircase layer adjacent to the first staircase layer. The second staircase layer includes a second plurality of interconnects in contact with the first plurality of interconnects. The staircase interconnect structure further includes a third staircase layer, the third staircase layer adjacent to the second staircase layer and having a third plurality of interconnects. The semiconductor package also includes a first integrated circuit (IC) chip in contact with the first plurality of pillar bumps and a second plurality of pillar bumps in contact with the first staircase layer. The semiconductor package also includes a second IC chip in contact with the first IC chip and the second plurality of pillar bumps.

[0053] In some embodiments, a method for forming a semiconductor package includes forming a first step layer on a carrier substrate. Forming the first step layer includes disposing a first dielectric layer on the carrier substrate and forming a first plurality of interconnects in the first dielectric layer. The method also includes disposing a blocking layer on the first step layer. The blocking layer contacts a top surface of at least one interconnect of the first plurality of interconnects. The method further includes forming a second step layer on the first step layer. The second step layer contacts the blocking layer. The method also includes removing the blocking layer and exposing a top surface of the at least one interconnect. The method also includes forming pillar bumps on the exposed top surface of the at least one interconnect. The method also includes mounting an integrated circuit (IC) chip on the pillar bumps.

[0054] Thus, the foregoing description of specific embodiments will demonstrate the general nature of the present disclosure such that others may readily modify and / or adapt such specific embodiments for various applications without undue experimentation, by applying knowledge within the purview of those skilled in the art, without departing from the general concepts of the disclosure. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology used herein is for the purpose of description and not limitation, and that the terminology or terminology used herein is to be interpreted by one of ordinary skill in the art in light of the teaching and guidance.

[0055] The embodiments of the present disclosure have been described above with the help of functional building blocks illustrating implementation of certain functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the certain functions and relationships thereof are appropriately implemented.

[0056] The Summary and Abstract sections may describe one or more (but not all) example embodiments of the present disclosure contemplated by the inventors and, as such, are not intended to limit the scope of the disclosure and appended claims in any way.

[0057] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0058] 200 Packaging Structure 202 Carrier Board 204 First Package 205 Package Boundaries 206 Second Package 208 Contact Pad 208a Contact Pad 208b Contact pad 208c Contact Pad 208d Contact Pad 210 Side View 220 Floor Plan 310 Dielectric layer 314 Blocking Layer 418 Vertical Interconnect 502 First Staircase 504 Second Staircase 506 Third Staircase 508 Fourth Staircase 510 Dielectric layer 514 Blocking Layer 518 Horizontal Interconnect 519 steps 602 Dielectric layer 604 Dielectric layer 610 Blocking Layer 612 Blocking Layer 618 Vertical Interconnect 620 Horizontal Interconnect 702 Dielectric layer 710 Blocking Layer 712 Blocking Layer 714 Dielectric Layer 718 Vertical Interconnect 720 Horizontal Interconnect 732 Dielectric Layer 740 Blocking Layer 742 Blocking Layer 754 Dielectric Layer 758 Vertical Interconnect 760 Horizontal Interconnect 916 pillar bump 918 pillar base 920 Pillar body 926 Pillar Bump 930 Pillar body 936 Pillar Bump 938 Pillar Base 940 Pillar body 946 chips 948 Integrated Circuits 950 Carrier 956 Pillar Bump 958 Pillar Base 960 Pillar body 1046 chips 1048 Integrated Circuits 1050 Carrier 1146 chips 1148 Integrated Circuits 1160 chips 1180 Molding Compound 1202 Redistribution Layer (RDL) 1204 Metal Bump 1246 chips 1300 Packaging Structure 1304 First Package 1305 Package Boundary 1306 Second Package 1316 Pillar Bump 1326 Pillar Bump 1346 chips 1402 RDL 1404 Metal Bump 1500 Packaging Structure 1502 Staircase layer 1504 Staircase layer L1 length L2 length

Claims

1. A semiconductor package comprising: the redistribution layer (RDL); an integrated circuit (IC) chip on a first side of the RDL; a staircase interconnect structure in direct contact with the first side of the RDL, the staircase interconnect structure including a staircase layer stacked on the RDL; a pillar bump on the step layer and connected to the IC chip, the pillar bump including a conductive material; 1. A semiconductor package comprising:

2. 2. The semiconductor package of claim 1, wherein the staircase layer further includes a first staircase layer and a second staircase layer stacked along a first direction, wherein in the second direction, a width of the first staircase layer is greater than a width of the second staircase layer, and the second direction is perpendicular to the first direction.

3. The semiconductor package of claim 2 , wherein the first step layer is between the second step layer and the RDL.

4. 3. The semiconductor package of claim 2, wherein the IC chip includes a first IC chip and a second IC chip stacked along the first direction, and at least a portion of the second IC chip is exposed to the first IC chip.

5. 5. The semiconductor package of claim 4, wherein the first IC chip is between the second IC chip and the RDL, the first IC chip is connected to the first staircase layer through one or more pillar bumps, and the second IC chip is connected to the second staircase layer through one or more pillar bumps.

6. The semiconductor package of claim 5 , wherein the one or more pillar bumps are disposed at the same horizontal level as the second staircase layer.

7. 5. The semiconductor package of claim 4, wherein the first IC chip is offset from the second IC chip such that one or more terminals of the first IC chip are directly above a remainder of the first stepped layer.

8. 5. The semiconductor package of claim 4, wherein the IC chip further includes a third IC chip between the first IC chip and the RDL, the third IC chip being connected to the RDL through one or more pillar bumps.

9. 9. The semiconductor package of claim 8, wherein the third IC chip includes a control circuit, and the first and second IC chips include NAND flash memory chips.

10. The semiconductor package of claim 1 , wherein the staircase interconnect structure further includes a vertical interconnect and a horizontal interconnect, and the pillar bump is connected to the horizontal interconnect.

11. The semiconductor package of claim 10 , wherein at least one of the horizontal interconnects is between one of the pillar bumps and one of the vertical interconnects.

12. a contact pad disposed on a second side of the RDL, the second side being opposite the first side. The semiconductor package of claim 1 further comprising:

13. A semiconductor package comprising: the redistribution layer (RDL); an integrated circuit (IC) chip on the side of the RDL; a first staircase interconnect structure and a second staircase interconnect structure directly contacting the side of the RDL, the first staircase interconnect structure including first staircase layers stacked along a first direction, the first staircase interconnect structure and the second staircase interconnect structure being on opposite sides of the IC chip along a second direction, the second direction being perpendicular to the first direction; a first pillar bump on the first step layer and connected to the IC chip, the first pillar bump including a conductive material; 1. A semiconductor package comprising:

14. 14. The semiconductor package of claim 13, wherein the first stepped layer includes a first layer and a second layer stacked along the first direction, and in the second direction, a width of the first layer is greater than a width of the second layer, and the first layer is between the second layer and the RDL.

15. 14. The semiconductor package of claim 13, wherein the IC chips include a first IC chip and a second IC chip stacked along the first direction, the first IC chip connected to the first staircase interconnect structure through the first pillar bump, and the second IC chip connected to the second staircase interconnect structure through a second pillar bump.

16. 16. The semiconductor package of claim 15, wherein the IC chip further includes a third IC chip, the second IC chip being between the first IC chip and the third IC chip, and the third IC chip being connected to the RDL through a third pillar bump.

17. 17. The semiconductor package of claim 16, wherein the first and second IC chips include NAND flash memory chips, and the third IC chip includes control circuitry.

18. 1. A method for forming a semiconductor packaging structure, the method comprising: providing a carrier substrate; forming a stepped interconnect structure on the carrier substrate, the forming comprising: forming a first step layer; and forming a second staircase layer on the first staircase layer, the second staircase layer covering a portion of the first staircase layer and leaving a remaining portion of the first staircase layer exposed; and forming a first pillar bump on the remaining portion of the first step layer; flip-mounting an integrated circuit (IC) chip onto the stepped interconnect structure through the first pillar bumps; replacing the carrier substrate with a redistribution layer (RDL); Including, The method wherein the staircase interconnect structure directly contacts the RDL.

19. The IC chip includes a first IC chip and a second IC chip stacked together, with at least a portion of the second IC chip exposed to the first IC chip, and the method further includes: flip-mounting the first IC chip on the first pillar bumps; forming a second pillar bump on the second step layer; flip-mounting the second IC chip on the second pillar bumps; 20. The method of claim 18, comprising:

20. The step of forming the first step layer includes: depositing a first dielectric layer over the carrier substrate; forming a plurality of vertical interconnects in the first dielectric layer; depositing a second dielectric layer over the first dielectric layer; forming a plurality of horizontal interconnects in the second dielectric layer; 20. The method of claim 18, comprising:

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