Circuit device, oscillator and processing system

Abstract

To provide a circuit arrangement and the like that enable accurate temperature detection by effectively using a temperature sensor circuit of the circuit arrangement.SOLUTION: A circuit arrangement 20 includes: an oscillation circuit 30 that generates an oscillation signal OSC by using an oscillator 10; a temperature sensor circuit 40 that outputs temperature detection data DTD; a temperature compensation circuit 60 that performs temperature compensation of the oscillatory frequency of the oscillation signal OSC based on the temperature detection data DTD; a memory 70 that stores correction data DCT for correcting the temperature detection data DTD to determine temperature; and an interface circuit 80 that outputs the temperature detection data DTD and the correction data DCT.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, an oscillator, a processing system, and the like. [Background technology]

[0002] Conventionally, circuit devices have been known that include an oscillator circuit that oscillates an oscillator such as a quartz crystal oscillator. Some of these circuit devices are provided with a temperature sensor circuit for temperature compensation of the oscillation frequency of the oscillator circuit. Patent Document 1 discloses an RTC (Real-Time Clock) that has a temperature compensation function and outputs an interrupt signal when the detected temperature exceeds a threshold value. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-222342 Summary of the Invention [Problem to be solved by the invention]

[0004] In a circuit device having an oscillator circuit and a temperature sensor circuit, if the temperature detection data from the temperature sensor circuit could be output externally, a processing device external to the circuit device could effectively use the temperature detection data from the temperature sensor circuit of the circuit device to measure the temperature of the surrounding environment, etc. In this case, to output accurate temperature detection data to the external processing device, it is necessary to provide a correction circuit inside the circuit device to correct the temperature detection result of the temperature sensor circuit. However, providing such a correction circuit can cause problems such as unnecessary power consumption in the correction circuit. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including an oscillation circuit that generates an oscillation signal using a vibrator, a temperature sensor circuit that outputs temperature detection data, a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data, a memory that stores correction data for correcting the temperature detection data to determine the temperature, and an interface circuit that outputs the temperature detection data and the correction data.

[0006] Another aspect of the present invention relates to an oscillator including a vibrator and a circuit device, wherein the circuit device includes an oscillation circuit that generates an oscillation signal using the vibrator, a temperature sensor circuit that outputs temperature detection data, a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data, a memory that stores correction data for correcting the temperature detection data to determine the temperature, and an interface circuit that outputs the temperature detection data and the correction data.

[0007] Another aspect of the present disclosure relates to a processing system that includes the oscillator described above and a processing device electrically connected to the oscillator, wherein the processing device performs a calculation process to correct the temperature detection data based on the correction data, thereby detecting the temperature. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows an example of the configuration of a circuit device according to an embodiment of the present invention. [Figure 2] FIG. 4 is a diagram illustrating the relationship between temperature detection data and temperature. [Figure 3] 3 shows a detailed configuration example of the circuit device of the present embodiment. [Figure 4] 3 shows a detailed configuration example of the circuit device of the present embodiment. [Figure 5] 10 shows a configuration example of a comparative example of the present embodiment. [Figure 6] 10 shows a configuration example of a comparative example of the present embodiment. [Figure 7] FIG. 10 is an explanatory diagram of the setting of upper and lower limit values ​​in a comparative example. [Figure 8] FIG. 10 is an explanatory diagram of generation of an interrupt signal in a comparative example. [Figure 9] FIG. 4 is an explanatory diagram of setting upper and lower limit values ​​in this embodiment. [Figure 10] FIG. 4 is an explanatory diagram of generation of an interrupt signal in this embodiment. [Figure 11] FIG. 2 is an explanatory diagram of the arithmetic processing of an arithmetic circuit. [Figure 12] FIG. 2 is an explanatory diagram of the arithmetic processing of an arithmetic circuit. [Figure 13] 1 shows an example of the configuration of a processing system including an oscillator and a processing device. [Figure 14] An example of the I / O circuit configuration of an interface circuit. [Figure 15] FIG. 4 is a signal waveform diagram illustrating an example of communication according to the present embodiment. [Figure 16] FIG. 4 is a signal waveform diagram illustrating an example of communication according to the present embodiment. [Figure 17] FIG. 2 is an explanatory diagram of an example of a communication protocol according to the present embodiment. [Figure 18] FIG. [Figure 19] First example of oscillator structure. [Figure 20] Second example of oscillator structure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the content of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

[0010] 1.Circuit device 1 shows an example of the configuration of a circuit device 20 according to this embodiment. The circuit device 20 according to this embodiment includes an oscillation circuit 30 that causes a vibrator 10 to oscillate, a temperature sensor circuit 40 that detects temperature, a temperature compensation circuit 60 that performs temperature compensation, a memory 70 that stores information, and an interface circuit 80 that performs interface processing for communication.

[0011] The vibrator 10 is an element that generates mechanical vibrations in response to an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a tuning fork-type quartz crystal vibrating piece, a double-ended tuning fork-type quartz crystal vibrating piece, or a quartz crystal vibrating piece with a thickness-shear vibration such as an AT-cut or SC-cut cut angle. For example, the vibrator 10 may be a vibrator built into a temperature-compensated quartz oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built into an oven-controlled quartz crystal oscillator (OCXO) that does have a thermostatic oven. Note that the vibrator 10 of this embodiment can be realized by various vibrating pieces, such as vibrating pieces other than tuning fork-type, double-ended tuning fork-type, or thickness-shear vibration types, or piezoelectric vibrating pieces made of materials other than quartz. For example, the vibrator 10 may be a surface acoustic wave (SAW) resonator or a micro-electromechanical systems (MEMS) resonator, which is a silicon vibrator formed using a silicon substrate.

[0012] The circuit device 20 is an integrated circuit device known as an IC (Integrated Circuit). For example, the circuit device 20 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. In FIG. 1, the circuit device 20 includes an oscillator circuit 30, a temperature sensor circuit 40, a temperature compensation circuit 60, a memory 70, and an interface circuit 80.

[0013] The oscillator circuit 30 is a circuit that oscillates the resonator 10. For example, the oscillator circuit 30 generates an oscillation signal OSC by oscillating the resonator 10. The oscillation signal OSC is an oscillation clock signal. As an example, the oscillator circuit 30 generates an oscillation signal OSC with a frequency of, for example, 32 kHz. However, the oscillation frequency is not limited to 32 kHz. For example, the oscillator circuit 30 can be realized by an oscillation driver circuit electrically connected to one end and the other end of the resonator 10, and passive elements such as capacitors and resistors. The driver circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The driver circuit is the core circuit of the oscillator circuit 30, and the driver circuit drives the resonator 10 with voltage or current to oscillate the resonator 10. Various types of oscillator circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used as the oscillator circuit 30. The oscillator circuit 30 also includes a variable capacitance circuit, the capacitance of which can be adjusted to adjust the oscillation frequency. The variable capacitance circuit can be realized, for example, by a capacitor array and a switch array connected to the capacitor array. The variable capacitance circuit can also be realized by a variable capacitance element such as a varactor. The connection in this embodiment is an electrical connection. An electrical connection is a connection that allows electrical signals to be transmitted, and is a connection that allows information to be transmitted by electrical signals. The electrical connection may be a connection via a passive element or the like.

[0014] The temperature sensor circuit 40 measures temperatures such as the ambient temperature of the resonator 10 and the circuit device 20 and outputs the measurement results as temperature detection data DTD. The temperature detection data DTD is data that, for example, monotonically increases or decreases with temperature within the operating temperature range of the circuit device 20. As shown in FIG. 4 (described later), the temperature sensor circuit 40 is a temperature sensor that utilizes the temperature dependency of the oscillation frequency of a ring oscillator 42. Specifically, as shown in FIG. 4, the temperature sensor circuit 40 includes a ring oscillator 42 and a counter 44. The counter 44 counts the output pulse signal, which is the oscillation signal of the ring oscillator 42, during a count period defined by a clock signal CK based on the oscillation signal OSC from the oscillation circuit 30, and outputs the count value as temperature detection data DTD. Note that the temperature sensor circuit 40 is not limited to this. For example, the temperature sensor circuit 40 may include an analog temperature sensor that outputs a temperature detection voltage by utilizing the temperature dependency of the forward voltage of a PN junction, and an A / D conversion circuit that A / D converts the temperature detection voltage and outputs the temperature detection data DTD.

[0015] The temperature compensation circuit 60 performs temperature compensation processing based on the temperature detection data DTD from the temperature sensor circuit 40. The temperature compensation processing is processing that suppresses and compensates for fluctuations in the oscillation frequency due to temperature fluctuations, for example. That is, the temperature compensation circuit 60 performs temperature compensation processing for the oscillation frequency of the oscillation circuit 30 so that the frequency remains constant even when there is a temperature fluctuation. Specifically, the temperature compensation circuit 60 performs temperature compensation processing based on digital calculations performed using the temperature detection data DTD from the temperature sensor circuit 40.

[0016] The memory 70 is a storage device that stores information. The memory 70 can be realized, for example, by a semiconductor memory. For example, the memory 70 is preferably realized by a non-volatile memory, but is not limited to this. The memory 70 stores various information necessary for the operation of the circuit device 20. The memory 70 also stores correction data DCT for correcting the temperature detection data DTD to obtain the temperature.

[0017] The interface circuit 80 is a circuit that interfaces with an external device, such as a circuit for communicating with an external processing device 100 shown in FIG. 13 (described later). In this embodiment, the interface circuit 80 outputs the temperature detection data DTD from the temperature sensor circuit 40 and the correction data DCT from the memory 70. That is, the interface circuit 80 outputs the temperature detection data DTD and the correction data DCT to the external processing device 100. The interface circuit 80 can be realized, for example, by a serial interface circuit that performs serial interface communication. For example, the interface circuit 80 may be realized by a serial interface circuit such as the one shown in FIG. 13 (described later), or by a serial interface circuit such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit). In SPI and I2C, serial interface communication is performed using a serial clock signal and a serial data signal. Note that a modification in which a parallel interface circuit that performs parallel interface communication is used as the interface circuit 80 is also possible.

[0018] As described above, the circuit device 20 of this embodiment includes, as shown in FIG. 1 , an oscillator circuit 30, a temperature sensor circuit 40, a temperature compensation circuit 60, a memory 70, and an interface circuit 80. The oscillator circuit 30 generates an oscillation signal OSC using the resonator 10, and the temperature sensor circuit 40 detects the temperature and outputs temperature detection data DTD. The temperature compensation circuit 60 performs temperature compensation for the oscillation frequency of the oscillation signal OSC based on the temperature detection data DTD. The memory 70 stores correction data DCT for correcting the temperature detection data DTD to determine the temperature. For example, during manufacturing and inspection of the circuit device 20 or a device such as an oscillator incorporating the circuit device 20, the correction data DCT for determining the temperature is calculated from the temperature detection data DTD output by the temperature sensor circuit 40. The calculated correction data DCT is then stored in the memory 70. The interface circuit 80 then outputs the temperature detection data DTD and the correction data DCT to an external device. The temperature detection data DTD is data for identifying the detected temperature and is data associated with the detected temperature. The correction data DCT is data used by the external processing device 100 to obtain a corresponding temperature from the temperature detection data DTD. For example, the correction data DCT is data for correcting variations in the correspondence between the temperature and the temperature detection data DTD.

[0019] As described above, in the circuit device 20 of this embodiment, in addition to the temperature detection data DTD, correction data DCT for correcting the temperature detection data DTD to obtain the temperature is output from the interface circuit 80 to the outside. Therefore, the external processing device 100 in Fig. 13 performs a calculation process to correct the temperature detection data DTD received from the interface circuit 80 based on the correction data DCT also received from the interface circuit 80, thereby making it possible to measure an accurate temperature corresponding to the temperature detection data DTD.

[0020] For example, FIG. 2 shows an example of the characteristics of the temperature detection data DTD with respect to temperature. FIG. 2 shows an example of the characteristics of the temperature detection data DTD for devices DVA, DVB, DVC, and DVD. The devices DVA, DVB, DVC, and DVD correspond to the circuit device 20 or the oscillator 4 in FIG. 3 (described later) in which the circuit device 20 is incorporated. For example, variations occur in the characteristics of the temperature detection data DTD due to variations in the device manufacturing process. For example, the characteristics of the temperature detection data DTD for devices DVA to DVD differ in slope SL and offset OFS, resulting in individual variations. The correction data DCT is used to correct such variations in the characteristics of the temperature detection data DTD with respect to temperature. For example, in the case of FIG. 2, the temperature can be expressed as the following equation (1) using the temperature detection data DTD.

[0021] Temperature (℃)=SL×DTD+OFS (1)

[0022] Therefore, in the case of FIG. 2, by using the slope SL and offset OFS as the correction data DCT, it is possible to accurately determine the temperature based on the temperature detection data DTD, even when individual variations occur. Taking the device DVA as an example, during the manufacturing and testing of the device DVA, an external device such as a tester can read the temperature detection data DTD output by the temperature sensor circuit 40 at each temperature to determine the slope SL and offset OFS as the correction data DCT. The determined correction data DCT is then written to the memory 70 of the circuit device 20, and the product is shipped. During actual operation of the device DVA, the interface circuit 80 of the device DVA outputs the temperature detection data DTD from the temperature sensor circuit 40 and the correction data DCT written to the memory 70. The external processing device 100 then performs the calculation process of the above equation (1) to correct the temperature detection data DTD based on the correction data DCT, thereby enabling temperature measurement.

[0023] Here, the correction data DCT is, for example, coefficient data of a polynomial that indicates the relationship between temperature and temperature detection data DTD. For example, in the above equation (1), the slope SL and offset OFS that are the correction data DCT are coefficient data of a first-order polynomial that indicates the relationship between temperature and temperature detection data DTD. More generally, the relationship between temperature and temperature detection data DTD can be expressed by a polynomial such as the following equation (2).

[0024] Temperature (℃)=C n ×DTD n +C n-1 ×DTD n-1 +C1×DTD+C0(2)

[0025] In this case, the correction data DCT is the coefficient data of the polynomial in the above equation (2), C n , C n-1 ...C1, C0. n is an integer equal to or greater than 1. In this way, if the characteristic showing the relationship between the temperature and the temperature detection data DTD can be expressed or approximated by a polynomial such as the above formula (2), the coefficient data of this polynomial, C n , C n-1 It becomes possible to use C1 and C0 as the correction data DCT, and the external processing device 100 can perform calculation processing to correct the temperature detection data DTD based on the correction data DCT, thereby enabling accurate temperature measurement.

[0026] The correction data DCT does not need to be the same across all temperature ranges, and different correction data DCT may be set depending on the temperature range when performing, for example, the equalizing calculation processes shown in Figures 11 and 12 described below. The correction method using the correction data DCT in this embodiment is not limited to this type of polynomial approximation method, and various modifications are possible, such as storing the correspondence between temperature and temperature detection data DTD in the form of a lookup table in the memory 70.

[0027] 2. Detailed configuration example 3 shows a detailed configuration example of the circuit device 20 of this embodiment and the oscillator 4 including the circuit device 20. In FIG. 3, the circuit device 20 includes an oscillation circuit 30, a temperature sensor circuit 40, a logic circuit 50, a nonvolatile memory 72, an interface circuit 80, an output circuit 90, and a power supply circuit 96. The oscillator 4 also includes a resonator 10 and the circuit device 20. The resonator 10 is electrically connected to the circuit device 20. For example, the resonator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, metal bumps, or the like of a package that houses the resonator 10 and the circuit device 20.

[0028] The oscillator circuit 30 is electrically connected to the vibrator 10 via pads PX1 and PX2. The pads PX1 and PX2 are pads for connecting the vibrator. A drive circuit for oscillation of the oscillator circuit 30 is provided between the pads PX1 and PX2. The oscillator circuit 30 also includes a variable capacitance circuit 32. The variable capacitance circuit 32 includes, for example, a capacitor array and a switch array connected to the capacitor array. The switches of the switch array of the variable capacitance circuit 32 are turned on and off based on frequency adjustment data from the temperature compensation circuit 60. For example, the variable capacitance circuit 32 includes a first capacitor array having a plurality of capacitors whose capacitance values ​​are binary-weighted. The variable capacitance circuit 32 also includes a first switch array having a plurality of switches, each of which turns on and off a connection between each capacitor of the first capacitor array and the pad PX1. The variable capacitance circuit 32 may also include a first variable capacitance circuit having a first capacitor array and a first switch array and connected to the pad PX1, and a second variable capacitance circuit having a second capacitor array and a second switch array and connected to the pad PX2. The switches of the first switch array and the second switch array are turned on and off based on the frequency adjustment data.

[0029] The logic circuit 50 is a control circuit that performs various control processes. For example, the logic circuit 50 performs overall control of the circuit device 20 and controls the operation sequence of the circuit device 20. The logic circuit 50 also performs various processes for controlling the oscillator circuit 30, controls the temperature sensor circuit 40 and the power supply circuit 96, and controls the reading and writing of information from and to the nonvolatile memory 72. The logic circuit 50 can be realized by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and routed using a gate array or the like.

[0030] The logic circuit 50 includes a temperature compensation circuit 60 and an interrupt signal generation circuit 62. Details of the interrupt signal generation circuit 62 will be described later with reference to FIG.

[0031] The temperature compensation circuit 60 obtains frequency adjustment data based on the temperature detection data DTD. Then, the capacitance value of the variable capacitance circuit 32 of the oscillation circuit 30 is adjusted based on the obtained frequency adjustment data, thereby achieving temperature compensation processing for the oscillation frequency of the oscillation circuit 30. For example, the nonvolatile memory 72 stores a lookup table LUT that represents the correspondence between the temperature detection data DTD and the frequency adjustment data. Then, the temperature compensation circuit 60 performs temperature compensation processing to obtain frequency adjustment data from the temperature detection data DTD using this lookup table LUT.

[0032] The nonvolatile memory 72 is a memory that retains information even when power is not supplied. For example, the nonvolatile memory 72 is a memory that can retain information even when power is not supplied and that allows information to be rewritten. The nonvolatile memory 72 stores various information necessary for the operation of the circuit device 20. The nonvolatile memory 72 can be realized by an EEPROM (Electrically Erasable Programmable Read-Only Memory) realized by a FAMOS memory (Floating gate Avalanche injection MOS memory) or a MONOS memory (Metal-Oxide-Nitride-Oxide-Silicon memory), or the like.

[0033] In FIG. 3, the nonvolatile memory 72 stores the lookup table LUT and the correction data DCT. The temperature compensation circuit 60 performs the temperature compensation process described above using the lookup table LUT. The temperature compensation circuit 60 may load information from the lookup table LUT into a storage circuit such as a register and perform the temperature compensation process based on the information loaded into the storage circuit. The nonvolatile memory 72, which corresponds to the memory 70 in FIG. 1, stores the correction data DCT. The interface circuit 80 outputs the correction data DCT stored in the nonvolatile memory 72 to the outside, in addition to the temperature detection data DTD from the temperature sensor circuit 40. The logic circuit 50, for example, controls the reading of the correction data DCT from the nonvolatile memory 72.

[0034] 3, the memory 70 in FIG. 1 is realized by the nonvolatile memory 72, and the correction data DCT is stored in the nonvolatile memory 72. In this way, the correction data DCT for correcting the temperature detection data DTD to obtain the temperature can be stored in the nonvolatile memory 72, and the correction data DCT can be read out from the nonvolatile memory 72 and output to the outside together with the temperature detection data DTD by the interface circuit 80.

[0035] The interface circuit 80 outputs a data signal DA to the first pad PDA. This data signal DA is then output to the outside via the first terminal TDA of the oscillator 4. For example, the interface circuit 80 outputs temperature detection data DTD and correction data DCT as the data signal DA. The interface circuit 80 also receives the data signal DA from the outside.

[0036] The output circuit 90 outputs a clock signal CK based on the oscillation signal OSC. For example, the output circuit 90 buffers the oscillation signal OSC, which is the oscillation clock signal from the oscillation circuit 30, and outputs it to the clock output pad PCK as the clock signal CK. This clock signal CK is then output to the outside via the clock output terminal TCK of the oscillator 4. For example, the output circuit 90 outputs the clock signal CK in a single-ended CMOS signal format. However, the output circuit 90 may also output the clock signal CK in a signal format other than CMOS. Furthermore, a clock signal generation circuit such as a PLL circuit that generates a clock signal CK with a frequency that is multiplied by the frequency of the oscillation signal OSC may be provided downstream of the oscillation circuit 30. The output circuit 90 may then buffer the clock signal CK generated by this clock signal generation circuit before outputting it.

[0037] The first pad PDA connected to the interface circuit 80 and the first terminal TDA of the oscillator 4 connected to the first pad PDA can also be used as an output enable pad and an output enable terminal. For example, when the first pad PDA is used as an output enable pad, the output circuit 90 outputs a clock signal CK to the outside when the first pad PDA and the first terminal TDA are set to an active level such as a high level. On the other hand, when the first pad PDA and the first terminal TDA are set to an inactive level such as a low level, the output circuit 90 sets the clock signal CK to a fixed voltage level such as a low level.

[0038] The power supply circuit 96 receives a power supply voltage VDD from the power supply pad PVDD and a ground voltage GND from the ground pad PGND, and supplies various power supply voltages for the internal circuits of the circuit device 20 to the internal circuits. For example, the power supply circuit 96 supplies a regulated power supply voltage obtained by regulating the power supply voltage VDD to each circuit of the circuit device 20, such as the oscillator circuit 30.

[0039] The power supply pad PVDD is a pad to which a power supply voltage VDD is supplied. The pad is a terminal of the circuit device 20, which is a semiconductor chip. For example, in the pad region, a metal layer is exposed from a passivation film, which is an insulating layer, and this exposed metal layer forms a pad, which is a terminal of the circuit device 20. For example, the power supply voltage VDD from an external power supply device is supplied to the power supply pad PVDD. The ground pad PGND is a terminal to which a ground voltage GND is supplied. GND can also be referred to as VSS, and the ground voltage is, for example, the ground potential. In this embodiment, the ground is appropriately referred to as GND. The power supply pad PVDD, the ground pad PGND, the clock output pad PCK, and the first pad PDA are electrically connected to the power supply terminal TVDD, the ground terminal TGND, the clock output terminal TCK, and the first terminal TDA, which are external terminals for external connection of the oscillator 4, respectively. For example, each of these pads and terminals is electrically connected using internal wiring of the package, bonding wires, metal bumps, or the like.

[0040] FIG. 4 shows a more detailed configuration example of the circuit device 20 of this embodiment. The temperature sensor circuit 40 includes a ring oscillator 42, a counter control unit 46, and a counter 44. The ring oscillator 42 is a circuit in which multiple delay elements are connected in a ring shape. Specifically, the ring oscillator 42 is a circuit in which an odd number of signal inversion circuits, such as inverter circuits, are connected in a ring shape, and outputs an output pulse signal, which is an oscillation signal. The counter 44 counts the number of pulses of the output pulse signal of the ring oscillator 42 using a clock signal based on the oscillation signal OSC and outputs temperature detection data DTD based on the count value obtained by the counting process. The counter control unit 46 controls the counter 44. For example, the counter 44 calculates the temperature detection data DTD by calculating the count value of the number of pulses of the output pulse signal during a count period defined by the clock signal.

[0041] The arithmetic circuit 61 performs arithmetic processing to adjust the temperature sensitivity of the temperature detection data DTD, and outputs the processed temperature detection data DTD to the lookup table LUT. The temperature sensitivity of the temperature detection data DTD is the degree of change in the temperature detection data DTD in response to a temperature change. The arithmetic processing of the arithmetic circuit 61 will be described in detail later with reference to FIGS. 11 and 12. Note that the arithmetic circuit 61 may be omitted and the temperature detection data DTD from the temperature sensor circuit 40 may be directly input to the lookup table LUT.

[0042] A nonvolatile memory 72 corresponding to the memory 70 in FIG. 1 stores a lookup table LUT that associates the temperature detection data DTD with the frequency adjustment data DFC. For example, in the lookup table LUT, each value of the temperature detection data DTD is associated with each value of the frequency adjustment data DFC. For example, the temperature detection data DTD is data that monotonically increases or decreases with temperature. Then, as shown in FIG. 4, an arithmetic circuit 61 is provided, which performs arithmetic processing to adjust the temperature sensitivity of the temperature detection data DTD. That is, arithmetic processing is performed to adjust the degree of change in the temperature detection data DTD relative to changes in temperature. As a result, in the temperature detection data DTD after arithmetic processing, the slope of the change in the temperature detection data DTD relative to changes in temperature differs depending on the temperature range.

[0043] The temperature compensation circuit 60 references the lookup table LUT and outputs frequency adjustment data DFC corresponding to the temperature detection data DTD. For example, the temperature compensation circuit 60 reads out the frequency adjustment data DFC corresponding to the temperature detection data DTD from the lookup table LUT and outputs it to the variable capacitance circuit 32, which is a frequency adjustment circuit of the oscillation circuit 30. By adjusting the capacitance of the variable capacitance circuit 32 using the frequency adjustment data DFC based on the temperature detection data DTD in this way, the oscillation frequency of the oscillation circuit 30 is adjusted, and temperature compensation processing of the oscillation frequency is realized.

[0044] 4, the circuit device 20 includes a calculation circuit 61 that performs a calculation process to adjust the temperature sensitivity and outputs the processed temperature detection data DTD to the lookup table LUT. For example, the calculation circuit 61 performs a conversion process to change the slope of the temperature detection data DTD relative to the temperature in a first temperature range from the slope of the temperature detection data DTD relative to the temperature in a second temperature range, as the calculation process to adjust the temperature sensitivity. By providing the calculation circuit 61 that performs such a calculation process to adjust the temperature sensitivity, even if the temperature sensitivity varies depending on the temperature range, it becomes possible to perform a calculation process to appropriately adjust the temperature sensitivity and output the processed temperature detection data DTD to the lookup table LUT.

[0045] 4, the temperature detection data DTD after the arithmetic processing by the arithmetic circuit 61 is output to the outside via the interface circuit 80. By outputting the temperature detection data DTD after the arithmetic processing in this manner, it is possible to output temperature detection data DTD with reduced individual variation compared to when outputting the temperature detection data DTD before the arithmetic processing. However, this embodiment is not limited to this, and the temperature detection data DTD before the arithmetic processing by the arithmetic circuit 61 may be output to the outside via the interface circuit 80.

[0046] As shown in FIG. 4 , the circuit device 20 also includes an interrupt signal generation circuit 62 that generates an interrupt signal INT. The interrupt signal generation circuit 62 generates the interrupt signal INT when the temperature detection data DTD exceeds an upper limit value UL or falls below a lower limit value LL. The upper limit value UL and the lower limit value LL may be written by the external processing device 100 via, for example, the interface circuit 80, or may be stored in a memory 70 such as the non-volatile memory 72. The generated interrupt signal INT is output to the external processing device 100 via, for example, the interface circuit 80. The provision of such an interrupt signal generation circuit 62 makes it possible to notify the external processing device 100 that the temperature corresponding to the temperature detection data DTD has exceeded the upper limit temperature or fallen below the lower limit temperature. This allows the external processing device 100 to execute interrupt processing corresponding to the interrupt signal INT.

[0047] The interrupt signal generating circuit 62 includes a first register 63, a second register 64, and a comparison circuit 65, as shown in FIG. 4 . The first register 63 stores an upper limit value UL, and the second register 64 stores a lower limit value LL. The comparison circuit 65 compares the temperature detection data DTD with the upper limit value UL or the lower limit value LL to generate the interrupt signal INT. The first register 63 and the second register 64 can be implemented by storage circuits such as flip-flop circuits. The external processing device 100 may write the upper limit value UL and the lower limit value LL to the first register 63 and the second register 64 via, for example, an interface circuit 80. Alternatively, a memory 70 such as a nonvolatile memory 72 may store the upper limit value UL and the lower limit value LL, and the upper limit value UL and the lower limit value LL may be loaded from the memory 70 into the first register 63 and the second register 64. The comparison circuit 65 includes comparators 66 and 67 and an OR circuit 68. The comparator 66 compares the value of the temperature detection data DTD with an upper limit value UL, and outputs a first comparison signal that becomes active when the value of the temperature detection data DTD exceeds the upper limit value UL. The comparator 67 compares the value of the temperature detection data DTD with a lower limit value LL, and outputs a second comparison signal that becomes active when the value of the temperature detection data DTD falls below the lower limit value LL. The OR circuit 68 outputs an interrupt signal INT that becomes active when either the first comparison signal from the comparator 66 or the second comparison signal from the comparator 67 becomes active. This interrupt signal INT is output to the outside, for example, via an interface circuit 80.

[0048] The interrupt signal generation circuit 62 configured as above stores an upper limit value UL and a lower limit value LL in the first register 63 and the second register 64, and generates an interrupt signal INT by comparing the upper limit value UL and the lower limit value LL with the temperature detection data DTD. This interrupt signal INT can then be used to notify an external processing device 100 or the like that the temperature corresponding to the temperature detection data DTD has exceeded the upper limit temperature or fallen below the lower limit temperature.

[0049] In this embodiment, the upper limit value UL and the lower limit value LL may be stored in a memory 70 such as a nonvolatile memory 72. For example, during manufacturing and testing of the circuit device 20 or the oscillator 4, an external device writes the upper limit value UL and the lower limit value LL calculated based on the correction data DCT to the memory 70 via the interface circuit 80. This allows the upper limit value UL and the lower limit value LL, corrected for individual variations based on the correction data DCT, to be written and stored in the memory 70. During normal operation of the circuit device 20 or the oscillator 4, the upper limit value UL and the lower limit value LL are loaded from the memory 70 to the first register 63 and the second register 64, and the interrupt signal generation circuit 62 generates an interrupt signal INT by comparing the loaded upper limit value UL and the lower limit value LL with the temperature detection data DTD. This allows the interrupt signal generation circuit 62 to output an appropriate interrupt signal INT generated by comparing the upper limit value UL and the lower limit value LL, corrected for individual variations, with the temperature detection data DTD.

[0050] 3 and 4, the temperature sensor circuit 40 outputs the temperature detection data DTD, and the nonvolatile memory 72, which is the memory 70, stores the correction data DCT. The interface circuit 80 then outputs the temperature detection data DTD and the correction data DCT to the outside. In this manner, the external processing device 100, for example, shown in FIG. 13, can perform a calculation process to correct the temperature detection data DTD based on the correction data DCT, thereby enabling accurate temperature detection.

[0051] For example, FIGS. 5 and 6 show configuration examples of comparative examples of this embodiment. In FIG. 5, an analog correction circuit 48 is provided in the temperature sensor circuit 40, and this analog correction circuit 48 corrects the temperature detection data DTD by correcting, for example, the current flowing through a transistor constituting a delay element of the ring oscillator 42. That is, the analog correction circuit 48 corrects the individual differences in the characteristics of the temperature detection data DTD with respect to the temperature described in FIG. 2. The interface circuit 80 then outputs the temperature detection data DTD thus corrected to the outside. Also, in FIG. 6, a digital correction circuit 49 is provided in the temperature sensor circuit 40, and this digital correction circuit 49 performs digital correction on the temperature detection data DTD output from the counter 44, thereby correcting the individual differences in the characteristics of the temperature detection data DTD with respect to the temperature.

[0052] 5 and 6, in which correction is performed using an analog correction circuit 48 or a digital correction circuit 49, the power consumption of the circuit device 20 increases due to the power consumption of the analog correction circuit 48 or the digital correction circuit 49. Furthermore, providing the analog correction circuit 48 or the digital correction circuit 49 increases the layout area of ​​the circuit of the circuit device 20, which increases costs. Furthermore, correction using the analog correction circuit 48 in FIG. 5 does not provide high accuracy in correcting individual variations, which causes a problem of degraded temperature measurement accuracy.

[0053] For example, in a circuit device 20 that performs temperature compensation processing using a lookup table (LUT), correction of temperature detection variations by the analog correction circuit 48 or the digital correction circuit 49 is essentially unnecessary. This is because in a circuit device 20 configured as such, both variations in temperature detection by the temperature sensor circuit 40 and variations in the temperature characteristics of the resonator 10 are corrected using the lookup table (LUT). However, in an oscillator 4 such as an RTC, the circuit device 20 cannot predict when the external processing device 100 will read the temperature detection data DTD. Furthermore, even if an interrupt is generated when an event occurs in which the temperature detected by the temperature detection data DTD exceeds an upper temperature limit or falls below a lower temperature limit, the circuit device 20 cannot predict when the event will occur. For this reason, in the comparative examples of FIGS. 5 and 6, correction of temperature detection variations by the analog correction circuit 48 or the digital correction circuit 49 is necessary, even though it is essentially unnecessary. This results in unnecessary power consumption by these circuits.

[0054] In this regard, according to the circuit device 20 of the present embodiment shown in FIGS. 1, 3, and 4, the temperature detection data DTD from the temperature sensor circuit 40 is output from the interface circuit 80 without correcting for variations in temperature detection. Correction data DCT for correcting the temperature detection data DTD to calculate the temperature is stored in a memory 70, such as a nonvolatile memory 72. The temperature detection data DTD without correction for variations in temperature detection and the correction data DCT from the memory 70 are output to the outside via the interface circuit 80. This allows an external processing device 100 to read the temperature detection data DTD and correction data DCT from the circuit device 20 and correct the temperature detection data DTD based on the correction data DCT to accurately detect the temperature. This temperature detection correction process is performed only the minimum number of times necessary throughout the entire system, thereby reducing power consumption throughout the entire system. Furthermore, according to this embodiment, the circuit device 20 does not need to include an analog correction circuit 48 or a digital correction circuit 49, as shown in FIGS. 5 and 6. This solves the problem of unnecessary power consumption due to corrections in the analog correction circuit 48 and the digital correction circuit 49, and the resulting increase in circuit size and cost caused by these circuits. The external processing device 100 that corrects the temperature detection data DTD based on the correction data DCT is realized by, for example, an MCU (Micro Controller Unit). Since the MCU has a computing unit, it has the advantage of being able to correct the temperature detection data DTD based on the correction data DCT and detect the temperature without adding hardware resources.

[0055] 7 and 8 are explanatory diagrams illustrating the setting of the upper limit value UL and the lower limit value LL and the generation of the interrupt signal INT in the comparative example of FIGS. 5 and 6. As shown in FIG. 7, in the comparative example, the upper limit value UL and the lower limit value LL are fixed values. For example, in FIG. 7, the upper limit value UL corresponding to 65°C is set to a fixed value of 1012, and the lower limit value LL corresponding to 0°C is set to a fixed value of 128. As shown in FIG. 8, when the temperature exceeds the upper limit temperature of 65°C and the value of the temperature detection data DTD exceeds the upper limit value UL=1012, the interrupt signal INT is generated. Also, when the temperature falls below the lower limit temperature of 0°C and the value of the temperature detection data DTD falls below the lower limit value LL=128, the interrupt signal INT is generated. As described above, in the comparative examples of FIGS. 5 and 6, because the upper limit value UL and the lower limit value LL are fixed values, the analog correction circuit 48 and the digital correction circuit 49 correct the temperature detection data DTD each time the temperature is measured. This results in unnecessary power consumption each time the temperature is measured.

[0056] 9 and 10 are explanatory diagrams illustrating the setting of the upper limit value UL and the lower limit value LL and the generation of the interrupt signal INT in this embodiment. As shown in FIG. 9 , in this embodiment, the upper limit value UL and the lower limit value LL are not fixed values ​​but are calculated based on the correction data DCT. For example, during actual operation of the circuit device 20, an external processing device 100 calculates the upper limit value UL and the lower limit value LL based on the correction data DCT and writes them to the first register 63 and the second register 64. Alternatively, during manufacturing and inspection of the circuit device 20 or the oscillator 4, an external device may calculate the upper limit value UL and the lower limit value LL and write them to the memory 70, and then load them from the memory 70 to the first register 63 and the second register 64 during actual operation. As shown in FIG. 10 , when the temperature exceeds the upper limit temperature of 65°C and the value of the temperature detection data DTD exceeds the upper limit value UL, an interrupt signal INT is generated. Similarly, when the temperature falls below the lower limit temperature of 0°C and the value of the temperature detection data DTD falls below the lower limit value LL, an interrupt signal INT is generated. In this case, in this embodiment, there is no need to provide the analog correction circuit 48 or the digital correction circuit 49, and therefore it is possible to prevent unnecessary power consumption by these circuits.

[0057] 3. Arithmetic circuit Next, the details of the arithmetic processing of the arithmetic circuit 61 in Fig. 4 will be explained. Fig. 11 shows the relationship between the temperature characteristic of the oscillation frequency and address assignment when the temperature detection data DTD output by the temperature sensor circuit 40 is used as an address of the lookup table LUT as is. Here, an example is shown in which the temperature detection data DTD is linear with respect to temperature, but it is sufficient for the temperature detection data DTD to be approximately linear with respect to temperature. Also, an example is shown in which the temperature characteristic of the oscillation frequency is quadratic with respect to temperature, but it is sufficient for the temperature characteristic to be such that the temperature sensitivity of the oscillation frequency changes depending on the temperature.

[0058] The temperature characteristics shown in Figure 11 are quadratic characteristics that are convex upward with the peak near room temperature. UT1 to UT3 are temperature ranges within a unit temperature range. Temperature range UT1 is near room temperature, and the frequency change per unit temperature FW1 is small. Temperature range UT2 is slightly away from room temperature, and the frequency change per unit temperature FW2 is medium. Temperature range UT3 is even further away from room temperature than temperature range UT2, and the frequency change per unit temperature FW3 is large. The frequency change per unit temperature corresponds to the temperature sensitivity of the oscillation frequency, and the further away from room temperature the temperature is, the greater the temperature sensitivity. The temperature sensitivity of the oscillation frequency is the degree of change in the oscillation frequency in response to a change in temperature.

[0059] The temperature ranges UT1 to UT3 of the unit temperature width correspond to the address ranges AW1 to AW3 of the lookup table LUT, and frequency change amounts FW1 to FW3 per unit temperature are assigned to these address ranges AW1 to AW3. Because the temperature detection data DTD is linear, the number of addresses included in each of the address ranges AW1 to AW3 is the same, so the frequency change amount per address is small in the temperature range UT1 and large in the temperature range UT3.

[0060] To achieve high-precision temperature compensation while efficiently utilizing the limited-capacity memory 70, it is desirable for the frequency change per address to be uniform. However, as described above, there are too many addresses assigned in the temperature range UT1 and not enough addresses assigned in the temperature range UT3. For example, reducing the number of addresses per unit temperature would optimize the assignment in the temperature range UT1, but the frequency change per address would increase in the temperature range UT3, reducing the accuracy of the temperature compensation. On the other hand, increasing the number of addresses per unit temperature would improve the accuracy of the temperature compensation in the temperature range UT3. However, in the temperature range UT1, the frequency change is small, but the address assignment increases, reducing the utilization efficiency of the memory 70. Thus, if the temperature detection data DTD output by the temperature sensor circuit 40 were used directly as the addresses of the lookup table LUT, it would be difficult to achieve high-precision temperature compensation while efficiently utilizing the limited-capacity memory 70, such as the nonvolatile memory 72.

[0061] FIG. 12 is a diagram showing an example of conversion of temperature detection data DTD by arithmetic processing by the arithmetic circuit 61. The arithmetic circuit 61 converts the temperature detection data DTD by arithmetic processing that adjusts the temperature sensitivity of the temperature detection data DTD. Here, for ease of understanding, the temperature detection data before conversion by the arithmetic circuit 61 is referred to as DTD, and the converted temperature detection data, which is the temperature detection data after conversion by the arithmetic circuit 61, is referred to as EDTD. The solid lines in FIG. 12 indicate the converted temperature detection data EDTD, and the dotted lines indicate a case where the temperature detection data DTD is used as is as the converted temperature detection data EDTD. In FIG. 12, the temperature detection data DTD and the converted temperature detection data EDTD are expressed in decimal numbers. Furthermore, EDTD[n:i+1], which are the upper bits of the converted temperature detection data EDTD, are shown as integers, and one integer value corresponds to one address.

[0062] 12, a larger value of the temperature detection data DTD corresponds to a higher temperature, and the range of 0 to 72 of the temperature detection data DTD corresponds to the operating temperature range of the circuit device 20. Here, the operating temperature range is divided into a temperature range RTC corresponding to the range of 0 to 24 of the temperature detection data DTD, a temperature range RTE corresponding to the range of 24 to 32 of the temperature detection data DTD, and a temperature range RTA corresponding to the range of 32 to 72 of the temperature detection data DTD. The temperature range RTE is near room temperature, and as described in FIG. 11, is a temperature range in which the temperature sensitivity of the oscillation frequency is small in the temperature characteristics of the oscillation frequency. The temperature ranges RTC and RTA are temperature ranges in which the temperature sensitivity of the oscillation frequency is greater than room temperature in the temperature characteristics of the oscillation frequency.

[0063] The arithmetic circuit 61 outputs the converted detected temperature data EDTD by not changing the slope of the detected temperature data DTD corresponding to the temperature range RTE near room temperature and by adding an offset to the detected temperature data DTD. The arithmetic circuit 61 also multiplies the slope of the detected temperature data DTD corresponding to the temperature ranges RTC and RTA, where the temperature sensitivity of the oscillation frequency is high, by 1.5 and by adding an offset to the detected temperature data DTD. The offset value added in the offset addition process is set so that the lower limit of the converted detected temperature data EDTD in the operating temperature range does not become negative. In FIG. 12, the offset value is set so that the lower limit of the converted detected temperature data EDTD is zero, but it is sufficient to set the offset value so that the lower limit of the converted detected temperature data EDTD is greater than zero.

[0064] In this way, the arithmetic circuit 61 performs arithmetic processing to adjust the temperature sensitivity of the temperature detection data DTD. For example, in the temperature ranges RTC and RTA in FIG. 12, arithmetic processing is performed to adjust the temperature sensitivity of the temperature detection data DTD so that the slope of the temperature detection data DTD becomes larger. This makes it possible to adjust the temperature sensitivity so that the temperature sensitivity of the temperature detection data DTD becomes larger in the temperature ranges RTC and RTA where the temperature sensitivity of the oscillation frequency is large. That is, according to this embodiment, the conversion processing of the temperature detection data DTD is performed so that the slope of the temperature detection data DTD varies depending on the temperature range. This makes it possible to adjust the slope of the temperature detection data DTD according to the temperature sensitivity in the temperature characteristics of the oscillation frequency. Specifically, the absolute value of the slope of the temperature detection data DTD can be increased in a temperature range where the temperature sensitivity is large, and the absolute value of the slope of the temperature detection data DTD can be decreased in a temperature range where the temperature sensitivity is small. Since the address of the lookup table LUT is specified by the temperature detection data DTD, the larger the absolute value of the slope of the temperature detection data DTD, the larger the number of addresses per unit temperature. This allows the address allocation per unit temperature to be large in temperature ranges with high temperature sensitivity, and small in temperature ranges with low temperature sensitivity, thereby achieving highly accurate temperature compensation while efficiently utilizing the limited capacity of memory 70.

[0065] 4. Interface circuit, processing system Next, detailed examples of the interface circuit 80 and the processing system 200 of this embodiment will be described. As shown in FIG. 13 , the processing system 200 of this embodiment includes an oscillator 4 and a processing device 100 electrically connected to the oscillator 4. For example, the oscillator 4 and the processing device 100 are electrically connected via wiring on a circuit board or the like. The processing system 200 is incorporated into, for example, an electronic device. The electronic device may be, for example, a network-related device such as a base station or a router; a high-precision measuring device that measures physical quantities such as distance, time, flow velocity, or flow rate; a biometric measuring device that measures biometric information; or an in-vehicle device. The electronic device may also be a mesh network device for sensors, an Internet of Things (IoT) device, a wearable device such as a head-mounted display device or a watch-related device, a robot, a printing device, a projection device, a mobile information terminal such as a smartphone, a content provider that distributes content, or an imaging device such as a digital camera or a video camera.

[0066] The processing device 100 can be realized by a processor such as an MPU (Micro Processor Unit), MCU (Micro Controller Unit), or CPU (Central Processing Unit), or a circuit device such as an ASIC (Application Specific Integrated Circuit). For example, the processing device 100, which is an external device, may include the circuit device and a circuit board on which the circuit device is mounted. The processing device 100 then performs arithmetic processing to correct the temperature detection data DTD based on the correction data DCT, thereby detecting the temperature. That is, as described with reference to FIGS. 1 and 3, the interface circuit 80 of the circuit device 20 transmits the temperature detection data DTD and the correction data DCT as a data signal DA, and the external processing device 100 receives the temperature detection data DTD and the correction data DCT. Specifically, the processing device 100 includes an interface circuit 110, which receives the temperature detection data DTD and the correction data DCT. The processing device 100 then performs arithmetic processing to correct the temperature detection data DTD based on the correction data DCT, thereby detecting the temperature corresponding to the temperature detection data DTD. The calculation process for correcting the temperature detection data DTD can be executed by a program running on the processor of the processing device 100, for example.

[0067] As described above, according to the processing system 200 of FIG. 13 , the process of correcting the temperature detection data DTD based on the correction data DCT and detecting the temperature is performed not by the circuit device 20 but by the external processing device 100. Therefore, the processing device 100 executes the process of correcting the temperature detection data DTD based on the correction data DCT and detecting the temperature when it needs to detect the temperature. For example, in the comparative examples of FIGS. 5 and 6 , the analog correction circuit 48 and the digital correction circuit 49 constantly execute the correction process for temperature detection, even when temperature detection is not required, resulting in unnecessary power consumption. In contrast, in FIG. 5 , the correction process for temperature detection is executed only the minimum number of times necessary throughout the entire processing system 200, thereby reducing the overall power consumption of the processing system 200.

[0068] 13, the circuit device 20 includes a clock output pad PCK, an output circuit 90 that outputs a clock signal CK based on the oscillation signal OSC to an external processing device 100 via the clock output pad PCK, and a first pad PDA. The clock output pad PCK is electrically connected to a clock output terminal TCK of the oscillator 4, and the first pad PDA is electrically connected to a first terminal TDA of the oscillator 4. The output circuit 90 also outputs a signal obtained by buffering the oscillation signal OSC as the clock signal CK based on the oscillation signal OSC.

[0069] Alternatively, a PLL circuit may be provided to generate a clock signal CK having a frequency multiplied by the frequency of the oscillation signal OSC from the oscillation circuit 30, and the output circuit 90 may output the clock signal CK from this PLL circuit to the clock output pad PCK. In this case, the clock signal CK based on the oscillation signal OSC has a frequency multiplied by the frequency of the oscillation signal OSC. For example, the PLL circuit may have a voltage-controlled oscillator circuit, compare the phase of the oscillation signal OSC, which is a reference clock signal, with a feedback clock signal, and output a clock signal CK having a frequency multiplied by the frequency of the oscillation signal OSC. In this case, the PLL circuit may be, for example, a fractional-N PLL circuit capable of fractional frequency multiplication.

[0070] The interface circuit 80 communicates with the processing device 100 using a data signal DA. Specifically, the processing device 100 has an interface circuit 110, and serial communication using the data signal DA is performed between the interface circuit 110, which acts as a master, and the interface circuit 80, which acts as a slave. For example, the processing device 100 has a data terminal EDA through which the data signal DA is input and output, a clock input terminal ECK through which a clock signal CK is input, a power supply terminal EVDD through which VDD is supplied, and a ground terminal EGND through which GND is supplied. The interface circuit 110 of the processing device 100 communicates with the interface circuit 80 using the clock signal CK input to the clock input terminal ECK and the data signal DA input and output by the data terminal EDA.

[0071] In this communication, the output circuit 90 outputs a clock signal CK to the processing device 100, which is the master of the communication. While the master normally outputs the clock signal for communication, in FIG. 13, the slave output circuit 90 outputs the clock signal CK. The interface circuit 80, which is the slave of the communication, receives a data signal DA synchronized with the clock signal CK from the processing device 100 via the first pad PDA. The processing device 100, which is the master, transmits the data signal DA synchronized with the clock signal CK from the slave, and the interface circuit 80, which is the slave, receives the transmitted data signal DA. Alternatively, the interface circuit 80, which is the slave of the communication, transmits the data signal DA to the processing device 100 via the first pad PDA in synchronization with the clock signal CK. The interface circuit 80, which is the slave, transmits the data signal DA synchronized with the clock signal CK, and the processing device 100, which is the master, receives the transmitted data signal DA. In this way, synchronous communication of the data signal DA becomes possible between the processing device 100, which is the communication master, and the interface circuit 80, which is the communication slave, based on the clock signal CK output by the slave side.

[0072] 13, a pull-up resistor RP is provided between the data line for the data signal DA and the power supply line for VDD. This pulls up the data line connecting the processing device 100 and the interface circuit 80. That is, the data line is pulled up to the power supply voltage level of VDD. In this way, when neither the interface circuit 80 nor the processing device 100 drives the data line low, the data line is pulled up to the high level, which is the power supply voltage level of VDD. Specifically, when the interface circuit 80 or the interface circuit 110 of the processing device 100 includes an I / O circuit 82 having an open-drain N-type transistor TR shown in FIG. 14 (described later), the data line is pulled up to the high level when the transistor TR is off. This enables serial data communication using the data line.

[0073] In FIG. 13, a pull-up resistor RP is provided between the data line for the data signal DA and the power supply line for VDD, but such a pull-up resistor RP may not be provided.

[0074] 13 is a four-terminal oscillator having a power supply terminal TVDD, a ground terminal TGND, a clock output terminal TCK, and a first terminal TDA. With such an oscillator 4 having a small number of terminals, the issue is how to achieve communication with an external processing device 100.

[0075] 13, a conceivable method is to set the operation mode to the communication mode during manufacturing and inspection, switch the clock output terminal TCK to a clock input terminal for communication, and switch the first terminal TDA, which is an output enable terminal, to a data terminal for communication. Then, a clock signal for communication from the master processing device 100 is input to the clock output terminal TCK, which has been switched to the clock input terminal, and communication of the data signal DA is performed using the first terminal TDA, which has been switched to the data terminal for communication.

[0076] However, in the method of this comparative example, the clock output terminal TCK is switched to a clock input terminal for communication, so the clock signal CK based on the oscillation signal OSC of the oscillator circuit 30 cannot be output from the clock output terminal TCK. Therefore, if the master processing device 100 is operating based on this clock signal CK or if there is another external device that operates using this clock signal CK, the processing device 100 and the other external device cannot operate based on the clock signal CK in the communication mode. In other words, it is not possible to output the clock signal CK to the outside and to communicate with the processing device 100 at the same time.

[0077] In this regard, according to the configuration of FIG. 13 , communication with the processing device 100 is performed using the clock signal CK output by the oscillator 4. That is, while communication with the processing device 100 is normally performed using a clock signal for communication output by the master, in FIG. 13 , communication with the processing device 100 is performed using the clock signal CK output by the oscillator 4, which is the slave. Therefore, unlike the method of the comparative example described above, it is not necessary to set the operating mode to a communication mode and switch the clock output terminal TCK to a clock input terminal for communication. Then, while outputting the clock signal CK from the clock output terminal TCK to the processing device 100 or other external devices, communication with the processing device 100 using the clock signal CK and the data signal DA can be performed. Therefore, even if the number of terminals of the oscillator 4 is small, for example, four terminals, it is possible to simultaneously output the clock signal CK from the clock output terminal TCK and communicate with the processing device 100 using the clock signal CK and the data signal DA.

[0078] Furthermore, even if the number of terminals of the oscillator 4 is five or more, for example, if the oscillator 4 is provided with a clock input terminal for communication, there is a problem in that noise due to the clock signal for communication input to the clock input terminal for communication adversely affects the signal characteristics of the clock signal CK. That is, in this case, since the clock signal CK output from the oscillator 4 and the clock signal for communication from the processing device 100 are asynchronous, noise due to the clock signal for communication is superimposed on the clock signal CK, causing noise such as jitter noise in the clock signal CK.

[0079] 13, communication with the processing device 100 is performed using the clock signal CK output by the oscillator 4 to the outside, instead of the clock signal for communication output by the processing device 100. That is, the clock signal CK output by the oscillator 4 to the outside is used as the clock signal for communication with the processing device 100. This makes it possible to effectively prevent the above-mentioned problem of noise due to the clock signal for communication being superimposed on the clock signal CK, thereby degrading the clock signal characteristics.

[0080] 13, the output circuit 90 outputs the clock signal CK even during periods other than the communication period. For example, the output circuit 90 outputs the clock signal CK during the communication period, and also outputs the clock signal CK during periods other than the communication period. In this way, the clock signal CK can be supplied to the processing device 100 or other external devices even during periods other than the communication period. This allows the processing device 100 or other external devices to operate using the clock signal CK as an operating clock signal or to perform predetermined processing based on the clock signal CK.

[0081] As an example of application of FIG. 13 , a 32 kHz clock signal CK from oscillator 4 may be supplied to an RTC circuit in a processing device 100, such as a microcomputer, to perform calendar timekeeping in the RTC. In this case, the calendar timekeeping must be performed without interruption, so the clock signal CK from oscillator 4 must be constantly supplied to the RTC circuit of the processing device 100. Meanwhile, while performing such calendar timekeeping, the processing device 100 may detect, for example, the environmental temperature and issue a warning if the temperature exceeds an upper limit or falls below a lower limit. In this case, the processing device 100 can effectively utilize the temperature detection data DTD from the temperature sensor circuit 40 of oscillator 4 to detect the temperature based on the temperature detection data DTD output from oscillator 4 via interface circuit 80, thereby issuing a warning. 13, the temperature detection data DTD from the oscillator 4 can be transmitted to the processing device 100 during communication, and the clock signal CK from the oscillator 4 can be constantly supplied to the RTC circuit during communication and periods other than communication, thereby realizing calendar timing processing. Therefore, the processing device 100 can simultaneously perform temperature detection based on the temperature detection data DTD and calendar timing processing based on the clock signal CK.

[0082] 14 shows an example of the configuration of an I / O circuit 82 included in the interface circuit 80 or the interface circuit 110. The I / O circuit 82 includes an open-drain N-type transistor TR and an input buffer BF. The IN / OUT terminals in FIG. 14 correspond to the first terminal TDA or the data terminal EDA in FIG. 13. The first terminal TDA corresponds to the data terminal of the oscillator 4.

[0083] The output signal OUT from the internal circuit is input to the gate of transistor TR after being buffered by, for example, an inverter IV. For example, when the output signal OUT goes low and the gate of transistor TR goes high, transistor TR turns on and the data line is driven low. On the other hand, when the output signal OUT goes high and the gate of transistor TR goes low, transistor TR turns off. In this case, the data line is pulled up to high by resistor RP in Figure 13. This makes it possible to transmit a data signal DA using the output signal OUT.

[0084] The IN / OUT terminal is connected to an input buffer BF, and the input signal IN at the IN / OUT terminal is buffered by the input buffer BF and input to the internal circuit, making it possible to receive a data signal DA using the input signal IN.

[0085] In a configuration in which the pull-up resistor RP of FIG. 13 is not provided, the I / O circuit 82 of FIG. 14 may be provided with a push-pull output circuit composed of a P-type transistor and an N-type transistor arranged in series between VDD and GND, for example, instead of the open-drain N-type transistor TR.

[0086] 15 and 16 are signal waveform diagrams illustrating an example of communication in this embodiment. FIG. 15 is a signal waveform diagram for a data write in which the processing device 100, which is the master, writes data to the oscillator 4. This data write by the master corresponds to data reception by the interface circuit 80 of the oscillator 4, which is the slave. FIG. 16 is a signal waveform diagram for a data read in which the processing device 100 reads data from the oscillator 4. This data read by the master corresponds to data transmission by the interface circuit 80 of the oscillator 4, which is the slave. Note that in FIGS. 15 and 16, the low level by the slave is shown as a schematic potential lower than the low level by the master, so that it is possible to distinguish between a case in which the master outputs a low level and a case in which the slave outputs a low level.

[0087] In the data write operation shown in FIG. 15 , the processing device 100, which is the master, transmits a communication start key, and the interface circuit 80, which is the slave, receives this communication start key. In this case, the processing device 100, which is the master, transmits the communication start key in synchronization with a clock signal CK from the slave. The interface circuit 80, which is the slave, then receives the communication start key in synchronization with the clock signal CK, determines whether the received communication start key is a key with an appropriate code according to the protocol, and determines that communication has started if it is a key with an appropriate code. In this manner, in this embodiment, the interface circuit 80 starts communication on the condition that it receives a communication start key from the processing device 100. In this manner, communication between the master and the slave is started on the condition that a communication start key with an appropriate code has been transmitted from the master to the slave, and appropriate communication between the master and the slave can be started using the communication start key as the starting point. Note that in this embodiment, the processing device 100 will be referred to simply as the master, and the interface circuit 80 will be referred to simply as the slave, as appropriate.

[0088] After sending the communication start key, the master outputs R / XW, which specifies whether it is a write or a read. In this R / XW, X represents negative logic, and the master outputs a high level when reading data, and a low level when writing data. In Figure 15, since it is a data write, the master outputs a low level as the XW of R / XW. That is, a low level is output when the open-drain N-type transistor in the master-side I / O circuit 82 in Figure 14 turns on.

[0089] In this way, when the master outputs a low level after the communication start key, the slave outputs an SLA indicating the slave's acknowledgement. Specifically, the slave outputs a low level as the SLA. As mentioned above, the low level by the slave is shown in FIG. 15 as a low level with a lower potential to distinguish it from the low level by the master.

[0090] When the slave outputs a low level as SLA in this way, the master writes an address to the slave. This address specifies the register in the slave to which data will be written. In this address write, the master sends address information as a data signal DA, and the slave receives this address information.

[0091] After the address write, the master outputs P / XC. P means Stop, which stops communication, and XC means Continue, which continues communication. The X in XC also stands for negative logic. In Figure 15, to continue communication, the master outputs a low level as the XC in P / XC. The master then sends the data to be written to the address specified in the address write as a data signal DA. This causes data from the master to be written to the register of the specified address among the registers in oscillator 4.

[0092] In the case of a data read in Figure 16, the master first sends a communication start key, and the slave receives this communication start key. Since Figure 16 is a data read, the master outputs a high level as the R in R / XW. The slave then outputs a low level as the SLA, which is an acknowledgement.

[0093] After the slave outputs the SLA in this way, a data read is performed. As will be described later, in this data read, the address for the data read is specified in advance. The data read in FIG. 16 is a slave write in which the slave writes data to the data line of the data signal DA. That is, the data read from the slave is written to the data line and transmitted to the master. Then, when the master outputs a low level as the XC of the P / XC to instruct the continuation of communication, the next data read is performed.

[0094] FIG. 17 is an explanatory diagram of an example of a communication protocol of this embodiment. In the data write of FIG. 17, the master outputs an 8-bit communication start key and XW, and then the slave outputs a 1-bit SLA. The master then writes an 8-bit address to specify the write address. The master then outputs a 1-bit XC to instruct the continuation of communication, and then transmits 8-bit data to the slave. This causes the slave to write the data to the specified write address. Next, the master outputs an XC to instruct the continuation of communication, and then transmits the next data. In this case, the write address is automatically updated in the slave, and the data from the master is written to the updated next write address. Then, the master outputs an XC to instruct the continuation of communication, and then transmits the next data to write to the slave. Then, when there is no more data to write next, the master outputs a 1-bit P to instruct the slave to stop communication.

[0095] Also, in the data read of Figure 17, after the master outputs an 8-bit communication start key and XW, the slave outputs a 1-bit SLA. Then the master writes an 8-bit address to specify the data read address, and then outputs a 1-bit P to instruct communication to stop. Next, the master outputs an 8-bit communication start key and R, and after the slave outputs a 1-bit SLA, the master reads and receives the 8-bit data from the slave. The data read address in this case is the address specified before the data read, as described above. Next, the master outputs XC to instruct communication to continue, and then reads and receives the next data from the slave. In this case, the data read address is automatically updated. Then, when there is no more data to read next, the master outputs a 1-bit P to instruct communication to stop.

[0096] As described above, in this embodiment, during the data write shown in FIG. 17 , when the processing device 100 outputs a low level after receiving the first data of a predetermined number of bits, the interface circuit 80 determines that communication has continued and receives the next second data of a predetermined number of bits. That is, during the data write by the master shown in FIG. 17 , the interface circuit 80, which is the slave, receives the first data of a predetermined number of bits, i.e., 8 bits. Specifically, the first data transmitted by the master is received and written to a register. Note that the predetermined number of bits is not limited to 8 bits and may be 16 bits, 32 bits, or the like. Then, when the processing device 100 transmits the first data and then outputs a low level as an XC signal indicating that communication should continue, the interface circuit 80 determines that communication has continued. Then, when the processing device 100 transmits the second data after outputting a low level as an XC signal, the interface circuit 80 receives the transmitted second data and writes the received second data to a register. In this way, the interface circuit 80 can determine whether communication will continue or not by detecting whether the processing device 100 has output a low level after receiving the first data, and can then receive the next second data. This allows the interface circuit 80 to continuously receive multiple pieces of data with a predetermined number of bits, such as the first data and the second data. Furthermore, if the processing device 100 does not output a low level after transmitting the first data, the data line is pulled up by the resistor RP and set to a high level, as shown in Figure 13, so the interface circuit 80 can determine that communication has stopped and will not continue.

[0097] In this embodiment, during data read in FIG. 17 , when the processing device 100 outputs a low level after transmitting a predetermined number of first data bits, the interface circuit 80 determines that communication has continued and transmits the next predetermined number of second data bits. That is, during data read by the master in FIG. 17 , the slave interface circuit 80 transmits the first data bits of 8 bits, which is the predetermined number of bits. Then, when the processing device 100 subsequently outputs a low level as an XC command to continue communication, the interface circuit 80 determines that communication has continued and transmits the next second data bits. In this manner, the interface circuit 80 can determine whether communication will continue by detecting whether the processing device 100 outputs a low level after transmitting the first data bits, and then transmit the next second data bits. This allows the interface circuit 80 to continuously transmit multiple data bits of predetermined numbers, such as the first data bits and the second data bits. Furthermore, if the processing device 100 does not output a low level after the interface circuit 80 transmits the first data, the data line is pulled up by the resistor RP and set to a high level, so that the interface circuit 80 can determine that communication has stopped and not continued.

[0098] In FIGS. 15 to 17, communication is performed such that when the logical level is "0", it is a low level, and when the logical level is "1", it is a high level. However, the present embodiment is not limited to this. For example, the interface circuit 80 may output a data signal DA of a first bit pattern when the logical level is "0", and may output a data signal DA of a second bit pattern when the logical level is "1". For example, in the data signal DA of the first bit pattern, a low level is output in the first half period TF1, and a high level is output in the second half period TL1. On the other hand, in the data signal DA of the second bit pattern, a low level is output in the first half period TF2, and a high level is output in the second half period TL2. Here, the relationships TF1 > TF2 and TL1 < TL2 hold. Also, the relationship TF1 + TL1 = TF2 + TL2 holds. The periods TF1, TL1, TF2, and TL2 are periods of a predetermined number of clocks. As an example, the period TF1 is a period of 4 clocks of the clock signal CK, and the period TL1 is a period of 3 clocks. Also, the period TF2 is a period of 2 clocks, and the period TL2 is a period of 5 clocks. By doing so, even when the frequency of the clock signal CK is high, it is possible to prevent an error from occurring in the communication of the data signal DA based on the clock signal CK and to realize appropriate communication processing.

[0099] In other words, in Figure 13, when the frequency of the clock signal CK is low, such as 32 kHz, there is little problem. However, when the frequency of the clock signal CK is high, communication using this clock signal CK may result in a communication error. For example, when transmitting and receiving a data signal DA between a master and a slave in synchronization with the clock signal CK, if the frequency of the clock signal CK is high, sampling of the data signal DA may not be completed in time, resulting in a communication error. In this regard, if the interface circuit 80 is configured as described above to output a data signal DA with a first bit pattern when the logic level is "0" and to output a data signal DA with a second bit pattern when the logic level is "1," such communication errors can be prevented. This enables reliable and stable communication between the master and the slave.

[0100] 10, when the temperature detection data DTD exceeds the upper limit UL or falls below the lower limit LL, the interface circuit 80 outputs an interrupt signal INT that becomes a predetermined voltage level for a given period via the first pad PDA to the processing device 100. For example, in FIG. 18, the interface circuit 80 outputs the interrupt signal INT that becomes a low level, which is a predetermined voltage level, for a given period TA. For example, when the temperature detection data DTD exceeds the upper limit UL or falls below the lower limit LL, the interface circuit 80 outputs the interrupt signal INT that becomes a low level from a high impedance state for the period TA.

[0101] For example, as shown in FIG. 13, the data line of the data signal DA is pulled up by a resistor RP. Therefore, unless the interface circuit 80 or the processing device 100 drives the data line low, the data line remains pulled up to a high level. When the temperature detection data DTD exceeds an upper limit UL or falls below a lower limit LL, the interface circuit 80 drives the data line low and outputs an interrupt signal INT that goes low during a period TA, as shown in FIG. 18. This allows the processing device 100 to detect that the interface circuit 80 has output the interrupt signal INT by detecting the low level of the data line. Upon detecting the interrupt signal INT, the processing device 100 can then appropriately execute processing when the temperature exceeds the upper limit or falls below the lower limit. For example, the processing device 100 can execute a warning process to notify the user that the temperature has exceeded the upper limit or fallen below the lower limit.

[0102] 5. Oscillator FIG. 19 shows a first structural example of the oscillator 4 of this embodiment. The oscillator 4 has a resonator 10, a circuit device 20, and a package 15 that houses the resonator 10 and the circuit device 20. The package 15 is made of, for example, ceramic or the like, and has an internal storage space in which the resonator 10 and the circuit device 20 are housed. The storage space is hermetically sealed and is preferably in a reduced pressure state that is close to a vacuum. The package 15 can suitably protect the resonator 10 and the circuit device 20 from impact, dust, heat, moisture, and the like.

[0103] The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of the base 16, which supports the resonator 10 and the circuit device 20, and the lid 17, which is bonded to the upper surface of the base 16 so as to form an accommodation space between the base 16 and the lid 17. The resonator 10 is supported via terminal electrodes on a stepped portion provided on the inside of the base 16. The circuit device 20 is disposed on the inside bottom surface of the base 16. Specifically, the circuit device 20 is disposed so that its active surface faces the inside bottom surface of the base 16. The active surface is the surface on which circuit elements of the circuit device 20 are formed. Bumps BMP are formed on the terminals of the circuit device 20. The circuit device 20 is supported on the inside bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, and the resonator 10 and the circuit device 20 are electrically connected via the bumps BMP, the internal wiring of the package 15, and the terminal electrodes. The circuit device 20 is also electrically connected to external terminals 18 and 19 of the oscillator 4 via bumps BMP and internal wiring of the package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. This makes it possible to output a clock signal or the like to the external device.

[0104] 19, the circuit device 20 is flip-mounted so that the active surface of the circuit device 20 faces downward, but this embodiment is not limited to such mounting. For example, the circuit device 20 may be mounted so that the active surface of the circuit device 20 faces upward. In other words, the circuit device 20 is mounted so that the active surface faces the vibrator 10.

[0105] FIG. 20 shows a second structural example of the oscillator 4. The oscillator 4 includes a resonator 10, a circuit device 20, and a package 15 that houses the resonator 10 and the circuit device 20. The package 15 includes a base 16 and a lid 17. The base 16 includes a first substrate 6, which is an intermediate substrate; a second substrate 7 having a substantially rectangular frame shape and stacked on the top surface of the first substrate 6; and a third substrate 8 having a substantially rectangular frame shape and stacked on the bottom surface of the first substrate 6. The lid 17 is bonded to the top surface of the second substrate 7, and the resonator 10 is housed in a housing space S1 formed by the first substrate 6, the second substrate 7, and the lid 17. For example, the resonator 10 is hermetically sealed in the housing space S1, preferably in a reduced pressure state close to a vacuum. This allows the resonator 10 to be suitably protected from impact, dust, heat, moisture, and the like. The housing space S2 formed by the first substrate and the third substrate 8 houses a circuit device 20, which is a semiconductor chip. Furthermore, on the bottom surface of the third substrate 8, external terminals 18 and 19 are formed, which are electrode terminals for external connection of the oscillator 4.

[0106] In the accommodation space S1, the vibrator 10 is connected to a first electrode terminal and a second electrode terminal (not shown) formed on the upper surface of the first substrate 6 via conductive connection parts CDC1 and CDC2. The conductive connection parts CDC1 and CDC2 may be implemented by conductive bumps such as metal bumps or by a conductive adhesive. Specifically, for example, a first electrode pad (not shown) formed on one end of the tuning-fork-shaped vibrator 10 is connected to a first electrode terminal formed on the upper surface of the first substrate 6 via the conductive connection part CDC1. The first electrode terminal is then electrically connected to a pad PX1 of the circuit device 20. A second electrode pad (not shown) formed on the other end of the tuning-fork-shaped vibrator 10 is connected to a second electrode terminal formed on the upper surface of the first substrate 6 via the conductive connection part CDC2. The second electrode terminal is then electrically connected to a pad PX2 of the circuit device 20. This allows one end and the other end of the vibrator 10 to be electrically connected to the pads PX1 and PX2 of the circuit device 20 via the conductive connection parts CDC1 and CDC2. Furthermore, conductive bumps BMP are formed on a plurality of pads of the circuit device 20, which is a semiconductor chip, and these conductive bumps BMP are connected to a plurality of electrode terminals formed on the bottom surface of the first substrate 6. The electrode terminals connected to the pads of the circuit device 20 are then electrically connected to external terminals 18, 19 of the oscillator 4 via internal wiring or the like.

[0107] The oscillator 4 may be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes a semiconductor substrate, a base having a through electrode penetrating between the first and second surfaces of the semiconductor substrate, a resonator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding material such as a metal bump, and external terminals provided on the second surface of the semiconductor substrate via an insulating layer such as a relocation wiring layer. An integrated circuit serving as the circuit device 20 is formed on the first or second surface of the semiconductor substrate. In this case, a first semiconductor wafer having multiple bases on which the resonators 10 and the integrated circuits are arranged is bonded to a second semiconductor wafer having multiple lids, and the multiple bases and lids are then bonded together. The oscillators 4 are then individually separated using a dicing saw or the like. This allows for the realization of a wafer-level package oscillator 4, enabling high-throughput, low-cost manufacturing of the oscillators 4.

[0108] As described above, the circuit device of this embodiment includes an oscillation circuit that generates an oscillation signal using a vibrator, a temperature sensor circuit that outputs temperature detection data, a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data, a memory that stores correction data for correcting the temperature detection data to determine the temperature, and an interface circuit that outputs the temperature detection data and the correction data.

[0109] According to this embodiment, the oscillator circuit generates an oscillation signal using a resonator, and the temperature sensor circuit detects temperature and outputs temperature detection data. The temperature compensation circuit performs temperature compensation for the oscillation frequency of the oscillation signal based on the temperature detection data, and the memory stores correction data for correcting the temperature detection data to determine the temperature. The interface circuit then outputs the temperature detection data and the correction data to an external device. This makes it possible to perform arithmetic processing to correct the temperature detection data from the interface circuit based on the correction data from the interface circuit, thereby detecting a temperature corresponding to the temperature detection data. This makes it possible to provide a circuit device or the like that enables accurate temperature detection by effectively utilizing the temperature sensor circuit of the circuit device.

[0110] In this embodiment, the memory may store a lookup table that associates temperature detection data with frequency adjustment data, the temperature compensation circuit may reference the lookup table and output the frequency adjustment data corresponding to the temperature detection data, and the oscillation circuit may generate an oscillation signal with an oscillation frequency corresponding to the frequency adjustment data.

[0111] In this way, frequency adjustment data corresponding to the temperature detection data is output from the lookup table, and this frequency adjustment data is used to adjust the oscillation frequency of the oscillation circuit, thereby realizing temperature compensation processing of the oscillation frequency.

[0112] Furthermore, this embodiment may include a calculation circuit that performs calculation processing to adjust the temperature sensitivity and outputs the temperature detection data that has undergone the calculation processing to the look-up table.

[0113] In this way, even if the temperature sensitivity differs depending on the temperature range, it is possible to perform a calculation process to appropriately adjust the temperature sensitivity, and output the processed temperature detection data to the look-up table.

[0114] In this embodiment, the memory may be a non-volatile memory.

[0115] In this way, correction data for correcting the temperature detection data to obtain the temperature can be stored in the nonvolatile memory, and this correction data can be read out from the nonvolatile memory and output to the outside together with the temperature detection data via the interface circuit.

[0116] In this embodiment, the correction data may be coefficient data of a polynomial that indicates the relationship between the temperature and the temperature detection data.

[0117] In this way, when the characteristics showing the relationship between the temperature and the temperature detection data can be expressed or approximated by a polynomial, the coefficient data of this polynomial can be used as correction data.

[0118] In addition, this embodiment may include an interrupt signal generating circuit that generates an interrupt signal when the temperature detection data exceeds an upper limit value or falls below a lower limit value.

[0119] By providing such an interrupt signal generating circuit, it becomes possible to notify an external device that the temperature corresponding to the temperature detection data has exceeded the upper limit temperature or fallen below the lower limit temperature.

[0120] In addition, in this embodiment, the interrupt signal generating circuit may include a first register that stores an upper limit value, a second register that stores a lower limit value, and a comparison circuit that compares the temperature detection data with the upper limit value or the lower limit value to generate an interrupt signal.

[0121] In this way, an upper limit value and a lower limit value are stored in the first register and the second register, and an interrupt signal can be generated by comparing the upper limit value or the lower limit value with the temperature detection data using a comparison circuit.

[0122] In this embodiment, the memory may store the upper limit value and the lower limit value.

[0123] In this way, it becomes possible to write and store in memory the upper and lower limit values ​​that have been corrected for individual variations based on the correction data.

[0124] In this embodiment, the interface circuit may include a clock output pad, an output circuit that outputs a clock signal based on the oscillation signal to an external processing device via the clock output pad, and a first pad, and the interface circuit may communicate with the processing device using a data signal. In the communication, the output circuit outputs the clock signal to the processing device that is the master of the communication, and the interface circuit that is the slave of the communication may receive a data signal synchronized with the clock signal transmitted from the processing device via the first pad, or may transmit a data signal synchronized with the clock signal to the processing device via the first pad.

[0125] In this way, synchronous communication of data signals becomes possible between the processing device acting as the master of communication and the interface circuit acting as the slave of communication, based on the clock signal output by the slave side.

[0126] In this embodiment, the interface circuit may also output an interrupt signal to the processing device via the first pad, the interrupt signal being at a predetermined voltage level for a given period of time, when the temperature detection data exceeds an upper limit value or falls below a lower limit value.

[0127] In this way, the external processing device can detect that the interface circuit has output an interrupt signal by detecting a predetermined voltage level on the data line, and can then appropriately perform processing when the temperature exceeds the upper limit or falls below the lower limit.

[0128] The oscillator of this embodiment includes a resonator and a circuit device. The circuit device includes an oscillation circuit that generates an oscillation signal using the resonator, a temperature sensor circuit that outputs temperature detection data, a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data, a memory that stores correction data for correcting the temperature detection data to determine the temperature, and an interface circuit that outputs the temperature detection data and the correction data.

[0129] According to this embodiment, the oscillator circuit generates an oscillation signal using a resonator, and the temperature sensor circuit detects temperature and outputs temperature detection data. The temperature compensation circuit performs temperature compensation for the oscillation frequency of the oscillation signal based on the temperature detection data, and the memory stores correction data for correcting the temperature detection data to determine the temperature. The interface circuit then outputs the temperature detection data and the correction data to an external device. This makes it possible to perform arithmetic processing to correct the temperature detection data from the interface circuit based on the correction data from the interface circuit, thereby detecting a temperature corresponding to the temperature detection data. This makes it possible to provide an oscillator or the like that enables accurate temperature detection by effectively utilizing the temperature sensor circuit of a circuit device.

[0130] The oscillator of this embodiment may include a clock output terminal and a first terminal. The circuit device may include an output circuit that outputs a clock signal based on the oscillation signal to an external processing device via the clock output terminal, and the interface circuit may communicate with the processing device using a data signal. In the communication, the output circuit may output the clock signal to the processing device that is the master of the communication, and the interface circuit that is the slave of the communication may receive a data signal synchronized with the clock signal transmitted from the processing device via the first terminal, or may transmit a data signal synchronized with the clock signal to the processing device via the first terminal.

[0131] In this way, synchronous communication of data signals becomes possible between the processing device acting as the master of communication and the interface circuit acting as the slave of communication, based on the clock signal output by the slave side.

[0132] The processing system of this embodiment also includes the above-mentioned oscillator and a processing device electrically connected to the oscillator, and the processing device may detect the temperature by performing arithmetic processing to correct the temperature detection data based on the correction data.

[0133] In this way, the calculation process for correcting the temperature detection data based on the correction data only needs to be performed at the necessary timing in the entire processing system, which makes it possible to reduce the power consumption of the entire processing system.

[0134] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit devices, oscillators, and processing systems are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0135] 4...oscillator, 6...first substrate, 7...second substrate, 8...third substrate, 10...resonator, 15...package, 16...base, 17...lid, 18, 19...external terminal, 20...circuit device, 30...oscillator circuit, 32...variable capacitance circuit, 40...temperature sensor circuit, 42...ring oscillator, 44...counter, 46...counter control unit, 48...analog correction circuit, 49...digital correction circuit, 50...logic circuit, 60...temperature compensation circuit, 61...arithmetic circuit, 62...interrupt signal generation circuit, 63...first register, 64...second register, 65...comparison circuit, 66, 67...comparator, 68...OR circuit, 70...memory, 72...non-volatile memory, 80...interface circuit, 82...I / O circuit, 90...output circuit, 96...power supply circuit, 100...processing device, 110...interface circuit, 200...processing system, BF...input buffer, BMP...bump, CDC1, CDC2...connection part, CK...clock signal, DA...data signal, DCT...correction data, DFC...frequency adjustment data, DTD...temperature detection data, ECK...clock input terminal, EDA...data terminal, EDTD...conversion temperature detection data, EGND...ground terminal, EVDD...power supply terminal, INT...interrupt signal, IV...inverter, UL...upper limit value, LL...lower limit value, LUT...lookup table, OFS...offset, SL...slope, OSC...oscillation signal, PCK...clock output pad, PDA...first pad, PGND...ground pad, PVDD...power supply pad, PX1, PX2...pads, RP...resistor, TCK...clock output terminal, TDA...first terminal, TGND...ground terminal, TVDD...power supply terminal, TR...transistor

Claims

1. an oscillator circuit that generates an oscillation signal using an oscillator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data; a memory for storing correction data for correcting the temperature detection data to obtain a temperature; an interface circuit that outputs the temperature detection data that has not been corrected by the correction data and the correction data to an external processing device; an interrupt signal generating circuit that generates an interrupt signal when the temperature detection data exceeds an upper limit value or falls below a lower limit value; Including, the correction data is coefficient data of a polynomial that indicates a relationship between the temperature and the temperature detection data, The interrupt signal generating circuit The upper limit value and the lower limit value calculated by the processing device based on the correction data are written from the processing device via the interface circuit, and the temperature detection data that has not been corrected by the correction data is compared with the upper limit value or the lower limit value to generate the interrupt signal.

2. 2. The circuit device according to claim 1, The interrupt signal generating circuit a first register that stores the upper limit value; a second register for storing the lower limit value; a comparison circuit that compares the temperature detection data with the upper limit value or the lower limit value and generates the interrupt signal; A circuit device comprising:

3. 3. The circuit device according to claim 1, The circuit device is characterized in that the memory is a nonvolatile memory, and the correction data is stored in the nonvolatile memory.

4. 4. The circuit device according to claim 1, The memory includes: storing a lookup table in which the temperature detection data and frequency adjustment data correspond to each other; The temperature compensation circuit outputting the frequency adjustment data corresponding to the temperature detection data by referring to the lookup table; The oscillator circuit comprises: A circuit device that generates the oscillation signal at the oscillation frequency corresponding to the frequency adjustment data.

5. 5. The circuit device according to claim 4, A circuit device comprising: an arithmetic circuit that performs arithmetic processing to adjust temperature sensitivity and outputs the temperature detection data that has undergone the arithmetic processing to the lookup table.

6. 6. The circuit device according to claim 1, a clock output pad; an output circuit that outputs a clock signal based on the oscillation signal to the external processing device via the clock output pad; A first pad; Including, The interface circuit communicating with said processing device via data signals; In the communication, The output circuit outputting the clock signal to the processing device that is the master of the communication; The interface circuit that is a slave in the communication A circuit device characterized in that the data signal transmitted from the processing device in synchronization with the clock signal is received via the first pad, or the data signal transmitted to the processing device in synchronization with the clock signal is transmitted via the first pad.

7. 7. The circuit device according to claim 6, The interface circuit A circuit device characterized in that when the temperature detection data exceeds the upper limit value or falls below the lower limit value, the interrupt signal, which becomes a predetermined voltage level for a given period, is output to the processing device via the first pad.

8. A vibrator and A circuit device; Including, The circuit device comprises: an oscillation circuit that generates an oscillation signal using the oscillator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data; a memory for storing correction data for correcting the temperature detection data to obtain a temperature; an interface circuit that outputs the temperature detection data that has not been corrected by the correction data and the correction data to an external processing device; an interrupt signal generating circuit that generates an interrupt signal when the temperature detection data exceeds an upper limit value or falls below a lower limit value; Including, the correction data is coefficient data of a polynomial that indicates a relationship between the temperature and the temperature detection data, The interrupt signal generating circuit an oscillator characterized in that the upper limit value and the lower limit value calculated by the processing device based on the temperature detection data and the correction data are written from the processing device via the interface circuit, and the temperature detection data not corrected by the correction data is compared with the upper limit value or the lower limit value to generate the interrupt signal.

9. 9. The oscillator according to claim 8, A clock output terminal; A first terminal; Including, The circuit device comprises: an output circuit that outputs a clock signal based on the oscillation signal to the external processing device via the clock output terminal; The interface circuit communicating with said processing device via data signals; In the communication, The output circuit outputting the clock signal to the processing device that is the master of the communication; The interface circuit that is a slave in the communication An oscillator characterized in that the data signal transmitted from the processing device in synchronization with the clock signal is received via the first terminal, or the data signal transmitted to the processing device in synchronization with the clock signal is transmitted via the first terminal.

10. an oscillator according to claim 8 or 9; the processing unit electrically connected to the oscillator; Including, The processing device includes: a processing system for detecting the temperature by performing a calculation process for correcting the temperature detection data based on the correction data;

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