Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of reducing the cost.SOLUTION: A semiconductor device 50 includes: a metal plate 10 having a base portion 10a and a terminal portion 10b separated from the base portion; a resin layer 12 which is provided to surround the metal plate and between the base portion and the terminal portion in a planar direction, and at which an upper surface and a lower surface of each of the base portion and the terminal portion are exposed; a semiconductor chip 14 mounted on the base portion; a first insulating layer 18 provided on the metal plate and the resin layer so as to cover the semiconductor chip; and one or more wires 20 which are provided on the first insulating layer, at least one wire 20a electrically connecting the semiconductor chip and the terminal portion to each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device having a semiconductor chip and a manufacturing method thereof. [Background technology]

[0002] A semiconductor device is known in which a semiconductor chip is mounted face-up on a metal base in a package having an insulating frame on the metal base, and the pattern on the insulating frame and the semiconductor chip are electrically connected using bonding wires (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2019-176149 Summary of the Invention [Problem to be solved by the invention]

[0004] The mounting method of Patent Document 1 has high heat dissipation properties because heat from the semiconductor chip is dissipated via the metal base, but it is costly because the semiconductor chips are mounted in individual packages.

[0005] The present disclosure has been made in view of the above-mentioned problems, and has an object to provide a semiconductor device and a manufacturing method thereof that can reduce costs. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a metal plate having a base portion and a terminal portion separated from the base portion; a resin layer disposed between the base portion and the terminal portion and surrounding the metal plate in a planar direction, exposing the upper and lower surfaces of the base portion and the terminal portion; a semiconductor chip mounted on the base portion; a first insulating layer disposed on the metal plate and the resin layer so as to cover the semiconductor chip; and one or more wirings disposed on the first insulating layer, at least one wiring electrically connecting the semiconductor chip and the terminal portion.

[0007] One embodiment of the present disclosure is a method for manufacturing a semiconductor device, including: a lead frame having a plurality of regions each having a base portion and a terminal portion separated from each other within each region; and a connection portion in adjacent regions of the plurality of regions that connects the base portion and the terminal portion in one region to the base portion and the terminal portion in another region; forming a resin layer between the base portion, the terminal portion, and the connection portion; mounting a semiconductor chip on the base portion in each of the plurality of regions; forming an insulating layer on the lead frame and the resin layer so as to cover the semiconductor chip; forming wiring on the insulating layer that electrically connects the semiconductor chip and the terminal portion; and, after the wiring forming step, forming a plurality of semiconductor devices corresponding to the plurality of regions by cutting the connection portion and the resin layer between the adjacent regions. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a semiconductor device and a method for manufacturing the same that can reduce costs. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment taken along the line AA in FIG. [Figure 3]FIG. 3 is a side view of the semiconductor device according to the first embodiment as viewed from the Y direction. [Figure 4] FIG. 4 is a side view of the semiconductor device according to the first embodiment as viewed from the X direction. [Figure 5] FIG. 5 is a perspective view of the metal layer and the resin layer extracted from the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a plan view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a plan view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9A] FIG. 9A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9B] FIG. 9B is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9C] FIG. 9C is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9D] FIG. 9D is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10A] FIG. 10A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10B] FIG. 10B is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10C] FIG. 10C is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10D] FIG. 10D is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11A] FIG. 11A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11B] FIG. 11B is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11C] FIG. 11C is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11D]FIG. 11D is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view of the semiconductor device according to the first embodiment mounted thereon. [Figure 13] FIG. 13 is a block diagram illustrating a high-frequency device as an example of a semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device according to a first comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including: a metal plate including a base portion and terminal portions separated from the base portion; a resin layer disposed between the base portion and the terminal portions and surrounding the metal plate in a planar direction, the resin layer exposing the upper and lower surfaces of the base portion and the terminal portions; a semiconductor chip mounted on the base portion; a first insulating layer disposed on the metal plate and the resin layer so as to cover the semiconductor chip; and one or more wirings disposed on the first insulating layer, at least one of which electrically connects the semiconductor chip and the terminal portions. This allows for the provision of a low-cost semiconductor device. (2) It is preferable that the metal plate has a first connection portion connected to the base portion and a second connection portion connected to the terminal portion, and that the base portion and the terminal portion are not exposed from the side surface of the resin layer, and that the side surfaces of the first connection portion and the second connection portion are exposed from the side surface of the resin layer. (3) It is preferable that an electronic component be mounted on the first insulating layer and connected to at least one of the one or more wirings. (4) The metal plate is preferably thicker than the first insulating layer. (5) It is preferable that a metal pillar be provided on the upper surface of the semiconductor chip, penetrate the first insulating layer, and connect the semiconductor chip to at least one of the one or more wirings. (6) It is preferable that the terminal portion and at least one of the one or more wires are connected via a through hole that penetrates the first insulating layer. (7) It is preferable that a second insulating layer is provided on the first insulating layer so as to cover the one or more wirings. (8) One embodiment of the present disclosure is a method for manufacturing a semiconductor device, the method including: forming a resin layer between a plurality of regions, each region having a base portion and a terminal portion separated from each other, and connecting portions in adjacent regions of the plurality of regions, the base portion and the terminal portion in one region, connecting the base portion and the terminal portion in one region to the base portion and the terminal portion in another region; mounting semiconductor chips on the base portions in the plurality of regions; forming an insulating layer on the lead frame and the resin layer so as to cover the semiconductor chips; forming wiring on the insulating layer, electrically connecting the semiconductor chips and the terminal portions; and, after the wiring forming step, cutting the connecting portions and the resin layer between the adjacent regions to form a plurality of semiconductor devices corresponding to the plurality of regions. This allows for providing a method for manufacturing a semiconductor device that can reduce costs.

[0011] [Details of the embodiments of the present disclosure] Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] Example 1 is an example in which a nitride semiconductor chip such as a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) is mounted using a chip-first process method with a fan-out panel level package (FO-PLP). FO-PLP is a method in which a package is manufactured on a rectangular substrate with a width of 500 mm to 700 mm, and then the rectangular substrate is cut into individual pieces to manufacture multiple semiconductor devices. The chip-first process method is a method in which a rewiring layer is formed after a semiconductor chip is mounted on a rectangular substrate.

[0013] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. As shown in FIG. 1, in a semiconductor device 50, a metal plate 10 includes a base portion 10a and a terminal portion 10b that are separated from each other. The metal plate 10 is made of, for example, a copper-based material, primarily composed of copper. The base portion 10a functions as a heat sink, and therefore the thickness of the metal plate 10 is, for example, 0.5 mm or more, e.g., 1 mm or more. A resin layer 12 is provided between the base portion 10a and the terminal portion 10b and surrounding the metal plate 10 in the planar direction. The resin layer 12 is, for example, an epoxy resin. The resin layer 12 has, for example, approximately the same thickness as the metal plate 10, and the lower and upper surfaces of the metal plate 10 are exposed from the resin layer 12. A metal film 28a is provided on the lower surface of the metal plate 10. The metal film 28a is, for example, a gold film, and is a film for improving solder wettability.

[0014] The semiconductor chip 14 is bonded onto the base portion 10a via a bonding material 15. The bonding material 15 is a metal layer formed by sintering a metal paste such as silver paste, for example, a metal layer formed by sintering a nano-silver paste with good heat dissipation properties. The semiconductor chip 14 is provided with, for example, a GaN HEMT, and for example, a GaN-based semiconductor layer is mainly provided on a SiC substrate. The semiconductor chip 14 may be an MMIC (Monolithic Microwave Integrated Circuit) integrated circuit. The thickness of the semiconductor chip 14 is, for example, 50 μm to 200 μm. A metal pillar 16 is provided on the semiconductor chip 14. The metal pillar 16 is, for example, a copper pillar, and is bonded to an electrode 17 provided on the semiconductor chip 14 by a bonding material. The bonding material is, for example, a metal layer formed by sintering a copper paste or a gold-tin paste, or a brazing material such as solder. The metal pillar 16 may be formed on the electrode 17 by plating or the like. The height and width of the metal pillar 16 are, for example, 50 μm to 200 μm. In addition to the semiconductor chip 14, a passive chip may be provided on the base portion 10a.

[0015] An insulating layer 18 is provided on the metal plate 10 and the resin layer 12 to cover the semiconductor chip 14. The insulating layer 18 is, for example, a resin layer such as an epoxy resin. The thickness of the insulating layer 18 is smaller than that of the metal plate 10, for example, 100 μm to 500 μm. The upper surfaces of the metal pillars 16 are exposed from the insulating layer 18. Through electrodes 22 are provided that penetrate the insulating layer 18 and connect to the terminal portions 10b. Wiring 20 is provided on the insulating layer 18. The wiring 20 is a rewiring layer, for example, a metal layer such as a copper layer or a gold layer. The rewiring layer refers to a wiring layer that relocates input / output signals from the input / output pads of the silicon die (corresponding to the semiconductor chip 14 in FIG. 1) to the input / output terminals of the package (corresponding to the semiconductor device 50 in FIG. 1). A metal film 28b is provided on the upper surface of the wiring 20. The metal film 28b is, for example, a gold film, and is a film that improves solder wettability. If the wiring 20 is a gold layer, the metal film 28b may not be provided.

[0016] An electronic component 26 connected to the wiring 20 is mounted on the insulating layer 18. The electronic component 26 is, for example, a surface mounted device (SMD) and is a discrete component such as a chip capacitor, a chip inductor, or a chip resistor. The electronic component 26 may be a semiconductor device. An electronic component may not be provided. Electrodes 26a of the electronic component 26 and the wiring 20 are bonded via a bonding material 27. The bonding material 27 is, for example, a brazing material such as solder. An insulating layer 24 is provided on the insulating layer 18 to cover the wiring 20 and the electronic component 26. The insulating layer 24 is, for example, a resin layer such as an epoxy resin. The insulating layer 24 has a thickness of, for example, 100 μm to 500 μm. The insulating layer 24 may not be provided. Another wiring may be provided on the insulating layer 24, and the other wiring may be electrically connected to the wiring 20 via another through electrode that penetrates another insulating layer. In this manner, multiple rewiring layers may be stacked.

[0017] Of the wiring 20, wiring 20a electrically connects terminal portion 10b and semiconductor chip 14. Wiring 20b electrically connects semiconductor chip 14 and electronic component 26. Wiring 20c electrically connects electronic component 26 and terminal portion 10b. Terminal portion 10b is a terminal for supplying a bias voltage to semiconductor chip 14 or a terminal for supplying a high-frequency signal. Wiring 20, which transmits a high-frequency signal, functions as a signal line, and the signal line and base portion 10a form a microstrip line. This makes it possible to suppress deterioration of high-frequency characteristics.

[0018] FIG. 2 is a planar cross-sectional view of the semiconductor device according to the first embodiment, specifically illustrating the cross section AA in FIG. 1 in detail. The normal direction to the top surface of the metal plate 10 is the Z direction, the long side direction of the semiconductor device in the planar direction is the X direction, and the short side direction is the Y direction. FIG. 1 corresponds to a cross section taken in the Z direction along the line BB in FIG. 2. As shown in FIG. 2, the metal plate 10 includes a base portion 10a, terminal portions 10b, and connection portions 10c and 10d. The base portion 10a and the terminal portions 10b are separated from each other. Two terminal portions 10b are provided on the +Y direction side of the base portion 10a, and two terminal portions 10b are provided on the -Y direction side of the base portion 10a. The number and arrangement of the terminal portions 10b can be appropriately determined. The connection portions 10c are connected to the +X direction side and the -X direction side of the base portion 10a. The connection portion 10d is connected to the +Y side of the terminal portion 10b provided on the +Y side of the base portion 10a, and the other connection portion 10d is connected to the -Y side of the terminal portion 10b provided on the -Y side of the base portion 10a.

[0019] FIG. 3 is a side view of the semiconductor device 50 according to the first embodiment, viewed from the outside along the Y direction. FIG. 4 is a side view of the semiconductor device 50 according to the first embodiment, viewed from the outside along the X direction. FIG. 5 is a perspective view of the metal plate 10 and the resin layer 12 of the semiconductor device 50 according to the first embodiment. As shown in FIGS. 3 and 4, an insulating layer 18 is provided on the resin layer 12, and an insulating layer 24 is provided on the insulating layer 18. As shown in FIGS. 3 and 5, when the semiconductor device 50 is viewed from the outside along the Y direction, the connecting portion 10d is exposed from the resin layer 12. As shown in FIGS. 4 and 5, when the semiconductor device 50 is viewed from the outside along the X direction, the connecting portion 10c is exposed from the resin layer 12.

[0020] [Manufacturing method of Example 1] 6 to 8 are plan views showing a method for manufacturing a semiconductor device according to Example 1. FIGS. 9A to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to Example 1. FIGS. 6 to 8 are plan views of a rectangular substrate, showing multiple regions 42 in which multiple semiconductor devices 50 are respectively formed. FIGS. 9A to 11D show a region 42 in which one semiconductor device 50 is formed and the vicinity of terminal portion 10b in an adjacent region 42. Note that the cross-sectional views and plan views are schematic views and do not necessarily match.

[0021] As shown in FIG. 6, a lead frame 11 is prepared. The lead frame 11 includes metal plates 10 that constitute the semiconductor device 50 shown in FIG. 2 and frame-shaped connection portions 10e that connect a plurality of the metal plates 10. The lead frame 11 has a plurality of regions 42 in which a plurality of semiconductor devices 50 are formed, arranged in a matrix. The connection portions 10e are provided in a lattice pattern surrounding the regions 42. The metal plates 10 each include a base portion 10a, a terminal portion 10b, and connection portions 10c and 10d. The metal plates 10 and the connection portions 10e are connected by the connection portions 10c and 10d. The connection portions 10c to 10e are so-called suspension leads, and the connection portions 10c to 10e maintain the plurality of metal plates 10 as a single unit to form the lead frame 11. The base portion 10a, the terminal portion 10b, and the connection portions 10c, 10d, and 10e are formed by hollowing out a single metal plate. Therefore, the base portion 10a, the terminal portion 10b, and the connecting portions 10c, 10d, and 10e are made of the same material and have approximately the same thickness. The length of one side of the plane of one region 42 is, for example, 1 mm to 50 mm, for example, 7 mm x 15 mm. The thickness of the lead frame 11 is, for example, 0.1 mm to 5 mm, for example, 1 mm.

[0022] 9A is a cross-sectional view taken along CC in FIG. 6, viewed in the X direction. As shown in FIG. 9A, the lead frame 11 is attached to a film 40. The film 40 is made of, for example, resin and protects the lower surface of the lead frame 11. FIG. 9B is a cross-sectional view taken along CC in FIG. 7, viewed in the X direction. As shown in FIGS. 7 and 9B, a resin layer 12 is formed in the spaces between the base portion 10a, the terminal portion 10b, and the connection portions 10c, 10d, and 10e within the lead frame 11. The resin layer 12 is formed, for example, by molding or potting. The upper and lower surfaces of the lead frame 11 are exposed from the resin layer 12.

[0023] As shown in FIG. 9C, following FIG. 9B, a semiconductor chip 14 having metal pillars 16 formed on its upper surface is mounted on the base portion 10a. A bonding material 15, such as a metal paste such as nanosilver paste, is partially applied to the base portion 10a. The semiconductor chip 14 is then mounted on the bonding material 15 and heat-treated. The bonding material 15 is sintered by the heat treatment. As a result, the semiconductor chip 14 is mounted on the base portion 10a. As shown in FIG. 9D, following FIG. 9C, an insulating layer 18 is formed on the lead frame 11 and the resin layer 12 to cover the semiconductor chip 14. For example, a resin film is attached to the lead frame 11 and the resin layer 12 using a vacuum laminator, and the insulating layer 18 is hardened by heat treatment. This forms the insulating layer 18. The insulating layer 18 may also be formed by applying softened resin to the lead frame 11 and the resin layer 12, as in a molding method, and hardening the resin by heat treatment.

[0024] As shown in FIG. 10A, following FIG. 9D, a through hole 19 is formed through the insulating layer 18. The through hole 19 is formed, for example, by irradiating the insulating layer 18 with laser light. The upper surface of the terminal portion 10b is exposed in the through hole 19. As shown in FIG. 10B, following FIG. 10A, the upper surface of the insulating layer 18 is ground. This exposes the upper surface of the metal pillar 16 from the upper surface of the insulating layer 18. The upper surfaces of the insulating layer 18 and the metal pillar 16 are substantially flat. As shown in FIG. 10C, following FIG. 10B, a metal layer 21 is formed on the insulating layer 18 and in the through hole 19. For example, plating is used to form the metal layer 21. The metal layer 21 in the through hole 19 becomes a through electrode 22. As shown in FIG. 10D, following FIG. 10C, a desired region of the metal layer 21 is removed, for example, by etching, to form a wiring 20.

[0025] As shown in FIG. 11A, following FIG. 10D, the film 40 is peeled off from the lead frame 11 and the resin layer 12. Metal films 28a and 28b are formed on the lower surface of the lead frame 11 and the upper surface of the wiring 20. For example, plating is used to form the metal films 28a and 28b. As shown in FIG. 11B, following FIG. 11A, an electronic component 26 is mounted on the metal film 28b using a bonding material 27. The bonding material 27 bonds the electrode 26a of the electronic component 26 to the metal film 28b. As shown in FIG. 11C, following FIG. 11B, an insulating layer 24 is formed on the insulating layer 18 so as to cover the wiring 20 and the electronic component 26. Insulating layer 24 The formation of the insulating film is carried out by, for example, a molding method or a lamination method.

[0026] FIG. 11D is a cross-sectional view taken along CC in FIG. 8, viewed in the X direction. As shown in FIG. 11D and FIG. 8, following FIG. 11C, the insulating layers 24, 18, the resin layer 12, and the connection portion 10e are cut in the cutting region 44. For example, a dicing method using a dicing blade is used for cutting. As a result, the connection portion 10e is removed, and the base portion 10a and the terminal portion 10b are separated in the region 42. In this way, the semiconductor device 50 is singulated. As shown in FIGS. 3 and 4, the connection portions 10c and 10d are Resin layer 12 exposed from.

[0027] Fig. 12 is a cross-sectional view of a mounted semiconductor device 50 according to the first embodiment. As shown in Fig. 12, a metal layer 32 is provided on a mounting substrate 30 such as a printed circuit board. The metal layer 32 and a metal film 28a of the semiconductor device 50 are joined via a solder layer 34. Because the metal film 28a has good solder wettability, the solder layer 34 is firmly joined to the metal film 28a.

[0028] [Example of high frequency device] A high-frequency power amplifier used in a mobile communication base station will be described as an example of a high-frequency device mounted on the semiconductor device 50. FIG. 13 is a block diagram showing a high-frequency device as an example of a semiconductor device according to the first embodiment. As shown in FIG. 13, the high-frequency device 100 includes amplifiers 61, 63a, and 63b and matching circuits 60, 62a, 62b, 64a, and 64b. The high-frequency device 100 is a two-stage Doherty amplifier. A high-frequency signal input from the input terminal Tin is amplified by the amplifier 61, further amplified by the amplifiers 63a and 63b, and output from the output terminal Tout. The amplifiers 61, 63a, and 63b are, for example, transistors, such as FETs, and are mounted on the semiconductor chips 14a to 14c, respectively.

[0029] The input terminal Tin is connected to an amplifier 61 via a matching circuit 60. The matching circuit 60 matches the input impedance of the input terminal Tin with the input impedance of the amplifier 61. The output of the amplifier 61 is branched and connected to amplifiers 63a and 63b via matching circuits 62a and 62b, respectively. The matching circuit 62a matches the output impedance of the amplifier 61 with the input impedance of the amplifier 63a. The matching circuit 62b matches the output impedance of the amplifier 61 with the input impedance of the amplifier 63b. The outputs of the amplifiers 63a and 63b are combined via matching circuits 64a and 64b, respectively, and connected to an output terminal Tout. The matching circuit 64a matches the output impedance of the amplifier 63a with the output impedance of the output terminal Tout. The matching circuit 64b matches the output impedance of the amplifier 63b with the output impedance of the output terminal Tout. The high-frequency signal input to the input terminal Tin and output from the output terminal Tout is, for example, a signal of 0.5 GHz to 100 GHz, and is typically 0.5 GHz It is a signal of ~10GHz.

[0030] 1 is the semiconductor chips 14a to 14c in FIG. 13, and the electronic components 26 in FIG. 1 are the capacitors, inductors, and resistors included in the matching circuits 60, 62a, 62b, 64a, and 64b in FIG.

[0031] FIG. 14 is a cross-sectional view of a semiconductor device 52 according to Comparative Example 1. FIG. 14 corresponds to the cross-sectional view of the semiconductor device 50 shown in FIG. 1 of Example 1. As shown in FIG. 14, in the semiconductor device 52 of Comparative Example 1, the metal plate 10 functions as a base portion 10a and does not have a terminal portion 10b. A through electrode 36 penetrating the insulating layer 24 is provided. In Comparative Example 1, the base portion 10a is used as a heat sink to improve heat dissipation. By using the wiring 20 as a signal line and forming a microstrip line between the signal line and the base portion 10a, high-frequency characteristics can be improved compared to when using bonding wires, as in Patent Document 1. The semiconductor chip 14 and electronic components 26 can be freely positioned, improving the degree of freedom in mounting. However, the semiconductor device 52 includes a through electrode 36 that penetrates vertically through the insulating layer 24 and a terminal 38 that connects the through electrode 36 that reaches the surface of the insulating layer 24 to the insulating layer 24. Connection to the mounting substrate for supplying ground potential and dissipating heat is made on the underside of the semiconductor device 52, i.e., the underside of the base portion 10a, and electrical connections to the semiconductor device 52, such as for signals and bias voltages, are made on the top side of the semiconductor device 52, i.e., from the upper terminals 38.

[0032] In contrast, in the semiconductor device 50 of Example 1, when viewed in a planar direction as shown in FIG. 2, the resin layer 12 is provided between the base portion 10a and the terminal portion 10b of the metal plate 10 and surrounds the base portion 10a except for the connection portion 10c. When viewed in a vertical cross section as shown in FIG. 12, the upper and lower surfaces of the base portion 10a and the terminal portion 10b of the metal plate 10 are exposed from the resin layer 12. The semiconductor chip 14 is mounted on the base portion 10a via a bonding material 15. An insulating layer 18 (first insulating layer) is provided on the metal plate 10 and the resin layer 12 so as to cover the semiconductor chip 14. One or more wirings 20 are provided on the insulating layer 18, and at least one wiring 20a electrically connects the semiconductor chip 14 and the terminal portion 10b. This, as with Comparative Example 1, improves heat dissipation, high-frequency characteristics, and flexibility in component placement. 12, by mounting the semiconductor device 50 on a mounting substrate 30, the base portion 10a and the terminal portion 10b can be bonded to the mounting substrate 30. Furthermore, compared to mounting semiconductor chips in individual packages as in Patent Document 1, the semiconductor device can be manufactured at lower cost.

[0033] Furthermore, if there is a gap between the base portion 10a and the terminal portion 10b, when the insulating layer 18 is formed on the metal plate 10, a portion of the insulating layer 18 may enter between the base portion 10a and the terminal portion 10b, causing a recess in the upper surface of the insulating layer 18. Furthermore, foreign matter may enter the gap between the base portion 10a and the terminal portion 10b during the manufacturing process or during product mounting. If the foreign matter is conductive, an electrical short may occur between the base portion 10a and the terminal portion 10b. In Example 1, the resin layer 12 is provided between the base portion 10a and the terminal portion 10b. This prevents a portion of the insulating layer 18 from entering the gap between the base portion 10a and the terminal portion 10b, causing a recess in the upper surface of the insulating layer 18. Furthermore, it is possible to prevent foreign matter from entering the gap between the base portion 10a and the terminal portion 10b.

[0034] In a method for manufacturing such a semiconductor device, as shown in FIG. 6, a lead frame 11 includes multiple regions 42, each having a base portion 10a and a terminal portion 10b separated from one another within the region 42, and connection portions 10c, 10d, and 10e connecting adjacent regions 42. Adjacent regions 42 are connected to one another within the multiple regions 42. The connection portions 10c, 10d, and 10e connect the base portion 10a and the terminal portion 10b in one region to the base portion 10a and the terminal portion 10b in the other adjacent region 42. As shown in FIG. 7, a resin layer 12 is formed between the base portion 10a, the terminal portion 10b, and the connection portions 10c-10e in the lead frame 11. As shown in FIG. 9C, a semiconductor chip 14 is mounted on each of the base portions 10a in the multiple regions 42. As shown in FIG. 9D, an insulating layer 18 is formed on the lead frame 11 and the resin layer 12 to cover the semiconductor chip 14. 10A to 10D, wiring 20 that electrically connects semiconductor chip 14 and terminal portion 10b is formed on insulating layer 18. After forming wiring 20, as shown in FIGS. 8 and 11D, connecting portions 10c, 10d, and 10e between adjacent regions 42 and resin layer 12 are cut along cutting regions 44 indicated by dotted lines in the figures, thereby forming a plurality of semiconductor devices 50 corresponding to the plurality of regions 42. This allows semiconductor device 50 to be manufactured using lead frame 11 having a plurality of regions 42, thereby reducing the cost of the semiconductor device.

[0035] When the semiconductor device 50 is manufactured in this manner, the metal plate 10 has a connection portion 10c (first connection portion) connected to the base portion 10a and a connection portion 10d (second connection portion) connected to the terminal portion 10b. FIG. 5 corresponds to a cut-out view of the metal plate 10 and the resin layer 12 in the region 42 in FIGS. 9B to 11C. As shown in FIG. 5, the base portion 10a and the terminal portion 10b are not exposed from the side surfaces of the resin layer 12, but the side surfaces of the connection portions 10c and 10d are exposed from the resin layer 12. This allows the semiconductor device to be manufactured using the lead frame 11, thereby reducing the cost of the semiconductor device.

[0036] When the metal plate 10 is used as a heat sink, the metal plate 10 becomes thick. If the metal plate 10 is thicker than the insulating layer 18, and a gap is formed between the base portion 10a and the terminal portion 10b, a portion of the insulating layer 18 is likely to enter the gap, as shown in FIG. 9D. Furthermore, foreign matter is likely to enter the gap. Furthermore, after the semiconductor chip 14 is mounted on the metal plate 10, it becomes difficult to etch the metal plate 10 to form the base portion 10a and the terminal portion 10b. Therefore, it is preferable to manufacture a semiconductor device using the above method. The thickness of the metal plate 10 is preferably at least 1.5 times the thickness of the insulating layer 18, and more preferably at least 2 times the thickness.

[0037] 1, the electronic component 26 is mounted on the insulating layer 18 and connected to at least one of the wirings 20b and 20c of the one or more wirings 20. This allows the electronic component 26 to be connected to the semiconductor chip 14 and the terminal portion 10b.

[0038] Furthermore, the metal pillar 16 is provided on the upper surface of the semiconductor chip 14, penetrates the insulating layer 18, and connects the semiconductor chip 14 to at least one of the wirings 20a and 20b of the wiring 20. This allows the semiconductor chip 14 to be electrically connected to the wirings 20a and 20b.

[0039] Furthermore, terminal portion 10b and at least one of wirings 20a and 20c of wiring 20 are connected via a through hole penetrating insulating layer 18. This allows electrical connection between wirings 20a and 20b and terminal portion 10b.

[0040] Furthermore, the insulating layer 24 (second insulating layer) is provided on the insulating layer 18 so as to cover the wiring 20. This makes it possible to seal the wiring 20 and the electronic components 26.

[0041] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0042] 10 metal plate 10a Base 10b Terminal section 10c~10e connection part 11 Lead frame 12 Resin layer 14, 14a to 14c Semiconductor chips 15, 27 Bonding material 16 Metal Pillar 17 electrodes 18 Insulation layer (first insulation layer) 19 Through hole 20, 20a~20c wiring 21, 32 metal layer 22, 36 Through electrode 24 Insulation layer (second insulation layer) 26 Electronic Components 26a electrode 28a, 28b metal film 30 Mounting board 34 solder layer 38 terminals 40 Film 42 areas 44 Cutting area 50, 52 Semiconductor device 60, 62a, 62b, 64a, 64b matching circuit 61, 63a, 63b Amplifiers 100 High Frequency Device

Claims

1. a metal plate having a base portion and a terminal portion separated from the base portion; a resin layer provided between the base portion and the terminal portion and surrounding the metal plate in a planar direction, the resin layer exposing upper and lower surfaces of the base portion and the terminal portion; a semiconductor chip mounted on the base portion; a first insulating layer provided on the metal plate and the resin layer so as to cover the semiconductor chip; one or more wirings provided on the first insulating layer, at least one of which electrically connects the semiconductor chip and the terminal portion; A semiconductor device comprising:

2. the metal plate includes a first connection portion connected to the base portion and a second connection portion connected to the terminal portion; The semiconductor device according to claim 1 , wherein the base portion and the terminal portion are not exposed from the side surface of the resin layer, and the side surfaces of the first connecting portion and the second connecting portion are exposed from the side surface of the resin layer.

3. 3. The semiconductor device according to claim 1, further comprising an electronic component mounted on the first insulating layer and connected to at least one of the one or more wirings.

4. The semiconductor device according to claim 1 , wherein the metal plate is thicker than the first insulating layer.

5. 5. The semiconductor device according to claim 1, further comprising a metal pillar provided on an upper surface of the semiconductor chip, penetrating the first insulating layer, and connecting the semiconductor chip to at least one of the one or more wirings.

6. 6. The semiconductor device according to claim 1, wherein the terminal portion and at least one of the one or more wirings are connected via a through hole that penetrates the first insulating layer.

7. 7. The semiconductor device according to claim 1, further comprising a second insulating layer provided on the first insulating layer so as to cover the one or more wirings.

8. a step of forming a resin layer between a base portion, the terminal portion, and the connecting portion in a lead frame including a plurality of regions each having a base portion and a terminal portion separated from each other within the region, and a connecting portion connecting the base portion and the terminal portion in one region to the base portion and the terminal portion in another region in adjacent regions of the plurality of regions; mounting semiconductor chips on the base portions in the plurality of regions; forming an insulating layer on the lead frame and the resin layer so as to cover the semiconductor chip; forming wiring on the insulating layer to electrically connect the semiconductor chip and the terminal portion; after the step of forming the wiring, cutting the connection portion and the resin layer between the adjacent regions to form a plurality of semiconductor devices corresponding to the plurality of regions; A method for manufacturing a semiconductor device comprising:

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