Semiconductor device manufacturing method and semiconductor device

Abstract

This method for manufacturing a semiconductor device comprises: a step for forming, on a substrate, a first organic insulating layer having a groove section; a step for forming, on the first organic insulating layer, a conductive layer composed of a conductive material so as to fill the groove section with the conductive material; a step for removing a portion of the conductive layer on the first organic insulating layer and obtaining a first wiring structure having a first wiring layer configured to include the conductive material filled in the groove section and the first organic insulating layer; a step for providing a second wiring structure having a second organic insulating layer and a second wiring layer; and a step for performing position matching so that the first wiring layer and the second wiring layer correspond to each other and pressing and stacking the first wiring structure and the second wiring structure. In the stacking step, the first wiring layer and the second wiring layer are joined and the first organic insulating layer and the second organic insulating layer are joined.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device manufacturing method including a method for stacking wiring layers, and the semiconductor device. More particularly, the present disclosure relates to a semiconductor device manufacturing method useful for efficiently and inexpensively manufacturing semiconductor devices that meet high demands for miniaturization and high density, and the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method for mounting chips with different performance levels in a single package, aiming to increase the density and performance of semiconductor packages. In this method, cost-effective, high-density interconnect technology between chips is important.

[0003] As an interconnect technology, in the field of semiconductor packaging, attention has been focused on flip-chip mounting, which connects semiconductor chips to each other and to a support member for mounting the semiconductor chip via multiple conductive bumps. In flip-chip mounting, stress due to differences in the thermal expansion coefficients of the respective connecting members can cause abnormal connections between the substrate and the semiconductor chip via the conductive bumps. For this reason, a method is known in which the conductive bumps are sealed by filling the spaces between the connecting members with a resin (underfill material) in order to alleviate this stress (see, for example, Patent Document 2). Furthermore, the use of negative-type photosensitive adhesive compositions has been investigated for connecting semiconductor chips to each other and to connecting the semiconductor chip to a support member for mounting the semiconductor chip (see, for example, Patent Document 3).

[0004] Also, a method has been proposed for manufacturing a solid-state imaging device by stacking semiconductor chips having different functions by CuCu bonding (see, for example, Patent Document 4).

[0005] It has also been proposed to stack semiconductor chips on build-up substrates, wafer-level package substrates, fan-out package substrates, interposer substrates, etc. For stacking semiconductor chips, a method has been considered in which the wiring width is expanded via multiple rewiring layers, bumps or pads are formed on the wiring, and the solder is melted by applying heat and / or pressure to stack the semiconductor chips (see, for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Special Publication No. 2012-529770 [Patent Document 2] Japanese Patent Application Publication No. 10-289969 [Patent Document 3] International Publication No. 2011 / 049011 [Patent Document 4] Japanese Patent Application Publication No. 2019-179782 [Non-patent literature]

[0007] [Non-Patent Document 1] Proceedings of 2009 Electronic Components and Technology Conference, 11-13 (2009). Summary of the Invention [Problem to be solved by the invention]

[0008] However, in order to match the diameter of the bumps or pads formed on the substrate with the diameter of the bumps or pads formed on the semiconductor chip (semiconductor element), multiple rewiring layers are required, which reduces productivity. In addition, the provision of rewiring results in insufficient miniaturization or density in some parts of the wiring layer. On the other hand, when connecting the substrate and the semiconductor chip by melting solder, the solder may deform and come into contact with adjacent bumps, reducing the yield of the semiconductor device. Furthermore, the shortened distance between the solders may reduce insulation reliability.

[0009] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can manufacture semiconductor devices having fine, high-density wiring layers with high yield in connecting semiconductor chips to each other, connecting a semiconductor chip to a semiconductor wafer or a support substrate for mounting the semiconductor chip, or connecting semiconductor wafers to each other. [Means for solving the problem]

[0010] The present disclosure relates to a method for manufacturing a semiconductor device, comprising the steps of: forming a first organic insulating layer having grooves on a substrate; forming a conductive layer made of a conductive material on the first organic insulating layer so as to fill the grooves with the conductive material; removing a portion of the conductive layer on the first organic insulating layer to obtain a first wiring structure having the first organic insulating layer and a first wiring layer formed with the conductive material filled in the grooves; providing a second wiring structure having a second organic insulating layer and a second wiring layer formed with the conductive material filled in the grooves of the second organic insulating layer and exposed from the surface; and aligning the first wiring layer and the second wiring layer so that they correspond to each other and laminating the first wiring structure and the second wiring structure under pressure, thereby bonding each wire of the first wiring layer to each wire of the second wiring layer and bonding the first organic insulating layer to the second organic insulating layer.

[0011] According to the above manufacturing method, the wiring layer of the semiconductor device is formed by joining the first wiring layer and the second wiring layer formed by filling the grooves with a conductive material, and in this case, it is possible to manufacture a semiconductor device having a fine and high-density wiring layer with a high yield.

[0012] The semiconductor device manufacturing method preferably further includes a step of forming a first barrier metal film on at least one of the bottom and side surfaces of the grooves in the first organic insulating layer before forming the conductive layer. In this case, in the semiconductor device manufactured, it is possible to prevent conductive materials (e.g., copper) from the wiring layer formed including the first wiring layer from diffusing into the first organic insulating layer, thereby impairing the insulating properties of the wiring layer. In this embodiment, the thickness of the first barrier metal film may be 0.001 μm or more and 0.5 μm or less. This more reliably prevents the diffusion of conductive materials into the organic insulating layer and ensures a sufficient cross-sectional area for each wiring in the wiring layer. The thickness of the first barrier metal film may be less than half the width or less than half the depth of the grooves in the first organic insulating layer. In this case, it is possible to more reliably prevent the diffusion of conductive materials, as described above.

[0013] In the above-described method for manufacturing a semiconductor device, a second barrier metal film is preferably provided on at least the side surfaces of the grooves of the second organic insulating layer, similar to the first organic insulating layer. Furthermore, in the laminating step, the first wiring layer and the second wiring layer are preferably aligned so that the misalignment between the first barrier metal film on the side surfaces of the grooves of the first organic insulating layer and the second barrier metal film on the side surfaces of the grooves of the second organic insulating layer in a direction intersecting the side surfaces is 50% or less of the thickness of the first barrier metal film. In this case, the first barrier metal film and the second barrier metal film can more reliably prevent the diffusion of conductive materials (e.g., copper) from the inner first wiring layer and the second wiring layer to the outer first organic insulating layer and the second organic insulating layer, and in particular, can prevent the diffusion of conductive materials from the junctions between the first barrier metal film and the second barrier metal film.

[0014] In the method for manufacturing a semiconductor device described above, in the step of obtaining the first wiring structure, a portion of the conductive layer on the first organic insulating layer may be removed by polishing so that the surface roughness of the first wiring layer of the first wiring structure is 0.05 μm or less. In this case, the first wiring layer and the second wiring layer can be bonded more reliably, and the wiring layer in the semiconductor device can function more appropriately.

[0015] In the method for manufacturing a semiconductor device, the surface roughness of the second wiring layer of the second wiring structure may be 0.05 μm or less, which allows the first wiring layer and the second wiring layer to be bonded more reliably, allowing the wiring layer in the semiconductor device to function more appropriately.

[0016] In the above-described semiconductor device manufacturing method, the melt viscosity at 250°C of the organic material constituting at least one of the first organic insulating layer and the second organic insulating layer may be 1 kPa·s or more and 1 MPa·s or less. In this case, the first organic insulating layer and the second organic insulating layer can be more reliably bonded together. More specifically, if the melt viscosity of the organic insulating material is less than 1 kPa·s, the ductility of the organic insulating layer may contaminate the first wiring layer when removing the conductive layer on the first organic insulating layer. However, by setting the melt viscosity of the organic insulating material to 1 kPa·s or more, such contamination can be prevented. Furthermore, if the melt viscosity of the organic insulating material is greater than 1 MPa·s, the heating temperature required to bond the organic insulating layers together may be increased, which may reduce productivity. However, by setting the melt viscosity of the organic insulating material to 1 MPa·s or less, the temperature required to bond the organic insulating layers together can be reduced, thereby improving productivity. In the above case, the melt viscosity of the material constituting at least one of the first organic insulating layer and the second organic insulating layer at 250°C is preferably 3 kPa·s or more, which further suppresses the flow of the resin during bonding. Furthermore, the melt viscosity of the organic insulating material at 250°C is preferably 5 kPa·s or more, which suppresses stress due to cure shrinkage. Meanwhile, the melt viscosity of the organic material constituting at least one of the first organic insulating layer and the second organic insulating layer at 250°C is preferably 0.8 MPa·s or less, which suppresses the formation of voids after bonding. Furthermore, the melt viscosity of the organic material at 250°C is preferably 0.5 MPa·s or less, which enables the first organic insulating layer and the second organic insulating layer to be bonded at low temperatures. Therefore, the melt viscosity of the organic material constituting at least one (preferably both) of the first organic insulating layer and the second organic insulating layer at 250°C is more preferably 5 kPa·s or more and 0.5 MPa·s or less.

[0017] In the above-described method for manufacturing a semiconductor device, in the step of obtaining the first wiring structure, the conductive layer on the first organic insulating layer may be removed by polishing so that the surface of the first wiring layer protrudes from the surface of the first organic insulating layer. In this case, unevenness on the bonding surface when the first wiring structure and the second wiring structure are bonded can be suppressed due to a difference in thermal expansion coefficient between the organic resin material constituting the organic insulating layer and the metal material constituting the wiring layer, and the first wiring structure and the second wiring structure can be more reliably laminated.

[0018] In the method for manufacturing a semiconductor device described above, the step of forming the first organic insulating layer may include the steps of disposing a photosensitive material on the substrate, exposing the photosensitive material to light, and developing the photosensitive material to form the first organic insulating layer. In this case, the first organic insulating layer itself and the grooves, etc. can be easily formed, thereby improving manufacturing efficiency.

[0019] In the above-described method for manufacturing a semiconductor device, the step of forming the first organic insulating layer may include the step of forming grooves on the first organic insulating layer. In this case, by disposing a photosensitive material on the substrate and exposing and developing the photosensitive material to form the first organic insulating layer having grooves, it becomes possible to form finer grooves, i.e., the individual wires of the first wiring layer, and to promote miniaturization and high density of the wiring layer.

[0020] In the method for manufacturing a semiconductor device, the line width of each wire in the first wiring layer may be 2 μm or less, and the thickness of each wire in the first wiring layer may be 1 μm or less, which makes it possible to form a finer and denser wiring layer.

[0021] In the above-described method for manufacturing a semiconductor device, a first semiconductor element may be disposed on the substrate on the side opposite the first organic insulating layer of the first wiring structure or within the substrate, and a second semiconductor element may be disposed on the second organic insulating layer on the side opposite the second wiring layer of the second wiring structure or within the second organic insulating layer, and the first semiconductor element may be electrically connected to the second semiconductor element by a wiring layer in which the first wiring layer and the second wiring layer are bonded. In this case, the first semiconductor element and the second semiconductor element can be directly or nearly directly connected by the fine wiring layer. Note that the semiconductor element here may include at least a semiconductor chip and a semiconductor wafer.

[0022] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a first wiring structure including a substrate, a first organic insulating layer provided on the substrate and having a first groove, and a first wiring layer formed of a conductive material filled in the first groove, and a second wiring structure including a second organic insulating layer having a second groove, and a second wiring layer formed of a conductive material filled in the second groove. The first wiring structure is stacked on the second wiring structure so that the first wiring layer and the second wiring layer are bonded and the first organic insulating layer and the second organic insulating layer are bonded.

[0023] In the above semiconductor device, the wiring layer is formed from the first wiring layer and the second wiring layer, so that similarly to the above, a semiconductor device having a fine and high-density wiring layer can be manufactured with a high yield.

[0024] The semiconductor device may further include a first semiconductor element disposed on the substrate on the side of the first wiring structure opposite the first organic insulating layer or within the substrate, and a second semiconductor element disposed on the second organic insulating layer on the side of the second wiring structure opposite the second wiring layer or within the second organic insulating layer. In this semiconductor device, the first semiconductor element may be electrically connected to the second semiconductor element by a wiring layer in which the first wiring layer and the second wiring layer are bonded. In this case, the first semiconductor element and the second semiconductor element can be directly or substantially directly connected by fine wiring. [Effects of the Invention]

[0025] According to the present disclosure, it is possible to provide a semiconductor device manufacturing method and a semiconductor device that can manufacture semiconductor devices having fine and high-density wiring layers with high yield. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor package. [Figure 2] FIG. 2 is a cross-sectional view showing a wiring member in the semiconductor package shown in FIG. [Figure 3] 3(a) to 3(d) are cross-sectional views schematically illustrating a process for forming a wiring member according to an embodiment of the present disclosure. [Figure 4] 4(a) to 4(d) are cross-sectional views schematically showing a process for forming a wiring member according to an embodiment of the present disclosure. [Figure 5] 5(a) and 5(b) are cross-sectional views schematically illustrating a process for forming a wiring member according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view schematically illustrating a process for forming a wiring member according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicated explanations will be omitted. Furthermore, unless otherwise specified, the positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0028] When terms such as "left," "right," "front," "back," "top," "bottom," "upper," "lower," "first," and "second" are used in the description and claims, they are intended for explanatory purposes and do not necessarily mean that these relative positions are permanent. The term "layer" encompasses not only structures that are formed over the entire surface when viewed in a plan view, but also structures that are formed only on a portion of the surface. The term "process" encompasses not only independent processes but also processes that cannot be clearly distinguished from other processes, as long as the intended purpose of the process is achieved. Numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to," respectively, as minimum and maximum values. In numerical ranges described in stages in this specification, the upper or lower limit of a certain numerical range may be replaced with the upper or lower limit of another numerical range.

[0029] First, referring to FIG. 1, an example of the configuration of a semiconductor package 1 (semiconductor device) connected by the semiconductor device manufacturing method according to this embodiment will be described. The semiconductor device manufacturing method of the present disclosure is suitable for configurations requiring miniaturization and increased pin count (high density). The manufacturing method of the present disclosure can also be used for package configurations requiring an interposer for mounting heterogeneous chips together. However, the manufacturing method of the present disclosure is not limited to these configurations and may be used in other configurations.

[0030] Fig. 1 is a schematic cross-sectional view showing an example of a semiconductor package. As shown in Fig. 1, the semiconductor package 1 is configured to include a substrate 10, semiconductor chips 20A to 20D (first semiconductor elements, second semiconductor elements), and a wiring member 30. The semiconductor chips 20A and 20B are mounted on the wiring member 30. The semiconductor chips 20C and 20D are disposed within the substrate 10. The semiconductor chips 20A and 20B may be fixed onto the wiring member 30 by underfills 3A and 3B or the like, or may be fixed directly onto a fourth insulating layer 38 (described later) of the wiring member 30 without using an underfill.

[0031] As an example, the substrate 10 is a sealed body formed by sealing the semiconductor chips 20C and 20D and the electrodes 11 and 12 with an insulating material 13. The semiconductor chips 20C and 20D in the substrate 10 may be connectable to an external device via the electrodes exposed from the insulating material 13. The semiconductor chips 20C and 20D function as, for example, a conductive path for electrically connecting the wiring member 30 and the external device to each other. The insulating material 13 is, for example, a curable resin having insulating properties.

[0032] The semiconductor chips 20A to 20D may be, for example, a graphic processing unit (GPU), a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a non-volatile memory such as a flash memory, an RF chip, a silicon photonics chip, a microelectromechanical system (MEMS), a sensor chip, etc. The semiconductor chips 20A to 20D may have TSVs and may be, for example, a stack of multiple semiconductor elements. In this case, semiconductor elements stacked using TSVs can be used as any of the semiconductor chips 20A to 20D. The thickness of the semiconductor chips 20A and 20B is, for example, 200 μm or less. From the viewpoint of thinning the semiconductor package 1, the thickness of the semiconductor chips 20A and 20B is preferably 100 μm or less. Furthermore, from the viewpoint of ease of handling, the thickness of the semiconductor chips 20A and 20B is more preferably 30 μm or more.

[0033] Next, the wiring member 30 will be described in detail with reference to FIG. 2. The wiring member 30 is an organic substrate that supports semiconductor chips and the like. For example, the wiring member 30 may be a build-up substrate formed by laminating a material (prepreg) in which glass cloth or carbon fiber is impregnated with resin, a substrate for wafer-level packaging, a coreless substrate, a substrate fabricated by thermally curing a sealing material, or a substrate in which a chip is sealed or embedded. The shape of the wiring member 30 depends on the shape of the substrate 10A described below, and may be a wafer shape (approximately circular in plan view) or a panel shape (approximately rectangular in plan view). From the viewpoint of suppressing warpage, the thermal expansion coefficient of the wiring member 30 is preferably, for example, 40 ppm / °C or less. From the viewpoint of the insulation reliability of the wiring member 30, the thermal expansion coefficient is preferably 20 ppm / °C or less.

[0034] 2, the wiring member 30 is provided on a substrate 10A. The substrate 10A is a support that supports the wiring member 30. The shape of the substrate 10A in plan view is, for example, circular or rectangular. If the substrate 10A is circular, it has a diameter of, for example, 200 mm to 450 mm. If the substrate 10 is rectangular, one side of the substrate 10 is, for example, 300 mm to 700 mm.

[0035] The substrate 10A may be, for example, a silicon substrate, a glass substrate, or a peelable copper foil. The substrate 10A may also be, for example, a build-up substrate, a wafer-level package substrate, a coreless substrate, a substrate fabricated by thermally curing a sealing material, or a substrate with a sealed or embedded chip. While FIG. 1 illustrates a configuration (substrate 10) in which semiconductor chips 20C and 20D are embedded in the substrate 10A, the substrate 10A may have other configurations. When a silicon substrate or a glass substrate is used as the substrate 10A, a temporary fixing layer (not shown) may be provided to temporarily fix the substrate 10A and the wiring member 30. In this case, removing the temporary fixing layer allows the substrate 10A to be easily peeled from the wiring member 30. The peelable copper foil is a laminate in which a support, a release layer, and a copper foil are stacked in this order. In the peelable copper foil, the support corresponds to the substrate 10A, and the copper foil corresponds to the material of the copper wiring included in the through wiring 33.

[0036] The wiring member 30 includes an organic insulating laminate 31 including a plurality of organic insulating layers, a plurality of wirings 32 arranged in the organic insulating laminate 31, through wirings 33 penetrating the organic insulating laminate 31, and surface wirings 34 formed on and near the surface of the organic insulating laminate 31. The plurality of wirings 32 form a wiring layer of the wiring member 30. This wiring layer may include the through wirings 33 and the surface wirings 34, and the through wirings 33 may be electrically connected to any of the plurality of wirings 32.

[0037] The organic insulating laminate 31 includes a first insulating layer 35 (first organic insulating layer), a second insulating layer 36 (first organic insulating layer), a third insulating layer 37 (second organic insulating layer), and a fourth insulating layer 38 (second organic insulating layer). The first insulating layer 35 to the fourth insulating layer 38 are laminated in this order on the substrate 10A. The organic insulating laminate 31 also has an opening H in which the through wiring 33 is provided, and has a groove portion T in which each wiring 32 is provided. The first insulating layer 35 and the second insulating layer 36 also have an opening Ha in which a part 33 of the through wiring 33 is provided.

[0038] A plurality of trenches T are provided in the second insulating layer 36 and the third insulating layer 37 so as to be sandwiched between the first insulating layer 35 and the fourth insulating layer 46. Each trench T has a substantially rectangular shape in a cross section perpendicular to the extension direction of the trenches T. That is, each trench T has a bottom surface formed by the surface of the first insulating layer 35, a side surface extending from the bottom surface to the fourth insulating layer 38, and a top surface formed by the back surface of the fourth insulating layer 38. The plurality of trenches T have a predetermined line width L (horizontal width) and space width S. Each of the line width L and the space width S is, for example, 0.5 μm to 10 μm, preferably 0.5 μm to 5 μm, and more preferably 2 μm to 5 μm. From the viewpoint of achieving high-density transmission of the wiring member 30, the line width L is preferably 1 μm to 5 μm. The line width L and the space width S may be set to be the same or different from each other. The line width L corresponds to the width of the trench T in a direction perpendicular to the extension direction of the trench T (width L in FIG. 2). The space width S corresponds to the distance between adjacent trenches T (width S in FIG. 2). The depth of the trench T corresponds to, for example, the total thickness of the second insulating layer 36 and the third insulating layer 37. The cross-sectional shape of the trench T is not limited to a substantially rectangular shape, and may be another shape (for example, a substantially semicircular shape).

[0039] The surface roughness of the inner surface of each groove T is preferably 0.01 μm to 0.1 μm. When the surface roughness is 0.01 μm or more, the first insulating layer 35, the second insulating layer 36, the third insulating layer 37, and the fourth insulating layer 38 in the groove T have good adhesion to the object (conductive material) that comes into contact with them, and good temperature cycle resistance. Here, temperature cycle resistance refers to resistance to volumetric changes, performance degradation, breakage, and the like that occur with temperature changes. Furthermore, when the surface roughness is 0.1 μm or less, short circuits in the wiring 32 made of a conductive material tend to be suppressed, and the high-frequency characteristics of the wiring 32 tend to be improved. The surface roughness of the inner surface of the groove T is calculated, for example, by observing the cross section of the groove T with an electron microscope. The surface roughness is the arithmetic mean roughness (Ra) defined in JIS B 0601 2001. Hereinafter, all references to "surface roughness" will be referred to as "surface roughness Ra."

[0040] The storage modulus of the first insulating layer 35, the second insulating layer 36, the third insulating layer 37, and the fourth insulating layer 38 (hereinafter sometimes abbreviated as "insulating layers 35-38") at room temperature is, for example, 500 MPa to 1000 GPa. Here, "room temperature" refers to approximately 25°C. A storage modulus of 500 MPa or more can suppress the extension of the insulating layers 35-38. For example, in the step of grinding the second insulating layer 36 or the third insulating layer 37, the second insulating layer 36 or the third insulating layer 37, which has expanded due to grinding, can be prevented from covering the wiring 32. Furthermore, a storage modulus of 10 GPa or less can prevent, for example, damage to a grinding blade, thereby suppressing excessive roughness of the surface of the second insulating layer 36, etc.

[0041] Furthermore, the melt viscosity at 250°C of the organic material constituting each of the insulating layers 35-38 is preferably 1 kPa·s or more and 1 MPa·s or less. In this case, bonding between the second insulating layer 36 and the third insulating layer 37 can be more reliably performed in the manufacturing method described below. More specifically, if the melt viscosity of the organic insulating material is less than 1 kPa·s, the wiring 32 (32a) may be contaminated due to the ductility of the organic insulating layer when removing the conductive layer portion on the second insulating layer 36. However, by setting the melt viscosity of the organic insulating material to 1 kPa·s or more, such contamination can be prevented. Furthermore, if the melt viscosity of the organic insulating material is greater than 1 MPa·s, the heating temperature required to bond the insulating layers 36 and 37 together must be high, which may reduce productivity. However, by setting the melt viscosity of the organic insulating material to 1 MPa·s or less, the temperature required to bond the insulating layers 36 and 37 together can be reduced, thereby improving productivity. In the above case, the melt viscosity of the material constituting the second insulating layer 36 and the third insulating layer 37 at 250°C is preferably 3 kPa·s or more, which further suppresses resin flow during bonding. Furthermore, the melt viscosity of the organic insulating material at 250°C is preferably 5 kPa·s or more, which suppresses stress due to cure shrinkage. Meanwhile, the melt viscosity of the organic material constituting the second insulating layer 36 and the third insulating layer 37 at 250°C is preferably 0.8 MPa·s or less, which suppresses the formation of voids after bonding. Furthermore, the melt viscosity of the organic material at 250°C is preferably 0.5 MPa·s or less, which enables the second insulating layer 36 and the third insulating layer 37 to be bonded at low temperatures. Therefore, the melt viscosity of the organic material constituting the second insulating layer 36 and the third insulating layer 37 at 250°C is more preferably 5 kPa·s or more and 0.5 MPa·s or less.

[0042] The thickness of each of the insulating layers 35 to 38 is, for example, 0.5 μm to 10 μm. When the thickness of each of the insulating layers 35 to 38 is 0.5 μm or more, the insulating layers 35 to 38 contribute to stress relaxation in the organic insulating laminate 31, and the temperature cycle resistance of the organic insulating laminate 31 can be improved. When the thickness of each of the insulating layers 35 to 38 is 10 μm or less, warping of the organic insulating laminate 31 is suppressed, and wiring and the like can be easily exposed when, for example, the second insulating layer 36 or the third insulating layer 37 is ground. From the viewpoint of forming wiring 32 with a width of 3 μm or less by performing exposure and development, the thickness of the second insulating layer 36 and the third insulating layer 37 is preferably 7 μm or less.

[0043] Each of the insulating layers 35-38 may be made of a cured product of a photosensitive resin composition. From the viewpoints of flatness and manufacturing costs of these layers, it is preferable to use a material (film-like organic insulating material) that is pre-formed into a film shape to form these layers. In this case, even if the surface roughness of the substrate 10A is 300 μm or more, a layer with a sufficiently small surface roughness value can be formed. It is preferable that the film-like organic insulating material can be laminated at 40°C to 120°C. By setting the laminating temperature to 40°C or higher, the tack (adhesiveness) of the organic insulating material at room temperature can be prevented from increasing and good handleability can be maintained. By setting the laminating temperature to 120°C or lower, the occurrence of warping in the organic insulating laminate 31 can be suppressed.

[0044] The thermal expansion coefficient of each of the insulating layers 35 to 38 after curing is, for example, 80 ppm / °C or less from the viewpoint of suppressing warpage of the organic insulating laminate 31. From the viewpoint of the insulation reliability of the wiring member 30, the thermal expansion coefficient of each of the insulating layers 35 to 38 after curing is preferably 70 ppm / °C or less. Furthermore, from the viewpoints of the stress relaxation property of the organic insulating material and processing accuracy, the thermal expansion coefficient of each of the insulating layers 35 to 38 after curing is more preferably 20 ppm / °C or more.

[0045] The photosensitive resin composition for forming each of the insulating layers 35 to 38 may include a composition containing at least a photoacid generator and a compound having a tertiary amino group or a nitrogen-containing heterocycle. This composition preferably further contains an alkali-soluble resin. Such a photosensitive resin composition can be prepared as either a negative or positive type.

[0046] The photoacid generator is not particularly limited as long as it is a compound that generates an acid upon irradiation with light. From the viewpoint of efficient acid generation, the photoacid generator is preferably, for example, an onium salt compound or a sulfonimide compound. Examples of the onium salt compound include iodonium salts and sulfonium salts. Specific examples include diaryliodonium salts such as diphenyliodonium trifluoromethanesulfonate, diphenyliodonium p-toluenesulfonate, diphenyliodonium hexafluoroantimonate, diphenyliodonium hexafluorophosphate, and diphenyliodonium tetrafluoroborate; triarylsulfonium salts such as triphenylsulfonium trifluoromethanesulfonate, triphenylsulfonium p-toluenesulfonate, and triphenylsulfonium hexafluoroantimonate; 4-tert-butylphenyl-diphenylsulfonium p-toluenesulfonate; and 4,7-di-n-butoxynaphthyltetrahydrothiophenium trifluoromethanesulfonate. Specific examples of the sulfonimide compound include N-(trifluoromethylsulfonyloxy)succinimide, N-(trifluoromethylsulfonyloxy)phthalimide, N-(trifluoromethylsulfonyloxy)diphenylmaleimide, N-(trifluoromethylsulfonyloxy)bicyclo[2.2.1]hept-5-ene-2,3-dicarboximide, N-(trifluoromethylsulfonyloxy)naphthalimide, N-(p-toluenesulfonyloxy)-1,8-naphthalimide, and N-(10-camphorsulfonyloxy)-1,8-naphthalimide.

[0047] From the viewpoint of resolution, a compound having a trifluoromethanesulfonate group, a hexafluoroantimonate group, a hexafluorophosphate group, or a tetrafluoroborate group may be used as the photoacid generator.

[0048] The alkali-soluble resin is not particularly limited as long as it has a phenolic hydroxyl group and / or a carboxyl group, and examples thereof include polyester resins, polyether resins, polyimide resins, polyamide resins, polyamideimide resins, polyetherimide resins, polyurethane resins, polyurethaneimide resins, polyurethaneamideimide resins, siloxane polyimide resins, polyesterimide resins, copolymers thereof and precursors thereof (such as polyamic acids), as well as polybenzoxazole resins, phenoxy resins, polysulfone resins, polyethersulfone resins, polyphenylene sulfide resins, polyester resins, polyether resins, polycarbonate resins, polyetherketone resins, (meth)acrylic copolymers, novolac resins, and phenolic resins.

[0049] The photosensitive resin composition is preferably soluble in a 2.38% by mass aqueous solution of tetramethylammonium hydroxide (TMAH aqueous solution). From the viewpoints of the resolution, storage stability, and insulation reliability of the photosensitive resin composition, the photosensitive resin composition preferably contains a compound having a phenolic hydroxyl group. Examples of the compound having a phenolic hydroxyl group include phenol / formaldehyde condensation novolac resin, cresol / formaldehyde condensation novolac resin, phenol-naphthol / formaldehyde condensation novolac resin, polyhydroxystyrene and its polymer, phenol-xylylene glycol condensation resin, cresol-xylylene glycol condensation resin, and phenol-dicyclopentadiene condensation resin.

[0050] The photosensitive resin composition preferably contains a thermosetting resin. Examples of thermosetting resins include acrylate resins, epoxy resins, cyanate ester resins, maleimide resins, allylnadimide resins, phenolic resins, urea resins, melamine resins, alkyd resins, unsaturated polyester resins, diallyl phthalate resins, silicone resins, resorcinol formaldehyde resins, triallyl cyanurate resins, polyisocyanate resins, resins containing tris(2-hydroxyethyl)isocyanurate, resins containing triallyl trimellitate, and thermosetting resins synthesized from cyclopentadiene. From the viewpoints of the resolution, insulation reliability, and adhesion to metals of the photosensitive resin composition, the thermosetting resin is more preferably a compound having a methylol group, an alkoxyalkyl group, or a glycidyl group.

[0051] Each of the insulating layers 35 to 38 may contain a filler. The filler content in each layer is preferably less than 1 mass %. From the viewpoint of ease of processing and processing accuracy, the average particle size of the filler is, for example, 500 nm or less. It is more preferable that each of the insulating layers 35 to 38 does not contain a filler.

[0052] As described above, the multiple wirings 32 are provided in the corresponding grooves T and function as conductive paths within the wiring member 30. For this reason, the width of the wirings 32 is approximately equal to the line width L of the grooves T, and the spacing between adjacent wirings 32 is approximately equal to the space width S of the grooves T. From the viewpoint of effectively functioning as conductive paths, the wirings 32 preferably contain a metal material having high conductivity. Examples of metal materials having high conductivity include copper, aluminum, or silver. These metal materials tend to diffuse into the organic insulating laminate 31 when heated. From the viewpoints of conductivity and cost, the metal material contained in the wirings 32 is preferably copper.

[0053] The wiring 32 is preferably covered with a barrier metal film 39 for preventing the metal material constituting the wiring 32 from diffusing into the organic insulating laminate 31. The barrier metal film 39 includes a first barrier metal film 39a provided between the wiring 32 (wiring 32a) and the first insulating layer 35 and the second insulating layer 36, and a second barrier metal film 39b provided between the wiring 32 (wiring 32b) and the third insulating layer 37 and the fourth insulating layer 38 (see FIG. 6). The first barrier metal film 39a is provided to separate the wiring 32 (wiring 32a) from the first insulating layer 35 and the second insulating layer 36, and covers part of the side surfaces and the bottom surface of the wiring 32. The second barrier metal film 39b is provided to separate the wiring 32 (wiring 32b) from the third insulating layer 37 and the fourth insulating layer 38, and covers the remaining side surfaces and the top surface of the wiring 32.

[0054] The barrier metal film 39, which is composed of the first barrier metal film 39a and the second barrier metal film 39b, contains at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold, which is a metal material that does not easily diffuse into the organic insulating layer. From the viewpoint of adhesion to the inner surface of the trench T, the barrier metal film 39 is preferably a titanium film or an alloy film containing titanium. Furthermore, from the viewpoint of forming the barrier metal film 39 by sputtering, the barrier metal film 39 is preferably a titanium film, a tantalum film, a tungsten film, a chromium film, or an alloy film containing at least one of titanium, tantalum, tungsten, and chromium.

[0055] The thickness of the barrier metal film 39 is less than half the width of the trench T and less than half the depth of the trench T, and is, for example, 0.001 μm to 0.5 μm. From the viewpoint of preventing diffusion of the metal material in the interconnect 32, the thickness of the barrier metal film 39 is preferably 0.01 μm to 0.5 μm. Furthermore, from the viewpoint of flatness of the barrier metal film 39 and increasing the amount of current flowing through the interconnect 32, the thickness of the barrier metal film 39 is preferably 0.001 μm to 0.3 μm. For these reasons, the thickness of the barrier metal film 39 is most preferably 0.01 μm to 0.3 μm. Note that the first barrier metal film 39a and the second barrier metal film 39b are preferably made of the same material, but may be made of different materials.

[0056] The through wiring 33 is a wiring embedded in the opening H of the organic insulating laminate 31, and functions as a connection terminal to an external device. The through wiring 33 is composed of a plurality of metal layers 33a, 33b, and 33c stacked on top of each other. The through wiring 33 is preferably in the form of a via, and the via diameter is, for example, 1 μm to 20 μm, preferably 1 μm to 5 μm, and more preferably 2 μm to 5 μm.

[0057] The surface wiring 34 is wiring for electrically connecting, for example, the semiconductor chip 20A and the semiconductor chip 20B mounted on the wiring member 30. Therefore, both ends of the surface wiring 34 are exposed from the wiring member 30, and the surface wiring 34 other than these both ends is embedded in the wiring member 30 (more specifically, the fourth insulating layer 38). Therefore, the fourth insulating layer 38 may be configured to include two or more organic insulating layers. Note that the surface wiring 34 does not necessarily have to be formed.

[0058] A method for manufacturing the wiring member 30 will be described below with reference to FIGS. (B) forming a first barrier metal film on the bottom and side surfaces of the grooves of the first organic insulating layer; (C) forming a conductive layer made of a conductive material on the first organic insulating layer so as to fill the grooves with the conductive material; (D) removing a portion of the conductive layer on the first organic insulating layer to obtain a first wiring structure having a first wiring layer composed of the first organic insulating layer and the first wiring layer composed of the conductive material filled in the grooves; (E) providing a second wiring structure having a second organic insulating layer and a second wiring layer composed of the conductive material filled in grooves provided in the second organic insulating layer and exposed from the surface; and (F) aligning the first wiring layer and the second wiring layer so that they correspond to each other and laminating the first wiring structure and the second wiring structure by applying pressure, wherein each wiring of the first wiring layer and each wiring of the second wiring layer are bonded and the first organic insulating layer and the second organic insulating layer are bonded.

[0059] First, as shown in FIG. 3(a), a metal layer 33a is formed on the substrate 10A. The metal layer 33a is formed by patterning a metal film formed on the substrate 10A. In this step, the metal layer 33a is formed by, for example, a coating method, a physical vapor deposition method (PVD method) such as vacuum deposition or sputtering, a printing method or spray method using a metal paste, or various plating methods. In this embodiment, for example, copper foil can be used as the metal film. The metal layer 33a forms a part (lower part) of the through wiring 33.

[0060] When a temporary fixing layer (not shown) is provided between the substrate 10A and the metal layer 33a, the temporary fixing layer may contain, for example, a resin containing a non-polar component such as polyimide, polybenzoxazole, silicone, or fluorine; a resin containing a component that expands or foams when heated or exposed to ultraviolet light; a resin containing a component that undergoes a crosslinking reaction when heated or exposed to ultraviolet light; or a resin that generates heat when exposed to light. Examples of methods for forming the temporary fixing layer include spin coating, spray coating, and lamination. From the viewpoint of achieving high levels of both ease of handling and carrier releasability, the temporary fixing layer is preferably one that is easily peeled off by external stimuli such as light or heat. From the viewpoint of being peelable so that the temporary fixing layer does not remain on the wiring member 30 to be manufactured later, the temporary fixing layer most preferably contains a resin that expands in volume when heated. When a temporary fixing layer is provided between the substrate 10A and the metal layer 33a, the metal layer 33a may be formed from a peelable copper foil. In this case, the substrate 10A corresponds to the support of the peelable copper foil, and the temporary fixing layer corresponds to the release layer of the peelable copper foil.

[0061] Subsequently, as shown in FIG. 3(b), a first photosensitive resin layer 35A made of a negative photosensitive resin composition is formed on the substrate 10A so as to cover the metal layer 33a.

[0062] Next, a photomask is placed on the first photosensitive resin layer 35A, and the first photosensitive resin layer 35A is exposed to light except for the areas that will become the openings H. As a result, exposed portions 35a and unexposed portions 35b are formed in the first photosensitive resin layer 35A, as shown in FIG. 3(c). The first photosensitive resin layer 35A can be exposed by a known method such as projection exposure, contact exposure, or direct writing exposure.

[0063] 3(d), a second photosensitive resin layer 36A is formed on the surface of the first photosensitive resin layer 35A after the exposure treatment. The thickness of the second photosensitive resin layer 36A is, for example, 7 μm or less.

[0064] Next, a photomask is placed on the second photosensitive resin layer 36A, and the second photosensitive resin layer 36A is exposed to light except for the areas that will become the openings H and the grooves T. As a result, exposed portions 36a and unexposed portions 36b are formed in the second photosensitive resin layer 36A, as shown in FIG. 4(a). The second photosensitive resin layer 36A can be exposed by a known method such as projection exposure, contact exposure, or direct writing exposure.

[0065] 4(b), an opening Ha penetrating the first photosensitive resin layer 35A and the second photosensitive resin layer 36A is formed, and a groove Ta (first groove) having the surface of the first photosensitive resin layer 35A as its bottom is formed in the second photosensitive resin layer 36A. For example, an alkaline aqueous solution such as sodium carbonate or TMAH, or an organic solvent such as PGMEA, PGME, or cyclopentanone can be used for the development process (removal of the unexposed portions 35b, 36b).

[0066] Next, the developed first photosensitive resin layer 35A and second photosensitive resin layer 36A are heated and cured. For example, the heating temperature is set to 100 to 200°C, and the heating time is set to 30 minutes to 3 hours. As a result, the first photosensitive resin layer 35A and second photosensitive resin layer 36A become the first insulating layer 35 and the second insulating layer 36, as shown in FIG. 4(c).

[0067] 4(d), a first barrier metal film 39a is formed to cover the surface of the second insulating layer 36 and the inner surfaces of the opening Ha and the trench Ta. In this step, the first barrier metal film 39a is formed by, for example, a coating method, a PVD method, a printing or spraying method using a metal paste, or various plating methods. In the case of a coating method, the first barrier metal film 39a is formed by coating a complex of palladium or nickel and then heating it. In the case of a metal paste, the first barrier metal film 39a is formed by coating a paste containing metal particles such as nickel or palladium on the surface of the second insulating layer 36 and the inner surfaces of the opening Ha and the trench Ta and then sintering it.

[0068] Next, as shown in FIG. 5A, a metal layer 32A is formed on the first barrier metal film 39a so as to fill the opening Ha and the groove Ta. In this step, the metal layer 32A is formed, for example, by a method using a metal paste or a plating method using the first barrier metal film 39a as a seed layer. The thickness of the metal layer 32A is preferably 0.5 to 3 times the total thickness of the first insulating layer 35 and the second insulating layer 36. When the thickness of the metal layer 32A is 0.5 times or more, it tends to be possible to suppress an increase in the surface roughness Ra of the wiring 32 formed in a later process. Furthermore, when the thickness of the metal layer 32A is 3 times or less, it tends to suppress warping of the metal layer 32A and to provide good adhesion to the second insulating layer 36.

[0069] 5(b), the metal layer 32A and the first barrier metal film 39a on the second insulating layer 36 are removed to expose the second insulating layer 36. As a result, the opening Ha is filled with metal to form the interconnect 33A. Furthermore, the trench Ta is filled with a metal that is a conductive material to form the interconnect 32a. After removing the metal layer 32A and the first barrier metal film 39a, a process for planarizing the surface of the second insulating layer 36 may be performed. In this case, CMP or a flycut method may be used.

[0070] When CMP is used in this step, the slurry that can be used may be, for example, a slurry containing alumina that is generally used for polishing resins, a slurry containing hydrogen peroxide and silica that is used for polishing first barrier metal film 39a, or a slurry containing hydrogen peroxide and ammonium persulfate that is used for polishing metal layer 32A. From the viewpoints of reducing costs and controlling the surface roughness Ra of second insulating layer 36 and interconnects 32a and 33A to 0.01 μm to 1 μm (more preferably 0.05 μm or less), it is preferable to use a slurry containing alumina to grind second insulating layer 36, first barrier metal film 39a, metal layer 32A (interconnects 32a), and interconnects 33A. Furthermore, when the second insulating layer 36, the first barrier metal film 39a, and the metal layer 32A (the interconnects 32a and 33A) are simultaneously planarized, dishing tends to occur in the interconnects 32a and 33A due to differences in polishing speed, resulting in significant impairment of the flatness of the combined surface of the second insulating layer 36 and the interconnects 32a and 33A. Therefore, to achieve a surface roughness Ra of 0.03 μm to 0.1 μm, it is more preferable to grind the second insulating layer 36, the first barrier metal film 39a, and the metal layer 32A (the interconnects 32a and 33A) by a flycut method using a surface planer. Note that this polishing may be performed so that the surface of the interconnect 32a protrudes from the surface of the second insulating layer 36. This polishing can adjust the difference between the thermal expansion of the second insulating layer 36 and the thermal expansion of the interconnects 32a, etc.

[0071] Through the above steps, a first wiring structure 30A having a multilayer structure as shown in Fig. 5(b) can be formed on the substrate 10A. The first wiring structure 30A shown in Fig. 5(b) can be manufactured by a simpler process than a conventional wiring layer having a multilayer structure.

[0072] 6, the second wiring structure 30B is first formed by a process similar to that for the first wiring structure 30A formed by the process described above. The second wiring structure 30B is configured to include, for example, a third insulating layer 37, a fourth insulating layer 38, a wiring 32b which is the remainder of the wiring 32, a wiring 33B which is the remainder of the through wiring 33, a surface wiring 34, and a second barrier metal film 39b. The wiring 32b and the second barrier metal film 39b (second barrier metal film) are formed in the trench portion Tb. The second wiring structure 30B may be fabricated by the same manufacturing process as the first wiring structure 30A described above, or by a different process. As described above, the third insulating layer 37 and the fourth insulating layer 38 may be made of the same material as the first insulating layer 35 and the second insulating layer 36, and the wirings 32b and 33B may be made of the same material as the wirings 32a and 33A. A wiring layer (second wiring layer) in second wiring structure 30B is formed from multiple wirings 32b. This wiring layer may include wirings 33B and surface wirings 34. Second wiring structure 30B may or may not include a substrate corresponding to substrate 10A, or may include a substrate during fabrication and then peel off. In second wiring structure 30B, a semiconductor chip or the like may be mounted on the surface of fourth insulating layer 38 opposite to third insulating layer 37 (or in fourth insulating layer 38).

[0073] Next, after preparation of the second wiring structure 30B is completed, as shown in FIG. 6 , the wirings 32a formed on the surface side of the first wiring structure 30A are aligned with the wirings 32b formed on the surface side of the second wiring structure 30B, and the wirings 33A of the first wiring structure 30A are aligned with the wirings 33B of the second wiring structure 30B. Then, the second wiring structure 30B is moved relatively toward the first wiring structure 30A and stacked while applying pressure. During this stacking, the first wiring structure 30A and the second wiring structure 30B may be stacked while being heated and pressurized. The heating temperature in this case is, for example, 25°C to 300°C. Through this stacking, the wirings 32a of the first wiring structure 30A are bonded to the wirings 32b of the second wiring structure 30B to form the wirings 32, and the wirings 33A of the first wiring structure 30A are bonded to the wirings 33B of the second wiring structure 30B to form the through wirings 33. At this time, the first barrier metal film 39a located outside each wiring 32a and the second barrier metal film 39b located outside each wiring 32b are also aligned and bonded together to form the barrier metal film 39. Each barrier metal film 39 covers the entire outside of each wiring 32, preventing the material constituting the wiring 32 from diffusing into the organic insulating layer. Note that, in this lamination process, the wiring 32a and the wiring 32b are preferably aligned so that the horizontal misalignment when bonding the first barrier metal film 39a and the second barrier metal film 39b is 50% or less of the thickness of the barrier metal film 39. Furthermore, during this bonding, the second insulating layer 36 of the first wiring structure 30A and the third insulating layer 37 of the second wiring structure 30B are bonded. By bonding the second insulating layer 36 and the third insulating layer 37, the wiring member 30 shown in FIG. 2 is formed.

[0074] Thereafter, if a semiconductor chip is not mounted on the wiring member 30, a necessary semiconductor chip is mounted on the rear surface of the substrate 10 or on the fourth insulating layer 38, etc., to complete the semiconductor package.

[0075] As described above, according to the method for manufacturing a semiconductor device according to this embodiment, the wiring layers of the semiconductor package 1 are formed by joining the wirings 32a and 32b formed by filling the grooves Ta and Tb with a conductive material. In this case, the semiconductor package 1 having a fine and high-density wiring layer can be manufactured with a high yield.

[0076] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, before forming the conductive layer, a first barrier metal film 39a is formed on the bottom and side surfaces of the trench portion Ta in the first insulating layer 35 and the second insulating layer 36. In this case, in the semiconductor device to be manufactured, it is possible to prevent a conductive material (e.g., copper) from the wiring 32 formed including the wiring 32a from diffusing into the first insulating layer 35 and the second insulating layer 36, thereby preventing the insulation properties of the wiring 32 from being impaired. Furthermore, the thickness of the first barrier metal film 39a may be 0.001 μm or more and 0.5 μm or less. In this case, it is possible to more reliably prevent the diffusion of the conductive material into the organic insulating layer and to ensure a sufficient cross-sectional area of ​​each wiring 32.

[0077] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, a second barrier metal film 39b is provided on the side and bottom surfaces of the groove Tb (second groove) in the third insulating layer 37 and the fourth insulating layer 38. In the lamination step, it is preferable to align the wiring 32a and the wiring 32b so that the horizontal misalignment between the first barrier metal film 39a and the second barrier metal film 39b is 50% or less of the thickness of the first barrier metal film 39a. In this case, the first barrier metal film 39a and the second barrier metal film 39b can more reliably prevent the diffusion of a conductive material (e.g., copper) that may diffuse from the wiring 32 to the outer organic insulating stack 31, and in particular, it becomes possible to prevent the diffusion of the conductive material from the junction between the first barrier metal film 39a and the second barrier metal film 39b.

[0078] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, in the step of obtaining first wiring structure 30A, portions of the conductive layer on second insulating layer 36 may be removed by polishing so that the surface roughness of wiring 32a of first wiring structure 30A is 0.05 μm or less. The surface roughness of wiring 32b of second wiring structure 30B may also be similarly polished. In this case, bonding between wiring 32a and wiring 32b can be more reliably performed, allowing wiring 32 in the semiconductor device to function more appropriately.

[0079] Furthermore, in the semiconductor device manufacturing method according to this embodiment, the melt viscosity at 250°C of the organic material constituting each of the insulating layers 35-38 may be 1 kPa·s or more and 1 MPa·s or less. In this case, bonding between the second insulating layer 36 and the third insulating layer 37 can be more reliably performed. More specifically, if the melt viscosity of the organic insulating material is less than 1 kPa·s, the wiring 32a may be contaminated due to the ductility of the organic insulating layer when removing the conductive layer portion on the second insulating layer 36. However, by ensuring that the melt viscosity of the organic insulating material is 1 kPa·s or more, such contamination can be prevented. Furthermore, if the melt viscosity of the organic insulating material is greater than 1 MPa·s, the heating temperature required to bond the organic insulating layers together would be high, which could reduce productivity. However, by ensuring that the melt viscosity of the organic insulating material is 1 MPa·s or less, the temperature required to bond the organic insulating layers together can be reduced, thereby improving productivity. In the above case, the melt viscosity of the material constituting each of the insulating layers 35-38 at 250°C is preferably 3 kPa·s or more, which further suppresses resin flow during bonding. Furthermore, the melt viscosity of the organic insulating material at 250°C is preferably 5 kPa·s or more, which suppresses stress due to cure shrinkage. On the other hand, the melt viscosity of the organic material constituting each of the insulating layers 35-38 at 250°C is preferably 0.8 MPa·s or less, which suppresses the formation of voids after bonding. Furthermore, the melt viscosity of the organic material at 250°C is preferably 0.5 MPa·s or less, which enables the second insulating layer 36 and the third insulating layer 37 to be bonded at low temperatures. Therefore, the melt viscosity of the organic material constituting each of the insulating layers 35-38 at 250°C is more preferably 5 kPa·s or more and 0.5 MPa·s or less.

[0080] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the conductive layer on second insulating layer 36 may be removed by polishing so that the surface of interconnect 32a protrudes from the surface of second insulating layer 36. Furthermore, the conductive layer on third insulating layer 37 may be removed by polishing so that the surface of interconnect 32b protrudes from the surface of third insulating layer 37. In this case, unevenness is prevented from being formed on the bonding surface when first wiring structure 30A and second wiring structure 30B are bonded, which is caused by a difference in thermal expansion coefficient between the organic resin material constituting the organic insulating layer and the metal material constituting the wiring layer, and first wiring structure 30A and second wiring structure 30B can be more reliably stacked.

[0081] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, a photosensitive material is disposed on the substrate 10A, and the photosensitive material is exposed and developed to form the first insulating layer 35 and the second insulating layer 36. In this case, the insulating layer itself and the grooves, etc., can be easily formed, improving manufacturing efficiency. Furthermore, it becomes possible to fabricate finer grooves, i.e., wiring 32a, which facilitates miniaturization and higher density of the wiring layer. The same applies to the manufacture of the second wiring structure 30B.

[0082] In the method for manufacturing a semiconductor device according to this embodiment, the line width of each of the wirings 32a, 32b may be 2 μm or less, and the thickness of each of the wirings 32a, 32b may be 1 μm or less, which makes it possible to form a finer and denser wiring layer. can be connected almost directly.

[0083] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and appropriate modifications may be made without departing from the spirit thereof. For example, in the above-described embodiments, an example in which semiconductor chips are connected using the wiring member 30 is shown, but the wiring member 30 may also be used to connect a semiconductor chip and a semiconductor wafer, or to connect semiconductor wafers together. The wiring member 30 may also be used for other connections. [Explanation of symbols]

[0084] 1...semiconductor package (semiconductor device), 10, 10A...substrate, 20A to 20D...semiconductor chip (semiconductor element), 30...wiring member, 31...organic insulating laminate, 32, 32a, 32b...wiring, 35...first insulating layer, 36...second insulating layer, 37...third insulating layer, 38...fourth insulating layer, 39...barrier metal film, 39a...first barrier metal film, 39b...second barrier metal film, T, Ta, Tb...groove portion.

Claims

1. forming a first organic insulating layer having a groove on a substrate; forming a conductive layer made of the conductive material on the first organic insulating layer so as to fill the groove with the conductive material; removing a portion of the conductive layer on the first organic insulating layer to obtain a first wiring structure having a first wiring layer including the conductive material filled in the groove and the first organic insulating layer; providing a second wiring structure having a second organic insulating layer and a second wiring layer including a conductive material filled in a groove provided in the second organic insulating layer and exposed from a surface; a lamination step of laminating the first wiring structure and the second wiring structure by applying pressure to the first wiring structure and the second wiring structure while aligning the first wiring layer and the second wiring layer so that they correspond to each other, wherein the wirings of the first wiring layer and the wirings of the second wiring layer are bonded to each other and the first organic insulating layer and the second organic insulating layer are bonded to each other; A method for manufacturing a semiconductor device, comprising:

2. The method further includes a step of forming a first barrier metal film on at least one of a bottom surface and a side surface of the groove portion of the first organic insulating layer before forming the conductive layer. The method for manufacturing a semiconductor device according to claim 1 .

3. the thickness of the first barrier metal film is 0.001 μm or more and 0.5 μm or less; The method for manufacturing a semiconductor device according to claim 2 .

4. a thickness of the first barrier metal film is less than half the width of the groove portion of the first organic insulating layer or less than half the depth of the groove portion; The method for manufacturing a semiconductor device according to claim 2 or 3.

5. a second barrier metal film is provided on at least a side surface of the groove portion of the second organic insulating layer; In the laminating step, the first wiring layer and the second wiring layer are aligned so that a positional deviation between the first barrier metal film on the side surface of the groove portion of the first organic insulating layer and the second barrier metal film on the side surface of the groove portion of the second organic insulating layer in a direction intersecting the side surface is 50% or less with respect to a thickness of the first barrier metal film.

5. The method for manufacturing a semiconductor device according to claim 2.

6. In the step of obtaining the first wiring structure, a portion of the conductive layer on the first organic insulating layer is removed by polishing so that the surface roughness of the first wiring layer of the first wiring structure is 0.05 μm or less. The method for manufacturing a semiconductor device according to any one of claims 1 to 5.

7. the surface roughness of the second wiring layer of the second wiring structure is 0.05 μm or less; The method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. the melt viscosity at 250°C of the organic material constituting at least one of the first organic insulating layer and the second organic insulating layer is 1 kPa·s or more and 1 MPa·s or less; The method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. In the step of obtaining the first wiring structure, the conductive layer on the first organic insulating layer is removed by polishing so that a surface of the first wiring layer protrudes from a surface of the first organic insulating layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 8.

10. the step of forming the first organic insulating layer includes the steps of disposing a photosensitive material on the substrate, and exposing and developing the photosensitive material to form the first organic insulating layer; The method for manufacturing a semiconductor device according to any one of claims 1 to 9.

11. the step of forming the first organic insulating layer includes the step of forming the groove portion on the first organic insulating layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 10.

12. The line width of each wiring in the first wiring layer is 2 μm or less, The thickness of each of the wirings in the first wiring layer is 1 μm or less. The method for manufacturing a semiconductor device according to any one of claims 1 to 11.

13. a first semiconductor element is disposed on a surface of the substrate opposite to the first organic insulating layer in the first wiring structure or within the substrate; a second semiconductor element is disposed on the second organic insulating layer on a surface of the second wiring structure opposite to the second wiring layer or within the second organic insulating layer; the first semiconductor element is electrically connected to the second semiconductor element by a wiring layer in which the first wiring layer and the second wiring layer are joined together; The method for manufacturing a semiconductor device according to any one of claims 1 to 12.

14. a first wiring structure including a substrate, a first organic insulating layer provided on the substrate and having a first groove, and a first wiring layer made of a conductive material filled in the first groove; a second wiring structure including a second organic insulating layer having a second groove and a second wiring layer made of a conductive material filled in the second groove; Equipped with a first wiring structure body stacked on the second wiring structure body so that the first wiring layer and the second wiring layer are bonded and the first organic insulating layer and the second organic insulating layer are bonded.

15. a first semiconductor element disposed on a surface of the first wiring structure opposite to the first organic insulating layer on the substrate or within the substrate; a second semiconductor element disposed on the second organic insulating layer on a surface of the second wiring structure opposite to the second wiring layer or within the second organic insulating layer; Further provided with the first semiconductor element is electrically connected to the second semiconductor element by a wiring layer in which the first wiring layer and the second wiring layer are joined together; The semiconductor device according to claim 14.

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