50Gb / s PAM4 Bidirectional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas Loop

Abstract

According to the present disclosure, a RF communication system using a bidirectional plastic waveguide link is presented. The system may include an RF transmitter configured to upconvert and transmit a transmission signal to a carrier frequency, an RF receiver configured to downconvert and receive a reception signal received at the carrier frequency, a bidirectional plastic waveguide device configured to provide a channel for transmitting the transmission signal and a channel for receiving the reception signal, and a microstrip-to-waveguide transition (MWT) configured to transmit a signal between the RF transmitter or the RF receiver and the bidirectional plastic waveguide device. The RF receiver may include a phase detector configured to detect a phase of the downconverted reception signal using a clock signal, and a phase synchronization device configured to adjust a phase of the clock signal based on the detected phase. With this configuration, the present disclosure may present a 50 Gb / s PAM4 bidirectional plastic waveguide link with carrier synchronization using a PI-based Costas loop that shows a significantly superior performance in terms of throughput-distance and energy efficiency compared to the prior art.

Description

[Technical Field]

[0001] The present disclosure relates to waveguide links, and more particularly to 50 Gb / s PAM4 bidirectional plastic waveguide links with carrier synchronization using PI-based Costas loops. [Background technology]

[0002] The demand for greater input / output (I / O) bandwidth in data sensors is increasing due to the explosive growth of network traffic. However, traditional high-speed interconnects face challenges along both functional and economic lines. Copper-based electrical links exhibit critical bandwidth limitations caused by skin loss. Optical links require significant capital expenditures for chip-to-fiber assembly and E / O (Electrical / Optical) and O / E conversion devices in short-reach, high-capacity links.

[0003] As an alternative to solving the problems of conventional high-speed interconnects, recent research has shown that plastic waveguide links, which exhibit inherent low-loss and wideband channel characteristics, could be a promising solution for providing power- and cost-efficient high-speed interconnects. However, prior art only demonstrates single-waveguide transmission due to the low confinement of the waveguide and limited carrier synchronization, which requires phase tuning of an external local oscillator (LO). Summary of the Invention [Problem to be solved by the invention]

[0004] To solve these problems, the present disclosure aims to provide a 50 Gb / s PAM4 bidirectional plastic waveguide link with carrier synchronization using a PI-based Costas loop. [Means for solving the problem]

[0005] According to one embodiment of the present disclosure, an RF receiver is presented that can include a phase detector configured to detect a phase of a downconverted received signal using a clock signal, and a phase synchronization device configured to adjust a phase of the clock signal based on the detected phase.

[0006] The phase synchronization device may also include a loop filter configured to determine a phase control value based on the output signal of the phase detector, and a phase adjuster configured to adjust the phase of the clock signal in accordance with the determined phase control value.

[0007] Furthermore, the loop filter may be a digital loop filter (DLF), and the phase synchronization device may include a sampler configured to sample the output signal of the phase detector based on a predetermined voltage reference value, and the digital loop filter is configured to determine a phase control value by accumulating the sampled values ​​output by the sampler.

[0008] The digital loop filter may also be a second order digital loop filter and is configured to determine the phase control value by accumulating the sum of a current sampled value and a previous sampled value.

[0009] Additionally, the loop filter may be an analog loop filter, and the phase adjuster is configured to adjust the phase of the clock signal in the analog domain.

[0010] The phase synchronization device may further include a multi-phase filter configured to generate an in-phase (I) clock signal and a quadrature-phase (Q) clock signal from a signal of a clock source and provide the generated clock signals to the phase adjuster.

[0011] The RF receiver may further include an in-phase (I) downconverting mixer, a quadrature-phase (Q) downconverting mixer, and a multiplier. The in-phase (I) downconverting mixer is configured to downconvert the received signal using the in-phase (I) clock signal that has been phase-adjusted by the phase adjuster and converted to a carrier frequency by the multiplier. The quadrature-phase (Q) downconverting mixer is configured to downconvert the received signal using the quadrature-phase (Q) clock signal that has been phase-adjusted by the phase adjuster and converted to a carrier frequency by the multiplier.

[0012] The phase detector is also configured to generate, based on the downconverted received signal from the in-phase (I) downconverting mixer and the downconverted received signal from the quadrature-phase (Q) downconverting mixer, an output signal proportional to a sine wave of twice (2θ) the phase offset (θ) between the received signal and the in-phase (I) clock signal.

[0013] The multiplier is also arranged between the in-phase (I) down-conversion mixer and the quadrature-phase (Q) down-conversion mixer and the phase synchronization device, or between the clock source and the phase synchronization device.

[0014] According to one embodiment of the present disclosure, an RF communication system is provided. The RF communication system may include an RF transmitter configured to upconvert a transmission signal to a carrier frequency and transmit the upconverted transmission signal, an RF receiver configured to downconvert a reception signal received at the carrier frequency and receive the downconverted reception signal, a bidirectional plastic waveguide device configured to provide a channel for transmitting the transmission signal and a channel for receiving the reception signal, and a microstrip-to-waveguide transition (MWT) configured to transmit signals between the RF transmitter or the RF receiver and the bidirectional plastic waveguide device. The RF receiver may include a phase detector configured to detect a phase of the downconverted reception signal using a clock signal, and a phase synchronization device configured to adjust the phase of the clock signal based on the detected phase.

[0015] The bidirectional plastic waveguide device may also include a first plastic waveguide unit and a second plastic waveguide unit, each of which includes a plastic waveguide and a metal cladding surrounding the plastic waveguide.

[0016] The MWT may also include a first MWT unit for transmitting the transmission signal from the RF transmitter to the first plastic waveguide unit, and a second MWT unit for transmitting the reception signal from the second plastic waveguide unit to the RF receiver.

[0017] The bidirectional plastic waveguide device may also include a metal shield disposed between the first and second plastic waveguide units. [Effects of the Invention]

[0018] According to the present disclosure, we present a 50 Gb / s PAM4 bidirectional plastic waveguide link with carrier synchronization using a PI-based Costas loop, which exhibits significantly superior performance in terms of throughput-distance and energy efficiency compared to the prior art.

[0019] Furthermore, according to the present disclosure, by enabling phase synchronization in a receiver without using modules such as an ADC or a DSP, it is possible to achieve technical effects of reducing power consumption and facilitating receiver design. [Brief explanation of the drawings]

[0020] [Figure 1A] 1 is a block diagram illustrating an RF communication system employing a bidirectional plastic waveguide link according to one embodiment of the present disclosure. [Figure 1B] FIG. 1 is an exemplary diagram illustrating a link budget for a bidirectional plastic waveguide link according to one embodiment of the present disclosure. [Figure 2A] 1 is an exemplary view of a board-to-waveguide connection viewed from above a printed circuit board; [Figure 2B] 1 is an exemplary view of a board-to-waveguide connection viewed from the underside of a printed circuit board. FIG. [Figure 2C] 10A and 10B are diagrams illustrating an example of a board-to-waveguide connection structure. [Figure 2D] 1 is an exemplary diagram showing the structure of a bidirectional plastic waveguide cable. [Figure 2E] 1 is an exemplary graph showing 1 m channel characteristics and channel crosstalk of a bidirectional plastic waveguide cable. [Figure 2F] 1 is an exemplary graph showing 1 m channel characteristics and channel crosstalk of a bidirectional plastic waveguide cable. [Figure 3A] 1 is a block diagram of a PI-based Costas Loop according to one embodiment of the present disclosure. [Figure 3B]1 is an exemplary graph illustrating a transfer function of a phase detector according to one embodiment of the present disclosure. [Figure 3C] 1 is a block diagram of a secondary DLF according to one embodiment of the present disclosure. [Figure 3D] 3B is an exemplary diagram showing phase synchronization at points A, B, and C of the PI-based Costas Loop of FIG. 3A. FIG. [Figure 4A] 1 is a block diagram illustrating an RF transmitter according to one embodiment of the present disclosure. [Figure 4B] 1 is a block diagram illustrating an RF receiver according to one embodiment of the present disclosure. [Figure 5A] 1 is a block diagram illustrating a configuration for testing data transmission in a bidirectional plastic waveguide link according to one embodiment of the present disclosure. [Figure 5B] FIG. 5B shows an eye diagram of the receiving end (Rx) output measured in the test of FIG. 5A. [Figure 5C] 5B is a graph showing the BER curve measured in the test of FIG. 5A. [Figure 6A] FIG. 1 illustrates a chip micrograph of an RF transmitter according to one embodiment of the present disclosure. [Figure 6B] FIG. 1 illustrates a chip micrograph of an RF receiver according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, when assigning reference numerals to components in each drawing, it should be noted that identical components are assigned the same numerals as much as possible even if they appear in different drawings. Furthermore, when describing the present invention, if it is determined that detailed description of known structures or functions may obscure the gist of the present invention, such detailed description will be omitted.

[0022] Various aspects of the present disclosure are described below. It should be understood that the inventions presented herein can be implemented in a wide variety of forms, and that any specific structure, function, or all of these presented herein are merely exemplary. Based on the inventions presented herein, one skilled in the art will understand that one aspect presented herein can be implemented independently of any other aspect, and that two or more such aspects can be combined in various ways. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects described herein. Furthermore, such an apparatus can be implemented or such a method can be practiced using other structure, function, or structure and function in addition to or other than one or more of the aspects described herein.

[0023] According to the present disclosure, a 50 Gb / s PAM4 bidirectional plastic waveguide link with carrier synchronization using a PI-based Costas loop is presented. In one embodiment, such a link can be realized as a 50 Gb / s PAM4 bidirectional plastic waveguide link with carrier synchronization using 70 GHz transmitter (Tx) and receiver (Rx) ICs in a 28 nm CMOS Fan-Out Wafer Level Packaging (FOWLP) process. Such a link can achieve a figure of merit (FoM) of 2.8 pJ / b / m, demonstrating state-of-the-art performance in terms of throughput-distance and energy efficiency.

[0024] FIG. 1A is a block diagram illustrating an RF communication system employing a bidirectional plastic waveguide link according to one embodiment of the present disclosure.

[0025] As shown in FIG. 1, the RF communication system may include RF chips 100, 100-2, microstrip-to-waveguide transitions (MWTs) 140, 141, and a bidirectional plastic waveguide (hereinafter referred to as "E-TUBE") device 150.

[0026] The RF chip 100 and the MWTs 140 and 141 are implemented on a printed circuit board (PCB) 180. The RF chip 100 may include an RF transmitter 110, an RF receiver 120, and a phase-locked loop (PLL) 130. The RF transmitter (Tx) 110 is configured to upconvert a transmit signal to a carrier frequency and transmit the upconverted signal. The RF receiver (Rx) 120 is configured to downconvert a receive signal received at the carrier frequency and receive the downconverted signal. The E-TUBE device 150 may provide a channel for transmitting a transmit signal and a channel for receiving a receive signal, and for this purpose may include a first plastic waveguide unit 151 for transmitting and a second plastic waveguide unit 152 for receiving. The MWT is configured to transmit signals between the RF transmitter 110 or RF receiver 120 and the E-TUBE device 150, and for this purpose may include a first MWT unit 140 for transmitting a transmission signal from the RF transmitter 110 to the first E-TUBE unit 151, and a second MWT unit 141 for transmitting a reception signal from the second E-TUBE unit 152 to the RF receiver 120. Also, although not represented by a separate reference numeral, the RF chip 100-2 may include corresponding components for transmission and reception between the E-TUBE device 150 and the RF chip 100, as shown in FIG. 1A.

[0027] In one embodiment, the carrier frequency may be in the 70 GHz frequency band, and input signals are transmitted and received (160) via the E-TUBE device 150 in a bandwidth of ∼25 GHz relative to 70 GHz. The PLL 130 can provide a clock signal from a clock source to the RF transmitter 110 and the RF receiver 120, which in such an embodiment can provide an external clock signal of 17.5 GHz. The RF transmitter 110 and the RF receiver 120 can each include multipliers 113, 123 that can convert the provided clock signal to the carrier frequency. In such an embodiment, the multipliers 113, 123 can be implemented as frequency quadruplers (x4) to generate a 70 GHz local oscillator (LO) signal from the 17.5 GHz clock signal. The phase synchronization device 124 in the RF receiver 120 can track the phase offset of the carrier signals generated from the independent clock sources, as described below.

[0028] The performance of such a waveguide channel and transceivers (Tx and Rx) can be determined by a link budget to meet a target bit error rate (BER). The link budget for an exemplary bidirectional plastic waveguide link of the present disclosure is shown in FIG. 1B.

[0029] 2A and 2B are illustrative diagrams of a board-to-waveguide (Board-to-Wg) connection viewed from the top and bottom of a printed circuit board (PCB), respectively, and FIG. 2C is an illustrative diagram showing a board-to-waveguide connection structure.

[0030] As mentioned above, the MWTs 140, 141 can efficiently transfer energy from the transmission line to the waveguide and from the waveguide to the transmission line. To this end, as shown in Figures 2A and 2C, the signals radiated from the MWTs 140, 141 can be directly coupled to the E-TUBE 150 mounted on the PCB 180 using, for example, a board-to-waveguide connector 170 made of aluminum, which can prevent electromagnetic leakage and coupling to adjacent channels. In one embodiment, the Tx and Rx MWTs (i.e., the first MWT unit 140 and the second MWT unit 141) are spaced 8 mm apart on the board.

[0031] FIG. 2D is an exemplary diagram showing the structure of a two-way plastic waveguide cable.

[0032] 2D, the E-TUBE device 150 can be realized as a cable capable of providing a bidirectional channel (a transmit channel and a receive channel) between the RF chip 100 and another RF chip 100-2. The E-TUBE device 150 can include a first E-TUBE unit 151 and a second E-TUBE unit 152 each including a plastic waveguide 153 and a metal cladding 154 surrounding the plastic waveguide to enable bidirectional communication, and a metal shield 155 disposed between the first and second E-TUBE units 151 and 152.

[0033] In one embodiment, the E-TUBE units 151 and 152 may be rectangular dielectric waveguides laminated with a metal film (i.e., surrounded by a metal cladding 154) and may exhibit a frequency-independent insertion loss of 5 dB / m and a group delay of 4 ns / m. The metal cladding 154 confines the radio waves and prevents electromagnetic leakage. As shown in FIG. 2D, the two E-TUBE units 151 and 152 are arranged in parallel with a metal shield 155 placed between the two units 151 and 152. The metal shield 155 prevents electromagnetic coupling between the two units 151 and 152 while preserving the original characteristics of each single E-TUBE channel.

[0034] 2E and 2F are exemplary graphs showing 1 meter channel performance and channel crosstalk of a two-way plastic waveguide cable.

[0035] Figure 2E shows the waveforms of the S-parameters S11 and S12 of the waveguide channel, and Figure 2F shows the NEXT (Near End Cross-talk) and FEXT (Far End Cross-talk) waveforms of the waveguide channel. The channel characteristics show an insertion loss of 13 dB at 70 GHz for a 1 m channel reach, and simulated NEXT and FEXT values ​​lower than -55 dB across the passband. The high-cutoff channel response enables more than 2x bandwidth-efficient single-sideband transmission when compared to conventional RF communications.

[0036] On the other hand, coherent demodulation requires carrier synchronization to maximize the output signal-to-noise ratio (SNR). However, phase offsets in the carrier signal arise from independent Tx / Rx LO generation, and phase delays through the E-TUBE channel cause SNR degradation. Traditionally, DSP-based baseband circuits have been used to overcome this degradation, but the high power consumption of such circuits at high speeds limits their general use.

[0037] Therefore, this disclosure seeks to present a low-power synchronization scheme based on the Costas Loop.

[0038] FIG. 3A is a block diagram of a PI-based Costas Loop according to one embodiment of the present disclosure.

[0039] Such a Costas loop is implemented in an RF receiver 120 and may include a downconverting mixer 122, a phase synchronizer 124, and a multiplier 123, as shown in FIG. 3. The downconverting mixer 122 may include an in-phase (I) downconverting mixer 210, a quadrature-phase (Q) downconverting mixer 211, and a phase detector (PD) 220. The phase synchronizer 124 may include a sampler 240, a loop filter 250, a phase adjuster (PI) 260, and a polyphase filter (PPF) 270. The phase detector 220 is configured to detect the phase of the downconverted received signal using a clock signal, and the phase synchronizer 124 is configured to adjust the phase of the clock signal based on the detected phase.

[0040] Specifically, the multiplier 123 can convert the phase-adjusted in-phase (I) clock signal and the phase-adjusted quadrature-phase (Q) clock signal output from the phase synchronization device 124 to a carrier frequency (ω0) and transmit them to the in-phase (I) downconversion mixer 210 and the quadrature-phase (Q) downconversion mixer 211, respectively. Alternatively, the multiplier 123 can convert a clock signal from a clock source to a carrier frequency (ω0) and transmit it to the phase synchronization device 124, and the phase synchronization device 124 can perform phase adjustment on the clock signal converted to the carrier frequency. In other words, depending on the embodiment, the multiplier 123 is arranged between the in-phase (I) downconversion mixer 210 and the quadrature-phase (Q) downconversion mixer 211 and the phase synchronization device 124, or between the clock source and the phase synchronization device 124.

[0041] The in-phase (I) down-converting mixer 210 receives an in-phase (I) clock signal (LO I ) to calculate the input signal (D in ) to produce a demodulated output proportional to cos(θ), and the quadrature (Q) downconverting mixer 211 can downconvert the quadrature (Q) clock signal (LO Q ) to calculate the input signal (D in ) can be downconverted to produce a demodulated output proportional to sin(θ), where θ is the ratio of the RF receive signal and the in-phase (I) clock signal (LO I ) is the phase offset between the RF receive signal and the in-phase (I) clock signal. Based on the downconverted receive signal (i.e., demodulated output) from in-phase (I) downconverting mixer 210 and the downconverted receive signal (i.e., demodulated output) from quadrature-phase (Q) downconverting mixer 211, phase detector 220 generates an output signal (V PD ) The resulting transfer function of phase detector 220 is as illustrated in FIG. 3B.

[0042] The loop filter 250 filters the output signal (V PD ) can determine a phase control value based on the determined phase control value. The phase adjuster (PI) 260 can adjust the phases of the clock signals (i.e., the in-phase (I) clock signal and the quadrature-phase (Q) clock signal) according to the determined phase control value.

[0043] In one embodiment, the loop filter 250 may be a digital loop filter (DLF), in which case the phase synchronization device 124 may include a sampler 240. The sampler 240 may be configured to sample the output signal (V PD ) based on a predetermined voltage reference value (Vref). In one embodiment, the sampler 240 may be a 1-bit sampler, which may sample the output of the phase detector 220 at the voltage reference value (Vref) using an asynchronous low-frequency clock (Async clk) to output a sampled value having a magnitude of 1 bit, i.e., 0 or 1. The digital loop filter (DLF) 250 is configured to determine a phase control value by accumulating the sampled values ​​output by the sampler 240. In one embodiment, the digital loop filter 250 may be a second-order digital loop filter (DLF), and the second-order DLF is as illustrated in FIG. 3C. As shown in FIG. 3C, the second-order DLF 250 can determine, for example, a 10-bit ([9:0]) phase control value by accumulating the sum of the current sampled value and the previous sampled value. The frequency offset between the Tx and Rx carrier signals can be removed by implementing the second-order DLF using simple digital logic as illustrated in FIG. 3C.

[0044] In other embodiments, the loop filter 250 may be an analog loop filter, in which case the phase synchronizer 124 does not include the sampler 240, and the phase adjuster 260 is configured to adjust the phase of the clock signal in the analog domain according to a phase control value determined by the analog loop filter 250. In other words, in such embodiments, the phase synchronizer 124 can be implemented to perform the phase adjustment in the analog domain.

[0045] Phase adjuster (PI) 260 is configured to adjust the phase of the clock signal (in this example, a 17.5 GHz clock signal) in accordance with the phase control value determined by loop filter 250, as described above. A PI-based Costas loop according to the present disclosure enables a low-jitter LO signal to be obtained compared to a VCO-based Costas loop, which does not cause additional jitter arising from VCO coupling in multi-channel communications. The 17.5 GHz clock signal phase-adjusted by phase adjuster 260 is either multiplied in frequency by multiplier 123 (by a factor of four in this example, a frequency quadrupler (x4)) to generate a clock signal (in this example, a 70 GHz LO signal) converted to a carrier frequency, or the phase adjustment is performed by phase adjuster 260 on the clock signal (i.e., the 70 GHz LO signal) converted to a carrier frequency by multiplier 123.

[0046] The multi-phase filter (PPF) 270 can generate a multi-phase signal having several phases from the received signal. In one embodiment, the multi-phase filter 270 is configured to generate an in-phase (I) clock signal and a quadrature-phase (Q) clock signal having two different phases (in this example, an in-phase (I) and a quadrature-phase (Q)) from a clock signal from a clock source (in this example, a 17.5 GHz clock signal) and provide the signals to the phase adjuster 260. In this case, the phase adjuster 260 can generate a phase-adjusted in-phase (I) clock signal and a phase-adjusted quadrature-phase (Q) clock signal, which are converted to a carrier frequency via the multiplier 123 and then input again to the in-phase (I) downconversion mixer 210 and the quadrature-phase (Q) downconversion mixer 211, respectively.

[0047] Alternatively, as described above, in other embodiments, the multiplier 123 (i.e., a frequency quadrupler) may be disposed between the PLL 130 and the phase synchronizer 124. In this case, the clock signal from the PLL 130 (a 17.5 GHz clock signal in this example) is converted to a carrier frequency (70 GHz in this example) by the multiplier 123 and then provided to the multi-phase filter 270 of the phase synchronizer 124. In this case, the multi-phase filter 270 is configured to generate an in-phase (I) clock signal and a quadrature-phase (Q) clock signal from the clock signal converted to the carrier frequency and provide them to the phase adjuster 260. As a result, the phase synchronizer 124 adjusts the phase of the clock signal in the carrier frequency band, and the phase-adjusted clock signals are transmitted directly to the downconversion mixer 122.

[0048] FIG. 3D is an exemplary diagram showing phase synchronization at points A, B, and C of the PI-based Costas Loop of FIG. 3A.

[0049] As shown in FIG. 3A , point A is the output of the in-phase (I) downconverting mixer 210, point B is the output of the quadrature-phase (Q) downconverting mixer 211, and point C is the output of the phase detector 220. In the phase region of −π / 2≦θ≦π / 2, the phase offset is locked to the origin, where the difference in the phase detector (PD) output decreases. The output swing of the in-phase (I) downconverting mixer 210 eventually converges to a maximum level, while the output swing of the quadrature-phase (Q) downconverting mixer 211 converges to a minimum. In a different phase region, the phase offset is locked to ±π, where the output swing of the in-phase (I) downconverting mixer 210 converges to a maximum, but the output polarity is reversed. Correction for the polarity reversal is performed during initialization, and subsequent phase offsets after initialization are forced to the origin by the Costas loop. The power-efficient implementation of a PI-based Costas loop is made possible by the simple architecture and moderate bandwidth requirements of such a loop.

[0050] The 70 GHz transceivers (Rx and Tx) can employ a direct-conversion architecture to take advantage of the wideband characteristics of the E-TUBE channel.

[0051] FIG. 4A is a block diagram illustrating an RF transmitter according to one embodiment of the present disclosure.

[0052] As shown in FIG. 4A, the RF transmitter (Tx) 110 can include an upconverting mixer (UCM) 111, a power amplifier (PA) 112, and a frequency quadrature amplifier 113. In one embodiment, the UCM 111 exhibits a 2 dB conversion gain with a 1 GHz sine wave input and draws 9 mA of current from a 1.1 V power supply. In another embodiment, the PA 112 can be a three-stage differential PA, and the upconverted signal from the UCM 111 is transmitted to the differential PA. The active stage of the differential PA 112 can rely on a common-source pair in each stage to achieve high gain and linearity. Capacitive neutralization can be implemented to increase power efficiency, allowing the same level of gain to be maintained using a lower bias current. An output matching network can convert the PA output from the differential PA to a single-ended signal for driving a single-ended MWT. A gain of 14 dB can be achieved over a bandwidth of 45 GHz to 70 GHz with a variability of less than 3 dB. The PA 112 can consume 90 mA at a supply voltage of 0.9 V, and the measured P1 dB of the RF transmitter 110 may be 7 dBm.

[0053] FIG. 4B is a block diagram illustrating an RF receiver according to one embodiment of the present disclosure.

[0054] As shown in FIG. 4B, the RF receiver (Rx) 120 can include a low-noise amplifier (LNA) 121, in-phase (I) and quadrature-phase (Q) downconverting mixers (DCMs) 210 and 211, a phase synchronizer 124, and a frequency quadrature amplifier 123. In one embodiment, the LNA 121 can be a two-stage differential LNA, and an input matching network can convert and transmit the single-ended Rx input to the differential LNA. The two-stage differential LNA 121 can minimize SNR degradation while increasing the power of the received input. The LNA can exhibit a measured gain of 16 dB across the 46 GHz to 70 GHz frequency band and can consume 15 mA at a supply voltage of 0.9 V. In one embodiment, the downconversion mixers 210, 211 may employ a Gilbert-type structure using a current bleeder with two resonant inductors and may consume 15 mA at a supply voltage of 1.1 V. The measured gain and noise figure of the Rx may be 20 dB and 8 dB. A replica DCM (i.e., quadrature (Q) DCM) 211 is used to generate a quadrature-phase modulated signal using a 90-degree out-of-phase LO. In one embodiment, the phase detector (PD) 220 may further employ a Gilbert cell and generate an output by using the quadrature data inputs generated from the I and Q DCMs 210, 211.

[0055] In one embodiment, the frequency quadruplers 113, 123 are implemented with two frequency doubler (2x) chains, where two stages of the push-push frequency doubler chain can generate a 70 GHz clock signal, and a buffer can suppress unwanted harmonic frequencies using an LC filter. The LO output is then finally distributed to the Tx and Rx mixers 111, 210, and 211. The quadrature phase shift of the LO can be achieved by utilizing physical delays in the distribution lines, which is insensitive to PVT variations.

[0056] FIG. 5A is a block diagram illustrating a configuration for testing data transmission in a bidirectional plastic waveguide link according to one embodiment of the present disclosure.

[0057] 5A, a 17.5 GHz clock signal is generated individually by a PLL 130 on each board 100, 100-2 and distributed to the RF Tx 110 and RF Rx 120. A pulse pattern generator (PPG) 320, 320-2 can generate and transmit an input signal to the board 100, 100-2, and a bit error rate tester (BERT) 330, 330-2 can measure the BER in a data transmission test.

[0058] Figure 5B shows the 2-phase measurement conducted through a 1 m E-TUBE channel. 31 Figure 5C shows the eye diagram of the Rx output at 50 Gb / s PAM4 with a PRBS (Pseudo Random Binary Sequence) pattern of -1. Figure 5C shows the BER curve measured in the test of Figure 5A. Here, the BER measured at 50 Gb / s with PRBS 31 is 1e. -9 For 3m 25Gb / s NRZ data transmission with a PRBS31 pattern, the -12 A BER of less than 1000 kB is observed. The total DC power of the Tx and Rx is 212 mW.

[0059] A comparison of the performance of the E-TUBE link according to the prior art and the present disclosure is shown in the table below.

[0060] [Table 1]

[0061] As shown in Table 1, the E-TUBE link of the present disclosure can achieve a FoM of 2.8 pJ / b / m, which represents an unprecedented level of performance in terms of throughput-distance results and energy efficiency compared to conventional technologies. Additionally, the E-TUBE link can present a high-speed I / O interface complying with 50GBASE-CR, a 50Gbps standard over twisted pair, to replace existing interconnects in high-throughput links, including 400 / 800Gb / s communications.

[0062] 6A and 6B are diagrams illustrating chip micrographs of an RF transmitter and an RF receiver according to an embodiment of the present disclosure. In one embodiment, the RF transmitter 110 and the RF receiver 120 can be implemented on a PCB 180 with the dimensions and layout shown in FIGS. 6A and 6B, but are not limited thereto and can be designed with different dimensions and layouts depending on the circuit integration level, process, etc.

[0063] The description of the embodiments presented is provided to enable any person skilled in the art to use or practice the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments presented herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0064] 100, 100-2: RF chip 110:RF transmitter 111: Upconvert mixer 112: Power amplifier (PA) 113: Multiplier 120: RF receiver 121: Low noise amplifier (LNA) 122: Downconverting mixer 123: Multiplier 124: Phase synchronizer 130: Phase Locked Loop (PLL) 140, 141: Microstrip to Waveguide Transition (MWT) Unit 150: Bidirectional plastic waveguide device 151, 152: Plastic wave guide unit 153: Plastic Waveguide 154: Metal cladding 155: Metal shield 170: Board-to-waveguide connector 180: Printed circuit board (PCB) 210: In-phase (I) down-converting mixer 211: Quadrature phase (Q) downconverting mixer 220: Phase detector (PD) 230, 280, 290: Buffer 240: Sampler 250: Loop filter 260: Phase adjuster (PI) 270: Multiphase Filter (PPF) 310: Oscillator 320, 320-2: Pulse pattern generator (PPG) 330, 330-2: Bit error rate tester (BERT)

Claims

1. 1. An RF receiver comprising: an in-phase (I) down-converting mixer and a quadrature-phase (Q) down-converting mixer, each utilizing a clock signal to down-convert the received signal and produce a demodulated output; a phase detector configured to detect the phase of the received signal downconverted by the in-phase (I) downconversion mixer and the quadrature-phase (Q) downconversion mixer to generate an output signal; a phase synchronization device configured to adjust the phase of the clock signal based on the detected phase; and including a multiplier, the in-phase (I) down-converting mixer is configured to down-convert the received signal using an in-phase (I) clock signal that has been phase-adjusted by the phase synchronization device and converted to a carrier frequency by the multiplier, and the quadrature-phase (Q) down-converting mixer is configured to down-convert the received signal using a quadrature-phase (Q) clock signal that has been phase-adjusted by the phase synchronization device and converted to a carrier frequency by the multiplier; The phase synchronization device comprises: a loop filter configured to determine a phase control value based on an output signal of the phase detector; a phase adjuster configured to adjust the phase of the clock signal in response to the determined phase control value; and a multi-phase filter configured to generate an in-phase (I) clock signal and a quadrature-phase (Q) clock signal from a signal of a clock source and provide the clock signals to the phase adjuster; RF receiver.

2. the loop filter is a digital loop filter (DLF); the phase synchronization device includes a sampler configured to sample the output signal of the phase detector based on a predetermined voltage reference value; the digital loop filter is configured to determine a phase control value by accumulating the sampled values ​​output by the sampler; 10. The RF receiver of claim 1.

3. the digital loop filter is a second-order digital loop filter and is configured to determine the phase control value by accumulating a sum of a current sampled value and a previous sampled value; 3. The RF receiver of claim 2.

4. the loop filter is an analog loop filter, and the phase adjuster is configured to adjust the phase of the clock signal in the analog domain.

10. The RF receiver of claim 1.

5. the phase detector is configured to generate, based on the downconverted received signal from the in-phase (I) downconverting mixer and the downconverted received signal from the quadrature-phase (Q) downconverting mixer, an output signal proportional to a sine wave of twice (2θ) the phase offset (θ) between the received signal and the in-phase (I) clock signal; 10. The RF receiver of claim 1.

6. the multiplier is disposed between the in-phase (I) down-converting mixer and the quadrature-phase (Q) down-converting mixer and the phase synchronization device, or between the clock source and the phase synchronization device; 10. The RF receiver of claim 1.

7. 1. An RF communication system comprising: an RF transmitter configured to upconvert a transmission signal to a carrier frequency and transmit the upconverted signal; an RF receiver configured to downconvert and receive a received signal at the carrier frequency; a bidirectional plastic waveguide device configured to provide a channel for transmission of the transmit signal and a channel for reception of the receive signal; a microstrip-to-waveguide transition (MWT) configured to transmit signals between the RF transmitter or the RF receiver and the bidirectional plastic waveguide device; The RF receiver includes: an in-phase (I) down-converting mixer and a quadrature-phase (Q) down-converting mixer, each utilizing a clock signal to down-convert the received signal and produce a demodulated output; a phase detector configured to detect the phase of the received signal downconverted by the in-phase (I) downconverting mixer and the quadrature-phase (Q) downconverting mixer to generate an output signal; a phase synchronization device configured to adjust the phase of the clock signal based on the detected phase; and including a multiplier, the in-phase (I) down-converting mixer is configured to down-convert the received signal using an in-phase (I) clock signal that has been phase-adjusted by the phase synchronization device and converted to a carrier frequency by the multiplier, and the quadrature-phase (Q) down-converting mixer is configured to down-convert the received signal using a quadrature-phase (Q) clock signal that has been phase-adjusted by the phase synchronization device and converted to a carrier frequency by the multiplier; The phase synchronization device comprises: a loop filter configured to determine a phase control value based on an output signal of the phase detector; a phase adjuster configured to adjust the phase of the clock signal in response to the determined phase control value; and a multi-phase filter configured to generate an in-phase (I) clock signal and a quadrature-phase (Q) clock signal from a signal of a clock source and provide the clock signals to the phase adjuster; RF communication system.

8. the loop filter is a digital loop filter (DLF); the phase synchronization device includes a sampler configured to sample the output signal of the phase detector based on a predetermined voltage reference value; the digital loop filter is configured to determine a phase control value by accumulating the sampled values ​​output by the sampler; 8. The RF communication system of claim 7.

9. the digital loop filter is a second-order digital loop filter and is configured to determine the phase control value by accumulating a sum of a current sampled value and a previous sampled value; 9. The RF communication system of claim 8.

10. the loop filter is an analog loop filter, and the phase adjuster is configured to adjust the phase of the clock signal in the analog domain.

8. The RF communication system of claim 7.

11. the phase detector is configured to generate, based on the downconverted received signal from the in-phase (I) downconverting mixer and the downconverted received signal from the quadrature-phase (Q) downconverting mixer, an output signal proportional to a sine wave of twice (2θ) the phase offset (θ) between the received signal and the in-phase (I) clock signal; 8. The RF communication system of claim 7.

12. the multiplier is disposed between the in-phase (I) down-converting mixer and the quadrature-phase (Q) down-converting mixer and the phase synchronization device, or between the clock source and the phase synchronization device; 8. The RF communication system of claim 7.

13. The bidirectional plastic waveguide device is a first plastic waveguide unit and a second plastic waveguide unit, each of which includes a plastic waveguide and a metal cladding surrounding the plastic waveguide; The MWT is a first MWT unit for transmitting the transmission signal from the RF transmitter to the first plastic waveguide unit; a second MWT unit for transmitting the received signal from the second plastic waveguide unit to the RF receiver.

8. The RF communication system of claim 7.

14. The bidirectional plastic waveguide device is a metal shield disposed between the first and second plastic waveguide units; 14. The RF communication system of claim 13.

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