Visualization device and program

The visualization device and program address clock synchronization and fluctuation issues by assessing clock states and rate adjustments, providing reliable one-way delay measurements with visual reliability indicators.

JP7747553B2Active Publication Date: 2025-10-01SEIKO SOLUTIONS
View PDF 5 Cites 0 Cited by

Patent Information

Application Number
JP2022036519
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2022-03-09
Publication Date
2025-10-01
Estimated Expiration
2042-03-09

AI Technical Summary

Technical Problem

Existing one-way delay measurement methods are unreliable due to clock synchronization issues and fluctuations, making it difficult to distinguish between network and clock-related fluctuations in measurement results.

Method used

A visualization device and program that assesses the synchronization state and rate adjustment values of communication devices' clocks, determining the reliability of one-way delay measurements and visually presenting the results with color coding to differentiate reliable and unreliable data.

Benefits of technology

Enables accurate presentation of one-way delay time with reliability indicators, allowing users to identify the cause of fluctuations and ensuring reliable measurement results.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 0007747553000001
    Figure 0007747553000001
  • Figure 0007747553000002
    Figure 0007747553000002
  • Figure 0007747553000003
    Figure 0007747553000003
Patent Text Reader

Abstract

To provide a visualization device and a program that can present one-way delay times so that the reliability of measurement results can be seen at a glance.SOLUTION: A visualization device includes: an acquisition unit that acquires a one-way delay time measured by each communication device between two communication devices that perform clock processing; a determination unit that obtains a synchronization state between each of the communication devices with an external reference clock or a rate adjustment value, which is a value for rate adjustment that each of the communication devices performs on its own clock unit for synchronizing with the reference clock, and determines reliability of the one-way delay time based on the synchronization state or the rate adjustment value; and a visualization unit that visualizes the acquired one-way delay time together with a determination result of the reliability.SELECTED DRAWING: Figure 3
Need to check novelty before this filing date? Find Prior Art

Description

[Technical Field]

[0001] The present invention relates to a visualization device and a program, and more particularly to a visualization device and a program for visualizing the measurement results of one-way delay time. [Background technology]

[0002] Conventionally, delay measurement using packet switching is performed by exchanging messages containing timestamps between the two hosts whose delays you want to measure (Figure 7). Figure 7 shows an example in which host A sends a first message to host B, which contains time information t1 from host A's clock unit, and when host B receives the first message, the clock unit of host B outputs time information T2. ​​It also shows an example in which host B sends a second message to host A, which contains time information T3 from host B's clock unit, and when host A receives the second message, the clock unit of host A outputs time information t4. In other words, each host has a local clock unit, and the timestamp is the time in each host's clock unit.

[0003] Using this timestamp, we can calculate the round-trip time (RTT) and one-way delay (OWD). One-way delay from host A to host B: OWD AB , and the one-way delay time OWD from host B to host A BA is calculated according to the following formula:

[0004] OWD AB =T2-t1 OWD BA =t4-T3

[0005] Furthermore, Patent Document 1 discloses a method for measuring transmission delay between devices. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-25474 Summary of the Invention [Problem to be solved by the invention]

[0007] When measuring one-way delay, if the clock on the host being measured is out of sync, the one-way delay calculated based on the timestamp of that out-of-sync clock will not be accurate. To measure accurate one-way delay, the clocks on each host must be synchronized. To synchronize the clocks, it is common to use time synchronization protocols such as NTP (Network Time Protocol) or PTP (Precision Time Protocol).

[0008] Furthermore, since clock fluctuations have a significant effect on the reliability of the measurement results, it is important for highly accurate one-way delay measurements that the clock is stable during measurement.

[0009] Furthermore, even if clocks are synchronized using packet-based time synchronization protocols such as NTP or PTP, clock fluctuations due to loss of synchronization and sudden rate adjustments during resynchronization can have a significant impact on the measurement accuracy of one-way delay time and the reliability of the measurement results.

[0010] Here is an example: If host A and host B are each synchronized using NTP, and while measuring the one-way delay between host A and host B, host A steps its clock in the positive direction by 10 ms to resynchronize, the measured one-way delay between host A and host B after the step will include the 10 ms step, and will not be the correct one-way delay measurement. When measuring one-way delay to measure network quality, such clock fluctuations have a significant impact on one-way delay, posing a serious problem regarding the reliability of the measurement results.

[0011] However, it is difficult to completely prevent such clock fluctuations. When such clock fluctuations occur, they affect the one-way delay measurement results at that time, but it is impossible to determine from the one-way delay measurement results whether the cause of the fluctuation in the measurement value is due to the network between hosts or clock fluctuations. In other words, even if one-way delay measurement data is judged to be unreliable during continuous one-way delay measurements, it is not possible to identify the cause of the fluctuation in the measurement value.

[0012] The present invention has been made to solve the above problems, and aims to provide a visualization device and program that can present one-way delay time so that the reliability of the measurement results can be seen at a glance. [Means for solving the problem]

[0013] In order to achieve the above object, the visualization device of the present invention is configured to include an acquisition unit that acquires the one-way delay time measured by each communication device between two communication devices that perform clock processing; a judgment unit that acquires the synchronization state between each of the communication devices and an external reference clock, or a rate adjustment value that is the value of the rate adjustment that each of the communication devices has made to its own clock unit in order to synchronize with the reference clock, and judges the reliability of the one-way delay time based on the synchronization state or the rate adjustment value; and a visualization unit that visualizes the acquired one-way delay time together with the reliability judgment result.

[0014] Here, the rate adjustment value is the degree of advancement or delay of the clock, for example, the length (in nanoseconds) by which the clock is made faster or slower per second.

[0015] According to this invention, the reliability of the one-way delay time is determined based on the synchronization state with the reference clock in each of the two communication devices or the rate adjustment value of the clock unit for synchronizing with the reference clock, and the acquired one-way delay time is visualized together with the reliability determination result, so that the one-way delay time can be presented so that the reliability of the measurement result can be seen at a glance.

[0016] The acquisition unit can be configured such that, between two communication devices that perform clock processing, each device receives a message including a transmission time from the other device, and acquires the one-way delay time from the difference between the reception time at its own device and the transmission time in the message.

[0017] In the visualization device, the visualization unit can visualize the measurement result of the one-way delay time using a color according to the reliability determination result.

[0018] Furthermore, in the visualization device, when the determination unit determines that the reliability of the one-way delay time is low, the determination unit further determines which communication device has low reliability based on the synchronization state or the rate adjustment value, and the visualization unit can visualize the one-way delay time using a color corresponding to the determination result of which communication device has low reliability.

[0019] Furthermore, in the visualization device, the acquisition unit acquires time series data of the one-way delay times, the determination unit determines the reliability of each of the one-way delay times included in the time series data of the one-way delay times, and the visualization unit visualizes the measurement results of each of the one-way delay times in time series, and can change the background color or the display color of the measurement results between the one-way delay times with high reliability and the one-way delay times with low reliability.

[0020] In addition, in the visualization device, the determination unit can determine that the reliability of the one-way delay time is high if the clock unit of each of the two communication devices is synchronized with the reference clock, and can determine that the reliability of the one-way delay time is low if the clock unit of at least one of the two communication devices is not synchronized with the reference clock.

[0021] In addition, in the visualization device, the judgment unit can judge that the reliability of the one-way delay time is high if the value calculated based on the rate adjustment value of the clock unit in each of the two communication devices is less than a threshold value, and can judge that the reliability of the one-way delay time is low if the value calculated based on the rate adjustment value of the clock unit of at least one of the two communication devices is equal to or greater than a threshold value.

[0022] The program of the present invention is a program for causing a computer to function as each part of the visualization device of the present invention. [Effects of the Invention]

[0023] According to the present invention, it is possible to present the one-way delay time together with the reliability of the measurement result. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a diagram illustrating an example of a clock processing system including a visualization processing device according to an embodiment of the present invention. [Figure 2] 1 is a block diagram showing a configuration of a clock processing device according to an embodiment of the present invention; [Figure 3] 1 is a block diagram showing a configuration of a visualization device according to an embodiment of the present invention. [Figure 4] FIG. 10 is a diagram showing an example of a screen that visualizes one-way delay time together with the reliability of the measurement results. [Figure 5] FIG. 2 is a flowchart showing a visualization process of the visualization device according to the embodiment of the present invention. [Figure 6] FIG. 10 is a diagram showing a process flow for determining the reliability of measurement results in the visualization device according to the embodiment of the present invention. [Figure 7] FIG. 10 is a diagram for explaining a method for measuring one-way delay time. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0026] <Outline of the embodiment of the present invention> In the embodiment of the present invention, the measurement result of one-way delay time is presented together with information indicating the reliability of the measurement result.

[0027] Regarding the reliability of the measurement results, for example, if the clock state is asynchronous, the time between the hosts measuring the one-way delay time is not synchronized, so the reliability of the one-way delay time measurement results can be determined to be low. Alternatively, if the absolute value of the clock rate adjustment value is equal to or greater than a certain threshold, the required measurement accuracy is not met, so the reliability of the one-way delay time measurement results can be determined to be low.

[0028] Here, an example of determining the state of the clock is shown below: The state of the clock can be determined from the synchronization state of the clock and the rate adjustment value of the clock.

[0029] For NTP, the clock synchronization status can be checked using the ntpq command to see if it is synchronized with the NTP server. For PTP, the clock synchronization status can be checked using the portState of portDS.

[0030] In addition, the clock rate adjustment value is the speed at which the own clock advances when synchronizing with the reference clock, i.e., when the difference between the reference clock and the clock of the own device is made zero, and it is checked whether its absolute value is less than a predetermined threshold value.

[0031] In addition, in an embodiment of the present invention, each clock processing device measures one-way delay time, and the measurement results and the clock state at that time are sent to a visualization device. The visualization device determines the reliability from the clock state and displays the reliability of the measurement results together with a time series graph showing the one-way delay measurement results.

[0032] <System configuration according to an embodiment of the present invention> The configuration of a clock processing system including a visualization device according to an embodiment of the present invention will be described. As shown in Fig. 1, clock processing system 100 including a visualization device according to an embodiment of the present invention comprises clock processing devices 10A and 10B, a reference clock generation device 20, and a visualization device 30, and clock processing devices 10A and 10B and reference clock generation device 20 are connected via a network N. Note that the clock processing device is an example of a communication device, and a communication device including a clock processing function is called a clock processing device.

[0033] The reference clock transmission device 20 is a server device that transmits time information of the reference clock. When the time synchronization protocol is NTP, it corresponds to an NTP server. Although a detailed description of the reference clock transmission device 20 will be omitted, the reference clock transmission device 20 has a reference clock and distributes the time information of the reference clock via the network N.

[0034] The clock processing devices 10A and 10B in this embodiment can be configured as a computer including a CPU, RAM, and ROM storing various programs and data. Functionally, as shown in Figure 2, the clock processing devices 10A and 10B include a communication unit 40, a one-way delay measurement unit 42, a time difference calculation unit 44, a local system clock control unit 46, a local system clock unit 48, and an information collection unit 50.

[0035] The communication unit 40 transmits and receives messages to and from the reference clock generation device 20 via the network N.

[0036] Specifically, the communication unit 40 receives a message including time information of the reference clock from the reference clock generation device 20. The communication unit 40 may have multiple ports.

[0037] Furthermore, the communication unit 40 of the clock processing device 10A transmits and receives messages to and from the clock processing device 10B via the network N. Furthermore, the communication unit 40 of the clock processing device 10B transmits and receives messages to and from the clock processing device 10A via the network N.

[0038] 7, the communication unit 40 of the clock processing device 10A transmits a first message including time information output by its own system clock unit 48 to the clock processing device 10B. The communication unit 40 of the clock processing device 10B receives the first message from the clock processing device 10A. The communication unit 40 of the clock processing device 10B transmits a second message including time information output by its own system clock unit 48 to the clock processing device 10A. The communication unit 40 of the clock processing device 10A receives the second message from the clock processing device 10B.

[0039] The one-way delay measurement unit 42 of the clock processing device 10B calculates the difference between the clock time information t1 included in the first message and the time information T2 output by its own system clock unit 48 when the first message is received as the one-way delay time OWD according to the following formula: AB Measured as.

[0040] OWD AB =T2-t1

[0041] The one-way delay measurement unit 42 of the clock processing device 10A calculates the difference between the clock time information T3 included in the second message and the time information t4 output by its own system clock unit 48 when the second message is received as the one-way delay time OWD according to the following formula: BA Measured as.

[0042] OWD BA =t4-T3

[0043] The local system clock unit 48 determines the time information of its own clock based on the rate adjustment value. Note that the local system clock unit 48 is an example of a clock unit.

[0044] Based on the time information of the reference clock contained in the message received from the reference clock transmission device 20, the time difference calculation unit 44 calculates the current time difference between the time information of its own clock and the time information of the reference clock.

[0045] The local system clock control unit 46 updates the time difference resolution rate so that if the reference clock is ahead of the local clock, it speeds up the rate of the local clock, and if it is behind, it slows down the rate, based on the current time difference calculated by the time difference calculation unit 44 and the time difference calculated last time. The time difference resolution rate is the rate for eliminating the time difference with the reference clock, and the natural rate is the rate for matching the speed of the reference clock, and both are updated using known methods.

[0046] The local system clock control unit 46 determines a rate adjustment value for its own clock based on the time difference cancellation rate and the inherent rate in order to make the time difference with the reference clock zero, outputs this to the local system clock unit 48, and updates the synchronization state with the reference clock to a state in which it is synchronized with the reference clock. If, for some reason, the rate adjustment value for its own clock cannot be determined, the local system clock control unit 46 updates the synchronization state with the reference clock to a state in which it is not synchronized with the reference clock.

[0047] The rate adjustment value determined above and the updated synchronization state with the reference clock are output to the information collecting unit 50.

[0048] The information collection unit 50 collects the measurement results of the one-way delay time, the synchronization state with the reference clock, and the rate adjustment value, and transmits the time series data of the one-way delay time, the time series data of the synchronization state with the reference clock, and the time series data of the rate adjustment value to the visualization device 30 via the communication unit 40.

[0049] The visualization device 30 in this embodiment can be configured as a computer including a CPU, RAM, and ROM storing a program for executing a visualization processing routine (described later) and various data. Functionally, the visualization device 30 includes a communication unit 60, an acquisition unit 62, a determination unit 64, a visualization unit 66, and a display unit 68, as shown in FIG.

[0050] The communication unit 60 transmits and receives messages to and from the clock processing devices 10A and 10B via the network N.

[0051] The acquiring unit 62 acquires time series data of one-way delay time, time series data of the synchronization state with the reference clock, and time series data of the rate adjustment value, all collected by the clock processing device 10A.

[0052] The acquiring unit 62 also acquires time series data of one-way delay time, time series data of the synchronization state with the reference clock, and time series data of the rate adjustment value, all collected by the clock processing device 10B.

[0053] The determination unit 64 determines the reliability of each one-way delay time included in the time series data of one-way delay times collected by the clock processing device 10A, based on the synchronization state with the reference clock and the rate adjustment value in each of the clock processing devices 10A and 10B.

[0054] Specifically, when the local clock of each of the clock processing devices 10A, 10B is synchronized with the reference clock corresponding to the measurement timing of the one-way delay time to be determined, and the absolute value of the rate adjustment value of the local clock of each of the clock processing devices 10A, 10B is less than the threshold value, the determination unit 64 determines that the local clock of each of the clock processing devices 10A, 10B is stable and the reliability of the one-way delay time to be determined is high. Also, when the local clock of at least one of the clock processing devices 10A, 10B is not synchronized with the reference clock corresponding to the measurement timing of the one-way delay time to be determined, the determination unit 64 determines that the local clock of at least one of the clock processing devices 10A, 10B is not stable and therefore the reliability of the one-way delay time to be determined is low. Furthermore, if the absolute value of the rate adjustment value of the own clock of at least one of the clock processing devices 10A, 10B is equal to or greater than a threshold value corresponding to the measurement timing of the one-way delay time to be determined, the determining unit 64 determines that the own clock of at least one of the clock processing devices 10A, 10B is unstable and therefore the reliability of the one-way delay time to be determined is low. Note that the stability of the clock may be determined based on whether or not the average value of the rate adjustment values ​​for the past several hours is equal to or greater than a threshold value, whether or not the differential value of the rate adjustment values ​​is equal to or greater than a threshold value, or whether or not the difference value of the rate adjustment values ​​is equal to or greater than a threshold value, and thereby determine the reliability of the one-way delay time.

[0055] Similarly, the judgment unit 64 judges the reliability of each one-way delay time included in the time series data of one-way delay time collected by the clock processing device 10B based on the synchronization state with the reference clock and the rate adjustment value in each of the clock processing devices 10A and 10B.

[0056] The visualization unit 66 displays a screen that visualizes the one-way delay time measurement results collected by the clock processing device 10A and the one-way delay time measurement results collected by the clock processing device 10B together with the reliability determination results on the display unit 68. At this time, the one-way delay time measurement results are visualized using a color that corresponds to the reliability determination result.

[0057] For example, as shown in Fig. 4, in a graph visualizing each measurement result of one-way delay time in a time series, the background display color is changed between periods with high reliability and periods with low reliability. Fig. 4 shows an example in which the background area for periods with high reliability of the measurement result is shown as a shaded area, and the background area for periods with low reliability of the measurement result is shown as a white area. One-way delay time OWD collected by the clock processing device 10B AB is shown by a dashed line, and the one-way delay time OWD collected by the clock processing device 10A is shown by a dashed line. BA The solid line indicates the period of high reliability. The display color may be green for a period of high reliability, and red for a period of low reliability.

[0058] Furthermore, a period of high reliability is a period during which the reliability of the one-way delay time measurement results is continuously determined to be high, and a period of low reliability is a period during which the reliability of the one-way delay time measurement results is continuously determined to be low.

[0059] <Operation of the embodiment of the present invention> First, the clock processing devices 10A and 10B according to the embodiment of the present invention periodically synchronize their own clocks with the reference clock based on the time information of the reference clock contained in a message received from the reference clock transmission device 20.

[0060] Specifically, in the clock processing devices 10A and 10B, the time difference calculation unit 44 calculates the current time difference between the time information of its own clock and the time information of the reference clock based on the time information of the reference clock contained in the message received from the reference clock transmission device 20.

[0061] In addition, in the clock processing devices 10A and 10B, the local system clock control unit 46 determines the rate adjustment value of the local clock based on the current time difference calculated by the time difference calculation unit 44 and the time difference calculated previously. The local clock synchronization state is also updated.

[0062] The clock processing devices 10A and 10B then periodically measure the one-way delay time.

[0063] Specifically, the communication unit 40 of the clock processing device 10A transmits a first message including the time information output by its own system clock unit 48 to the clock processing device 10B.

[0064] The communication unit 40 of the clock processing device 10B receives the first message from the clock processing device 10A.

[0065] The communication unit 40 of the clock processing device 10B transmits a second message including the time information output by its own system clock unit 48 to the clock processing device 10A.

[0066] The communication unit 40 of the clock processing device 10A receives the second message from the clock processing device 10B.

[0067] The one-way delay measurement unit 42 of the clock processing device 10B calculates the difference between the clock time information t1 included in the first message and the time information T2 output by the system clock unit 48 when the first message is received as the one-way delay time OWD. AB Measured as.

[0068] The one-way delay measurement unit 42 of the clock processing device 10A calculates the difference between the clock time information T3 included in the second message and the time information t4 output by the system clock unit 48 when the second message is received as the one-way delay time OWD. BA Measured as.

[0069] Next, in the clock processing devices 10A and 10B, the information collection unit 50 periodically collects the measurement results of the one-way delay time, the synchronization state with the reference clock, and the rate adjustment value, and periodically transmits the time series data of the one-way delay time, the time series data of the synchronization state with the reference clock, and the time series data of the rate adjustment value to the visualization device 30 via the communication unit 40.

[0070] As described above, the one-way delay time is measured periodically. Furthermore, in the clock processing devices 10A and 10B, the local clocks are periodically synchronized by a time synchronization protocol. The measurement of the one-way delay time and the synchronization of the local clocks in the clock processing devices 10A and 10B are performed asynchronously.

[0071] Next, the processing by the visualization device 30 will be described with reference to Fig. 5. Every time the visualization device 30 receives time series data of one-way delay time, time series data of the synchronization state with the reference clock, and time series data of the rate adjustment value from each of the clock processing devices 10A and 10B, the visualization device 30 executes a visualization processing routine shown in Fig. 5.

[0072] First, in step S100, the acquiring unit 62 acquires time series data of one-way delay time, time series data of the synchronization state with the reference clock, and time series data of the rate adjustment value collected by the clock processing device 10A.

[0073] The acquiring unit 62 also acquires time series data of one-way delay time, time series data of the synchronization state with the reference clock, and time series data of the rate adjustment value, all collected by the clock processing device 10B.

[0074] In step S102, the determination unit 64 determines the reliability of each one-way delay time included in the time series data of one-way delay times collected by the clock processing device 10A, based on the synchronization state with the reference clock and the rate adjustment value in each of the clock processing devices 10A and 10B.

[0075] Similarly, the judgment unit 64 judges the reliability of each one-way delay time included in the time series data of one-way delay time collected by the clock processing device 10B based on the synchronization state with the reference clock and the rate adjustment value in each of the clock processing devices 10A and 10B.

[0076] Step S102 is realized by the processing routine shown in FIG.

[0077] Here, the processing routine shown in FIG. 6 is repeatedly executed to determine the one-way delay time included in the time series data of one-way delay time collected by the clock processing device 10A and the one-way delay time included in the time series data of one-way delay time collected by the clock processing device 10B.

[0078] In step S110, the determination unit 64 determines whether the local clock of each of the clock processing devices 10A and 10B is synchronized with the reference clock at the timing when the one-way delay time to be determined is measured. If the local clocks of both the clock processing devices 10A and 10B are synchronized with the reference clock, the process proceeds to step S112. On the other hand, if the local clock of at least one of the clock processing devices 10A and 10B is not synchronized with the reference clock, the process proceeds to step S118.

[0079] In step S112, the determination unit 64 determines the stability of the clock based on the rate adjustment value of the local clock in each of the clock processing devices 10A and 10B at the timing when the one-way delay time to be determined is measured. If the value calculated based on the rate adjustment value of the local clock in both of the clock processing devices 10A and 10B is less than the threshold, the process proceeds to step S114. On the other hand, if the value calculated based on the rate adjustment value of the local clock in at least one of the clock processing devices 10A and 10B is equal to or greater than the threshold, the process proceeds to step S116.

[0080] In step S114, the determining unit 64 determines that the clocks of the clock processing devices 10A and 10B are stable, and determines that the one-way delay time to be determined is highly reliable.

[0081] In step S116, the judgment unit 64 determines that the value calculated based on the rate adjustment value of at least one of the clock processing devices 10A, 10B is large, that the clock itself is unstable, and that the reliability of the one-way delay time being judged is low.

[0082] In step S118, the judgment unit 64 determines that at least one of the clock processing devices 10A, 10B is not synchronized with the reference clock and that its own system clock unit 48 is not stable, and determines that the reliability of the one-way delay time being judged is low.

[0083] Then, in step S104 of the visualization processing routine, the visualization unit 66 visualizes the one-way delay time measurement results collected by the clock processing device 10A and the one-way delay time measurement results collected by the clock processing device 10B together with the reliability determination results. At this time, a screen visualizing the one-way delay time measurement results using a color corresponding to the reliability determination result is displayed on the display unit 68, and the visualization processing routine ends.

[0084] As described above, the visualization device 30 according to the embodiment of the present invention determines the reliability of the one-way delay time based on the synchronization state with the reference clock in each of the clock processing devices 10A, 10B and the rate adjustment value of the clock for synchronizing with the reference clock, and visualizes the measurement result of the one-way delay time together with the reliability determination result, thereby making it possible to present the one-way delay time so that the reliability of the measurement result can be seen at a glance.

[0085] Moreover, by visualizing the reliability judgment results of the measurement results overlaid on the one-way delay time measurement results, it becomes possible to grasp at a glance whether the reliability is high or low. It is also possible to determine whether fluctuations in one-way delay time are due to fluctuations in the clock of the clock processing device.

[0086] The present invention is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the spirit and scope of the present invention.

[0087] For example, in the above-described embodiment, the clock processing device and the visualization device are configured as separate devices, but this is not limiting. Each clock processing device may function as a visualization device. In this case, the reliability of the measurement result may be determined each time the one-way delay time is measured by each clock processing device. Alternatively, the reliability of the measurement result may be determined periodically, separately from the timing at which the one-way delay is measured by each clock processing device. Furthermore, each clock processing device may transmit the collected time series data of the one-way delay time, time series data of the synchronization state with the reference clock, and time series data of the rate adjustment value to the other clock processing devices.

[0088] Furthermore, in a time series graph showing the measurement results of one-way delay time, if it is determined that the measurement results are unreliable, the background color of the graph may be changed to distinguish whether the clock is unstable because it is out of sync or because the absolute value of the clock rate adjustment value is equal to or greater than a threshold. This allows the cause of the unreliability to be determined from the background color of the graph.

[0089] Furthermore, in the above-described embodiment, an example has been described in which the background display color is changed depending on the reliability judgment result, but this is not limited to this. The display color of the measurement result may be changed. For example, in a time series graph showing the measurement result of one-way delay, the color of the graph line may be changed depending on the clock state. Furthermore, in a table showing the measurement result of one-way delay time, the background color of the table may be changed depending on the clock state. Furthermore, in a table showing the measurement result of one-way delay time, the color of the text in the table may be changed depending on the clock state.

[0090] Furthermore, when it is determined that the reliability of the one-way delay time is low, it may be further determined which clock processing device is less reliable based on the synchronization state or the rate adjustment value, and the one-way delay time may be visualized using a color corresponding to the determination result of which clock processing device is less reliable. For example, when changing the background color according to the reliability determination result, a display color corresponding to the determination result of which clock processing device is less reliable may be used.

[0091] The graphs created by the visualization device may be output to a printer and printed out, allowing them to be used for creating status reports, etc.

[0092] Furthermore, the graphs created by the visualization device may be transferred to a terminal owned by the person in charge of managing the device, making it possible to ask for instructions from the person in charge in the event of an abnormality.

[0093] In addition, although the example has been described in which time-series data on one-way delay time, synchronization status, and rate adjustment value are periodically transmitted from each clock processing device, the present invention is not limited to this. Transmission (continuous transmission) may be performed each time one-way delay is measured. [Explanation of symbols]

[0094] 10A, 10B Clock processing unit 20 Reference clock generator 30 Visualization device 40 Communications Department 42 One-way delay measurement unit 44 Time difference calculation section 46 System clock control unit 48 System clock section 50 Information Gathering Department 60 Communications Department 62 Acquisition Department 64 Judgment section 66 Visualization section 68 Display section 100 Clock processing system including visualization device

Claims

1. an acquisition unit that acquires one-way delay times measured by each of two communication devices that perform clock processing; a determination unit that acquires a synchronization state between each of the communication devices and an external reference clock, or a rate adjustment value that is a rate adjustment value that each of the communication devices has made to its own clock unit in order to synchronize with the reference clock, and determines the reliability of the one-way delay time based on the synchronization state or the rate adjustment value; a visualization unit that visualizes the acquired one-way delay time together with the reliability determination result; A visualization device including:

2. The visualization device according to claim 1 , wherein the visualization unit visualizes the one-way delay time using a color corresponding to the result of the reliability determination.

3. When the determination unit determines that the reliability of the one-way delay time is low, the determination unit further determines which of the communication devices has low reliability based on the synchronization state or the rate adjustment value; 3. The visualization device according to claim 1, wherein the visualization unit visualizes the one-way delay time using a color according to a result of determining which communication device has lower reliability.

4. the acquisition unit acquires time series data of the one-way delay time, the determination unit determines the reliability for each of the one-way delay times included in the time-series data of the one-way delay times; 4. The visualization device according to claim 2 or 3, wherein the visualization unit visualizes the measurement results of each of the one-way delay times in a time series, and changes a background color or a display color of the measurement results depending on whether the one-way delay time has high reliability or low reliability.

5. The determination unit If the clock units of the two communication devices are synchronized with the reference clock, it is determined that the reliability of the one-way delay time is high; If the clock unit of at least one of the two communication devices is not synchronized with the reference clock, the reliability of the one-way delay time is determined to be low. A visualization device according to any one of claims 1 to 4.

6. The determination unit If the value calculated based on the rate adjustment value of the clock unit in each of the two communication devices is less than a threshold value, it is determined that the reliability of the one-way delay time is high; A visualization device according to any one of claims 1 to 5, wherein if a value calculated based on the rate adjustment value of the clock unit of at least one of the two communication devices is greater than or equal to a threshold value, the reliability of the one-way delay time is determined to be low.

7. A program for causing a computer to function as each part of the visualization device according to any one of claims 1 to 6.

Citation Information

Patent Citations

  • Time synchronization system of transmission network

    JP1998142361A

  • Time synchronization device, time synchronization method, and time synchronization program

    JP2014027381A

  • Communication device, communication system, and network condition determination method

    JP2015207994A

  • Delay measurement method, delay measurement apparatus, and program

    JP2016025474A

  • Time Synchronization Using Packet-Layer and Physical-Layer Protocols

    US20110261917A1