Semiconductor packaging method

Abstract

The present invention relates to a semiconductor packaging method, and more particularly, to a semiconductor packaging method for packaging semiconductor devices by a wafer-level packaging method. The semiconductor packaging method according to an embodiment of the present invention includes the steps of: providing a wafer having a plurality of semiconductor devices; forming a conductive pattern layer on the wafer using a mask member provided separately from the wafer; and cutting the wafer into individual semiconductor devices.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor packaging method, and more particularly to a semiconductor packaging method for packaging semiconductor devices by a wafer-level packaging method. [Background technology]

[0002] The packaging process is a process of wrapping and packaging semiconductor devices to protect them from the external environment. This packaging process also involves the process of forming conductive patterns to organize the wiring of semiconductor devices so that signals can be exchanged with external devices.

[0003] In the existing packaging process, a wafer having a plurality of semiconductor devices is cut along dicing lines to separate the wafer into individual semiconductor devices, and then a packaging process is performed for each of the separated semiconductor devices. In this existing packaging process, the packaging process must be performed on a chip-by-chip basis, which takes a very long time to package all the semiconductor devices.

[0004] For this reason, a wafer-level packaging method has recently been used in which a packaging process is first performed on a wafer having a plurality of semiconductor devices, and then the wafer is diced into individual semiconductor devices.

[0005] In such wafer-level packaging methods, a conductive pattern for arranging wiring of semiconductor devices is generally formed using a photolithography method. However, such photolithography involves complicated processes, such as coating a wafer with photoresist, performing exposure, development, and etching processes, and then removing the photoresist, which makes it difficult to effectively reduce the time required to package semiconductor devices. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Republic of Korea Publication Patent No. 10-2001-0061786 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention provides a semiconductor packaging method that can improve the productivity of semiconductor devices. [Means for solving the problem]

[0008] A semiconductor packaging method according to an embodiment of the present invention includes the steps of providing a wafer having a plurality of semiconductor elements, and forming a conductive pattern layer on the wafer using a mask member provided separately from the wafer, the conductive pattern layer being electrically connected to the plurality of semiconductor elements.

[0009] The step of providing a wafer may include providing a wafer having a passivation layer formed on the wafer including the plurality of semiconductor elements.

[0010] The step of forming the conductive pattern layer may include the steps of placing the mask member on the wafer and supplying a conductive material to the wafer so that the conductive material passes through the mask member, thereby depositing the conductive material on the wafer.

[0011] The step of disposing the mask member may include aligning the mask member on the wafer.

[0012] The step of disposing the mask member may dispose the mask member above the wafer so as to be spaced apart from the wafer.

[0013] The step of depositing the conductive material may be performed by a sputtering process.

[0014] The step of disposing the mask member and the step of depositing the conductive material may be performed in different chambers.

[0015] The step of disposing the mask member and the step of depositing the conductive material may be performed simultaneously on different wafers.

[0016] The method may further include, after the step of forming the conductive pattern layer, cutting the wafer into individual semiconductor elements.

[0017] The mask member may comprise a shadow mask. [Effects of the Invention]

[0018] According to the semiconductor packaging method of an embodiment of the present invention, a conductive pattern layer is formed on a wafer having a plurality of semiconductor elements through a single process using a mask member provided separately from the wafer, thereby minimizing the number of processes for forming the conductive pattern layer.

[0019] This minimizes the time required to manufacture semiconductor devices, and minimizes the cost of materials used in the process, improving the productivity of semiconductor devices. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a schematic diagram of a semiconductor packaging equipment according to an embodiment of the present invention; [Figure 2] FIG. 1 is a diagram showing a vapor deposition apparatus according to an embodiment of the present invention. [Figure 3] 1A to 1C are diagrams illustrating a semiconductor packaging method according to an embodiment of the present invention; [Figure 4] 1A-1C are diagrams illustrating steps in packaging a semiconductor device according to an embodiment of the present invention. [Figure 5] 1A-1C are diagrams illustrating steps in packaging a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A-1C are diagrams illustrating steps in packaging a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A-1C are diagrams illustrating steps in packaging a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A-1C are diagrams illustrating steps in packaging a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A-1C are diagrams illustrating steps in packaging a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, the embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. These embodiments are provided merely to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art. The drawings may be exaggerated to explain the present invention in detail, and the same reference numerals in the drawings refer to the same components.

[0022] FIG. 1 is a schematic diagram of a semiconductor packaging system according to an embodiment of the present invention, and FIG. 2 is a diagram of a deposition apparatus according to an embodiment of the present invention.

[0023] Referring to FIGS. 1 and 2, a semiconductor packaging equipment according to an embodiment of the present invention may include a cassette 10, an equipment front end module (EFEM) 20, a transfer module (TM) 30, a mask stocker 40, a mask aligner 50, and a vapor deposition (VD) 60.

[0024] Semiconductor packaging equipment can be broadly classified into a cluster type and an inline type depending on the arrangement of the equipment. Here, the cluster type refers to a structure in which multiple other equipment are arranged around one equipment, for example, a conveying device 30, and the inline type refers to a structure in which multiple equipment are arranged in a series. The following description will be given using an example in which semiconductor packaging equipment has a cluster type arrangement, but it goes without saying that embodiments of the present invention can also be applied to semiconductor packaging equipment having an inline type arrangement.

[0025] The cassette 10 stores wafers on which a plurality of unit circuits are formed. A first passivation layer may be further formed on the wafer to cover the plurality of unit circuits. Here, the term "wafer" refers to a substrate on which a plurality of unit circuits are arranged. The unit circuit may refer to a semiconductor device and its wiring structure for performing functions such as information conversion, storage, and calculation. The cassette 10 may store a plurality of wafers on which a plurality of semiconductor devices and a first passivation layer are formed. A plurality of cassettes 10 may be provided, including a cassette 10 for providing wafers to an equipment front-end module 20 (described below) and a cassette 10 for receiving wafers from the equipment front-end module 20.

[0026] In a semiconductor chip manufacturing facility, wafers are loaded into cassettes 10 and provided to an equipment front-end module 20. Although not shown, the wafers provided to the equipment front-end module 20 can be transferred to a transport device 30 via a load lock chamber.

[0027] The wafers stored in the load lock chamber can be transferred to the mask storage device 40, mask alignment device 50, deposition device 60, and auxiliary device 70 by a transfer device 30 equipped with a transfer robot for transferring the wafers. Here, the mask storage device 40 may include a mask storage chamber for storing a mask for forming a conductive pattern layer on the wafer, and the mask alignment device 50 may include a mask alignment chamber for placing a mask removed from the mask storage chamber on the wafer and aligning the mask and the wafer. Furthermore, the deposition device 60 may include a deposition chamber for forming a conductive pattern layer on the wafer using the mask, and the auxiliary device 70 may include an auxiliary chamber for performing auxiliary functions such as heating the wafer.

[0028] Here, the deposition device 60 may include a deposition chamber 610 , a support 620 , a backing plate 630 , and a target 640 .

[0029] The deposition chamber 610 forms a process space where a deposition process is performed, and the deposition chamber 610 can be connected to a predetermined vacuum pump (not shown) to maintain a vacuum state inside the deposition chamber 610. The deposition chamber 610 may further include a gate valve (not shown) for placing a wafer on the support 620 or for transferring the wafer to the outside of the deposition chamber 610, and an exhaust port (not shown) for exhausting process gases and by-products from within the process space.

[0030] A gas supply pipe (not shown) for supplying an inert gas, such as argon (Ar) gas, may be connected to the deposition chamber 610. The gas supply pipe may be connected to the deposition chamber 610 so that the inert gas is supplied to a region where plasma discharge occurs, i.e., a region between the target 640 and the wafer.

[0031] The support 620 is located inside the deposition chamber 610 and supports a wafer to be loaded into the deposition chamber 610. The support 620 may include a built-in heating element such as a heating coil for heating the wafer placed therein. The support 620 may be disposed in the deposition chamber 610 so that at least one of lifting, rotation, and movement can be performed by an elevator (not shown). For example, the support 620 may be lifted and lowered so that the wafer gradually approaches or moves away from the target 640 from an initial position during the sputtering process. The support 620 may rotate the substrate S clockwise or counterclockwise during the sputtering process, or may periodically rotate the substrate S clockwise and counterclockwise.

[0032] The backing plate 630 supports the target 640 and allows a voltage to be applied to the target 640. To this end, the backing plate 630 may be electrically connected to an external power source 650, such as a DC power source, an AC power source, or an RF power source, to supply plasma power to the target 640 from the external power source 650.

[0033] The target 640 is disposed inside the deposition chamber 640 so as to face the support 620. In this case, the target 640 may be formed of a conductive material for forming a conductive pattern layer on the wafer and may have an area larger than the wafer. The target 640 may be disposed on the backside of the backing plate 630 and may be spaced a predetermined distance from and face the wafer.

[0034] Although not shown, it goes without saying that the deposition apparatus 60 may further include a magnetic field forming means disposed inside the deposition chamber 640 .

[0035] The magnetic field generating means vibrates at a certain period (or width) and moves in a certain direction during the sputtering process to form a magnetic field on the surface of the target 640, thereby uniformly distributing the erosion area of ​​the target 640 caused by the magnetic field over the entire area of ​​the target 640 and maximizing the utilization efficiency of the target 640. In addition, the magnetic field generating means uses the magnetic field to form high-density plasma on the surface of the target 640, thereby improving the deposition rate of the conductive pattern layer deposited on the wafer. To this end, the magnetic field generating means may include a magnet module and a magnet moving module.

[0036] Hereinafter, the method for manufacturing a semiconductor chip according to the embodiment of the present invention will be described in more detail with reference to Figures 3 to 9. The method for manufacturing a semiconductor chip according to the embodiment of the present invention may be a method for manufacturing a semiconductor chip using the semiconductor chip manufacturing equipment described above, and therefore, the content described above in relation to the semiconductor chip manufacturing equipment is applicable as is, and therefore, a description of the overlapping content will be omitted.

[0037] FIG. 3 is a diagram schematically showing a method for manufacturing a semiconductor chip according to an embodiment of the present invention.

[0038] Referring to FIG. 3, a method for manufacturing a semiconductor chip according to an embodiment of the present invention includes a step (S100) of providing a wafer W having a plurality of semiconductor elements D and a step (S200) of forming a conductive pattern layer MP1 or MP2 on the wafer W using a mask member M1 or M2.

[0039] In the step of providing a wafer W (S100), a wafer W having a plurality of semiconductor elements D formed thereon is provided, as shown in Fig. 4. Here, the wafer W refers to a substrate having a plurality of unit circuits arranged on it. As mentioned above, the unit circuit may refer to the semiconductor elements D and their wiring structure for performing functions such as information conversion, storage, and calculation.

[0040] Meanwhile, in the step of providing a wafer W, as shown in Fig. 5, a wafer W having a first passivation layer P1 formed thereon can be provided, the wafer W including a plurality of semiconductor elements D. The plurality of semiconductor elements D may each have an input / output pad for electrical connection with an external device. In this case, the first passivation layer P1 is formed on the plurality of semiconductor elements D so as to expose the input / output pad of each semiconductor element D.

[0041] The first passivation layer P1 can be formed by first forming a first passivation film on the wafer W, and then patterning the formed first passivation film by laser drilling or photolithography, or by patterning using a mask. In this case, the first passivation layer can be made of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy, silicone, oxide film (SiO x ) and nitride film (SiN x ) may be formed from at least one material.

[0042] In the step (S200) of forming the conductive pattern layer MP1 or MP2, the conductive pattern layer MP1 or MP2 is formed on the wafer W using a mask member M1 or M2. Here, the conductive pattern layer MP1 or MP2 may include a conductive metal pattern layer. Meanwhile, the mask member M1 or M2 may be formed of a metal material, or may be formed in a film shape using a synthetic resin such as polyimide. Such a mask member M1 or M2 may include a shadow mask provided separately from the wafer W.

[0043] The step (S200) of forming the conductive pattern layer MP1 or MP2 may include forming the first conductive pattern layer MP1 on the first passivation layer P1 and forming the second conductive pattern layer MP2 on the second passivation layer P2. The step of forming the conductive pattern layer MP1 or MP2 may also include disposing a mask member M1 or M2 on the wafer W and supplying a conductive material, for example, a metal material, to the wafer W so that the conductive material passes through the mask member M1 or M2, thereby depositing the conductive material on the wafer W in the same shape as the pattern of the mask member M1 or M2.

[0044] In wafer-level packaging, a wafer W having a plurality of semiconductor elements D is first packaged and then diced into a plurality of semiconductor chips. Conventionally, photolithography has been used to form conductive patterns for arranging the wiring of the semiconductor elements. However, this photolithography method involves complex processes such as coating the wafer W with photoresist, performing exposure, development, and etching processes, and then removing the photoresist, which results in a problem of taking a very long time to package the wafer W.

[0045] Therefore, in an embodiment of the present invention, by forming a conductive pattern layer using mask member M1 or M2 on a wafer on which multiple semiconductor elements are formed, the number of steps required to form the conductive pattern layer can be minimized.

[0046] In the step of forming the first conductive pattern layer MP1, as shown in Fig. 6, the first conductive pattern layer MP1 is formed on the exposed region formed in the first passivation layer P1. Here, the first conductive pattern layer MP1 serves to rewire the electrical path of the semiconductor element D. That is, the first conductive pattern layer MP1 rewires the electrical path of the semiconductor element D in order to electrically connect the semiconductor chip to external devices regardless of the positions of the input / output pads of the semiconductor element D. Such a first conductive pattern layer MP1 can be made of a highly conductive metal material such as copper, silver, aluminum, nickel, etc., or an alloy material containing other components.

[0047] Here, a first mask member M1 may be used to form the first conductive pattern layer MP1. That is, the step of forming the first conductive pattern layer MP1 may include the steps of: placing the first mask member M1 on the wafer W on which the first passivation layer P1 has been formed; and supplying a first conductive material onto the wafer W so as to pass through the first mask member M1, thereby forming the first conductive pattern layer MP1 on the first passivation layer P1 in the same shape as the pattern of the first mask member M1.

[0048] In this case, in the step of forming the first conductive pattern layer MP1, a first mask member M1 may be disposed and aligned above the wafer W so as to be spaced apart from the wafer W, and a first conductive material may be supplied onto the wafer W so as to pass through the first mask member M1 to form the first conductive pattern layer MP1. In this case, the step of disposing the first mask member MP1 and the step of depositing the first conductive material may be performed in different chambers. That is, since the semiconductor packaging equipment may include a mask alignment device and a deposition device as described above, the step of disposing the first mask member MP1 and the step of depositing the first conductive material may be performed in different devices, i.e., different chambers.

[0049] Alternatively, the step of disposing the first mask member MP1 and the step of depositing the first conductive material may be performed simultaneously on different wafers. That is, in the semiconductor packaging equipment according to the embodiment of the present invention, the mask alignment device and the deposition device are provided separately, so that while the mask member is disposed on and aligned on one wafer in the mask alignment device, the first conductive material can be deposited on another wafer in the deposition device.

[0050] In this case, a chemical vapor deposition process may be performed to form the first conductive pattern layer MP1, but the step of forming the first conductive pattern layer MP1 may also be performed by a sputtering process in which particles emitted from a metal target are deposited on the first passivation layer P1.

[0051] Then, as shown in FIG. 7, a step of forming a second passivation layer P2 on the first conductive pattern layer MP1 may be performed.

[0052] In the step of forming the second passivation layer P2, a second passivation film is first formed on the first conductive pattern layer MP1, and the formed second passivation film is then patterned by laser drilling or photolithography, or directly patterned using a mask, to form the second passivation layer P2. At this time, the second passivation layer P2 can be formed from polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy, silicone, oxide film (SiO x ) and nitride film (SiN x ) may be formed from at least one material.

[0053] On the other hand, the second passivation layer P2 may be formed from a material different from that of the first passivation layer P1. When the first passivation layer P1 and the second passivation layer P2 are formed from different materials, the permeated moisture or the like moves along the boundary between the films made of different materials, increasing the movement distance, thereby making it possible to prevent the permeation of moisture or the like.

[0054] After the second passivation layer P2 is formed, a step of forming a second conductive pattern layer MP2 on the second passivation layer P2 may be performed. In the step of forming the second conductive pattern layer MP2, as shown in FIG. 8, the second conductive pattern layer MP2 is formed on the exposed region formed in the second passivation layer P2. Here, the second conductive pattern layer MP2 serves as a seed layer for forming the conductive bump B. Such a second conductive pattern layer MP2 may be made of a metal material such as copper, silver, aluminum, nickel, chromium, titanium, or tungsten, or an alloy material containing other elements. The second conductive pattern layer MP2 may also be formed by stacking multiple layers. In this case, the second conductive pattern layer MP2 may be formed by stacking multiple layers of chromium, chromium-copper alloy, and copper, multiple layers of titanium-tungsten alloy and copper, or multiple layers of aluminum, nickel, and copper.

[0055] Here, a second mask member M2 may be used to form the second conductive pattern layer MP2. That is, the step of forming the second conductive pattern layer MP2 may include the steps of: placing the second mask member M2 on the wafer W on which the second passivation layer P2 has been formed; and supplying a second conductive material onto the wafer W so as to pass through the second mask member M2, thereby forming the second conductive pattern layer MP2 on the second passivation layer P2 in the same shape as the pattern of the second mask member M2.

[0056] In this case, in the step of forming the second conductive pattern layer MP2, a second mask member M2 may be disposed and aligned on the wafer W so as to be spaced apart from the wafer W, and the second conductive material may be supplied onto the wafer W so as to pass through the second mask member M2 to form the second conductive pattern layer MP2. In this case, the step of disposing the second mask member MP2 and the step of depositing the second conductive material may be performed in different chambers, and the step of disposing the second mask member MP2 and the step of depositing the second conductive material may be performed simultaneously on different wafers, as in the case of the first conductive pattern layer MP1.

[0057] In addition, a chemical vapor deposition process may be performed to form the second conductive pattern layer MP2, but the step of forming the second conductive pattern layer MP2 may also be performed by a sputtering process in which particles emitted from a metal target are deposited on the second passivation layer P2, as in the case of the first conductive pattern layer MP1.

[0058] Next, as shown in FIG. 9, a step of forming conductive bumps B on the second conductive pattern layer MP2 may be performed.

[0059] Here, an electrolytic plating process may be used as a method for forming the conductive bump B. Alternatively, the conductive bump B may be formed by directly forming a conductive solder on the second conductive pattern layer MP2, in which case the conductive bump B may be formed on the second conductive pattern layer MP2 based on a ball drop process using a ball drop stencil or a screen printing process.

[0060] In the embodiment of the present invention, a structure in which the first conductive pattern layer MP1 and the second conductive pattern layer MP2 are used to rewire the electrical paths of a semiconductor element has been described as an example, but it goes without saying that it is also possible to form an additional conductive pattern layer between the first conductive pattern layer MP1 and the second conductive pattern layer MP2 and rewire the electrical paths of a semiconductor element using three or more conductive pattern layers.

[0061] Next, as shown in Fig. 10, a step (S300) of cutting the wafer into individual semiconductor elements may be performed. In the step (S300) of cutting the wafer, the wafer is cut along dicing lines to form a plurality of semiconductor chips each including at least one semiconductor element D.

[0062] As described above, according to the semiconductor packaging method of the present invention, a conductive pattern layer is formed on a wafer having a plurality of semiconductor elements through a single process using a mask member provided separately from the wafer, thereby minimizing the number of processes for forming the conductive pattern layer.

[0063] This minimizes the time required to manufacture semiconductor devices, minimizes the cost of materials used in the process, and improves the productivity of semiconductor devices.

[0064] Although the preferred embodiments of the present invention have been described and illustrated using specific terms in the above, these terms are merely for the purpose of clearly describing the present invention, and it is clear that various modifications and changes can be made to the embodiments of the present invention and the terms used without departing from the technical spirit and scope of the claims. These modified embodiments should not be understood separately from the spirit and scope of the present invention, but should be considered to belong to the scope of the claims of the present invention.

Claims

1. providing a wafer comprising a plurality of semiconductor devices; placing a mask member over the wafer; applying a conductive material to the wafer so as to pass through the mask member to form a conductive pattern layer on the wafer; A semiconductor packaging method comprising:

2. The step of providing a wafer includes:

2. The semiconductor packaging method according to claim 1, further comprising providing a wafer on which a passivation layer is formed on the wafer having the plurality of semiconductor elements.

3. The step of placing the mask member includes:

2. The semiconductor packaging method according to claim 1, further comprising aligning the mask member on the wafer.

4. The step of placing the mask member includes:

2. The semiconductor packaging method according to claim 1, further comprising the step of placing the mask member on the wafer so as to be spaced apart from the wafer.

5. The step of depositing a conductive material includes:

10. The semiconductor packaging method of claim 1, performed by a sputtering process.

6. 2. The semiconductor packaging method according to claim 1, wherein the step of disposing the mask member and the step of forming the conductive pattern layer are performed in different chambers.

7. 7. The semiconductor packaging method according to claim 6, wherein the step of disposing the mask member and the step of forming the conductive pattern layer are performed simultaneously on different wafers.

8. After the step of forming the conductive pattern layer, 2. The semiconductor packaging method of claim 1, further comprising the step of cutting the wafer into individual semiconductor devices.

9. 2. The semiconductor packaging method of claim 1, wherein the mask member comprises a shadow mask.

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