Semiconductor device and power module

Abstract

To provide a semiconductor device and a power module, in which power cycle tolerance can be improved, as well as a manufacturing method thereof.SOLUTION: A semiconductor device comprises: a semiconductor chip 12; and a silver firing cap 22 that is formed to cover a source pad electrode 14 on the semiconductor chip. The semiconductor chip is arranged on a first substrate electrode 10B, and has one end of a copper wire 18 bonded on the silver firing cap by means of an ultrasonic wave.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device and a power module. [Background technology]

[0002] As the junction temperature Tj of power modules rises, the power cycle tolerance of conventional technology (aluminum wire) is becoming more difficult. Therefore, in recent years, copper wire has been used instead of aluminum wire to extend the lifespan. Also, upper wiring such as lead material or electrode posts is sometimes used instead of wire. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-4544 [Patent Document 2] Japanese Patent Application Laid-Open No. 2000-100849 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-4796 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when bonding copper wire onto a semiconductor chip, the ultrasonic power is much greater than that of aluminum wire, destroying the device.

[0005] Furthermore, when using upper wiring such as lead materials or electrode posts, Pb-free solder is used as the joining material. However, when Pb-free solder is used, in devices that can withstand temperatures of 200°C or higher, such as silicon carbide (SiC), the melting point is close to the junction temperature Tj = 200°C, and the ΔTj power cycle becomes larger, so the power cycle capability (power cycle life) is reduced.

[0006] The present embodiment provides a semiconductor device and a power module that can improve the power cycle resistance. [Means for solving the problem]

[0007] According to one aspect of this embodiment, a semiconductor device is provided, which includes: a semiconductor chip that performs switching operations between a first electrode formed on an interlayer insulating film on the front surface side and a second electrode formed on a back surface side in response to a signal connected to a control electrode formed on the interlayer insulating film formed on the front surface side; a high heat-resistant film formed on the front surface side, electrically connected to the first electrode, partially covering the first electrode, but not covering the control electrode; a thin film formed between the first electrode and the high heat-resistant film; and a first wire or flat upper wiring having one end electrically connected to the high heat-resistant film. [Effects of the Invention]

[0008] According to this embodiment, it is possible to provide a semiconductor device and a power module that can improve the power cycle resistance. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 10 is a schematic bird's-eye view of a semiconductor device according to Comparative Example 1. [Figure 2] 1A and 1B are schematic bird's-eye views of a semiconductor device according to a first embodiment, showing a state before copper wire bonding and a state after copper wire bonding; [Figure 3] FIG. 2 is a schematic cross-sectional structural view showing a simulation model of the semiconductor device according to the first embodiment. [Figure 4] 4 is a graph showing the effect of the simulation model shown in FIG. 3. [Figure 5] FIG. 10 is a schematic bird's-eye view of a semiconductor device according to Comparative Example 2. [Figure 6] FIG. 10 is a schematic bird's-eye view of a semiconductor device according to a second embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional structural view showing a simulation model 1 (cap structure) of the semiconductor device according to the second embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional structural view showing a simulation model 2 (solder structure) of a semiconductor device according to Comparative Example 2. [Figure 9] 10 is a graph showing the comparison results between Simulation Model 1 and Simulation Model 2. [Figure 10] 1 is a graph showing the relationship between ΔTj power cycle and power cycle life. [Figure 11] FIG. 10 is a diagram showing a state in which a crack has occurred in the wire material. [Figure 12] A graph showing that the amount of strain saturates over time. [Figure 13] 1A to 1D are diagrams showing a method for manufacturing a semiconductor device according to the first or second embodiment, in which (a) is a diagram showing a semiconductor chip, (b) is a diagram showing a mask printing step, (c) is a diagram showing a drying step, and (d) is a diagram showing a firing step. [Figure 14] 14 is a photograph of a silver firing cap manufactured by the manufacturing method shown in FIG. 13. [Figure 15] 10A and 10B are diagrams (photographs) showing the configuration of a module using a semiconductor device according to a second embodiment, in which (a) is a bird's-eye view and (b) is a plan view. [Figure 16] 16 is a diagram (photo) of the structure after the module shown in FIG. 15 has been molded. [Figure 17] A partially enlarged photograph of the module shown in Figure 15. [Figure 18] A partially enlarged photograph of the module shown in Figure 15. [Figure 19] 16 is a photograph showing the entire module shown in FIG. 15. [Figure 20] A partially enlarged photograph of the module shown in Figure 15. [Figure 21] FIG. 1 is a schematic configuration diagram of a module using a semiconductor device according to a first embodiment. [Figure 22] FIG. 5 is a schematic diagram showing changes in current and temperature during a ΔTj power cycle test of the semiconductor device according to the first or second embodiment. [Figure 23] 10 shows an example of a temperature profile in a thermal cycle test of the semiconductor device according to the first or second embodiment. [Figure 24] 1A is a schematic circuit representation of a SiC MISFET in a one-in-one module, and FIG. 1B is a schematic circuit representation of an IGBT in a one-in-one module, which is a semiconductor device according to the first or second embodiment. [Figure 25] FIG. 2 is a detailed circuit representation of a SiC MISFET in a one-in-one module, which is a semiconductor device according to the first or second embodiment. [Figure 26] 1A is a schematic circuit representation of a SiC MISFET in a two-in-one module, and FIG. 1B is a schematic circuit representation of an insulated gate bipolar transistor (IGBT) in a two-in-one module, which is a semiconductor device according to the first or second embodiment. [Figure 27] 3A and 3B are examples of semiconductor devices applied to the semiconductor device according to the first or second embodiment, and are a schematic cross-sectional structural view of an SiC MISFET and a schematic cross-sectional structural view of an IGBT. [Figure 28] FIG. 2 is a schematic cross-sectional structural view of a SiC MISFET including a source pad electrode SP and a gate pad electrode GP, which is an example of a semiconductor device applied to the semiconductor device according to the first or second embodiment. [Figure 29] FIG. 2 is a schematic cross-sectional structural view of an IGBT including an emitter pad electrode EP and a gate pad electrode GP, which is an example of a semiconductor device applied to the semiconductor device according to the first or second embodiment. [Figure 30] FIG. 1 is a schematic cross-sectional structural view of a SiC DI (Double Implanted) MISFET, which is an example of a semiconductor device applicable to the semiconductor device according to the first or second embodiment. [Figure 31] FIG. 1 is a schematic cross-sectional structural view of a SiC trench (T: Trench) MISFET, which is an example of a semiconductor device applicable to the semiconductor device according to the first or second embodiment. [Figure 32]In a schematic circuit configuration of a three-phase AC inverter configured using the semiconductor device according to the first or second embodiment, (a) an example of a circuit configuration in which a SiC MISFET is used as a semiconductor device and a snubber capacitor is connected between a power supply terminal PL and a ground terminal NL, and (b) an example of a circuit configuration in which an IGBT is used as a semiconductor device and a snubber capacitor is connected between a power supply terminal PL and a ground terminal NL. [Figure 33] FIG. 1 is a schematic circuit diagram of a three-phase AC inverter configured using the semiconductor device according to the first or second embodiment in which SiC MISFETs are applied as semiconductor devices. [Figure 34] 1 is a schematic circuit diagram of a three-phase AC inverter configured using the semiconductor device according to the first or second embodiment in which IGBTs are applied as semiconductor devices. DETAILED DESCRIPTION OF THE INVENTION

[0010] Next, embodiments will be described with reference to the drawings. In the following description of the drawings, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following explanation. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0011] Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below. Various modifications can be made to these embodiments within the scope of the claims.

[0012] [Comparative Example 1] As already explained, as the junction temperature Tj of the power module rises, the power cycle resistance of aluminum wire becomes more severe. Therefore, in the semiconductor device according to Comparative Example 1, as shown in FIG. 1, a copper wire 18 is used to connect the first substrate electrode 10B and the second substrate electrode 20B. Specifically, a semiconductor chip 12 is placed on the first substrate electrode 10B, and ultrasonic waves are applied to a predetermined position 18B of the source pad electrode 14 on the semiconductor chip 12 to bond the copper wire 18. Reference numeral 16 denotes a gate pad electrode.

[0013] However, in the semiconductor device according to Comparative Example 1, extremely large ultrasonic power is required to bond the copper wire 18, which may destroy the device. Alternatively, a pad structure must be created to prevent the device from being destroyed, which makes the device structure complicated.

[0014] [First embodiment] (Semiconductor Devices) FIG. 2 is a schematic bird's-eye view of the semiconductor device according to the first embodiment.

[0015] As shown in FIG. 2(a), the semiconductor device according to the first embodiment includes a semiconductor chip 12 and a highly heat-resistant fired film 22 formed to cover the source pad electrode 14 on the semiconductor chip 12.

[0016] For example, the highly heat-resistant fired film 22 may be a silver fired film or a copper fired film. Hereinafter, the silver fired film will be referred to as a "silver fired cap 22" and the copper fired film will be referred to as a "copper fired cap 22."

[0017] 2(b), the semiconductor chip 12 is placed on the first substrate electrode 10B, and one end of the copper wire 18 is ultrasonically bonded onto the baked silver cap 22. The other end of the copper wire 18 is ultrasonically bonded to the second substrate electrode 20B.

[0018] It is to be noted that an Al wire or a clad wire may be used instead of the copper wire 18. In the case of a clad wire, the center is formed of Cu, and Al is bonded to cover the Cu at the center. The clad wire has higher heat resistance and lower thermal resistance than the Al wire.

[0019] Here, the first substrate electrode 10B and the second substrate electrode 20B can also be configured as conductor patterns on the chip-mounting surface of an insulating substrate (circuit board) such as a circuit board made of a metal-ceramic-metal bonded structure, such as a DBC (Direct Bonding Copper) substrate, a DBA (Direct Brazed Aluminum) substrate, or an AMB (Active Metal Brazed, Active Metal Bond) substrate. The same metal material is generally used for the front-side electrode and the back-side electrode of the insulating substrate. For example, a Cu / Al2O3 / Cu structure is applicable to a DBC substrate, an Al / AlN / Al structure is applicable to a DBA substrate, and a Cu / Si3N4 / Cu structure is applicable to an AMB substrate. However, the front-side electrode and the back-side electrode have slightly different roles. The front-side electrode is used to bond chips and electrodes, and cuts patterns to serve as a positive (P) power electrode, negative (N) power electrode, output (Out) power electrode, etc. The back electrode has the role of conducting heat downwards by being joined to a cooler or a heat spreader.

[0020] As described above, the semiconductor device according to the first embodiment employs a structure in which the source pad electrode 14 on the semiconductor chip 12 is capped with a highly heat-resistant sintered material (silver sintered or copper sintered). This buffers the power of the ultrasonic waves applied during copper wire bonding, preventing the device from being destroyed by the large load applied during copper wire bonding, thereby improving the power cycle resistance.

[0021] (Reduction of damage to devices by silver-fired caps) 3 is a schematic cross-sectional structural diagram showing a simulation model of the semiconductor device according to the first embodiment. As shown in FIG. 3, an oxide film 25 is formed on a silicon carbide (SiC)-based semiconductor chip 12, an aluminum electrode 26 is formed on the oxide film 25, a gold (Au) thin film 28 is formed on the aluminum electrode 26 by a plating process, and a baked silver cap 22 is formed on the gold thin film 28.

[0022] Here, aluminum electrodes 26 are shown as an example, but the material of the electrodes is not limited to aluminum, and may be copper (Cu).

[0023] The gold thin film 28 is for attaching the baked silver cap 22. Instead of the gold thin film 28, a silver thin film or a palladium (Pd) thin film may be formed.

[0024] 4 is a graph showing the effect of the simulation model shown in FIG. 3. The horizontal axis represents the film thickness t of the baked silver cap 22. The vertical axis represents the maximum principal stress ratio acting on the oxide film 25 when a displacement DA is applied to the baked silver cap 22. Here, the stress acting on the oxide film 25 when there is no baked silver cap 22 is set to "1" (see point P1).

[0025] As can be seen from the arrow P in FIG. 4, the presence of the baked silver cap 22 dramatically reduces the stress applied to the oxide film 25. Specifically, when the thickness t of the baked silver cap 22 is 5 μm, the maximum principal stress ratio is approximately 0.4 (see point P2). When the thickness t of the baked silver cap 22 is 10 μm, the maximum principal stress ratio is approximately 0.2 (see point P3). When the thickness t of the baked silver cap 22 is 30 μm, the maximum principal stress ratio is approximately 0.1 (see point P4). The thickness t of the baked silver cap 22 is not particularly limited, but is preferably, for example, approximately 10 μm to 100 μm (see line Q).

[0026] As described above, in the semiconductor device according to the first embodiment, electrodes on the device are capped using baked silver. This cap structure acts as a buffer, making it possible to reduce damage from the copper wire 18. Of course, the use of copper wire 18 also enables very strong bonding, which has the effect of increasing power cycle resistance.

[0027] Comparative Example 2 As already explained, as the junction temperature Tj of the power module rises, the power cycle resistance of aluminum wire becomes more severe. Therefore, in the semiconductor device according to Comparative Example 2, as shown in Figure 5, the first substrate electrode 10B and the second substrate electrode 20B are connected using upper wiring 24 such as a lead material or an electrode pillar.

[0028] When using upper wiring 24 such as lead material or electrode posts, Pb-free solders 17A and 17B are used as the joining material. Pb-free solders 17A and 17B are Sn-based solders containing tin (Sn) as the primary component with silver (Ag), copper (Cu), and other additives. However, when Pb-free solders 17A and 17B are used in devices that can withstand temperatures above 200°C, such as silicon carbide (SiC), the melting point is close to the junction temperature Tj = 200°C, and the ΔTj power cycle becomes larger, resulting in a lower power cycle capability.

[0029] [Second embodiment] (Semiconductor Devices) FIG. 6 is a schematic bird's-eye view of a semiconductor device according to the second embodiment.

[0030] As shown in FIG. 6, the semiconductor device of the second embodiment, like the first embodiment, comprises a semiconductor chip 12 and a highly heat-resistant fired film 22 formed to cover the source pad electrode 14 on the semiconductor chip 12.

[0031] As in the first embodiment, the highly heat-resistant baked film 22 is a baked silver cap 22 (or a baked copper cap 22). The film thickness t of the baked silver cap 22 is not particularly limited, but is preferably, for example, about 10 μm to 100 μm.

[0032] The semiconductor chip 12 is placed on the first substrate electrode 10B, and one end of the flat upper wiring 24 is joined to the highly heat-resistant fired film 22 using solder 26A as a joining material. The other end of the upper wiring 24 is joined to the second substrate electrode 20B using solder 26B as a joining material. As with Comparative Example 2, Pb-free solder can be used for the solders 26A and 26B.

[0033] As described above, in the semiconductor device according to the second embodiment, the source pad electrode 14 on the semiconductor chip 12 is capped with a high heat-resistant sintered material (silver or copper), and conventional solder is applied thereon. This reduces the cumulative equivalent strain on the solder, making it possible to improve the power cycle resistance.

[0034] (Comparison of cumulative equivalent strain with and without silver baked cap) 7 is a schematic cross-sectional view showing a simulation model 1 (cap structure) of a semiconductor device according to the second embodiment. As shown in FIG. 7, in simulation model 1, Pb-free solder 17A is used on baked silver cap 22. It is assumed that the thickness of solders 17A and 17B is 100 μm, and the thickness of baked silver cap 22 is 50 μm. It is assumed that the back surface of substrate electrode 10B is cooled at 65° C.

[0035] 8 is a schematic cross-sectional structural diagram showing a simulation model 2 (solder structure) of a semiconductor device according to Comparative Example 2. As shown in FIG. 8, simulation model 2 uses only Pb-free solders 17A and 17B. That is, baked silver cap 22 is not disposed on semiconductor chip 12, but is disposed only below semiconductor chip 12. The film thickness of solders 17A and 17B is assumed to be 150 μm.

[0036] Figure 9 is a graph showing the results of comparing Simulation Model 1 and Simulation Model 2. The vertical axis shows the accumulated equivalent strain applied to the solder, and the horizontal axis shows the junction temperature Tj. The accumulated equivalent strain is used as a guideline for estimating the lifespan of materials such as solder. For the same material, the greater the accumulated equivalent strain, the shorter the lifespan.

[0037] The line segment S connecting points S1 and S2 represents the change in accumulated equivalent strain in simulation model 2 (solder structure). As can be seen from line segment S, in the solder structure, the accumulated equivalent strain increases as the junction temperature Tj rises.

[0038] On the other hand, the line segment C+S connecting points C1 and C2 represents the change in accumulated equivalent strain in simulation model 1 (cap structure). As can be seen from the line segment C+S, in the cap structure, the accumulated equivalent strain hardly changes even when the junction temperature Tj changes due to the buffering effect of the baked silver cap 22.

[0039] Specifically, it was found that the cap structure reduces the cumulative equivalent strain by approximately 32% compared to the solder structure when the junction temperature Tj is 120°C (see points C1 and S1).Furthermore, it was found that the cumulative equivalent strain reduces by approximately 44% when the junction temperature Tj is 200°C (see points C2 and S2).

[0040] As described above, the cap structure has the effect of improving the power cycle resistance, or maintaining the power cycle resistance even when the ΔTj power cycle and MaxTj become large.

[0041] Here, the ΔTj power cycle is the difference between the maximum value MaxTj of the junction temperature Tj when the power cycle is turned on and the junction temperature MinTj when the power cycle is turned off, as shown in the following equation: If MaxTj is 150°C and MinTj is 50°C, the ΔTj power cycle is 100°C, and if MaxTj is 200°C and MinTj is 50°C, the ΔTj power cycle is 150°C.

[0042]

number

[0043] The relationship between the ΔTj power cycle and power cycle life is shown schematically in Figure 10. Normally, as shown in Figure 10, when the ΔTj power cycle is low, the life tends to be longer (see T1), and when the ΔTj power cycle is high, the life tends to be shorter (see T2). Also, wire materials that are bonded at a point are prone to cracks 18C (see Figure 11), while lead materials that are bonded at a surface tend to have a longer life.

[0044] (Relationship between solder life and cumulative equivalent strain) Next, we will explain how to calculate fatigue life. A large load is repeatedly applied so that inelastic strain (plastic strain, creep strain) occurs, and the number of repetitions is small (10 5 Low-cycle fatigue is defined as the fatigue life of a material that is fractured in less than 100 cycles. The fatigue life of low-cycle fatigue is expressed by the Manson-Coffin law shown below.

[0045]

number

[0046] Δε P is the plastic strain amplitude [-], and N j is the plastic fatigue (fatigue life) [times], and C and N are material properties.

[0047]

number

[0048] ε ac_ne (fin_step) is the cumulative equivalent strain in the second cycle, and ε ac_ne (ref_step) is the cumulative equivalent strain in the first cycle. As shown in Figure 12, the amount of strain saturates over time, so Equation 3 is set to a value between the first and second cycles. According to the Manson-Coffin law, Δε P The smaller the accumulated equivalent strain, the longer the life of the solder.

[0049] As described above, in the semiconductor device according to the second embodiment, Pb-free solders 17A and 17B are used on the baked silver cap 22. This allows the baked silver cap 22 to buffer the stress that the solder was directly subjected to, thereby reducing the cumulative equivalent strain on the solder and improving the power cycle resistance.

[0050] [Manufacturing method] A method for manufacturing a semiconductor device according to the first or second embodiment will be described below.

[0051] First, as shown in FIG. 13(a), a thin gold film 28 is formed on the top of the semiconductor chip 12. Next, as shown in FIG. 13(b), a squeegee 30 is used to push firing paste 22P through the openings in a mask 28M, and mask printing is performed on the area corresponding to the source pad electrode 14. Next, as shown in FIG. 13(c), the semiconductor chip 12 on which the firing paste 22P has been mask-printed is dried on a hot plate 32. Finally, as shown in FIG. 13(d), the semiconductor chip 12 is fired (heat + pressure) using heating plates 34U and 34D. This allows a silver fired cap 22 to be formed on the top of the semiconductor chip 12, as shown in FIG. 14.

[0052] In the above process, a dispensing method may be used instead of mask printing, and a fired film of similar quality can be produced using the dispensing method.

[0053] [Module] The configuration of a power module including a plurality of semiconductor devices according to the first or second embodiment will be described below.

[0054] 15 is a diagram (photograph) of the configuration of a module using a semiconductor device according to the second embodiment, where (a) is a bird's-eye view and (b) is a plan view. As shown in FIG. 15, a first substrate electrode 10B and a second substrate electrode 20B are connected by upper wiring 24. Signal electrode terminals G1, D1, and S1 and signal electrode terminals G4, D4, and S4 are extended outward from the first substrate electrode 10B and the second substrate electrode 20B, respectively. Of course, it is also possible to connect substrate electrodes other than the first substrate electrode 10B and the second substrate electrode 20B by the upper wiring 24. Furthermore, a power terminal P corresponding to the drain D1 of the high-level MISFET Q1 is connected to the substrate electrode 10B, and a power terminal O (output terminal) corresponding to the drain D4 of the low-level MISFET Q4 or the source S1 of the high-level MISFET Q1 is connected to the substrate electrode 20B. Furthermore, a power terminal N corresponding to the source S4 of the low-level MISFET Q4 is connected to a land electrode connected to the source pad electrode S1 of the low-level MISFET Q1 via the upper wiring 24. In the above explanation, the high-level MISFET Q1 and the low-level MISFET Q4 correspond to semiconductor devices constituting the circuit of a two-in-one module as shown in FIG. 26(a), for example. Incidentally, they may also be IGBTs Q1 and Q4 of a two-in-one module as shown in FIG. 26(b). The same applies hereinafter.

[0055] Fig. 16 is a diagram (photograph) of the configuration after molding the module shown in Fig. 15. As shown in Fig. 16, first substrate electrode 10B and second substrate electrode 20B are molded from resin M or the like.

[0056] Figures 17 and 18 are partially enlarged photographs of the module shown in Figure 15. As shown in Figures 17 and 18, a semiconductor chip 12 is placed on a first substrate electrode 10B. A baked silver cap 22 is formed on the semiconductor chip 12, and upper wiring 24 is joined onto the baked silver cap 22 using solders 26A and 26B.

[0057] Fig. 19 is a photograph showing the entire module shown in Fig. 15. Fig. 20 is a photograph showing a partial enlargement of the module shown in Fig. 15. As shown in Figs. 19 and 20, the semiconductor chip 12 is connected to signal electrode terminals G1, D1, S1 and signal electrode terminals G4, D4, S4 via wires W.

[0058] 21 is a schematic diagram of a module using the semiconductor device according to the first embodiment. As shown in FIG. 21, it is also possible to bond a plurality of copper wires 18 to one semiconductor chip 12.

[0059] [Bonding energy] Next, the bonding energy used in ultrasonic bonding will be described.

[0060] As shown in the following equation, the bonding energy is the time integral of the friction coefficient μ, velocity v, and pressure P during bonding. Both the friction coefficient μ and velocity v are functions of pressure P. Generally, the higher the bonding energy, the higher the bonding strength.

[0061]

number

[0062] [ΔTj power cycle test] Current I in a ΔTj power cycle test of the semiconductor device according to the first or second embodiment C A schematic diagram of the change in temperature T is shown in FIG.

[0063] As shown in FIG. 22, the ΔTj power cycle test is a test in which the junction temperature is increased and decreased in a relatively short cycle, and can be used to evaluate the life of, for example, a wire junction.

[0064] In the case of a power cycle test, the semiconductor device module is repeatedly energized and cut off to heat the chip, as shown in Fig. 22. In the ΔTj power cycle test of the semiconductor device according to the first or second embodiment, for example, Tj = 150°C for 2 seconds, then turned off and the time until the temperature drops to the cooling temperature (for example, Tj = 50°C, off time = 18 seconds) is repeated.

[0065] [Thermal cycle test] An example of a temperature profile in a thermal cycle test for the semiconductor device according to the first or second embodiment is shown in FIG. 23. The thermal cycle test was carried out in an air atmosphere over a temperature range of -40°C to +150°C. One thermal cycle had a period of 80 minutes, consisting of 30 minutes at -40°C, 10 minutes for heating from -40°C to +150°C, 30 minutes at +150°C, and 10 minutes for cooling from +150°C to -40°C. The forward voltage drop Vf and reverse breakdown voltage Vr were measured every 100 cycles, and no degradation in characteristics was observed.

[0066] Normally, when the junction begins to deteriorate in a thermal cycle test or power cycle test, resistance increases in tests in which a high current is passed in the forward direction, and the forward voltage Vf changes. If the power cycle resistance includes characteristic degradation, but the degradation progresses slowly, the power cycle resistance can be evaluated as high.

[0067] From the results of the ΔTj power cycle test and the heat cycle test, it is clear that the bonding strength of the copper wire 18 or the upper wiring 24 of the semiconductor device according to the first or second embodiment is sufficiently ensured.

[0068] In the first and second embodiments, the copper wire 18 or the solder 26A is disposed on the silver-baked cap 22, but this is not limiting. For example, the upper wiring 24 may be bonded to the silver-baked cap 22 by baking silver. Baking silver on the silver-baked cap 22 can increase the film thickness. This allows for higher heat resistance than the solder 26A, and improves reliability.

[0069] [Specific examples of semiconductor devices] In the semiconductor device 20 according to the first or second embodiment, a schematic circuit representation of the SiC MISFET of the one-in-one module is shown as in FIG. 24(a), and a schematic circuit representation of the IGBT of the one-in-one module is shown as in FIG. 24(b).

[0070] FIG. 24(a) shows a diode DI connected in anti-parallel to a MISFET Q. The main electrodes of the MISFET Q are represented by a drain terminal DT and a source terminal ST. Similarly, FIG. 24(b) shows a diode DI connected in anti-parallel to an IGBT Q. The main electrodes of the IGBT Q are represented by a collector terminal CT and an emitter terminal ET. A fast recovery diode (FRD) or a Schottky barrier diode (SBD) may be attached externally as the diode DI. Alternatively, it is also possible to use only a diode formed in the semiconductor substrate of the MISFET.

[0071] Moreover, a detailed circuit representation of the SiC MISFET of the one-in-one module in the semiconductor device 20 according to the first or second embodiment is shown in FIG.

[0072] Furthermore, multiple MISFETs may be built into one module. For example, five chips (MISFET x 5) can be mounted, and up to five of each MISFET can be connected in parallel. It is also possible to mount some of the five chips for use as diode DI.

[0073] More specifically, as shown in FIG. 25, sense MISFETs are connected in parallel to the MISFET. The sense MISFETs are formed as fine transistors in the same chip as the MISFET. In FIG. 25, SS is a source sense terminal, CS is a current sense terminal, and G is a gate signal terminal. In the first or second embodiment, In terms of form, the semiconductor device Q has sensing MISFETs Qs formed as miniaturized transistors within the same chip.

[0074] Moreover, a schematic circuit representation of the SiC MISFET of the two-in-one module in the semiconductor device 20T according to the first or second embodiment is shown in FIG. 26(a).

[0075] As shown in Figure 26(a), two MISFETs Q1 and Q4 and diodes D1 and D4 connected in anti-parallel to the MISFETs Q1 and Q4 are built into one module. G1 is the gate signal terminal of MISFET Q1, and S1 is the source terminal of MISFET Q1. G4 is the gate signal terminal of MISFET Q4, and S4 is the source terminal of MISFET Q4. P is the positive power supply input terminal, N is the negative power supply input terminal, and O is the output terminal.

[0076] Furthermore, in the semiconductor device 20T according to the first or second embodiment, a schematic circuit representation of the IGBT of the two-in-one module is shown as shown in FIG. 26(b). As shown in FIG. 26(b), two IGBTs Q1 and Q4 and diodes D1 and D4 connected in anti-parallel to the IGBTs Q1 and Q4 are built into one module. G1 is the gate signal terminal of the IGBT Q1, and E1 is the emitter terminal of the IGBT Q1. G4 is the gate signal terminal of the IGBT Q4, and E4 is the emitter terminal of the IGBT Q4. P is the positive power supply input terminal, N is the negative power supply input terminal, and O is the output terminal.

[0077] (Example of semiconductor device configuration) Examples of semiconductor devices applicable to the first or second embodiment include a SiC MISFET having a schematic cross-sectional structure shown in FIG. 27(a) and an IGBT having a schematic cross-sectional structure shown in FIG. 27(b).

[0078] As an example of the semiconductor device 110(Q) applicable to the first or second embodiment, a schematic cross-sectional structure of a SiC MISFET, as shown in FIG. 27( a), includes a semiconductor substrate 126 made of an n-high resistance layer, p body regions 128 formed on the front surface side of the semiconductor substrate 126, source regions 130 formed on the front surface of the p body regions 128, a gate insulating film 132 arranged on the front surface of the semiconductor substrate 126 between the p body regions 128, a gate electrode 138 arranged on the gate insulating film 132, a source electrode 134 connected to the source regions 130 and the p body regions 128, and an n-type gate insulating film 138 arranged on the back surface of the semiconductor substrate 126 opposite to the front surface. + Drain region 124 and n + and a drain electrode 136 connected to the drain region 124.

[0079] In FIG. 27(a), the semiconductor device 110 is configured as a planar gate n-channel vertical SiC MISFET, but as shown in FIG. 31 described later, it may also be configured as an n-channel vertical SiC TMISFET or the like.

[0080] Furthermore, in the semiconductor device 110(Q) applicable to the first or second embodiment, a GaN-based FET or the like can be adopted instead of a SiC MISFET.

[0081] The semiconductor device 110 applicable to the first or second embodiment can be either a SiC-based or GaN-based power device.

[0082] Furthermore, the semiconductor device 110 applicable to the first or second embodiment can be made of a semiconductor known as a wide-gap type having a band gap energy of, for example, 1.1 eV to 8 eV.

[0083] Similarly, as an example of a semiconductor device 110A(Q) applicable to the first or second embodiment, an IGBT, as shown in FIG. 27( b), includes a semiconductor substrate 126 made of an n-high resistance layer, p-body regions 128 formed on the front surface side of the semiconductor substrate 126, emitter regions 130E formed on the front surface of the p-body regions 128, a gate insulating film 132 arranged on the front surface of the semiconductor substrate 126 between the p-body regions 128, a gate electrode 138 arranged on the gate insulating film 132, an emitter electrode 134E connected to the emitter regions 130E and the p-body regions 128, and a p-type emitter electrode 134E arranged on the back surface of the semiconductor substrate 126 opposite to the front surface. + Collector region 124P and p + and a collector electrode 136C connected to the collector region 124P.

[0084] In FIG. 27(b), the semiconductor device 110A is configured as a planar gate n-channel vertical IGBT, but may also be configured as a trench gate n-channel vertical IGBT or the like.

[0085] 28 shows a schematic cross-sectional structure of a SiC MISFET including a source pad electrode SP and a gate pad electrode GP, which is an example of a semiconductor device 110 applicable to the first or second embodiment. The gate pad electrode GP is connected to a gate electrode 138 disposed on a gate insulating film 132, and the source pad electrode SP is connected to a source electrode 134 connected to the source region 130 and the p-body region 128.

[0086] 28, the gate pad electrode GP and the source pad electrode SP are disposed on an interlayer insulating film 144 for passivation that covers the surface of the semiconductor device 110. Note that a fine-structure transistor structure may be formed in the semiconductor substrate 126 below the gate pad electrode GP and the source pad electrode SP, similar to the central part of FIG. 27(a) or FIG.

[0087] Furthermore, as shown in FIG. 28, in the central transistor structure as well, the source pad electrode SP may be arranged to extend on the interlayer insulating film 144 for passivation.

[0088] 29 shows a schematic cross-sectional structure of an IGBT including a source pad electrode SP and a gate pad electrode GP, which is an example of a semiconductor device 110A applied to the first or second embodiment. The gate pad electrode GP is connected to a gate electrode 138 disposed on a gate insulating film 132, and the emitter pad electrode EP is connected to an emitter electrode 134E connected to the emitter region 130E and the p-body region 128.

[0089] 29, the gate pad electrode GP and the emitter pad electrode EP are disposed on an interlayer insulating film 144 for passivation that covers the surface of the semiconductor device 110A. Note that a microstructure IGBT structure may be formed in the semiconductor substrate 126 below the gate pad electrode GP and the emitter pad electrode EP, similar to that shown in FIG. 27(b) or the central portion of FIG. 29.

[0090] Furthermore, as shown in FIG. 29, in the IGBT structure in the central portion, the emitter pad electrode EP may be arranged to extend on the interlayer insulating film 144 for passivation.

[0091] -SiC DIMISFET- FIG. 30 shows a schematic cross-sectional structure of a SiC DIMISFET, which is an example of a semiconductor device 110 applicable to the first or second embodiment.

[0092] As shown in FIG. 30, the SiC DIMISFET applicable to the first or second embodiment includes a semiconductor substrate 126 made of an n-high resistance layer, a p-body region 128 formed on the surface side of the semiconductor substrate 126, and an n-type semiconductor layer 128 formed on the surface of the p-body region 128. +a source region 130, a gate insulating film 132 disposed on the surface of the semiconductor substrate 126 between the p-body region 128, a gate electrode 138 disposed on the gate insulating film 132, a source electrode 134 connected to the source region 130 and the p-body region 128, and an n-type gate insulating film 138 disposed on the back surface of the semiconductor substrate 126 opposite to the front surface. + Drain region 124 and n + and a drain electrode 136 connected to the drain region 124.

[0093] In FIG. 30, semiconductor device 110 includes p-body region 128 and n-type junctions formed on the surface of p-body region 128. + The source region 130 is formed by double ion implantation (DI), and the source pad electrode SP is connected to a source electrode 134 connected to the source region 130 and the p-body region 128. The gate pad electrode GP (not shown) is connected to a gate electrode 138 arranged on the gate insulating film 132. Furthermore, the source pad electrode SP and the gate pad electrode GP (not shown) are arranged on an interlayer insulating film 144 for passivation that covers the surface of the semiconductor device 110, as shown in FIG.

[0094] As shown in FIG. 30, in the SiC DIMISFET, a depletion layer as shown by the dashed line is formed in the semiconductor substrate 126 made of the n-high resistance layer sandwiched between the p-body regions 128, and therefore the channel resistance R JFET Furthermore, a body diode BD is formed between p body region 128 and semiconductor substrate 126, as shown in FIG.

[0095] -SiC TMISFET- An example of a semiconductor device 110 applicable to the first or second embodiment, a schematic cross-sectional structure of a SiC TMISFET, is shown in FIG.

[0096] As shown in FIG. 31, a SiC TMISFET applicable to the first or second embodiment includes a semiconductor substrate 126N made of an n-layer, a p-body region 128 formed on the surface side of the semiconductor substrate 126N, and an n-type semiconductor layer 129 formed on the surface of the p-body region 128. + a source region 130; a trench gate electrode 138TG formed in a trench extending through the p-body region 128 and reaching the semiconductor substrate 126N via a gate insulating layer 132 and interlayer insulating films 144U and 144B; a source electrode 134 connected to the source region 130 and the p-body region 128; and an n-type gate electrode 138TG disposed on the back surface of the semiconductor substrate 126N opposite to the front surface. + Drain region 124 and n + and a drain electrode 136 connected to the drain region 124.

[0097] 31, semiconductor device 110 has a trench gate electrode 138TG formed in a trench that penetrates p-body region 128 and reaches semiconductor substrate 126N, with gate insulating layer 132 and interlayer insulating films 144U and 144B interposed therebetween, and source pad electrode SP is connected to source electrode 134 connected to source region 130 and p-body region 128. Gate pad electrode GP (not shown) is connected to gate electrode 138 arranged on gate insulating film 132. Furthermore, source pad electrode SP and gate pad electrode GP (not shown) are arranged on interlayer insulating film 144U for passivation that covers the surface of semiconductor device 110, as shown in FIG.

[0098] In the SiC TMISFET, the channel resistance R associated with the junction FET (JFET) effect like in the SiC DIMISFET is JFET Furthermore, a body diode BD is formed between p body region 128 and semiconductor substrate 126N.

[0099] In the schematic circuit configuration of a three-phase AC inverter 140 configured using the semiconductor device according to the first or second embodiment, an example of a circuit configuration in which a SiC MISFET is used as the semiconductor device and a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL is shown in FIG. 32(a). Similarly, when the semiconductor device according to the first or second embodiment is used, In the schematic circuit configuration of the configured three-phase AC inverter 140A, an example of a circuit configuration in which an IGBT is used as a semiconductor device and a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL is shown in FIG. 32(b).

[0100] When the semiconductor device according to the first or second embodiment is connected to a power supply E, a large surge voltage Ldi / dt is generated due to the inductance L of the connection line, due to the fast switching speed of the SiC MISFET or IGBT. For example, if the current change di=300 A and the time change dt due to switching=100 nsec, then di / dt=3×109 (A / s). The surge voltage Ldi / dt varies depending on the value of inductance L, but this surge voltage Ldi / dt is superimposed on the power supply V. This surge voltage Ldi / dt can be absorbed by a snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

[0101] (Example of application using semiconductor devices) Next, with reference to FIG. 33, a three-phase AC inverter 140 configured using the semiconductor device according to the first or second embodiment in which SiC MISFETs are applied as semiconductor devices will be described.

[0102] 33, the three-phase AC inverter 140 includes a gate drive section 150, a semiconductor device section 152 connected to the gate drive section 150, and a three-phase AC motor section 154. The semiconductor device section 152 is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor section 154. Here, the gate drive section 150 is connected to SiC MISFETs Q1·Q4, SiC MISFETs Q2·Q5, and SiC MISFETs Q3·Q6.

[0103] The semiconductor device section 152 is connected between the positive terminal (+) and negative terminal (-) of the converter 148 to which the storage battery (E) 146 is connected, and includes SiC MISFETs Q1-Q4, Q2-Q5, and Q3-Q6 that form an inverter. Freewheel diodes D1-D6 are connected in antiparallel between the sources and drains of the SiC MISFETs Q1-Q6, respectively.

[0104] Next, with reference to FIG. 34, a three-phase AC inverter 140A configured using the semiconductor device 20T according to the first or second embodiment, in which IGBTs are used as semiconductor devices, will be described.

[0105] 34, the three-phase AC inverter 140A includes a gate drive unit 150A, a semiconductor device unit 152A connected to the gate drive unit 150A, and a three-phase AC motor unit 154A. The semiconductor device unit 152A is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 154A. Here, the gate drive unit 150A is connected to IGBTs Q1·Q4, IGBTs Q2·Q5, and IGBTs Q3·Q6.

[0106] The semiconductor device unit 152A is connected between the positive terminal (+) and negative terminal (-) of the converter 148A to which the storage battery (E) 146A is connected, and includes IGBTs Q1, Q4, Q2, Q5, and Q3, Q6 that form an inverter configuration. Furthermore, freewheel diodes D1 to D6 are connected in antiparallel between the emitters and collectors of the IGBTs Q1 to Q6, respectively.

[0107] The semiconductor device or power module according to this embodiment can be formed into any of one-in-one, two-in-one, four-in-one, six-in-one, and seven-in-one types. is.

[0108] As described above, according to the present embodiment, it is possible to provide a semiconductor device, a power module, and a manufacturing method thereof that are capable of improving the power cycle resistance.

[0109] [Other embodiments] Although the embodiments have been described above, the descriptions and drawings that form part of this disclosure are illustrative and should not be understood as limiting. From this disclosure, various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art.

[0110] As such, it includes various embodiments not described here. [Industrial Applicability]

[0111] The semiconductor device and power module of this embodiment can be used in semiconductor module manufacturing techniques such as IGBT modules, diode modules, and MOS modules (Si, SiC, GaN), and can be applied to a wide range of application fields such as inverters for HEVs / EVs, inverters for industrial equipment, and converters. [Explanation of symbols]

[0112] 10B...first substrate electrode 12...Semiconductor chip 14...Source pad electrode 16...Gate pad electrode 17A, 17B, 26A, 26B...Solder 18...Copper wire 20B...second substrate electrode 22...High heat-resistant baked film (silver baked cap, copper baked cap) 24...Upper wiring 25...Oxide film 26...Aluminum electrode 28...gold thin film Tj: Junction temperature

Claims

1. a semiconductor chip that performs a switching operation between a first electrode formed on the interlayer insulating film on the front surface side and a second electrode formed on the back surface side in response to a signal connected to a control electrode formed on the interlayer insulating film on the front surface side; a high heat-resistant film formed on the front surface side, electrically connected to the first electrode, partially covering the first electrode, and not covering the control electrode; a thin film formed between the first electrode and the high heat resistance film; a first wire or flat upper wiring whose one end is electrically connected to the high heat resistance film; Equipped with The high heat resistance film is a silver fired film or a copper fired film. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein said high heat resistance film is thicker than said first electrode.

3. 2. The semiconductor device according to claim 1, wherein said thin film is a gold, silver or palladium thin film.

4. The semiconductor device according to claim 1 , wherein the first electrode is an aluminum or copper electrode.

5. The device further includes a first electrode pattern formed on an insulating substrate, a second electrode pattern arranged apart from the first electrode pattern in a plan view, and a third electrode pattern; The semiconductor device according to claim 1 , wherein the semiconductor chip is disposed on the first electrode pattern.

6. 6. The semiconductor device according to claim 5, further comprising a second wire electrically connecting said third electrode pattern and said control electrode.

7. 7. The semiconductor device according to claim 6, wherein external connection terminals are connected to said first to third electrode patterns, respectively.

8. 6. The semiconductor device according to claim 5, further comprising a third wire connected directly to a region of the first electrode pattern that is not covered by the high heat resistance film, separate from the first wire or the upper wiring that is connected to the high heat resistance film on the first electrode pattern.

9. 8. The semiconductor device according to claim 7, further comprising a resin that seals said first to third electrode patterns, said semiconductor chip, said first wire or said upper wiring, and at least a part of said external connection terminal.

10. 6. The semiconductor device according to claim 5, wherein the first wire comprises a plurality of wires, one end of each of the plurality of first wires being bonded to the high heat resistance film and the other end being bonded to the second electrode pattern.

11. A semiconductor device as described in Claim 5, wherein the thickness of the upper wiring is thicker than the thickness of the first electrode pattern.

12. 10. The semiconductor device according to claim 9, wherein the semiconductor chip comprises a first SiC MISFET and a second SiC MISFET connected in series with the first SiC MISFET, and a first diode and a second diode connected in anti-parallel to the first SiC MISFET and the second SiC MISFET, respectively, are sealed in the resin.

13. 2. The semiconductor device according to claim 1, wherein said high heat resistance film is disposed on said first electrode as a cap with chamfered corners.

14. 2. The semiconductor device according to claim 1, wherein the highly heat-resistant film has a thickness ranging from 10 μm to 100 μm.

15. The first wire comprises a copper wire, an Al wire, or a clad wire in which Al is bonded to cover a central Cu portion, The semiconductor device according to claim 1 , wherein one end of said first wire is ultrasonically bonded.

16. the semiconductor chip includes a power transistor; 2. The semiconductor device according to claim 1, wherein said power transistor is formed below a location where said first electrode is provided.

17. 7. The semiconductor device according to claim 6, wherein a power terminal is connected to said first electrode pattern and said second electrode pattern, and a signal electrode terminal is connected to said third electrode pattern.

18. A power module comprising a plurality of semiconductor devices according to claim 1.

19. 2. The semiconductor device according to claim 1, wherein the semiconductor chip comprises a plurality of chips connected in parallel.

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