Display device

Abstract

To provide a display device that can suppress a change in luminance by an off-leak of a switching transistor.SOLUTION: A display device 1 comprises a plurality of pixels, and each of the plurality of pixels comprises: a light emitting element EL; a holding capacitor Cs; a drive transistor TD; and a writing transistor T3. The holding capacitor Cs is formed of: a lower part electrode 310 that is connected to a gate electrode of the drive transistor TD, and connected to the writing transistor T3; a first insulation layer 140; a first top part electrode 220 that is connected to a source electrode of the drive transistor TD, and has a first facing part to be arranged facing the lower part electrode 310; a second insulation layer 150; and a second top part electrode 320 that is connected to the source electrode of the drive transistor TD, and has a second facing part to be arranged facing the lower part electrode 310, in which the first facing part and second facing part are formed in a part where the first and second facing parts are not overlapped, and the lower part electrode 310 is formed so as to overlap each of the first facing part and second facing part.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] Organic EL elements are known as electro-optical elements used in self-luminous display devices. Organic EL elements are electro-optical elements that utilize the phenomenon of light emission when an electric field is applied to an organic thin film, and color gradations are obtained by controlling the value of the current flowing through the organic EL element. Therefore, organic EL display devices that use organic EL elements are provided with a pixel circuit for each pixel, which includes a drive transistor for controlling the amount of current through the organic EL element, a storage capacitor for storing a control voltage for the drive transistor, and a sampling transistor (write transistor) for writing the control voltage to the storage capacitor (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-057947 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the charge held in the storage capacitor is reduced due to off-leakage of a switching transistor such as a writing transistor, the light-emitting current flowing through a light-emitting element such as an organic EL element is reduced, and the desired brightness cannot be maintained, that is, the brightness may change due to off-leakage. Patent Document 1 does not disclose how to suppress the change in brightness due to off-leakage of a writing transistor.

[0005] Therefore, the present disclosure provides a display device that can suppress changes in luminance due to off-leakage of a switching transistor. [Means for solving the problem]

[0006] A display device according to one aspect of the present disclosure is a display device including a plurality of pixels arranged two-dimensionally, each of the plurality of pixels including a light-emitting element, a storage capacitor for storing a data signal supplied via a data signal line, a drive transistor for supplying a current corresponding to the data signal to the light-emitting element, and a write transistor connected between the data signal line and a gate electrode of the drive transistor, the write transistor having one of a source electrode and a drain electrode connected to the data signal line, and the storage capacitor including a gate electrode of the drive transistor and a first electrode layer connected to the write transistor, and a first insulating layer covering the first electrode layer. a second electrode layer connected to the source electrode of the driving transistor and having a first opposing portion arranged on the first insulating layer opposite the first electrode layer; a second insulating layer covering the first insulating layer and the second electrode layer; and a third electrode layer connected to the source electrode of the driving transistor and at least a portion of which is formed on the second insulating layer, the third electrode layer having a second opposing portion arranged opposite the first electrode layer, wherein the first opposing portion and the second opposing portion are formed at positions where they do not overlap each other in a planar view of the display device, and the first electrode layer is formed to overlap each of the first opposing portion and the second opposing portion in the planar view. [Effects of the Invention]

[0007] According to the display device according to one aspect of the present disclosure, it is possible to suppress a change in luminance due to off-leakage of the switching transistor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view schematically showing the configuration of a pixel circuit of a display device according to a comparative example. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and schematically showing the configuration of a pixel circuit of a display device according to a comparative example. [Figure 3]FIG. 3 is a block diagram showing a functional configuration of the display device according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a configuration of a pixel circuit of the display device according to the first embodiment. [Figure 5] FIG. 5 is a plan view schematically showing the configuration of a pixel circuit of the display device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. 5, schematically showing the configuration of a pixel circuit of the display device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5, schematically showing the configuration of a pixel circuit of the display device according to the first embodiment. [Figure 8] FIG. 8 is a diagram for explaining the effect of the display device according to the first embodiment. [Figure 9] FIG. 9 is a timing chart of various gate control signals of the display device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view schematically showing a first example of the configuration of a pixel circuit of a display device according to Embodiment 2, taken along a cutting line corresponding to cutting line VI-VI in FIG. [Figure 11] FIG. 11 is a cross-sectional view schematically showing a second example of the configuration of a pixel circuit of a display device according to Embodiment 2, taken along a cutting line corresponding to cutting line VI-VI in FIG. [Figure 12] FIG. 12 is a cross-sectional view schematically showing the configuration of a pixel circuit of a display device according to Embodiment 2, taken along a line corresponding to line VII-VII in FIG. [Figure 13] FIG. 13 is a diagram illustrating a method for manufacturing a display device according to the second embodiment. [Figure 14] FIG. 14 is a plan view schematically showing the configuration of a pixel circuit of a display device according to the third embodiment. [Figure 15] FIG. 15 is a cross-sectional view taken along the line XV-XV in FIG. 14, schematically showing the configuration of a pixel circuit of the display device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Background to this disclosure) Prior to describing the present disclosure, the background to the present disclosure will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view schematically showing the configuration of a pixel circuit 1011 of a display device according to a comparative example. FIG. 2 is a cross-sectional view schematically showing the configuration of the pixel circuit 1011 of the display device according to the comparative example, taken along the II-II cutting line in FIG. 1. Note that, hereinafter, the circuit and the region in which the circuit is formed may be referred to by the same reference numeral.

[0010] 1, the sub-pixel circuits 1011R, 1011G, and 1011B are formed in three sub-pixel regions 1011R, 1011G, and 1011B, respectively, which are obtained by dividing the pixel region 1011. The sub-pixel circuits 1011R, 1011G, and 1011B have the same configuration.

[0011] The pixel circuit 1011 is formed by, for example, a first wiring layer, a semiconductor layer, and a second wiring layer arranged in this order on a substrate 110. The first wiring layer mainly includes control signal lines INI, REF, and WS, reference voltage lines VINI and VREF, and a storage capacitor Cs R , Cs G , Cs B The second wiring layer is used as one electrode of the data signal line Vdat (for example, the lower electrode 210 shown in FIG. 2) and the gate electrode of each transistor. The semiconductor layer is used as the channel region of each transistor. R , Vdat G , Vdat B , positive power supply line VCC, holding capacitance Cs R , Cs G , Cs B The other electrode (for example, the first upper electrode 220 shown in FIG. 2) and the source electrode and drain electrode of each transistor are used. Different layers are connected to each other by vias. The positive power supply line VCC is an example of a power supply line.

[0012] The light-emitting element EL included in the pixel circuit 1011 R , E.L. G , E.L.B The storage capacitors Cs R , Cs G , Cs B Data signal (data voltage) Vdat held in R , Vdat G , Vdat B The light is emitted at a brightness according to the storage capacitance Cs R , Cs G , Cs B Each of these has a driving transistor TD R , T.D. G , T.D. B The charge for determining the potential difference Vgs between the gate and source of each of the data signal lines Vdat R , Vdat G , Vdat B It is accumulated through

[0013] Although not shown in the figure, a planarization layer is provided to cover the substrate, the first wiring layer, the semiconductor layer, and the second wiring layer, and the light-emitting element EL R , E.L. G , E.L. B is formed on the planarization layer.

[0014] In the above, "R", "G", and "B" are added to the reference numerals of the components according to the sub-pixel circuit, but in the following, when there is no need to distinguish between the three sub-pixel circuits, the reference numerals may be used without the "R", "G", and "B" notation. R , Cs G , Cs B For example, it may also be referred to as a storage capacitance Cs.

[0015] As shown in FIG. 2, the pixel circuit 1011 has a cross-sectional configuration including a substrate 110, a first undercoat layer 120, a second undercoat layer 130, a first insulating layer 140, a second insulating layer 150, metal layers 160 and 180, a light-emitting layer 170, a fourth insulating layer 200, a lower electrode 210, a first upper electrode 220, a positive power supply line VCC, and a data signal line Vdat GIn the example of FIG. 2, the display device is a top-emission type display device. That is, the light-emitting element EL R , E.L. G , E.L. B The light emitted from the surface of the substrate 110 is emitted in the positive direction of the Z axis.

[0016] The substrate 110 is, for example, a glass substrate or a glass film. On the substrate 110, a plurality of pixels (pixel circuits 1011) are formed.

[0017] The first undercoat layer 120 is provided so as to cover the surface of the substrate 110. The first undercoat layer 120 is, for example, an insulating layer (silicon nitride layer) made of a silicon nitride film.

[0018] The second undercoat layer 130 is provided so as to cover the surface of the first undercoat layer 120. The second undercoat layer 130 is, for example, an insulating layer (silicon oxide layer) made of a silicon oxide film. Note that the first wiring layer is formed by electrodes formed on the second undercoat layer 130.

[0019] The undercoat layer is not limited to SiO or SiN, but may be any thin film having barrier properties, and its thickness may be changed as appropriate.

[0020] The lower electrode 210 is part of an electrode formed on the second undercoat layer 130, and functions as one electrode for forming the storage capacitor Cs_conv. The lower electrode 210 is connected to the gate electrodes of the write transistor T3 and the drive transistor TD.

[0021] The first insulating layer 140 is provided so as to cover the second undercoat layer 130 on which one or more electrodes (first wiring layer) including the lower electrode 210 are formed. The first insulating layer 140 is filled between the lower electrode 210 and the first upper electrode 220. The first insulating layer 140 is, for example, a silicon oxide film, but may also be composed of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. The second wiring layer is formed by electrodes formed on the first insulating layer 140. Note that the storage capacitance Cs_conv shown in FIG. 2 corresponds to the storage capacitance Cs shown in FIG. 1.

[0022] The first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat are part of electrodes formed on the first insulating layer 140. In this embodiment, the first upper electrode 220 has a portion (first opposing portion) that is provided opposite the lower electrode 210, and functions as the other electrode for forming the storage capacitance Cs_conv. The first opposing portion is a portion of the first upper electrode 220 that overlaps with the lower electrode 210 in a plan view. Note that "A" and "B" being provided opposite each other means that no other metal layer is formed at least partially between "A" and "B".

[0023] The positive power supply line VCC is connected to the drain electrode of the drive transistor TD and the power supply 30 (see FIG. 3), and is elongated in the X-axis direction in plan view.

[0024] Data signal line Vdat G is a data signal line of the sub-pixel circuit 1011G adjacent to the sub-pixel circuit 1011B. G is provided at a position that does not overlap the lower electrode 210 (the lower electrode 210 of the pixel circuit 1011R) in a plan view.

[0025] The second insulating layer 150 is formed on the first upper electrode 220 and the data signal line Vdat GThe second insulating layer 150 is provided so as to cover the first insulating layer 140 on which a plurality of electrodes (second wiring layer) including the above-mentioned electrodes are formed. The second insulating layer 150 has a thickness (length in the Z-axis direction) greater than that of the first insulating layer 140. The second insulating layer 150 is, for example, a silicon oxide film, but may also be made of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. The second insulating layer 150 may also be made of an inorganic insulating film and an organic insulating film. The organic insulating film functions, for example, as a planarizing layer for planarizing the surface of the substrate 110.

[0026] The metal layer 160 is an electrode for forming an EL layer, and is, for example, an anode. The metal layer 160 is formed for each sub-pixel.

[0027] The light emitting layer 170 is provided for each region partitioned by the third insulating layer 190, and emits light in response to a light emitting current that corresponds to the amount of charge stored in the storage capacitor Cs.

[0028] The metal layer 180 is an electrode for forming an EL layer, and is, for example, a cathode. The metal layer 180 is connected to the negative power supply line VCATH. The metal layer 180 is formed so as to collectively cover a plurality of pixels. The metal layer 180 is an example of a fourth electrode layer.

[0029] The third insulating layer 190 is a bank (partition) that divides the surface of the substrate 110 to form the light-emitting layer 170. The third insulating layer 190 is made of a photosensitive thermosetting resin.

[0030] The light-emitting layer 170, the third insulating layer 190, and the metal layers 160 and 180 form an EL layer.

[0031] In addition, a protective film, a sealing resin, and a sealing substrate may be laminated in this order on the EL layer (not shown).

[0032] The lower electrode 210, the first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat are made of a metal such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti), or an alloy.

[0033] As described above, in the pixel circuit according to the comparative example, the lower electrode 210, the first upper electrode 220, and the first insulating layer 140 between the lower electrode 210 and the first upper electrode 220 form the storage capacitor Cs_conv.

[0034] 1, polysilicon semiconductor TFTs (Thin Film Transistors) are generally used for switching transistors such as the compensation transistor T2 and the write transistor T3, in order to emphasize high-speed operation. However, polysilicon semiconductor TFTs have a relatively large off-leak current due to leakage caused by crystal defects and the like, and the charge held in the storage capacitor Cs_conv is released, which reduces the potential difference Vgs between the gate and source of the drive transistor TD and reduces the light-emitting current flowing through the light-emitting element EL, making it impossible to display at the desired brightness (desired gradation value) or to maintain the desired brightness.

[0035] The off-leakage current of polysilicon semiconductor TFTs tends to depend heavily on process control (control of Si crystallinity) during manufacturing, and existing technologies have limitations on how much it can be reduced. Examples of factors that cause off-leakage current include subthreshold leakage current (leakage between drain and source), gate leakage current (leakage through the gate insulating film), GIDL (Gate-Induced-Drain-Leakage current), and junction leakage current (crystal defect leakage current).

[0036] Therefore, the inventors of the present application have conducted extensive research into a display device that can suppress changes in luminance due to off-leakage of a switching transistor, and have devised the display device described below.

[0037] Each embodiment of the present disclosure will be described below with reference to the drawings. Note that each embodiment described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, component placement positions, connection forms, etc. shown in each of the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in each of the following embodiments, components that are not recited in the independent claims of the present disclosure will be described as optional components.

[0038] Furthermore, each drawing is a schematic diagram and is not necessarily a precise illustration. In each drawing, substantially the same components are denoted by the same reference numerals, and redundant explanations will be omitted or simplified.

[0039] In this specification and drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a right-handed three-dimensional Cartesian coordinate system. In each embodiment, the Z-axis direction is the stacking direction of each layer. In this specification, "planar view" means a view of the pixel circuit along the thickness direction of the pixel circuit.

[0040] Furthermore, in this specification, terms indicating the relationship between elements, such as identical and parallel, terms indicating the shape of elements, such as rectangular and elongated, as well as numerical values ​​and numerical ranges, are not expressions that only express the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent (e.g., about 10%).

[0041] (Embodiment 1) [1-1. Display Device Configuration] First, a schematic configuration of a display device 1 according to this embodiment will be described with reference to Fig. 3 to Fig. 5. Fig. 3 is a block diagram showing the functional configuration of the display device 1 according to this embodiment. In the following description, for simplicity, signals and wiring that transmits the signals may be referred to by the same reference numerals.

[0042] 3, the display device 1 includes a display module 10, a control unit 20, and a power supply 30. The display module 10 includes a display panel 12 (display unit), a gate driver 13, and a data driver .

[0043] The display panel 12 is configured by arranging a plurality of pixel circuits 11 (pixels) two-dimensionally (in a matrix). That is, the display panel 12 has a plurality of pixel rows L. Each pixel circuit 11 has sub-pixel circuits 11R, 11G, and 11B (sub-pixels) corresponding to the emitted colors of R, G, and B, respectively. In the present embodiment, an example will be described in which each of the plurality of pixels constituting the plurality of pixel rows L has an organic EL element as a light-emitting element, but this is not limiting. The display panel 12 may also have QLED (Quantum-dot Light Emitting Diode) elements as light-emitting elements.

[0044] Each row of the matrix is ​​provided with three control signal lines INI, REF, and WS connected to the pixel circuits 11 arranged in the same row. The control signal lines INI, REF, and WS transmit control signals INI, REF, and WS supplied from the gate driver 13 to the pixel circuits 11. Note that the number of control signal lines and the control signals are merely examples and are not limited to these. The control signal lines INI, REF, and WS are also examples of scanning lines.

[0045] The scanning lines are arranged for each of a plurality of pixel rows L, and are provided to select a pixel row L into which a data signal corresponding to a video signal is to be written.

[0046] Each column in the matrix is ​​provided with three data signal lines Vdat connected to a plurality of pixel circuits 11 arranged in the same column. R , Vdat G , Vdat B The data signal line Vdat R , Vdat G , Vdat B are the data signals Vdat related to the light emission brightness of R, G, and B supplied from the data driver 14. R , Vdat G, Vdat B are transmitted to the pixel circuit 11, respectively.

[0047] 3, the gate driver 13 is arranged on one side of the display panel 12, but it may be arranged on both sides. Furthermore, the data driver 14 may be mounted on the display panel 12 by COG (Chip on Glass) or COF (Chip on Film).

[0048] The control unit 20 controls each component of the display module 10. The control unit 20 receives a video signal from an external device and supplies control signals to the gate driver 13 and the data driver 14 for displaying an image of each frame of the video signal on the display panel 12.

[0049] The power supply 30 supplies operating power to the display panel 12, the gate driver 13, the data driver 14, and the control unit 20. The power supply 30 supplies, for example, reference voltages VINI, VREF, a positive power supply voltage VCC, and a negative power supply voltage VCATH to the display panel 12.

[0050] Here, the detailed configuration of pixel circuit 11 will be described with reference to Fig. 4 to Fig. 7. Fig. 4 is a circuit diagram showing the configuration of pixel circuit 11 of display device 1 according to the present embodiment.

[0051] 4, the sub-pixel circuits 11R, 11G, and 11B that make up the pixel circuit 11 have the same configuration. The configuration of the pixel circuit 11 will be described below, focusing on the sub-pixel circuit 11R.

[0052] The sub-pixel circuit 11R includes an initialization transistor T1 R and the compensation transistor T2 R and write transistor T3 R and the storage capacitance Cs R and the drive transistor TD R and light-emitting element EL RThe sub-pixel circuit 11R also has control signal lines INI, REF, and WS, reference voltage lines VINI and VREF, and a data signal line Vdat R , a positive power supply line VCC, and a negative power supply line VCATH. R and compensation transistor T2 R is not a required component.

[0053] Initialization transistor T1 R is turned on in response to the control signal INI, and the driving transistor TD R The source node of the VINI is set to the reference voltage (standard voltage).

[0054] Compensation transistor T2 R is turned on in response to the control signal REF, and the driving transistor TD R A reference voltage VREF is supplied to the gate electrode (gate node) of the light-emitting element EL R This corresponds to initializing the potential of the electrode (e.g., anode).

[0055] Write transistor T3 R is turned on in accordance with the control signal WS, and the data signal Vdat R The voltage of the storage capacitance Cs R Write transistor T3 R is the data signal line Vdat R and drive transistor TD R Specifically, the write transistor T3 R The data signal line Vdat is connected to one of the source electrode and the drain electrode. R and the other of the source electrode and the drain electrode is connected to the compensation transistor T2 R one of the source electrode and the drain electrode of the driving transistor TD R is connected to the gate electrode of

[0056] Drive transistor TD ROne of the source electrode and the drain electrode is connected to the positive power supply line VCC, and the other of the source electrode and the drain electrode is connected to the light-emitting element EL R The anode of the storage capacitor Cs R The data signal Vdat held in R The light-emitting element EL R As a result, the light-emitting element EL R is the data signal Vdat R It emits light at a brightness according to the

[0057] Holding capacity Cs R is the data signal line Vdat R The data signal Vdat is supplied via R As will be described in detail later, the storage capacitance Cs R is the storage capacitance Cs according to the comparative example R The storage capacity Cs according to the present disclosure is larger than that of R is realized by a combined capacitance of the storage capacitance Cs_conv shown in the comparative example and the storage capacitance Cs_add (see FIG. 6).

[0058] Light-emitting diode (EL) R is a self-luminous light-emitting element, and in this embodiment, is an organic EL (Electro Luminescence) element. R The anode electrode of the drive transistor TD R The light-emitting element EL is connected to one of the source electrode and the drain electrode of the light-emitting element EL. R A cathode voltage (negative power supply voltage VCATH) is applied to the cathode electrode via a cathode power supply line (negative power supply line VCATH).

[0059] The gate potential Vg R is the drive transistor TD R The gate electrode potential is Vs R is the drive transistor TD R 1 shows the potential of the source electrode.

[0060] Each of the transistors described above is, for example, an n-type thin film transistor (n-type TFT), but may be a p-type thin film transistor (p-type TFT). Each of the transistors described above may be, for example, a polysilicon semiconductor TFT, but is not limited to this.

[0061] Here, the cross-sectional configuration of the pixel circuit 11 will be described with reference to Figs. 5 to 7. Fig. 5 is a plan view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment. Fig. 6 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along the VI-VI cutting line in Fig. 5. Fig. 7 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along the VII-VII cutting line in Fig. 5.

[0062] As shown in FIGS. 5 to 7, the pixel circuit 11 according to the present embodiment has a lower electrode 310 instead of the lower electrode 210 of the pixel circuit 1011 according to the comparative example, and further has a second upper electrode 320 and a fourth insulating layer 200.

[0063] The lower electrode 310 is connected to the driving transistor TD R and the gate electrode of the write transistor T3 R and functions as one electrode for forming the storage capacitors Cs_conv and Cs_add. The lower electrode 310 is an electrode having a larger area in a plan view than the lower electrode 210 according to the comparative example. The lower electrode 310 is formed, for example, to cover a part of the first upper electrode 220 and the second upper electrode 320 in a plan view. For example, the lower electrode 310 is provided so as to overlap with each of the first opposing portion of the first upper electrode 220 and the second opposing portion of the second upper electrode 320 in a plan view. For example, the lower electrode 310 is formed across the positive power supply line VCC. Note that the lower electrode 310 is connected to the data signal line (the data signal line Vdat G ) do not overlap in plan view.

[0064] The lower electrode 310, in plan view, is made up of a first electrode portion 310a that is a portion facing the first upper electrode 220, a second electrode portion 310b that faces the first electrode portion 320a, a third electrode portion 310c that faces the second electrode portion 320b, and a driving transistor TD R The lower electrode 310 has a fourth electrode portion 310d connected to the gate electrode of the first upper electrode 220. The lower electrode 310 covers the first upper electrode 220 (for example, a first opposing portion described later), the first electrode portion 320a, and the second electrode portion 320b.

[0065] The first electrode portion 310a is, for example, rectangular, and the second electrode portion 310b and the third electrode portion 310c are elongated. For example, the second electrode portion 310b and the third electrode portion 310c are elongated along the positive power supply line VCC. In a plan view, the lower electrode 310 has a configuration in which the positive power supply line VCC is sandwiched between the second electrode portion 310b and the third electrode portion 310c. The first electrode portion 310a corresponds to the lower electrode 210 shown in the comparative example. The fourth electrode portion 310d is an example of a first wiring portion.

[0066] In plan view, the portion of the lower electrode 310 that overlaps with the first upper electrode 220 and the second upper electrode 320, i.e., the portion of the lower electrode 310 that covers the first upper electrode 220 and the second upper electrode 320, is an example of a third opposing portion. In addition, in plan view, the portion of the first upper electrode 220 that overlaps with the lower electrode 310 is an example of a first opposing portion. It can also be said that the first upper electrode 220 has a first opposing portion that is disposed opposite the lower electrode 310 on the first insulating layer 140. The first upper electrode 220 is an example of a second electrode layer.

[0067] As shown in FIGS. 6 and 7, the pixel circuit 11 has a second upper electrode 320 and a third insulating layer 190 between a second insulating layer 150 and a metal layer 160.

[0068] The first insulating layer 140 is formed so as to cover the second undercoat layer 130 on which one or more electrodes (first wiring layer) including the lower electrode 310 are formed. It can also be said that the first insulating layer 140 is formed so as to cover the lower electrode 310.

[0069] The second insulating layer 150 is formed so as to cover the first insulating layer 140 on which one or more electrodes (second wiring layer) including the first upper electrode 220 are formed. It can also be said that the second insulating layer 150 covers the first upper electrode 220 and the first insulating layer 140.

[0070] The second upper electrode 320 is at least partially formed on the second insulating layer 150 and functions as the other electrode for forming the storage capacitor Cs_add. R The second upper electrode 320 is connected to one of the source electrode and drain electrode of the initialization transistor T1 via the connection portion 330. In other words, the second upper electrode 320 is electrically connected to the first upper electrode 220 and has the same potential. In this embodiment, the second upper electrode 320 is connected to the first upper electrode 220 via the connection portion 330. R The second upper electrode 320 is connected to one of the source electrode and the drain electrode via a connection portion 330. The second upper electrode 320 is an example of a third electrode layer.

[0071] The connection section 330 connects the first upper electrode 220 to the driving transistor TD R The connection portion 330 is connected to one of the source electrode and the drain electrode of the semiconductor device. The connection portion 330 is an example of a second wiring portion.

[0072] 7, the connection between the connection portion 330 and the second upper electrode 320 is realized at a contact portion C. A through-hole 151 is formed in the second insulating layer 150 at a position where the connection portion 330 and the second upper electrode 320 (for example, the third electrode portion 320c) overlap, and the connection portion 330 and the second upper electrode 320 are connected via the through-hole 151. For example, the connection portion 330 formed directly on the first insulating layer 140 and the second upper electrode 320 are connected via the through-hole 151. It can also be said that the second upper electrode 320 is electrically connected to the source electrode of the driving transistor TD via the connection portion 330.

[0073] The second upper electrode 320 has a first electrode portion 320a, a second electrode portion 320b, and a third electrode portion 320c. In this embodiment, the second upper electrode 320 is formed directly on the second insulating layer 150.

[0074] The first electrode portion 320a has a portion facing the second electrode portion 310b, and is connected to the positive power supply line VCC and the data signal line Vdat R The first electrode portion 320a is provided on the lower electrode side. The first electrode portion 320a is elongated in the X-axis direction along the positive power supply line VCC. The first electrode portion 320a is a portion that overlaps with the lower electrode 310 (for example, the second electrode portion 310b) in a plan view.

[0075] The second electrode portion 320b has a portion facing the third electrode portion 310c, and is connected to the positive power supply line VCC and the data signal line of the adjacent sub-pixel (in the example of FIG. 5, the data signal line Vdat G ) The first electrode portion 320a is elongated in the X-axis direction along the positive power supply line VCC. The second electrode portion 320b is a portion that overlaps with the lower electrode 310 (for example, the third electrode portion 310c) in a plan view.

[0076] The first electrode portion 320a and the second electrode portion 320b are provided at positions that do not overlap with the first opposing portions in a plan view. The first electrode portion 320a and the second electrode portion 320b are formed to sandwich the positive power supply line VCC in a plan view. The first electrode portion 320a and the second electrode portion 320b may be provided parallel to each other in a plan view. The length of the second electrode portion 320b in the X-axis direction may be the same as the length of the first electrode portion 320a in the X-axis direction. The first electrode portion 320a and the second electrode portion 320b are an example of a second opposing portion.

[0077] The third electrode portion 320c is elongated in a direction intersecting (for example, a direction perpendicular to) the longitudinal direction (X-axis direction) of the first electrode portion 320a and the second electrode portion 320b in a plan view, and is provided to electrically connect the first electrode portion 320a and the second electrode portion 320b to the connection portion 330. The third electrode portion 320c is formed, for example, so as to cover the inner surface of the through-hole 151. Furthermore, the third electrode portion 320c intersects with the fourth electrode portion 310d in a plan view, and overlaps with a part of the fourth electrode portion 310d.

[0078] In order to prevent an increase in the parasitic capacitance of the existing wiring, the second upper electrode 320 is preferably formed in a region where there are no signal lines or the like below.

[0079] The fourth insulating layer 200 is provided so as to cover the second insulating layer 150 on which one or more electrodes (third wiring layer) including the second upper electrode 320 are formed. The fourth insulating layer 200 is, for example, a silicon oxide film, but may also be made of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film.

[0080] The constituent material of each electrode layer described above may be, for example, a single element or alloy containing one of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), and copper (Cu). Alternatively, it may be a compound containing at least one of these elements or a laminated film containing two or more of these elements. Alternatively, a transparent conductive film such as ITO may be used.

[0081] As described above, in the pixel circuit 11 according to the present embodiment, in addition to the storage capacitance Cs_conv shown in the pixel circuit 1011 according to the comparative example, the storage capacitance Cs_add is formed by the lower electrode 310, the second upper electrode 320, and the first insulating layer 140 and the second insulating layer 150 between the lower electrode 310 and the second upper electrode 320. Specifically, the storage capacitance Cs_add is formed by a combined capacitance of the first auxiliary storage capacitance between the second electrode unit 310b and the first electrode unit 320a, the second auxiliary storage capacitance between the third electrode unit 310c and the second electrode unit 320b, and the third auxiliary storage capacitance between the fourth electrode unit 310d and the third electrode unit 320c.

[0082] The storage capacitance Cs_add can be calculated by the following formula 1, where S is the area where the lower electrode 310 and the second upper electrode 320 overlap in plan view, and d1 is the distance between the lower electrode 310 and the second upper electrode 320.

[0083] Cs_add=ε0×εx×S / d1 (Formula 1)

[0084] Here, ε0 represents the dielectric constant of a vacuum, and εx represents the relative dielectric constant. Furthermore, the total storage capacitance Cs of the pixel circuit 11 can be calculated by the following (Equation 2).

[0085] Cs=Cs_conv+Cs_add (Formula 2)

[0086] The storage capacitance Cs is greater than the storage capacitance Cs_conv.

[0087] In this way, the display device 1 according to the present embodiment can make the storage capacitance Cs larger than the storage capacitance Cs_conv described in the comparative example.

[0088] In addition, in a plan view, the area where the second electrode portion 310b and the first electrode portion 310a overlap and the area where the third electrode portion 310c and the second electrode portion 310b overlap may be equal, for example. That is, the storage capacitance Cs_add formed by the second electrode portion 310b and the first electrode portion 310a may be equal to the storage capacitance Cs_add formed by the third electrode portion 310c and the second electrode portion 310b. Note that the two storage capacitances Cs_add are not limited to being equal and may be different from each other.

[0089] [1-2. Effect of increasing storage capacity] The effect of increasing the storage capacitance Cs will be described with reference to FIG. 8. FIG. 8 is a diagram for explaining the effect of the display device 1 according to this embodiment. The vertical axis of FIG. 8 represents the degree of decrease in pixel current (light-emitting current), and the horizontal axis represents time. FIG. 8 shows a comparison of the degree of decrease in pixel current over one frame between the display device 1 and a display device of the prior art, based on the value of the pixel current at the start of one frame. Note that the prior art refers to a display device in which the storage capacitance of the pixel circuit is formed only by the storage capacitance Cs_conv, of the storage capacitances Cs_conv and Cs_add.

[0090] As shown in FIG. 8, in the display device 1 according to this embodiment, the decrease in pixel current over one frame is suppressed compared to the display device of the prior art (see "Improved -ΔIpix" in FIG. 8). The display device 1 has a larger storage capacitance Cs than the conventional display device, and therefore the amount of accumulated charge is also larger than the conventional display device. On the other hand, the amount of pixel current that leaks due to off-leakage is constant regardless of the storage capacitance Cs. In other words, in the display device 1, the ratio of the amount of charge reduction due to off-leakage to the amount of accumulated charge is small. Therefore, in the display device 1 according to this embodiment, as shown in FIG. 8, the degree of decrease in pixel current is mitigated, thereby suppressing the decrease in light-emitting current and making it possible to suppress changes in brightness due to off-leakage.

[0091] For example, when the combined storage capacitance of the storage capacitance Cs_conv and the storage capacitance Cs_add is 1.5 times the storage capacitance of the storage capacitance Cs_conv alone, R , T.D. G , T.D. B Since the decrease in the gate-source potential difference Vgs can be suppressed to approximately 0.67 times, the decrease in the pixel current Ipix can be suppressed accordingly.

[0092] Since the display device 1 according to the present embodiment has a configuration in which a combined storage capacitance Cs of the storage capacitance Cs_conv and the storage capacitance Cs_add is formed, the pixel current increases as the storage capacitance increases. Therefore, in the display device 1, the data signal may be adjusted so that the pixel current flowing through the light-emitting element EL when the pixel value is the same matches that in a configuration in which the storage capacitance Cs is formed only by the storage capacitance Cs_conv (for example, a configuration according to a comparative example).

[0093] [1-3. Pixel circuit operation] The operation of pixel circuit 11 will be described with reference to Fig. 9. Fig. 9 is a timing chart showing various gate control signals (control signals INI, REF, WS) of display device 1 according to the present embodiment.

[0094] 9, the period from time t1 to time t4 is a light-off period. At time t1, the control signal REF changes from a low level to a high level, and the compensation transistor T2 R , T2 G , T2 B is turned on, the light-off period begins. From time t2 to time t3, the control signal REF is at a low level, the control signal INI is at a high level, and an initialization period is performed during which an initialization operation is performed. From time t3 to time t4, the control signal REF is at a high level, the control signal INI is at a low level, and a threshold compensation period (Vth compensation period) is performed during which a threshold compensation operation is performed.

[0095] Between time t4 and time t5, the control signal WS is at a high level, so that the write transistor T3 R , T3 G , T3 B is turned on, and the storage capacitance Cs R , Cs G , Cs B Each of the data signal lines Vdat R , Vdat G , Vdat B The data signals held in each of these capacitors are written. The period from time t4 to time t5 is a data writing period. During the period from time t4 to time t5, for example, charges are stored simultaneously in the storage capacitors Cs_conv and Cs_add.

[0096] Then, at time t5, the control signal WS goes low, causing the light-emitting element EL R , E.L. G , E.L. B will light up.

[0097] The off period is a period for initial setting, and more specifically, a period during which the subpixel circuit is not lit (i.e., black display). If there are n pixel rows and one horizontal period is 1H, the off period is, for example, a period defined by n×H. Note that "black display" is not limited to complete black (non-emission), but may also include substantially black, and may include, for example, a brightness below a predetermined value.

[0098] [1-4. Effects, etc.] The effects of the display device 1 will be described below, but for convenience, the light-emitting element EL R , E.L. G , E.L. B is described as a light-emitting element EL, and the data signal line and the data signal Vdat R , Vdat G , Vdat B is written as the data signal line and data signal Vdat, and the storage capacitance Cs R , Cs G , Cs B is written as the storage capacitor Cs, and the drive transistor TD R , T.D. G , T.D. B is referred to as the drive transistor TD, and the write transistor T3 R , T3 G , T3 B is referred to as write transistor T3.

[0099] As described above, the display device 1 according to this embodiment is a display device including a plurality of pixels (pixel circuits 11) arranged two-dimensionally. Each of the plurality of pixels includes a light-emitting element EL, a storage capacitor Cs that stores a data signal supplied via a data signal line Vdat, a drive transistor TD that supplies a current corresponding to the data signal Vdat to the light-emitting element EL, and a write transistor T3 connected between the data signal line Vdat and the gate electrode of the drive transistor TD, with one of its source electrode and drain electrode connected to the data signal line Vdat. The storage capacitor Cs includes a lower electrode 310 (an example of a first electrode layer) connected to the gate electrode of the drive transistor TD and the write transistor T3, a first insulating layer 140 that covers the lower electrode 310, a first upper electrode 220 that is connected to the source electrode of the drive transistor TD and has a first opposing portion disposed on the first insulating layer 140 opposite the lower electrode 310, a second insulating layer 150 that covers the first insulating layer 140 and the lower electrode 310, and a second insulating layer 150 that is connected to the source electrode of the drive transistor TD and has a small The display device 1 is formed of a second upper electrode 320 (an example of a third electrode layer) at least a portion of which is formed on the second insulating layer 150, and the second upper electrode 320 has a second opposing portion (e.g., a first electrode portion 320a and a second electrode portion 320b) arranged opposite the lower electrode 310, and the first opposing portion and the second opposing portion are formed in positions where they do not overlap each other in a planar view of the display device 1, and the lower electrode 310 is formed so as to overlap each of the first opposing portion and the second opposing portion in a planar view.

[0100] As a result, in addition to the storage capacitance Cs_conv formed by the lower electrode 310, the first upper electrode 220 (first opposing portion), and the first insulating layer 140, a storage capacitance Cs_add formed by the lower electrode 310, the second upper electrode 320 (second opposing portion), and the first insulating layer 140 (or the first insulating layer 140 and the second insulating layer 150) is formed. That is, in the display device 1, the storage capacitance Cs is increased compared to the conventional case in each of the multiple pixels. As described with reference to FIG. 8, such a display device 1 accumulates a larger amount of charge than the conventional case, and is therefore less susceptible to the effects of off-leakage. Therefore, the display device 1 according to this embodiment can suppress changes in luminance due to off-leakage of the writing transistor T3 (switching transistor).

[0101] The second opposing portion is formed directly on the second insulating layer 150.

[0102] As a result, a storage capacitance Cs_add is formed by the second opposing portion (e.g., the first electrode portion 320a and the second electrode portion 320b) formed directly on the second insulating layer 150 and the lower electrode 310, thereby increasing the storage capacitance Cs for each pixel.

[0103] In addition, the lower electrode 310 has a third opposing portion that covers the first opposing portion and the second opposing portion, and a fourth electrode portion 310d that connects the third opposing portion and the gate electrode of the driving transistor TD, and the second upper electrode 320 overlaps a portion of the fourth electrode portion 310d (an example of a first wiring portion) in a planar view.

[0104] As a result, a capacitance is formed also in the portion where the second upper electrode 320 and the fourth electrode portion 310d overlap, so that the storage capacitance Cs_add can be further increased.

[0105] The first opposing portion has a rectangular shape in a plan view, and the second opposing portion has an elongated shape in a plan view.

[0106] As a result, the first opposing portion and the second opposing portion are formed in different shapes, so that even if there is a limit to the layout area in which the first opposing portion and the second opposing portion can be provided, the storage capacitance Cs_add can be effectively increased.

[0107] In addition, in a plan view, the second insulating layer 150 has a through hole 151 formed at a position where a connection portion 330 (an example of a second wiring portion) that connects the first upper electrode 220 and the source electrode of the driving transistor TD overlaps with the second upper electrode 320, and the second upper electrode 320 is electrically connected to the source electrode of the driving transistor TD via the through hole 151.

[0108] This allows the second upper electrode 320 to be formed wider, thereby further increasing the storage capacitance Cs_add.

[0109] Furthermore, the second opposing portion is provided with a positive power supply line VCC (an example of a power supply line) that is connected to the drain electrode of the drive transistor TD and is formed in an elongated shape in a planar view, and the second opposing portion is formed to sandwich the positive power supply line VCC in a planar view.

[0110] This makes it possible to effectively increase the storage capacitance Cs_add by utilizing the space around the positive power supply line VCC in a plan view.

[0111] (Embodiment 2) The display device according to the present embodiment will be described below with reference to FIGS. 10 to 13. The following description will focus on differences from the first embodiment, and descriptions of the same or similar aspects as those in the first embodiment will be omitted or simplified. In the present embodiment, an example will be described in which the other electrode forming the storage capacitor Cs_add is formed at a position below the upper surface of the second insulating layer 150. A configuration in which the other electrode is formed in a through-hole in the second insulating layer 150 will be described using FIG. 10, and a configuration in which the other electrode is formed in a recess with a bottom in the second insulating layer 150 will be described using FIG. 11.

[0112] [2-1. Display Device Configuration] FIG. 10 is a cross-sectional view schematically showing a first example of the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along a cutting line corresponding to the cutting line VI-VI in FIG.

[0113] 10, the first electrode portion 320a and the second electrode portion 320b of the second upper electrode 320 are formed not on the second insulating layer 150 but in through holes 152 and 153 formed in the second insulating layer 150. In the example of FIG. 10, the through holes 152 and 153 are recesses that penetrate the second insulating layer 150 in the Z-axis direction. It can also be said that recesses (through holes 152 and 153) that penetrate to the first insulating layer 140 side (the negative Z-axis side) are formed in the second insulating layer 150 at positions that overlap the first electrode portion 320a and the second electrode portion 320b in a plan view.

[0114] In this case, the first electrode portion 320a and the second electrode portion 320b are formed on the first insulating layer 140. That is, the first electrode portion 320a and the second electrode portion 320b and the first upper electrode 220 are formed in the same layer (second wiring layer), and the distance d2 to the lower electrode 310 is equal. The distance d2 is shorter than the distance d1.

[0115] The first electrode portion 320a is disposed between the first upper electrode 220 and the positive power supply line VCC so as not to contact each other in a cross-sectional view, and the second electrode portion 320b is disposed between the positive power supply line VCC and the data signal line Vdat G In other words, the first electrode portion 320a and the second electrode portion 320b are arranged between the first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat G The first electrode portion 320a and the second electrode portion 320b have a portion facing the lower electrode 310 (first portion).

[0116] The storage capacitance Cs_add can be calculated using the following equation (3), where S is the area where the lower electrode 310 and the second upper electrode 320 overlap in a planar view, and d2 is the distance between the lower electrode 310 and the second upper electrode 320.

[0117] Cs_add=ε0×εx×S / d2 (Formula 3)

[0118] The first electrode portion 320a is formed so as to cover the inner surface 152a of the through hole 152, and the second electrode portion 320b is formed so as to cover the inner surface 153a of the through hole 153. The through holes 152 and 153 are, in plan view, connected to the electrodes of the second wiring layer (the first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat G The through-hole 152 is formed in a position not overlapping with the first upper electrode 220 and the positive power supply line VCC in a plan view, and is elongated along the positive power supply line VCC. The through-hole 153 is formed in a position not overlapping with the positive power supply line VCC and the data signal line Vdat in a plan view. G The through holes 152 and 153 are formed in an elongated shape along the positive power supply line VCC between the positive power supply line VCC and the positive power supply line VCC. For example, the through holes 152 and 153 are parallel through grooves in a plan view.

[0119] A portion of the first electrode portion 320a formed on the inner surface 152a of the through-hole 152 (an example of the second portion) and a portion of the second electrode portion 320b formed on the inner surface 153a of the through-hole 153 (an example of the second portion) extend along the positive power supply line VCC in a planar view. By forming electrodes on the inner surfaces 152a and 153a, capacitance is formed between the electrodes and the lower electrode 310. In other words, by forming electrodes on the inner surfaces 152a and 153a, it is expected that the effect of further increasing the storage capacitance Cs_add is achieved. The second portion is connected to the first portion.

[0120] The number of through holes 152 and 153 formed in the second insulating layer 150 is not limited to two, and may be one, or three or more, as long as they are formed in a region where the lower electrode 310 and the second upper electrode 320 overlap in a plan view. Furthermore, the through holes 152 and 153 are not limited to being through grooves, and may be realized by a plurality of cylindrical through holes.

[0121] FIG. 11 is a cross-sectional view schematically showing a second example of the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along a cutting line corresponding to the cutting line VI-VI in FIG.

[0122] 11, the first electrode portion 320a and the second electrode portion 320b of the second upper electrode 320 are formed in recesses 154 and 155 formed in the second insulating layer 150. In the example of FIG. 11, the recesses 154 and 155 are bottomed (open) grooves that do not penetrate the second insulating layer 150 in the Z-axis direction. It can also be said that the second insulating layer 150 has bottomed recesses 154 and 155 that are recessed toward the first insulating layer 140 side (the negative Z-axis side) at positions that overlap the first electrode portion 320a and the second electrode portion 320b in a plan view.

[0123] Since the recesses 154 and 154 are bottomed grooves, the first electrode portion 320a and the second electrode portion 320b are formed on the bottom surfaces of the recesses 154 and 155. That is, the first electrode portion 320a and the second electrode portion 320b are formed between the second wiring layer and the third wiring layer, and the distance to the lower electrode 310 is distance d3. Distance d3 is smaller than distance d1 and larger than distance d2 (see FIG. 10).

[0124] The recesses 154 and 155 are formed at the same positions as the through holes 152 and 153 in a plan view.

[0125] The storage capacitance Cs_add can be calculated by the following equation (4), where S is the area where the lower electrode 310 and the second upper electrode 320 overlap in plan view, and d3 is the distance between the lower electrode 310 and the second upper electrode 320.

[0126] Cs_add=ε0×εx×S / d3 (Equation 4)

[0127] The first electrode portion 320a is formed so as to cover the inner surface of the recess 154, and the second electrode portion 320b is formed so as to cover the inner surface of the recess 155.

[0128] FIG. 12 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, cut along a cut line corresponding to the VII-VII cut line in FIG. 5.

[0129] As shown in FIG. 12, since the second upper electrode 320 overlaps with the third electrode portion 310c in plan view, a holding capacitor Cs_add is also formed between the second upper electrode 320 and the third electrode portion 310c. Thereby, the holding capacitor Cs can be further increased. In the example of FIG. 12, no recess is formed above the third electrode portion 310c. Above the third electrode portion 310c is a region where the third electrode portion 310c and the fourth electrode portion 310d overlap in plan view. Since this region is physically close to the driving transistor TD, no recess is formed in this region in consideration of the influence on the operation of the driving transistor TD.

[0130] In this case, let the area where the second electrode portion 310b and the first electrode portion 320a overlap in plan view be S1, the holding capacitor formed by the second electrode portion 310b and the first electrode portion 320a be Cs_add_1 (the holding capacitor Cs_add between the second electrode portion 310b and the first electrode portion 320a in FIG. 12), the area where the fourth electrode portion 310d and the third electrode portion 320c overlap in plan view be S2, and the holding capacitor formed by the second electrode portion 310b and the first electrode portion 320a be Cs_add_2 (the holding capacitor Cs_add between the fourth electrode portion 310d and the third electrode portion 320c in FIG. 12). The following relationship (Equation 5) holds.

[0131] Cs_add_2 / S2 < Cs_add_1 / S1 ···(Equation 5)

[0132] Note that the second insulating layer 150 has a bottomed recess formed above the third electrode portion 310c so as not to affect the operation of the driving transistor TD, and the second upper electrode 320 may be formed on the bottom surface of the recess. The depth of such a recess can be obtained, for example, by experiments or the like.

[0133] The number of recesses 154 and 155 formed in second insulating layer 150 is not limited to two, and may be one, or three or more, as long as they are formed in a region that overlaps with lower electrode 310 in plan view. Furthermore, recesses 154 and 155 are not limited to groove-shaped recesses, and may be realized by a plurality of cylindrical recesses.

[0134] [2-2. Display Device Manufacturing Method] Next, a method for manufacturing the through-holes 151, recesses 154, and recesses 155 shown in FIGS. 11 and 12 will be described with reference to FIG. 13. FIG. 13 is a diagram for explaining a method for manufacturing the display device 1 according to the present embodiment. FIG. 13 schematically shows an exposure step for forming the through-holes 151, recesses 154, and recesses 155. Note that the amount of light (e.g., UV light) incident on the photomask 500 is, for example, uniform in plan view. Furthermore, the resin that is the material for the second insulating layer 150 is assumed to be a positive photosensitive resin, but is not limited to this.

[0135] The second insulating layer 150 is formed by forming a first wiring layer including a lower electrode 310 on the first insulating layer 140, applying a positive photosensitive resin for forming the second insulating layer 150, hardening it (temporarily hardening) by pre-baking, exposing it to light using a photomask 500 shown in Figure 13, removing the resin in the etched areas with a developer, and finally hardening it (mainly hardening) by post-baking.

[0136] 13, through-holes 151, recesses 154, and recesses 155 are formed by an exposure process using photomask 500. Photomask 500 has a light-shielding portion 510, a transmitting portion 520, and a halftone portion 530. Photomask 500 is a multi-tone mask configured to have, in addition to light-shielding portion 510, two or more transmitting portions having different light transmittances.

[0137] The light-shielding portion 510 is provided in an area where the through-hole 151, the recess 154, and the recess 155 are not formed (for example, an area including the area where the third electrode portion 310c is formed), and is a portion that blocks light incident on the photomask 500.

[0138] The transmitting portion 520 is provided in the region where the through-hole 151 is formed, and is a portion that transmits light incident on the photomask 500.

[0139] The halftone portion 530 is provided in an area where a bottomed groove is formed (for example, an area where the first electrode portion 310a and the second electrode portion 310b are formed), and is a portion that transmits a portion of light incident on the photomask 500. The halftone portion 530 has a lower transmittance than the transmitting portion 520 and a higher transmittance than the light-shielding portion 510. The halftone portion 530 is provided in an elongated shape in the X-axis direction.

[0140] By using such a photomask 500, grooves having different depths (for example, through grooves and through holes) can be formed by a single exposure. When forming the through holes 152 and 153 shown in FIG. 10, a photomask in which the halftone portions 530 are replaced with the transmissive portions 520 may be used.

[0141] [2-3. Effects, etc.] As described above, the second insulating layer 150 of the display device 1 according to this embodiment has bottomed recesses 154 and 155 recessed toward the first insulating layer 140 (negative Z-axis side) at positions overlapping the lower electrode 310 (an example of a first electrode layer) in a planar view, and the second opposing portions (e.g., the first electrode portion 320a and the second electrode portion 320b) may be formed on the bottom surfaces of the recesses 154 and 155.

[0142] This allows the distance between the first electrode unit 320a and the second electrode unit 320b and the lower electrode 310 to be reduced, thereby further increasing the storage capacitance Cs_add. Furthermore, the second insulating layer 150 is present between the first electrode unit 320a and the second electrode unit 320b and the underlying signal lines. Therefore, the display device 1 can increase the storage capacitance Cs while preventing the first electrode unit 320a and the second electrode unit 320b from shorting out with other signal lines.

[0143] In addition, the second insulating layer 150 has through holes 152 and 153 (examples of recesses) that penetrate toward the first insulating layer 140 at a position that overlaps the lower electrode 310 in a planar view, and the second opposing portion is formed directly on the first insulating layer 140.

[0144] This allows the distance between the first electrode unit 320a and the second electrode unit 320b and the lower electrode 310 to be reduced to the distance d2 between the first upper electrode 220 and the lower electrode 310, thereby further increasing the storage capacitance Cs_add. Therefore, the display device 1 can further increase the storage capacitance Cs.

[0145] The second opposing portion is composed of a first portion opposing the lower electrode 310 and a second portion formed on the inner surface of the recess (for example, the inner surfaces 152a and 153a of the through holes 152 and 153).

[0146] This forms a capacitance between the second portion and the lower electrode 310, thereby further increasing the storage capacitance Cs_add.

[0147] (Embodiment 3) The display device according to the present embodiment will be described below with reference to FIGS. 14 and 15. The following description will focus on differences from the first embodiment, and descriptions of the same or similar aspects as those of the first embodiment will be omitted or simplified. In the present embodiment, a case will be described in which a VCC auxiliary line 410 and a VCATH auxiliary line 420 are formed in the pixel circuit 11. Note that FIG. 14 illustrates an example in which both the VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed in the pixel circuit 11, but it is sufficient if at least one of the VCC auxiliary line 410 and the VCATH auxiliary line 420 is formed.

[0148] [3-1. Display Device Configuration] Fig. 14 is a plan view schematically showing the configuration of pixel circuit 11 of display device 1 according to the present embodiment. Fig. 15 is a cross-sectional view schematically showing the configuration of pixel circuit 11 of display device 1 according to the present embodiment, taken along line XV-XV in Fig. 14.

[0149] 14 and 15, the pixel circuit 11 of the display device 1 according to the present embodiment includes, in addition to the pixel circuit 11 according to the first embodiment, a VCC auxiliary line 410 and a VCATH auxiliary line 420. The VCC auxiliary line 410 is an example of a first auxiliary line, and the VCATH auxiliary line 420 is an example of a second auxiliary line.

[0150] The VCC auxiliary line 410 is electrically connected to the positive power supply line VCC, and is a line provided in the pixel circuit 11 to suppress a voltage drop of the positive power supply voltage VCC in the display area. The VCC auxiliary line 410 is, for example, a metal line having a lower resistance than the positive power supply line VCC. For example, the VCC auxiliary line 410 is a metal line. In addition, the VCC auxiliary line 410 is, for example, a line that is closer to the data signal line Vdat (in the example of FIG. 14 , the data signal line Vdat R The VCC auxiliary line 410 is formed in an elongated shape along the data signal line Vdat so as to overlap at least a part of the VCC auxiliary line 410 with the data signal line Vdat, but does not have to overlap with the data signal line Vdat. The VCC auxiliary line 410 is provided, for example, in each pixel.

[0151] The VCATH auxiliary line 420 is electrically connected to the metal layer 180 and is a line provided in the pixel circuit 11 to suppress a voltage drop of the negative power supply voltage VCATH in the display area. The VCATH auxiliary line 420 is, for example, a metal line having a lower resistance than the metal layer 180. For example, the VCATH auxiliary line 420 is a metal line. In addition, the VCATH auxiliary line 420 is, for example, a line that is electrically connected to the data signal line Vdat (in the example of FIG. 14, the data signal line Vdat B The VCATH auxiliary line 420 is formed in an elongated shape along the data signal line Vdat so as to overlap at least a part of the VCATH auxiliary line 420 with the data signal line Vdat, but does not have to overlap with the data signal line Vdat. The VCATH auxiliary line 420 is provided in each pixel, for example.

[0152] Such a VCC auxiliary line 410 and a VCATH auxiliary line 420 are formed on the second insulating layer 150, and the pixel circuit 11 including the VCC auxiliary line 410 and the VCATH auxiliary line 420 is formed on the fourth insulating layer 200. The VCC auxiliary line 410 and the VCATH auxiliary line 420 are provided at positions that do not overlap with the lower electrode 310 and the connection portion 330 in a plan view.

[0153] Therefore, in a pixel circuit 11 having a VCC auxiliary line 410 and a VCATH auxiliary line 420, the second upper electrode 320 can be formed in an area other than the area where the VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed in a planar view without forming an additional layer.

[0154] Data signal line Vdat R The distance between the VCC auxiliary line 410 and the data signal line Vdat R and the distance between the first electrode portion 320a and the second electrode portion 320b is d5, the following (Equation 6) holds.

[0155] d4>d5 (Formula 6)

[0156] As a result, since the insulating layer (second insulating layer 150) below the VCC auxiliary line 410 is thick, the data signal line Vdat R and the VCC auxiliary line 410. R and the VCC auxiliary line 410 can be maintained insulated.

[0157] Although the VCATH auxiliary line 420 is not shown in FIG. 15, the data signal line Vdat R The distance between the VCATH auxiliary line 420 and the VCATH auxiliary line 420 is also d4.

[0158] At least a part of the second electrode portion 320b and the third electrode portion 320c is provided closer to the lower electrode 310 (negative Z-axis side) than the VCC auxiliary line 410 and the VCATH auxiliary line 420 in a cross-sectional view.

[0159] [3-2. Effects, etc.] As described above, the display device 1 according to the present embodiment includes the positive power supply line VCC, which is connected to the drain electrode of the drive transistor TD and formed in a long shape in a plan view, and the VCC auxiliary line 410 (an example of a first auxiliary line), which is connected to the positive power supply line VCC and has a lower resistance than the positive power supply line VCC. The VCC auxiliary line 410 may be formed on the second insulating layer 150. The display device 1 according to the present embodiment also includes the metal layer 180 (an example of a fourth electrode layer), which is connected to the cathode electrode of the light-emitting element EL and covers a plurality of pixels, and the VCATH auxiliary line 420 (an example of a second auxiliary line), which is connected to the metal layer 180 and has a lower resistance than the metal layer 180, and the VCATH auxiliary line 420 may be formed on the second insulating layer 150.

[0160] As a result, in a display device 1 provided with at least one of the VCC auxiliary line 410 and the VCATH auxiliary line 420, the second upper electrode 320 can be formed on the second insulating layer 150 provided for forming the at least one auxiliary line. In other words, the display device 1 does not need to include an insulating layer dedicated to forming the second upper electrode 320. Therefore, a display device 1 capable of suppressing changes in luminance due to off-leakage can be realized at low cost.

[0161] (Other embodiments) While the display device according to the present disclosure has been described above based on each embodiment, the display device according to the present disclosure is not limited to the above-described each embodiment. The present disclosure also includes other embodiments realized by combining any of the components in each embodiment, modifications obtained by applying various modifications to each embodiment that would occur to those skilled in the art without departing from the spirit of the present disclosure, and various devices incorporating a display device according to the present embodiment.

[0162] For example, one of the grooves (grooves for forming a storage capacitor) formed in the second insulating layer may be a through groove and the other may be a groove with a bottom.

[0163] The present disclosure may also be realized as a display panel alone. The present disclosure may also be realized in a configuration that does not include a power supply and a control unit. Such a display panel includes a plurality of pixels arranged two-dimensionally, each of which includes a light-emitting element, a storage capacitor that stores a data signal supplied via a data signal line, a drive transistor that supplies a current corresponding to the data signal to the light-emitting element, and a write transistor connected between the data signal line and a gate electrode of the drive transistor, the write transistor having one of its source electrode and drain electrode connected to the data signal line. The storage capacitor is formed by: a first electrode layer connected to the gate electrode of the drive transistor and the write transistor; a first insulating layer formed on the first electrode layer; a second electrode layer connected to the source electrode of the drive transistor and having a first electrode portion disposed on the first insulating layer opposite the first electrode layer; a second insulating layer formed on the first insulating layer; and a third electrode layer connected to the source electrode of the drive transistor, at least a portion of which is formed on the second insulating layer, the third electrode layer having a second electrode portion disposed opposite the first electrode layer. The first electrode portion and the second electrode portion are provided at positions where they do not overlap each other in a plan view of the display panel, and the first electrode layer covers the first electrode portion and the second electrode portion. Note that an IC constituting the control portion may be mounted on the display panel.

[0164] The present disclosure may also be realized as an active matrix substrate alone, or may be realized in a configuration that does not include a power source, a control unit, or an EL layer (e.g., a light-emitting layer and electrode layers sandwiching the light-emitting layer). Such an active matrix substrate is an active matrix substrate used in a display device having a plurality of pixels arranged two-dimensionally, and each pixel circuit for forming the plurality of pixels includes a light-emitting element, a storage capacitor for storing a data signal supplied via a data signal line, a drive transistor for supplying a current corresponding to the data signal to the light-emitting element, and a write transistor connected between the data signal line and the gate electrode of the drive transistor, the write transistor having one of its source electrode and drain electrode connected to the data signal line. The storage capacitor is formed by: a first electrode layer connected to the gate electrode of the drive transistor and the write transistor; a first insulating layer formed on the first electrode layer; a second electrode layer connected to the source electrode of the drive transistor and having a first electrode portion arranged on the first insulating layer opposite the first electrode layer; a second insulating layer formed on the first insulating layer; and a third electrode layer connected to the source electrode of the drive transistor, at least a portion of which is formed on the second insulating layer, the third electrode layer having a second electrode portion arranged opposite the first electrode layer. The first electrode portion and the second electrode portion are provided at positions where they do not overlap each other in a plan view of the active matrix substrate, and the first electrode layer covers the first electrode portion and the second electrode portion.

[0165] Furthermore, in each of the above embodiments, the display panel has been described as a top-emission structure display panel, but it may also be a bottom-emission structure display panel.

[0166] Furthermore, the control unit and the data driver in each of the above embodiments may be realized by one IC, or may be realized by different ICs.

[0167] In addition, the initialization transistor T1 in each of the above embodiments G and T1 B The function and configuration of, for example, the initialization transistor T1 Rand the compensation transistor T2 G and T2 B The function and configuration of the compensation transistor T2 R and write transistor T3 G and T3 B The function and configuration of, for example, the write transistor T3 R is the same as the driving transistor TD G and TD B The function and configuration of the driving transistor TD R may be the same as

[0168] Furthermore, the light-emitting element EL in each of the above embodiments G and EL B The function and configuration of the light-emitting element EL R may be the same as

[0169] In addition, the storage capacitor Cs G and Cs B The function and configuration of the storage capacitor Cs R may be the same as

[0170] Furthermore, although the display devices in the above embodiments have been described as examples in which color images are displayed, the present invention is not limited to this, and for example, monochrome images may also be displayed. [Industrial Applicability]

[0171] The present disclosure is useful for, for example, display devices using organic EL elements and the like. [Explanation of symbols]

[0172] 1 Display device 10 Display Module 11 Pixel circuit 11B, 11G, 11R sub-pixel circuits 12 Display panel 13 Gate Driver 14 Data Driver 20 Control Unit 30 power supply 110 Substrate 120 First undercoat layer 130 Second undercoat layer 140 First insulating layer 150 Second insulating layer 151 Through hole 152, 153 through holes (recesses) 152a, 153a inner surface 154, 155 recess 160 metal layer 180 Metal layer (4th electrode layer) 170 Light-emitting layer 190 Third insulating layer 200 4th insulating layer 220 First upper electrode (second electrode layer) 310 Lower electrode (first electrode layer) 310a 1st electrode part 310b 2nd electrode part 310c, 320c 3rd electrode part 310d 4th electrode part (1st wiring part) 320 2nd upper electrode (3rd electrode layer) 320a 1st electrode part (2nd opposing part) 320b Second electrode part (second opposing part) 330 Connection section (second wiring section) 410 VCC auxiliary line (1st auxiliary line) 420 VCATH auxiliary line (second auxiliary line) 500 photomasks 510 Light blocking part 520 Transparent part 530 Halftone section C Contact part Cs, Cs B , Cs G , Cs R , Cs_add, Cs_conv retention capacity d1, d2, d3, d4, d5 distance EL B , E.L. G , E.L. R Light-emitting element INI Initialization signal line, control signal L pixel rows REF Reference signal line, control signal t1, t2, t3, t4, t5 time T1 B , T1 G , T1 R Initialization Transistor T2 B , T2 G , T2 R Compensation Transistor T3 B , T3 G , T3 R Write transistor TD B , T.D. G , T.D. R Drive transistor VCATH negative power line, negative power supply voltage VCC Positive power supply line (power supply line), positive power supply voltage Vdat B , Vdat G , Vdat R Data signal line, data signal WS Write signal line, control signal

Claims

1. A display device comprising a plurality of pixels arranged two-dimensionally, Each of the plurality of pixels is A light-emitting element; a storage capacitor that stores a data signal supplied via a data signal line; a driving transistor that supplies a current corresponding to the data signal to the light emitting element; a write transistor connected between the data signal line and the gate electrode of the drive transistor, one of a source electrode and a drain electrode of the write transistor being connected to the data signal line; The retention capacity is a first electrode layer connected to a gate electrode of the drive transistor and the write transistor; a first insulating layer covering the first electrode layer; a second electrode layer connected to a source electrode of the driving transistor and having a first opposing portion disposed on the first insulating layer so as to oppose the first electrode layer; a second insulating layer covering the first insulating layer and the second electrode layer; a third electrode layer connected to the source electrode of the driving transistor, at least a portion of which is formed on the second insulating layer, the third electrode layer having a second opposing portion disposed opposite to the first electrode layer; the first opposing portion and the second opposing portion are formed at positions that do not overlap with each other in a plan view of the display device, The first electrode layer is formed so as to overlap with each of the first opposing portion and the second opposing portion in the plan view. Display device.

2. The second opposing portion is formed directly on the second insulating layer. The display device according to claim 1 .

3. a recess having a bottom recessed toward the first insulating layer at a position overlapping the first electrode layer in the plan view; The second opposing portion is formed on the bottom surface of the recess. The display device according to claim 1 .

4. a recessed portion that penetrates the second insulating layer toward the first insulating layer at a position that overlaps the first electrode layer in the plan view, The second opposing portion is formed on the first insulating layer. The display device according to claim 1 .

5. The second opposing portion is composed of a first portion opposing the first electrode layer and a second portion formed on the inner surface of the recess.

5. The display device according to claim 3 or 4.

6. moreover, a power supply line connected to a drain electrode of the driving transistor and formed in an elongated shape in the plan view; a first auxiliary line connected to the power supply line and having a lower resistance than the power supply line; The first auxiliary line is formed on the second insulating layer. The display device according to any one of claims 1 to 5.

7. moreover, a fourth electrode layer connected to a cathode electrode of the light-emitting element and covering the plurality of pixels; a second auxiliary line connected to the fourth electrode layer and having a lower resistance than the fourth electrode layer; The second auxiliary line is formed on the second insulating layer. The display device according to any one of claims 1 to 6.

8. The first electrode layer is a third opposing portion covering the first opposing portion and the second opposing portion; a first wiring portion connected to the gate electrode of the driving transistor; The third electrode layer overlaps a part of the first wiring portion in the plan view. The display device according to any one of claims 1 to 7.

9. The first opposing portion has a rectangular shape in the plan view, The second opposing portion has an elongated shape in the plan view. The display device according to claim 8 .

10. a through hole is formed in the second insulating layer at a position where, in the plan view, a second wiring portion that connects the second electrode layer and the source electrode of the driving transistor and the third electrode layer overlaps with each other; The third electrode layer is electrically connected to the source electrode of the driving transistor through the through hole. The display device according to any one of claims 1 to 9.

11. further comprising a power supply line connected to a drain electrode of the driving transistor and formed in an elongated shape in the plan view, The second opposing portion is formed to sandwich the power line in the plan view. The display device according to any one of claims 1 to 5.

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