Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving characteristics.SOLUTION: According to one embodiment, a semiconductor device includes a first terminal, a second terminal, a third terminal, a first transistor of a normally-off type, a second transistor of a normally-on type, and a diode. The first transistor includes a first source, a first drain, and a first gate. The first source is electrically connected to the first terminal. The first drain is electrically connected to the second terminal. The first gate is electrically connected to the third terminal. The second transistor includes a second source, a second drain, and a second gate. The second drain is electrically connected to the second terminal. The second gate is electrically connected to the first terminal. The diode includes an anode and a cathode. The anode is electrically connected to the first terminal. The cathode is electrically connected to the second source.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, in semiconductor devices such as transistors, improvements in characteristics are desired. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2015-501079 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor device capable of improving characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first terminal, a second terminal, a third terminal, a normally-off first transistor, a normally-on second transistor, and a diode. The first transistor includes a first source, a first drain, and a first gate. The first source is electrically connected to the first terminal. The first drain is electrically connected to the second terminal. The first gate is electrically connected to the third terminal. The second transistor includes a second source, a second drain, and a second gate. The second drain is electrically connected to the second terminal. The second gate is electrically connected to the first terminal. The diode includes an anode and a cathode. The anode is electrically connected to the first terminal. The cathode is electrically connected to the second source. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a circuit diagram illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram illustrating the operation of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram illustrating the operation of the semiconductor device according to the first embodiment. [Figure 4] 4(a) and 4(b) are graphs illustrating the characteristics of the semiconductor device. [Figure 5] FIG. 5 is a schematic view illustrating the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a schematic view illustrating the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a schematic view illustrating the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view illustrating the semiconductor device according to the third embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view illustrating the semiconductor device according to the fourth embodiment. [Figure 12] FIG. 12 is a schematic plan view illustrating the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a circuit diagram illustrating a semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 110 according to the embodiment includes a first terminal 81, a second terminal 82, a third terminal 83, a first transistor 51, a second transistor 52, and a diode 53.

[0009] The first transistor 51 is a normally-off type. The first transistor 51 includes a first source 51s, a first drain 51d, and a first gate 51g. The first source 51s is electrically connected to a first terminal 81. The first drain 51d is electrically connected to a second terminal 82. The first gate 51g is electrically connected to a third terminal 83.

[0010] The second transistor 52 is a normally-on type. The second transistor 52 includes a second source 52s, a second drain 52d, and a second gate 52g. The second drain 52d is electrically connected to the second terminal 82. The second gate 52g is electrically connected to the first terminal 81.

[0011] The diode 53 includes an anode 53a and a cathode 53c. The anode 53a is electrically connected to the first terminal 81. The cathode 53c is electrically connected to the second source 52s.

[0012] In the semiconductor device 110, the current flowing between the first terminal 81 and the second terminal 82 can be controlled by the potential of the third terminal 83. The potential of the third terminal 83 may be, for example, a potential based on the potential of the first terminal 81. The third terminal 83 functions as a gate terminal of the semiconductor device 110.

[0013] In the semiconductor device 110 according to the embodiment, as will be described later, loss during reflux can be reduced, and a semiconductor device with improved characteristics can be provided.

[0014] An example of the characteristics of the semiconductor device 110 will now be described. 2 and 3 are circuit diagrams illustrating the operation of the semiconductor device according to the first embodiment. 2, in the first state ST1, when an on-voltage Von is applied to the third terminal 83, a first current I1 flows. The first current I1 flows from the second terminal 82 to the first terminal 81.

[0015] As shown in FIG. 3, the potential of the third terminal 83 becomes an off-voltage Voff. For example, the off-voltage Voff is lower than the on-voltage Von. For example, the off-voltage Voff is the potential of the first terminal 81. The state transitions from the first state ST1 to the second state ST2 (off state). In the off state, depending on the configuration of the external circuit, the potential of the first terminal 81 becomes higher than the potential of the second terminal 82. In this case, a second current I2 flows through the second transistor 52. The second current I2 flows in a direction from the first terminal 81 to the second terminal 82.

[0016] For example, switching between the first state ST1 and the second state ST2 is repeated. For example, when the first transistor 51 is in the on state, the second transistor 52 is in the off state. For example, when the first transistor 51 is in the off state, the second transistor 52 is in the on state. When the potential of the first terminal 81 becomes higher than the potential of the second terminal 82, it is possible to cause the first transistor 51 to be turned on, thereby allowing current to flow through the first transistor 51. However, there is a dead time between when the first terminal 81 becomes high potential and when the first transistor 51 is turned on.

[0017] Losses occur during dead time. This corresponds to the loss during freewheeling. The loss during freewheeling becomes significant, for example, when the switching frequency increases.

[0018] In this embodiment, the diode 53 is provided between the second source 52s of the second transistor 52 and the first terminal 81. This makes it possible to lower the on-voltage during dead time, thereby suppressing loss during freewheeling.

[0019] 4(a) and 4(b) are graphs illustrating the characteristics of the semiconductor device. FIG. 4(a) corresponds to the semiconductor device 110 according to the embodiment. FIG. 4(b) corresponds to the semiconductor device 119 of the reference example. In the semiconductor device 119, a first transistor 51 and a second transistor 52 are provided, but a diode 53 is not provided. In the semiconductor device 119, the second source 52s is electrically connected to the first terminal 81. The horizontal axis of these figures is the source-drain voltage Vsd. The source-drain voltage Vsd corresponds to the voltage between the first terminal 81 and the second terminal 82. The vertical axis of these figures is the drain current Id. The drain current Id corresponds to the current flowing between the first terminal 81 and the second terminal 82.

[0020] 4(b), in the semiconductor device 119 of the reference example, the absolute value of the threshold voltage Vth2 is large, which results in a high on-voltage during the dead time.

[0021] As shown in FIG. 4(a), in the semiconductor device 110 according to the embodiment, the absolute value of the threshold voltage Vth1 is smaller than the absolute value of the threshold voltage Vth2. The smaller threshold voltage Vth1 is due to the provision of the diode 53. In the semiconductor device 110, the on-voltage during dead time can be reduced. This reduces loss during freewheeling. The semiconductor device 110 functions as, for example, a field effect transistor (FET) having a body diode.

[0022] The absolute value of the threshold voltage Vth2 is, for example, 3.5 V. The absolute value of the threshold voltage Vth1 is, for example, 1.2 V. For example, in the case of switching at 3 kW and a frequency of 1 MHz, the loss during freewheeling in the semiconductor device 119 is approximately 0.4 W. In contrast, under the same conditions, the loss during freewheeling in the semiconductor device 110 is approximately 0.1 W. According to the embodiment, the loss during freewheeling can be suppressed. A semiconductor device with improved characteristics can be provided.

[0023] An example of the configuration of the semiconductor device will be described below. 5 to 7 are schematic views illustrating the semiconductor device according to the first embodiment. Fig. 5 is a plan view, Fig. 6 is a cross-sectional view taken along line A1-A2 in Fig. 5, and Fig. 7 is a cross-sectional view taken along line B1-B2 in Fig. 5.

[0024] 5 to 7, the semiconductor device 110 further includes a device substrate 80s. The device substrate 80s is, for example, an insulating substrate for mounting components. The device substrate 80s includes a first substrate surface 80f. The positions of the first transistor 51, the second transistor 52, and the diode 53 relative to the first substrate surface 80f are fixed.

[0025] 5 and 6, a first direction D1 from the first transistor 51 to the second transistor 52 is along the first substrate surface 80f. As shown in Fig. 5, a direction from the diode 53 to at least a part of the second transistor 52 is along the first substrate surface 80f.

[0026] The first direction D1 is the X-axis direction. A direction perpendicular to the X-axis direction is the Z-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is the Y-axis direction.

[0027] 6, a second direction D2 from the first substrate surface 80f to the first transistor 51 intersects with the first direction D1. The direction from the first substrate surface 80f to the second transistor 52 is along the second direction D2. The second direction D2 is, for example, the Z-axis direction.

[0028] 5 and 6, the direction from the first source 51s to the first drain 51d is along the first direction D1. The position of the first gate 51g in the first direction D1 is between the position of the first source 51s in the first direction D1 and the position of the first drain 51d in the first direction D1.

[0029] 5 and 6, the direction from the second drain 52d to the second source 52s is along the first direction D1. The position of the second gate 52g in the first direction D1 is between the position of the second drain 52d in the first direction D1 and the position of the second source 52s in the first direction D1.

[0030] 5, the first source 51s, the first drain 51d, the first gate 51g, the second source 52s, the second drain 52d, and the second gate 52g extend along a third direction D3. The third direction D3 intersects with a plane including the first direction D1 and the second direction D2. The third direction D3 is, for example, the Y-axis direction.

[0031] 5, in this example, the first terminal 81, the second terminal 82, and the third terminal 83 are fixed to the first substrate surface 80f. In this example, the position of the first transistor 51 in the third direction D3 is 、 The position of the second transistor 52 in the third direction D3 is between the position of the first terminal 81 in the third direction D3 and the position of the second terminal 82 in the third direction D3. The position of a portion of the third terminal 83 in the third direction D3 is between the position of the first terminal 81 in the third direction D3 and the position of the first transistor 51 in the third direction D3. The position of another portion of the third terminal 83 in the third direction D3 is between the position of the diode 53 in the third direction D3 and the position of the second transistor 52 in the third direction D3. In the embodiment, the positions and planar shapes of the first terminal 81, the second terminal 82, and the third terminal 83 can be modified in various ways.

[0032] 5 and 6, in this example, the semiconductor device 110 includes a transistor substrate 51Sb. For example, a first transistor 51 and a second transistor 52 are mounted on the transistor substrate 51Sb. The transistor substrate 51Sb is fixed to a device substrate 80s.

[0033] As shown in FIG. 8, the first transistor 51 includes a first transistor semiconductor member 51M. The second transistor 52 includes a second transistor semiconductor member 52M. The second transistor semiconductor member 52M may be separate from the first transistor semiconductor member 51M. The second transistor semiconductor member 52M may be continuous with the first transistor semiconductor member 51M. The first transistor semiconductor member 51M is one semiconductor chip. The second transistor semiconductor member 52M is another semiconductor chip. The first transistor semiconductor member 51M and the second transistor semiconductor member 52M may be different regions of one semiconductor chip.

[0034] As will be described later, the first transistor semiconductor member 51M and the second transistor semiconductor member 52M may include GaN. The first transistor 51 and the second transistor 52 include, for example, a nitride semiconductor.

[0035] 7, in this example, the cathode 53c is between the first substrate surface 80f and the anode 53a. The diode 53 includes a diode semiconductor material 53M. The diode semiconductor material 53M includes silicon. The diode 53 may be a silicon diode.

[0036] For example, the diode 53 may be a Schottky barrier diode. The withstand voltage of the diode 53 may be 1 / 5 or less of the withstand voltage of the first transistor 51. The withstand voltage of the diode 53 may be 1 / 8 or less of the withstand voltage of the first transistor 51. The withstand voltage of the diode 53 is equal to or greater than the absolute value of the threshold voltage of the second transistor 52. The desired operation can be stably achieved.

[0037] 7, in this example, the semiconductor device 110 includes a diode substrate 53Sb. The diode 53 is mounted on the diode substrate 53Sb. The diode substrate 53Sb is fixed to the device substrate 80s.

[0038] In this example, a diode conductive layer 53E is provided on a diode substrate 53Sb. The cathode 53c is electrically connected to the diode conductive layer 53E.

[0039] 5 and 7, the diode conductive layer 53E and the second source 52s are electrically connected by a second source wiring 52sL. As shown in Fig. 5 and 7, the anode 53a is electrically connected to the first terminal 81 by an anode wiring 53aL.

[0040] As shown in FIG. 5, the first source 51s is electrically connected to the first terminal 81 by a first source wiring 51sL. As shown in FIG. 5, the first gate 51g is electrically connected to the third terminal 83 by a first gate wiring 51gL. As shown in FIG. 5, the second gate 52g is electrically connected to the third terminal 83 by a second gate wiring 52gL. As shown in FIG. 5, the first drain 51d is electrically connected to the second terminal 82 by a first drain wiring 51dL. As shown in FIG. 5, the second drain 52d is electrically connected to the second terminal 82 by a second drain wiring 52dL.

[0041] As shown in FIG. 5, the distance between the first gate 51g and the first drain 51d in the first direction D1 is defined as a first distance Lgd1. The distance between the second gate 52g and the second drain 52d in the first direction D1 is defined as a second distance Lgd2. The first distance Lgd1 is preferably substantially the same as the second distance Lgd2. For example, the first distance Lgd1 is preferably 0.8 to 1.2 times the second distance Lgd2. This allows, for example, the two transistors to have substantially the same breakdown voltage.

[0042] As shown in FIG. 5, the length of the first gate 51g along the third direction D3 of the portion facing the first drain 51d is defined as a first length Wg1. The length of the second gate 52g along the third direction D3 of the portion facing the second drain 52d is defined as a second length Wg2. The first length Wg1 is preferably substantially the same as the second length Wg2. For example, the first length Wg1 is preferably 0.8 to 1.2 times the second length Wg2. This allows, for example, the two transistors to have substantially the same on-resistance.

[0043] 5, a plurality of first sources 51s, a plurality of first drains 51d, and a plurality of first gates 51g may be provided in the first transistor 51. The position of one of the plurality of first gates 51g in the first direction D1 is between the position of one of the plurality of first sources 51s in the first direction D1 and the position of one of the plurality of first drains 51d in the first direction D1.

[0044] 5, a plurality of second sources 52s, a plurality of second drains 52d, and a plurality of second gates 52g may be provided in the second transistor 52. The position of one of the plurality of second gates 52g in the first direction D1 is between the position of one of the plurality of second sources 52s in the first direction D1 and the position of one of the plurality of second drains 52d in the first direction D1.

[0045] An example of the first transistor 51 and the second transistor 52 will be described below. FIG. 8 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. FIG. 8 corresponds to a part of the cross-section along line A1-A2 in FIG. 5. As shown in FIG. 8, the first transistor 51 includes a first semiconductor region 11 and a second semiconductor region 12. The first transistor 51 may include a first transistor substrate 51S. The first transistor substrate 51S may be, for example, a silicon substrate, a GaN substrate, or a SiC substrate. The first semiconductor region 11, the second semiconductor region 12, and the first transistor substrate 51S are included in the first transistor semiconductor member 51M. The first semiconductor region 11 is provided on the first transistor substrate 51S. The second semiconductor region 12 is provided on the first semiconductor region 11. The first transistor substrate 51S may include a buffer layer or the like.

[0046] The first semiconductor region 11 contains Al x1 Ga 1-x1 N (0 ≦ x1 < 1). The first semiconductor region 11 contains, for example, GaN. The composition ratio x1 is, for example, 0 or more and 0.1 or less.

[0047] The second semiconductor region 12 contains Al x2 Ga 1-x2 N (x1 < x2 ≦ 1). The second semiconductor region 12 contains AlGaN. The composition ratio x2 is, for example, more than 0.1 and 0.35 or less.

[0048] The first semiconductor region 11 includes a first partial region 11a, a second partial region 11b, a third partial region 11c, a fourth partial region 11d, and a fifth partial region 11e. The direction from the first partial region 11a to the first source 51s is along the second direction D2. The direction from the second partial region 11b to the first drain 51d is along the second direction D2. The direction from the third partial region 11c to the first gate 51g is along the second direction D2.

[0049] The position along the first direction D1 of the fourth partial region 11d is between the position along the first direction D1 of the first partial region 11a and the position along the first direction D1 of the third partial region 11c. The position along the first direction D1 of the fifth partial region 11e is between the position along the first direction D1 of the third partial region 11c and the position along the first direction D1 of the second partial region 11b.

[0050] The second semiconductor region 12 includes a first semiconductor portion 12a and a second semiconductor portion 12b. The direction from the fourth sub-region 11d to the first semiconductor portion 12a is along the second direction D2. The direction from the fifth sub-region 11e to the second semiconductor portion 12b is along the second direction D2.

[0051] At least a portion of the first gate 51g is located between the first semiconductor portion 12a and the second semiconductor portion 12b in the first direction D1. For example, a portion of the first gate 51g may be located between the fourth partial region 11d and the fifth partial region 11e in the first direction D1.

[0052] For example, in the fourth partial region 11d and the fifth partial region 11e, a carrier region is formed in a portion facing the second semiconductor region 12. The carrier region is, for example, a two-dimensional electron gas. The first transistor 51 is, for example, a normally-off type HEMT.

[0053] The first source 51s is electrically connected to the first semiconductor portion 12a, and the first drain 51d is electrically connected to the second semiconductor portion 12b.

[0054] As shown in FIG. 8, the first transistor 51 includes a first insulating layer 41. The first insulating layer 41 includes a first insulating region 41a. The first insulating region 41a is located between the third partial region 11c and the first gate 51g. The first insulating region 41a functions as, for example, a gate insulating film. The first insulating layer 41 includes, for example, silicon and oxygen. The first insulating layer 41 includes, for example, SiO2.

[0055] 8, the first transistor 51 may include a first nitride member 31. The first nitride member 31 may include Al y1 Ga 1-y1It includes N(0 < y1 ≤ 1). The first nitride member 31 may include, for example, AlN. A part of the first nitride member 31 is between the third partial region 11c and the first insulating region 41a. By providing a part of the first nitride member 31 between the third partial region 11c and the first insulating region 41a, for example, a lower on-resistance can be obtained. The thickness of the first nitride member 31 may be, for example, 0.1 nm or more and 5 nm or less.

[0056] As shown in FIG. 8, the first transistor 51 may further include a first insulating member 51i. A part of the first insulating member 51i is between the fifth partial region 11e and another part of the first nitride member 31 in the second direction D2. In one example, the first insulating member 51i includes silicon and nitrogen. The first insulating member 51i includes SiN. By providing the first insulating member 51i, for example, a higher breakdown voltage can be obtained.

[0057] As shown in FIG. 8, in the first transistor 51, a first gate wiring layer 51ga may be provided. In the first transistor 51, a first field plate sFP1, a second field plate sFP2, and a third field plate sFP3 may be provided. These conductive members are insulated by an interlayer insulating layer 58a.

[0058] As shown in FIG. 8, in this example, the second transistor 52 includes a third semiconductor region 13 and a fourth semiconductor region 14. The second transistor 52 may include a second transistor substrate 52S. The second transistor substrate 52S may be, for example, a silicon substrate, a GaN substrate, or a SiC substrate, etc. The third semiconductor region 13, the fourth semiconductor region 14, and the second transistor substrate 52S are included in the second transistor semiconductor member 52M. The third semiconductor region 13 is provided on the second transistor substrate 52S. The fourth semiconductor region 14 is provided on the third semiconductor region 13. The second transistor substrate 52S may include a buffer layer or the like.

[0059] The third semiconductor region 13 is Al x3 Ga 1-x3It includes N(0≦x3<1). The third semiconductor region 13 includes, for example, GaN. The composition ratio x3 is, for example, 0 or more and 0.1 or less.

[0060] The fourth semiconductor region 14 includes Al x4 Ga 1-x4 N(x3<x4≦1). The fourth semiconductor region 14 includes, for example, AlGaN. The composition ratio x4 is, for example, more than 0.1 and 0.35 or less. A part of the fourth semiconductor region 14 is between the third semiconductor region 13 and the second gate 52g.

[0061] The second transistor 52 includes a second insulating member 52i. The second insulating member 52i is between the above-mentioned part of the fourth semiconductor region 14 and the second gate 52g.

[0062] For example, in the third semiconductor region 13, a carrier region is formed in a portion facing the fourth semiconductor region 14. The carrier region is, for example, a two-dimensional electron gas. The second transistor 52 is, for example, a normally-on type HEMT.

[0063] As shown in FIG. 8, in the second transistor 52, a second gate wiring layer 52ga may be provided. In the second transistor 52, a fourth field plate sFP4, a fifth field plate sFP5, and a sixth field plate sFP6 may be provided. These conductive members are insulated by the interlayer insulating layer 58b.

[0064] In the example of the semiconductor device of FIG. 8, the first transistor 51 is one semiconductor chip. The second transistor 52 is another one semiconductor chip.

[0065] As described below, the first transistor 51 and the second transistor 52 may be provided on one semiconductor chip.

[0066] (Second Embodiment) FIG. 9 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. Fig. 9 is a cross-sectional view corresponding to a portion of the cross section taken along line A1-A2 in Fig. 1. As shown in Fig. 9, a first transistor 51 and a second transistor 52 are provided in a semiconductor device 120 according to the second embodiment. In the semiconductor device 120, the configurations of the first transistor 51 and the second transistor 52 are different from the configurations of the first transistor 51 and the second transistor 52 in the semiconductor device 110. Except for this, the configuration of the semiconductor device 120 may be similar to the configuration of the semiconductor device 110.

[0067] In the semiconductor device 120, the semiconductor member included in the second transistor 52 is continuous with the semiconductor member included in the first transistor 51. The configuration of the first transistor 51 in the semiconductor device 120 is the same as the configuration of the first transistor 51 in the semiconductor device 110. An example of the configuration of the second transistor 52 in the semiconductor device 120 will be described below.

[0068] 9, the first semiconductor region 11 includes a sixth partial region 11f, a seventh partial region 11g, and an eighth partial region 11h. The second partial region 11b is located between the fifth partial region 11e and the seventh partial region 11g in the first direction D1. The sixth partial region 11f is located between the second partial region 11b and the seventh partial region 11g. The eighth partial region 11h is located between the sixth partial region 11f and the seventh partial region 11g.

[0069] The direction from the sixth partial region 11f to the second drain 52d is along the second direction D2. The direction from the seventh partial region 11g to the second source 52s is along the second direction D2. The direction from the eighth partial region 11h to the second gate 52g is along the second direction D2.

[0070] The second semiconductor region 12 includes a third semiconductor portion 12c. At least a part of the third semiconductor portion 12c is located between the eighth sub-region 11h and the second gate 52g.

[0071] 9, the second transistor 52 includes a second insulating member 52i. A part of the second insulating member 52i is located between the third semiconductor portion 12c and the second gate 52g. The second insulating member 52i functions as, for example, a gate insulating film.

[0072] In one example, the second insulating member 52i may contain the same material as the first insulating member 51i. For example, the film that will become the first insulating member 51i is used as the second insulating member 52i. This allows for efficient manufacturing. The first insulating member 51i and the second insulating member 52i contain, for example, SiN.

[0073] 9, the thickness of the first insulating region 41a along the second direction D2 is defined as a first thickness t1. The first thickness t1 corresponds to the substantial thickness of the gate insulating film in the first transistor 51. The thickness of the second insulating member 52i along the second direction D2 is defined as a second thickness t2. The second thickness t2 corresponds to the thickness of the gate insulating film in the second transistor 52.

[0074] For example, the second thickness t2 may be thinner than the first thickness t1. For example, if the first insulating region 41a contains SiO2 and the second insulating member 52i contains SiN, these materials have different dielectric constants. By using different thicknesses, for example, it is possible to prevent the threshold voltage of the second transistor 52 from becoming higher than necessary.

[0075] 9, the first semiconductor region 11 may include a ninth sub-region 11i. The position of the ninth sub-region 11i in the first direction D1 is between the position of the second drain 52d in the first direction D1 and the position of the second gate 52g in the first direction D1.

[0076] The second transistor 52 may include a second nitride member 32. The second nitride member 32 may include Al y2 Ga 1-y2It includes N(0 < y2 ≤ 1). The second nitride member 32 includes, for example, AlN. Another part of the second insulating member 52i is between a part of the third semiconductor portion 12c and the second nitride member 32. A part of the third semiconductor portion 12c is between the ninth partial region 11i and the above-mentioned another part of the second insulating member 52i.

[0077] (Third Embodiment) FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view corresponding to a part of the cross-section taken along line A1 - A2 in FIG. 1. As shown in FIG. 10, in the semiconductor device 130 according to the third embodiment, the first transistor 51 and the second transistor 52 are provided. In the semiconductor device 130, the configurations of the first transistor 51 and the second transistor 52 are different from those of the first transistor 51 and the second transistor 52 in the semiconductor device 120. Except for this, the configuration of the semiconductor device 130 may be the same as that of the semiconductor device 120.

[0078] In the semiconductor device 130, in the first transistor 51 and the second transistor 52, the drains are shared. The configuration of the first transistor 51 in the semiconductor device 130 may be the same as that of the first transistor 51 in the semiconductor device 110.

[0079] As shown in FIG. 10, in the semiconductor device 130, the first semiconductor region 11 includes the sixth partial region 11f and the seventh partial region 11g. The second partial region 11b is between the fifth partial region 11e and the sixth partial region 11f in the first direction D1. The seventh partial region 11g is between the second partial region 11b and the sixth partial region 11f. The direction from the sixth partial region 11f to the second source 52s follows the second direction D2. The direction from the seventh partial region 11g to the second gate 52g follows the second direction D2.

[0080] The second semiconductor region 12 includes the third semiconductor portion 12c. At least a part of the third semiconductor portion 12c is between the seventh partial region 11g and the second gate 52g.

[0081] The second drain 52d is continuous with the first drain 51d. The boundary between the second drain 52d and the first drain 51d may be unclear. The first drain 51d is shared by the first transistor 51 and the second transistor 52.

[0082] (Fourth embodiment) FIG. 11 is a schematic cross-sectional view illustrating the semiconductor device according to the fourth embodiment. Fig. 11 is a cross-sectional view corresponding to a portion of the cross section taken along line B1-B2 in Fig. 1. As shown in Fig. 11, a diode 53 is provided in a semiconductor device 140 according to the fourth embodiment. In the semiconductor device 140, the configuration of the diode 53 is different from the configuration of the diode 53 in the semiconductor device 110. Except for this, the configuration of the semiconductor device 140 may be similar to the configuration of the semiconductor device 110.

[0083] 11, the semiconductor device 140 includes a device substrate 80s. The device substrate 80s includes a first substrate surface 80f. The position of the diode 53 relative to the first substrate surface 80f is fixed. In the semiconductor device 140, the anode 53a is located between the first substrate surface 80f and the cathode 53c.

[0084] The semiconductor device 140 includes a diode substrate 53Sb. A diode 53 is mounted on the diode substrate 53Sb. The diode substrate 53Sb is fixed to the device substrate 80s. A diode conductive layer 53E is provided on the diode substrate 53Sb. The anode 53a is electrically connected to the diode conductive layer 53E. The diode conductive layer 53E is electrically connected to the first terminal 81 by an anode wiring 53aL. The cathode 53c is electrically connected to the second source 52s by a second source wiring 52sL.

[0085] The configuration of the diode 53 in the semiconductor device 140 may be applied to the semiconductor device 120 and the semiconductor device 130 .

[0086] (Fifth embodiment) FIG. 12 is a schematic plan view illustrating the semiconductor device according to the fifth embodiment. 12 , the semiconductor device 150 according to the fifth embodiment includes a plurality of first transistors 51 and a plurality of second transistors 52. One of the plurality of second transistors 52 is located between one of the plurality of first transistors 51. One of the plurality of first transistors 51 is located between one of the plurality of second transistors 52.

[0087] The first sources 51s of the plurality of first transistors 51 are electrically connected to the first terminal 81 (see FIG. 1). The first gates 51g of the plurality of first transistors 51 are electrically connected to the third terminal 83 (see FIG. 1). The first drains 51d of the plurality of first transistors 51 are electrically connected to the second terminal 82 (see FIG. 1).

[0088] The second source 52s of each of the second transistors 52 is electrically connected to the cathode 53c (see FIG. 1). The second gate 52g of each of the second transistors 52 is electrically connected to the first terminal 81 (see FIG. 1). The second drain 52d of each of the second transistors 52 is electrically connected to the second terminal 82 (see FIG. 1).

[0089] In the semiconductor device 150, a normally-off first transistor 51 and a normally-on second transistor 52 are arranged alternately. During switching, an on-current and a reflux current flow efficiently through these transistors. For example, the first transistor 51 and the second transistor 52 share a drain electrode. This reduces the effective wiring resistance, further reducing losses.

[0090] In an embodiment, information about the length and thickness can be obtained by electron microscopy, etc. Information about the composition of the material can be obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy Dispersive X-ray spectroscopy), etc. The embodiment may include the following configurations (e.g., technical solutions). (Configuration 1) A first terminal; A second terminal; A third terminal; a normally-off first transistor including a first source, a first drain, and a first gate, the first source electrically connected to the first terminal, the first drain electrically connected to the second terminal, and the first gate electrically connected to the third terminal; a normally-on second transistor including a second source, a second drain, and a second gate, the second drain being electrically connected to the second terminal, and the second gate being electrically connected to the first terminal; a diode including an anode and a cathode, the anode electrically connected to the first terminal and the cathode electrically connected to the second source; A semiconductor device comprising: (Configuration 2) a device substrate including a first substrate surface; the positions of the first transistor, the second transistor, and the diode relative to the first substrate surface are fixed; a first direction from the first transistor to the second transistor is along a surface of the first substrate; 2. The semiconductor device of claim 1, wherein a direction from the diode to at least a portion of the second transistor is along the first substrate surface and intersects with the first direction. (Configuration 3) a device substrate including a first substrate surface; the position of the diode relative to the first substrate surface is fixed; 2. The semiconductor device of claim 1, wherein the cathode is between the first substrate surface and the anode. (Configuration 4) a device substrate including a first substrate surface; the position of the diode relative to the first substrate surface is fixed; 2. The semiconductor device of claim 1, wherein the anode is between the first substrate surface and the cathode. (Configuration 5) a second direction from the first substrate surface to the first transistor intersects with the first direction; a direction from the first substrate surface to the second transistor is along the second direction; a direction from the first source to the first drain is along the first direction; a position of the first gate in the first direction is between a position of the first source in the first direction and a position of the first drain in the first direction; a direction from the second drain to the second source along the first direction; a position of the second gate in the first direction is between a position of the second drain in the first direction and a position of the second source in the first direction; the first source, the first drain, the first gate, the second source, the second drain, and the second gate are arranged along a third direction, 3. The semiconductor device according to configuration 2, wherein the third direction intersects with a plane including the first direction and the second direction. (Configuration 6) 6. The semiconductor device of claim 5, wherein a first distance along the first direction between the first gate and the first drain is greater than or equal to 0.8 times and less than or equal to 1.2 times a second distance along the first direction between the second gate and the second drain. (Configuration 7) 7. The semiconductor device of claim 5, wherein a first length of a portion of the first gate facing the first drain along the third direction is 0.8 to 1.2 times a second length of a portion of the second gate facing the second drain along the third direction. (Configuration 8) The first transistor is Al x1 Ga 1-x1 a first semiconductor region including N (0≦x1<1); Alx2 Ga 1-x2 A second semiconductor region containing N(x1 < x2 ≤ 1), and including The first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The direction from the first partial region to the first source is along the second direction. The direction from the second partial region to the first drain is along the second direction. The direction from the third partial region to the first gate is along the second direction. The position along the first direction of the fourth partial region is between the position along the first direction of the first partial region and the position along the first direction of the third partial region. The position along the first direction of the fifth partial region is between the position along the first direction of the third partial region and the position along the first direction of the second partial region. The second semiconductor region includes a first semiconductor portion and a second semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The direction from the fifth partial region to the second semiconductor portion is along the second direction. At least a part of the first gate is between the first semiconductor portion and the second semiconductor portion in the first direction. The semiconductor device according to any one of Configurations 5 to 7. (Configuration 9) The first transistor further includes a first insulating layer including a first insulating region. The first insulating region is between the third partial region and the first gate. The semiconductor device according to Configuration 8. (Configuration 10) The first transistor is Al y1 Ga 1-y1 further includes a first nitride member containing N(0 < y1 ≤ 1). A part of the first nitride member is between the third partial region and the first insulating region. The semiconductor device according to Configuration 9. (Configuration 11) The first transistor further includes a first insulating member, The semiconductor device according to Configuration 10, wherein a part of the first insulating member is between the fifth partial region and another part of the first nitride member. (Configuration 12) The first semiconductor region includes a sixth partial region, a seventh partial region, and an eighth partial region, The second partial region is between the fifth partial region and the seventh partial region in the first direction, The sixth partial region is between the second partial region and the seventh partial region, The eighth partial region is between the sixth partial region and the seventh partial region, The direction from the sixth partial region to the second drain is along the second direction, The direction from the seventh partial region to the second source is along the second direction, The direction from the eighth partial region to the second gate is along the second direction, The second semiconductor region includes a third semiconductor portion, The semiconductor device according to Configuration 11, wherein the third semiconductor portion is between the eighth partial region and the second gate. (Configuration 13) The second transistor further includes a second insulating member, A part of the second insulating member is between at least a part of the third semiconductor portion and the second gate, The semiconductor device according to Configuration 12, wherein the second insulating member includes a material included in the first insulating member. (Configuration 14) The semiconductor device according to Configuration 13, wherein a second thickness of the second insulating member along the second direction is thinner than a first thickness of the first insulating region along the second direction. (Configuration 15) The second transistor includes Al y2 Ga 1-y2 The second transistor further includes a second nitride member containing N(0 < y2 ≤ 1), The semiconductor device according to Configuration 14, wherein another part of the second insulating member is between a part of the third semiconductor portion and the second nitride member. (Configuration 16) The first semiconductor region includes a sixth partial region and a seventh partial region, The second partial region is between the fifth partial region and the sixth partial region in the first direction, The seventh partial region is between the second partial region and the sixth partial region, The direction from the sixth partial region to the second source is along the second direction, The direction from the seventh partial region to the second gate is along the second direction, The second semiconductor region includes a third semiconductor portion, At least a part of the third semiconductor portion is between the seventh partial region and the second gate, The second drain is continuous with the first drain, The first drain is shared by the first transistor and the second transistor, and the semiconductor device according to Configuration 11. (Configuration 17) The second transistor, Al x3 Ga 1-x3 A third semiconductor region containing N(0≦x3<1), and Al x4 Ga 1-x4 A fourth semiconductor region containing N(x3<x4≦1), and A second insulating member, and including, A part of the fourth semiconductor region is between the third semiconductor region and the second gate, The second insulating member is between the part of the fourth semiconductor region and the second gate, and the semiconductor device according to any one of Configurations 5 to 7. (Configuration 18) The diode includes a diode semiconductor member, and The diode semiconductor member includes silicon, and the semiconductor device according to Configuration 1. (Configuration 19) The diode is a Schottky barrier diode, 2. The semiconductor device according to configuration 1, wherein the breakdown voltage of the diode is equal to or less than 1 / 5 of the breakdown voltage of the first transistor and is equal to or greater than the absolute value of the threshold voltage of the second transistor. (Configuration 20) a plurality of the first transistors and a plurality of the second transistors are provided; one of the plurality of second transistors is located between one of the plurality of first transistors and another of the plurality of first transistors; 2. The semiconductor device of claim 1, wherein the one of the plurality of first transistors is between the one of the plurality of second transistors and another one of the plurality of second transistors.

[0091] According to the embodiment, it is possible to provide a semiconductor device that can improve characteristics.

[0092] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements included in the semiconductor device, such as terminals, transistors, diodes, semiconductor regions, and insulating members, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0093] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0094] In addition, all semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0095] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0096] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0097] 11-14: first to fourth semiconductor regions, 11a-11i: first to ninth partial regions, 12a-12c: first to third semiconductor portions, 31, 32: first and second nitride members, 41: first insulating layer, 41a: first insulating region, 51, 52: first and second transistors, 51M, 52M: first and second transistor semiconductor members, 51S, 52S: first and second transistor substrates, 51Sb: transistor substrate, 51d, 52d: first and second drains, 51dL, 52dL: first and second drain wirings, 51g, 52g: first and second gates, 51gL, 52gL: first and second gate wirings, 51ga, 52ga: first and second gate wiring layers, 51i, 52i: first and second insulating members, 51s, 52s: first and second sources, 51sL, 52sL: first and second source wirings, 53: diode, 53E: conductive layer for diode, 53M: diode semiconductor member, 53Sb: diode substrate, 53a: anode, 53aL: anode wiring, 53c: cathode, 58a, 58b: interlayer insulating layer, 80f: first substrate surface, 80s: device substrate, 81-83: first to third terminals, 110, 119, 120, 130, 140, 150: semiconductor device, D1-D3: first to third directions, I1, I2: first and second currents, Id: drain current, Lgd1, Lgd2: first and second distances, ST1, ST2: first and second states, Voff: off voltage, Von: on voltage, Vsd: source-drain voltage, Vth1, Vth2: threshold voltage, Wg1, Wg2: first and second lengths, sFP1 to sFP6: first to sixth field plates, t1, t2: first and second thicknesses

Claims

1. A first terminal; A second terminal; A third terminal; a normally-off first transistor including a first source, a first drain, and a first gate, the first source being electrically connected to the first terminal, the first drain being electrically connected to the second terminal, and the first gate being electrically connected to the third terminal; a normally-on second transistor including a second source, a second drain, and a second gate, the second drain being electrically connected to the second terminal, and the second gate being electrically connected to the first terminal; a diode including an anode and a cathode, the anode electrically connected to the first terminal and the cathode electrically connected to the second source; Equipped with a device substrate including a first substrate surface; the positions of the first transistor, the second transistor, and the diode relative to the first substrate surface are fixed; a first direction from the first transistor to the second transistor is along a surface of the first substrate; a direction from the diode to at least a portion of the second transistor is along the first substrate surface and intersects with the first direction; a second direction from the first substrate surface to the first transistor intersects with the first direction; a direction from the first substrate surface to the second transistor is along the second direction; a direction from the first source to the first drain is along the first direction; a position of the first gate in the first direction is between a position of the first source in the first direction and a position of the first drain in the first direction; a direction from the second drain to the second source is along the first direction; a position of the second gate in the first direction is between a position of the second drain in the first direction and a position of the second source in the first direction; the first source, the first drain, the first gate, the second source, the second drain, and the second gate are aligned along a third direction; the third direction intersects with a plane including the first direction and the second direction, The first transistor is a first semiconductor region including Al x1 Ga 1-x1 N (0≦x1<1); a second semiconductor region including Al x2 Ga 1-x2 N (x1<x2≦1); Including, the first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region; a direction from the first partial region to the first source along the second direction; a direction from the second region to the first drain is along the second direction; a direction from the third partial region to the first gate is along the second direction; a position of the fourth partial region along the first direction is between a position of the first partial region along the first direction and a position of the third partial region along the first direction; a position of the fifth partial region along the first direction is between the position of the third partial region along the first direction and a position of the second partial region along the first direction; the second semiconductor region includes a first semiconductor portion and a second semiconductor portion; a direction from the fourth region to the first semiconductor portion is along the second direction; a direction from the fifth portion region to the second semiconductor portion is along the second direction; at least a portion of the first gate is between the first semiconductor portion and the second semiconductor portion in the first direction; the first transistor further includes a first insulating layer including a first insulating region; the first insulating region is between the third portion region and the first gate; the first transistor further includes a first nitride material including Al y1 Ga 1-y1 N (0<y1≦1); a portion of the first nitride member is between the third portion region and the first insulating region; the first transistor further includes a first insulating member; a portion of the first insulating member is between the fifth region and another portion of the first nitride member; the first semiconductor region includes a sixth partial region, a seventh partial region, and an eighth partial region; the second partial region is located between the fifth partial region and the seventh partial region in the first direction, the sixth partial region is between the second partial region and the seventh partial region, the eighth partial region is located between the sixth partial region and the seventh partial region, a direction from the sixth region to the second drain is along the second direction; a direction from the seventh partial region to the second source is along the second direction; a direction from the eighth partial region to the second gate is along the second direction; the second semiconductor region includes a third semiconductor portion; the third semiconductor portion is between the eighth portion region and the second gate; the second transistor further includes a second insulating member; a portion of the second insulating member is between at least a portion of the third semiconductor portion and the second gate; The semiconductor device, wherein the second insulating member includes a material contained in the first insulating member.

2. The semiconductor device according to claim 1 , wherein a second thickness of said second insulating member along said second direction is thinner than a first thickness of said first insulating region along said second direction.

3. The second transistor is Al ｙ２ Ga １－ｙ２ N (0<y2≦1), The semiconductor device according to claim 2 , wherein another portion of the second insulating member is between the portion of the third semiconductor portion and the second nitride member.

4. 2. The semiconductor device according to claim 1, wherein a first distance along the first direction between the first gate and the first drain is 0.8 to 1.2 times a second distance along the first direction between the second gate and the second drain.

5. 2. The semiconductor device according to claim 1, wherein a first length along the third direction of a portion of the first gate facing the first drain is 0.8 to 1.2 times a second length along the third direction of a portion of the second gate facing the second drain.

6. The position of the diode relative to the first substrate surface is fixed, The semiconductor device according to claim 1 , wherein the cathode is between the first substrate surface and the anode.

7. The position of the diode relative to the first substrate surface is fixed, The semiconductor device according to claim 1 , wherein the anode is between the first substrate surface and the cathode.

8. The second transistor is Al ｘ３ Ga １－ｘ３ a third semiconductor region including N (0≦x3<1); Al ｘ４ Ga １－ｘ４ a fourth semiconductor region including N (x3<x4≦1); Including, a portion of the fourth semiconductor region is between the third semiconductor region and the second gate; The semiconductor device according to claim 1 , wherein the second insulating member is located between the portion of the fourth semiconductor region and the second gate.

9. the diode includes a diode semiconductor material; The semiconductor device according to claim 1 , wherein the diode semiconductor material comprises silicon.

10. the diode is a Schottky barrier diode, 2. The semiconductor device according to claim 1, wherein the breakdown voltage of said diode is equal to or less than 1 / 5 of the breakdown voltage of said first transistor and is equal to or greater than the absolute value of the threshold voltage of said second transistor.

11. A first terminal; A second terminal; A third terminal; a normally-off first transistor including a first source, a first drain, and a first gate, the first source being electrically connected to the first terminal, the first drain being electrically connected to the second terminal, and the first gate being electrically connected to the third terminal; a normally-on second transistor including a second source, a second drain, and a second gate, the second drain being electrically connected to the second terminal, and the second gate being electrically connected to the first terminal; a diode including an anode and a cathode, the anode electrically connected to the first terminal and the cathode electrically connected to the second source; Equipped with the diode is a Schottky barrier diode, a breakdown voltage of the diode is equal to or less than 1 / 5 of a breakdown voltage of the first transistor and is equal to or greater than an absolute value of a threshold voltage of the second transistor.

12. a plurality of the first transistors and a plurality of the second transistors are provided; one of the plurality of second transistors is between one of the plurality of first transistors and another one of the plurality of first transistors; 12. The semiconductor device according to claim 1, wherein the one of the plurality of first transistors is located between the one of the plurality of second transistors and another one of the plurality of second transistors.

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