Semiconductor Devices

Abstract

To provide a semiconductor device including a transistor with stable electrical characteristics.SOLUTION: In a semiconductor device, a transistor 60a includes a conductor 62a, a conductor 62b, an insulator 65, an insulator 63, an insulator 64, an insulator 66a, a semiconductor 66b, a conductor 68a, a conductor 68b, an insulator 66c, an insulator 72, and a conductor 74. Here, the conductor 62a and the conductor 62b serve as a back gate of the transistor 60a, and the insulator 65, the insulator 63, and the insulator 64 serve as gate insulating films for the back gate of the transistor 60a. The conductor 68a and the conductor 68b serve as a source or a drain of the transistor 60a. The insulator 72 serves as a gate insulating film of the transistor 60a, and the conductor 74 serves as a gate of the transistor 60a.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. For example, the present invention relates to a method for manufacturing a transistor and a semiconductor device. The present invention relates to a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. The present invention also relates to a manufacturing method of a display device, a liquid crystal display device, a light emitting device, a storage device, and an electronic device. The present invention also relates to a display device, a liquid crystal display device, a light emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. The vessel may include a semiconductor device. [Background technology]

[0004] In recent years, transistors using oxide semiconductors (typically In-Ga-Zn oxide) have been developed. Oxide semiconductors have a long history, and are now being used in integrated circuits. In 1988, the use of crystalline In-Ga-Zn oxide in semiconductor devices was disclosed. In 1995, a transistor using an oxide semiconductor was developed (see Patent Document 1). It has been invented and its electrical properties have been disclosed (see Patent Document 2).

[0005] Furthermore, there are transistors that use silicon (Si) as the semiconductor layer and transistors that use oxide semiconductors as the semiconductor layer. A semiconductor device that combines a transistor using a silicon layer with a silicon nitride layer is attracting attention (see Patent Document 3). (see). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 63-239117 [Patent Document 2] Special table 11-505377 [Patent Document 3] Patent Publication No. 2011-119674 Summary of the Invention [Problem to be solved by the invention]

[0007] One of the objects of the present invention is to provide a semiconductor device having a transistor with stable electrical characteristics. Alternatively, a semiconductor device having a transistor with a small leakage current when non-conducting is provided. Another object of the present invention is to provide a transistor having normally-off electrical characteristics. Another object of the present invention is to provide a semiconductor device having a highly reliable transistor. An object of the present invention is to provide a semiconductor device having the above structure.

[0008] Another object of the present invention is to provide a module including the semiconductor device. An object of the present invention is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. One of the objectives is to provide a novel electronic device. do.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0010] (1) In one aspect of the present invention, a first conductor is formed on a semiconductor substrate, and a first a second insulator that is less permeable to hydrogen than the first insulator is formed on the first insulator; An insulator is deposited, a third insulator is deposited on the second insulator, and a first insulator is deposited on the third insulator. A hard mask having an opening is formed, and a resist having a second opening is formed on the hard mask. A mask is formed, and the third insulator is etched using the resist mask to form the third insulator. A third opening is formed in the body, and the second insulator is etched using a resist mask to form the first insulating layer. A fourth opening is formed in the second insulator, the resist mask is removed, and a hard mask is used to form a fourth opening. The first to third insulators are etched to form a fifth insulating film on the first to third insulators. An opening is formed, and a second conductor is formed to cover the inner wall and bottom surface of the fifth opening. A third conductor is formed on the second conductor so as to fill the opening, and a hard mask and a second conductor are formed. The second conductor and the third conductor are subjected to a polishing process to remove the hard mask, and the second conductor and the third conductor are subjected to a polishing process to remove the hard mask. The heights of the upper surfaces of the second conductor and the third insulator are made to be approximately the same, and the heights of the upper surfaces of the second conductor and the third insulator are made to be approximately the same. an oxide semiconductor is formed on the second insulator, and the second insulator is in contact with the second conductor at the edge of the fifth opening; The second conductor is a conductor that is less permeable to hydrogen than the third conductor. This is the manufacturing method.

[0011] (2) Another aspect of the present invention is that in (1), the maximum value of the width of the second opening is equal to the width of the first opening. This is a method for manufacturing a semiconductor device having a capacitance smaller than the minimum value of .

[0012] (3) Another aspect of the present invention is that in either (1) or (2), the second conductor is A method for manufacturing a semiconductor device containing tantalum and nitrogen.

[0013] (4) Another aspect of the present invention is the semiconductor device according to any one of (1) to (3), wherein the second insulator is A method for manufacturing a semiconductor device containing aluminum and oxygen.

[0014] (5) Another aspect of the present invention is a semiconductor device including: a semiconductor substrate; a first insulator formed on the semiconductor substrate; A second insulator formed on the first insulator and a third insulator formed on the second insulator. a plug embedded in the first insulator, the second insulator, the third insulator, and a third insulator; a first transistor formed on the semiconductor substrate; and a first The transistor is electrically connected to the plug, and the plug is connected to the first insulator to the third insulator. The first conductor is formed in contact with the second conductor. The second transistor is formed including an oxide semiconductor, and the second insulator is formed of the first insulator. The first conductor is less permeable to hydrogen than the second conductor, and the first conductor is less permeable to hydrogen than the second conductor. It is a semiconductor device.

[0015] (6) Another aspect of the present invention is the semiconductor device (5) in which the first conductor contains tantalum and nitrogen. It is a semiconductor device.

[0016] (7) Another aspect of the present invention is that in either (5) or (6), the second insulator is The semiconductor device includes aluminum and oxygen.

[0017] (8) Another embodiment of the present invention is the oxide semiconductor according to any one of (5) to (7). Indium, element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf), A semiconductor device containing lead and oxygen.

[0018] (9) Another aspect of the present invention is the semiconductor substrate according to any one of (5) to (8). The semiconductor device has silicon. [Effects of the Invention]

[0019] A semiconductor device including a transistor with stable electrical characteristics can be provided. Alternatively, to provide a semiconductor device having a transistor with a small leakage current when non-conducting. Alternatively, a semiconductor device having a transistor having normally-off electrical characteristics can be provided. Alternatively, a semiconductor device having a highly reliable transistor can be provided. It is possible.

[0020] Alternatively, a module having the semiconductor device can be provided. It is possible to provide a device or an electronic device having the module. A conductor device may be provided, or a novel module may be provided. Alternatively, a novel electronic device can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above will be self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10]1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a diagram illustrating the range of atomic ratios of oxide semiconductors according to the present invention. [Figure 27] A diagram explaining the InMZnO4 crystal. [Figure 28] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 29] 1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 30] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 31] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 32] Cross-sectional TEM image of a-like OS. [Figure 33] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 34] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 36] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 37] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 38] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 39] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 40] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 41] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Figure 42] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 43] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 44] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 45] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 46] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 47]FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 48] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 49] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 50] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 51] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 52] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 53] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 54] FIG. 10 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 55] 1 is a cross-sectional SEM image according to Example 1. [Figure 56] 1 is a cross-sectional SEM image according to Example 1. [Figure 57] 1 is a cross-sectional SEM image according to Example 1. [Figure 58] 1 is a cross-sectional SEM image according to Example 1. [Figure 59] 1 is a cross-sectional STEM image according to Example 1. [Figure 60] 1 is a cross-sectional STEM image according to Example 1. [Figure 61] FIG. 10 is a cross-sectional view of the structure of a sample according to Example 2. [Figure 62] FIG. 10 is a diagram showing the results of TDS measurement according to Example 2. [Figure 63] FIG. 10 is a diagram showing the results of TDS measurement according to Example 2. [Figure 64] FIG. 10 is a graph showing the measurement results of sheet resistance according to Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0023] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details can be easily made by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used It is used in common among different drawings. When referring to the same thing, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0024] The configurations shown in the following embodiments may be applied or combined as appropriate with other configurations shown in the embodiments. Combinations, substitutions, etc. can be made to form one embodiment of the present invention.

[0025] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. This may be the case.

[0026] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do this.

[0027] Also, a voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." In this case, the positive potential and the negative potential are defined based on that potential.

[0028] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. Therefore, for example, "first" should not be changed to "second" or "third." In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers The term and the ordinal number used to identify an aspect of the present invention may not match.

[0029] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be called an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily an "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0030] Also, even if a material is written as a "semiconductor," if the conductivity is sufficiently high, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily a "conductor" Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0031] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements present at concentrations of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of States) in the conductor and carrier migration The mobility and crystallinity may decrease. In the case of semiconductors, impurities that change the properties of the semiconductor include, for example, Group 1 elements, There are elements from Group 2, Group 13, Group 14, Group 15, and transition metals other than the main component. In particular, for example, hydrogen (which is also contained in water), lithium, sodium, silicon, boron In the case of oxide semiconductors, impurities such as hydrogen can cause Therefore, oxygen vacancies may be formed. Impurities that change the properties include, for example, oxygen, group 1 elements excluding hydrogen, group 2 elements, These include Group 13 elements and Group 15 elements.

[0032] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value, the maximum value, in the region where the channel is formed. , the minimum or average value.

[0033] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate electrode overlaps with the electrode (the area where current flows) forms a channel. The length of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. In the detailed description, the channel width is any one value, the maximum value in the region where the channel is formed. , the minimum or average value.

[0034] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the side surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be increased. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0035] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0036] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length is the length of the part where the source and drain face each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referring to a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0037] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0038] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. The content of oxygen is preferably 55 atomic % or more and 65 atomic % or less, and nitrogen is preferably 100 atomic % or more. 1 atomic % to 20 atomic %; silicon is 25 atomic % to 35 atomic %; hydrogen is 0.1 It refers to silicon nitride oxide and silicon dioxide contained in a concentration range of 10 atomic % or more. The composition of the material is such that the nitrogen content is higher than the oxygen content, and preferably the nitrogen content is 5. 5 atomic % to 65 atomic %; oxygen 1 atomic % to 20 atomic %; silicon 25 atomic % % or more and 35 atomic % or less, and hydrogen is contained in a concentration range of 0.1 atomic % or more and 10 atomic % or less. This refers to the following.

[0039] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0040] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0041] (Embodiment 1) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 25 will be used to explain.

[0042] <How to make wiring and plugs> Hereinafter, as a part of the configuration of a semiconductor device according to one embodiment of the present invention, the manufacturing method of wiring and plugs will be described. The method will be described with reference to the cross-sectional views and top views shown in Figures 1 to 4. A cross-sectional view and a top view corresponding to the dashed dotted line X1-X2 are shown.

[0043] 1 to 4, a conductor 12 (hereinafter, sometimes referred to as a conductive film or wiring) Conductors embedded in openings 17f formed in the insulators 13a, 14b, and 15c. The process of connecting the conductive body 20a and the conductive body 21a is described. The upper and lower parts of the opening 17f have different shapes, and the lower part of the opening 17f (hereinafter referred to as opening 17fa) is , which functions as a via hole or a contact hole, and the upper part of the opening 17f (hereinafter, the opening 17fb) functions as a groove for embedding wiring patterns, etc. The portion of the conductor 20a and the conductor 21a embedded in the opening 17fa functions as a plug. The portions of the conductive body 20a and the conductive body 21a embedded in the opening 17fb function as wiring or the like. .

[0044] First, a conductor 12 is formed on a substrate. The conductor 12 may have a single layer structure or a laminated structure. It may have a layer structure. The substrate is not shown in FIGS. 1 to 4. Other conductive materials, insulators, or semiconductors may be provided between the bodies 12.

[0045] The conductor 12 is formed in the same manner as the hard mask 16, the conductor 20, and the conductor 21, which will be described later. You can use the same method.

[0046] Next, the insulator 13 is formed on the conductor 12. The insulator 13 may have a single layer structure. The insulator 13 may be formed by a sputtering method, a chemical vapor deposition (C VD (Chemical Vapor Deposition) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method or pulsed laser deposition (PLD:Pulsed Laser Deposition) method, atomic layer deposition (ALD) method This can be done using the atomic layer deposition (ALD) method. .

[0047] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0048] Next, the insulator 14 is formed on the insulator 13. The insulator 14 may have a single layer structure. The insulator 14 may be formed by a method such as sputtering, CVD, or MBE. The method can be carried out by using a PLD method, an ALD method, or the like.

[0049] The insulator 14 is preferably made of a material that is less permeable to hydrogen and water than the insulator 13. The insulator 14 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride or the like can be used. By using these as the insulator 14, This allows it to function as an insulating film that has the effect of blocking the diffusion of hydrogen and water.

[0050] Next, the insulator 15 is formed on the insulator 14. The insulator 15 may have a single layer structure. The insulator 15 may be formed by a sputtering method, a CVD method, an MBE method, or the like. The method can be carried out by using a PLD method, an ALD method, or the like.

[0051] Next, a material for the hard mask 16 is deposited on the insulator 15. The material of 6 may be a conductor such as a metal material, or an insulator. The material for the hard mask 16 may be formed as a single layer or as a laminate of an insulator and a conductor. In this specification, the term "hard mask" refers to a material other than resist (metal material The hard mask 16 is made of a material such as silicon or an insulating material. The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. do.

[0052] Next, a hard mask is formed using a resist mask formed by lithography or the like. The material of 16 is etched to form a hard mask 16 having an opening 17a (FIG. 1(A) )(B). Here, FIG. 1(A) corresponds to the dashed line X1-X2 shown in FIG. 1(B). In the following, similarly, cross-sectional views and top views are shown corresponding to the dashed dotted line X1-X2. .

[0053] Here, the opening 17a is a hole for filling an opening 17fb, that is, a wiring pattern, which will be formed in a later step. Therefore, the upper surface shape of the opening 17a corresponds to the wiring pattern. becomes.

[0054] For details of the lithography method, see the description of the resist mask 18a below. The etching for forming the hard mask 16 is dry etching. For dry etching, it is preferable to use a coating, and the description of the insulator 15, etc. can be taken into consideration.

[0055] Next, a resist mask 1 having an opening 17b is formed on the insulator 15 and the hard mask 16. 1(C)(D) 。 Here, the resist mask 18a is a hard mask. It is preferable that the resist is formed so as to cover the mask 16. This also includes the case where an organic coating film or the like is formed under the resist.

[0056] Here, the opening 17b is an opening 17fa, that is, a via hole or a contact hole, to be formed in a later step. Therefore, the upper surface of the opening 17b corresponds to a via hole or a contact hole. Also, it is compatible with via holes or contact holes. The opening 17b is formed in the opening 17a corresponding to the groove in which the wiring pattern is to be embedded. In this case, it is preferable that the maximum width of the opening 17b is equal to or smaller than the minimum width of the opening 17a. For example, the width of the opening 17b in the X1-X2 direction shown in FIG. This is equal to or less than the width of the opening 17a in the X1-X2 direction shown in (A) and (B). By doing so, the via hole or contact hole can be placed with a margin relative to the groove of the wiring pattern. It can be formed by holding it.

[0057] The opening 17b has a circular top surface, but is not limited to this. For example, The upper surface may be elliptical, triangular, rectangular or other polygonal shape. In the case of a corner shape, the corners may be rounded.

[0058] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the resist patterned area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. An immersion technique may be used in which the substrate is filled with a liquid (for example, water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. Which dry etching process is used, or which wet etching process is used, or which dry In addition to the etching process, a wet etching process is performed, or the wet etching process In addition, a dry etching process can be performed.

[0059] Next, the insulator 15 is etched using the resist mask 18a to form an opening 17c. Insulator 15a is formed (see FIGS. 2(A) and 2(B)). Etching is performed until the top surface of the insulator 14 is exposed. It is preferable to use a chip.

[0060] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0061] Next, the insulator 14 is etched using the resist mask 18a to form an opening 17d. Insulator 14a is formed (see FIGS. 2(C) and (D)). Etching is performed until the top surface of the insulator 13 is exposed. It is preferable to use a dry etching device similar to that described above. This can be done.

[0062] Furthermore, when forming the opening 17d, it is not necessary to stop the etching on the top surface of the insulator 13. For example, as shown in FIG. 5(A), the opening 17d is formed, and the insulator 13 is A portion of the insulator 13b is etched to form a recessed portion at a position overlapping the opening 17d. You may do so.

[0063] Next, the resist mask 18a is removed (see FIGS. 3(A) and 3(B)). If an organic coating film is formed under 18a, it can be removed together with the resist mask 18a. The resist mask 18a is preferably removed by dry etching such as ashing. Or, wet etching is performed, or dry etching is performed in addition to wet etching. Wet etching or wet etching plus dry etching This can be done by performing processing.

[0064] After removing the resist mask 18a, a by-product is formed around the upper edge of the opening 17c. By-products 22 may be formed (see Figs. 5(B) and (C)). 14, the components contained in the insulator 15 or the resist mask 18a, or the insulator 14 or The by-product 22 is formed by containing components contained in the etching gas for the insulator 15. It can be removed when the opening 17e is formed in the process.

[0065] Next, the insulators 13, 14a, and 15a are etched using the hard mask 16. The insulators 13a, 14b, and 15b are formed by etching, and the openings 17e are formed in the insulators 13a, 14b, and 15b. (See FIGS. 3(C) and (D)). Here, the upper surface of the conductor 12 is exposed through the opening 17e. At this time, the edge of the opening 17a of the hard mask 16 is also etched. The hard mask 16a may be formed by etching. The edge of the opening 17a has a tapered shape, and the upper part of the edge of the opening 17a is rounded. For etching, it is preferable to use dry etching. The same as above can be used.

[0066] Here, the opening 17e is located at the bottom and is formed using the insulator 14a as a mask. 7ea and an opening 17eb located above the opening 17ea and formed using the hard mask 16 as a mask. The opening 17ea can be considered to be a via hole or contact hole in a later process. The opening 17eb functions as a groove into which a wiring pattern or the like will be embedded in a later process. It functions as:

[0067] The insulator 15b has a periphery of the opening 17eb (which may also be referred to as the inner wall of the opening 17eb). As shown in FIG. 3(D), the tapered shape of the insulator 15b is The perforated portion may be formed so that it is visible from the top surface.

[0068] The insulators 13a and 14b are formed on the edge of the opening 17ea (also called the inner wall of the opening 17ea). It is preferable that the opening 17ea of ​​the insulator 14b has a tapered shape. It is preferable that the upper part of the edge of the opening 17ea is rounded. As a result, in a subsequent process, the conductor 20 having high blocking performance against hydrogen can be formed with good coverage. As shown in FIG. 3(D), the tapered portion of the insulator 13a extends from the upper surface. Sometimes they are formed so that they are visible.

[0069] In order to etch the opening 17ea into such a shape, the above-mentioned dry etching Therefore, the etching rate of the insulator 13 is excessively large relative to the etching rate of the insulator 14a. For example, if the etching rate of the insulator 13 is larger than that of the insulator 14a, The etching rate should be 8 times or less, preferably 6 times or less, and more preferably 4 times or less. stomach.

[0070] By carrying out the dry etching under these conditions, a tapered edge of the opening 17ea is formed. Furthermore, the by-product 22 shown in Figs. 5(B) and (C) is formed. Even if the by-products 22 are removed, the upper edge of the opening 17ea of ​​the insulator 14b is However, the shape may be rounded.

[0071] However, the shape of the opening 17e is not necessarily limited to the above shape. The inner walls of the openings 17ea and 17eb are formed substantially perpendicular to the insulator 14b and the conductor 12. The opening 17eb may be formed in the insulator 15b and the insulator 14b. b, or the opening 17eb may be formed in the insulator 15b, the insulator 14b, and the insulator It may be formed on the edge body 13a.

[0072] Next, the conductor 20 is formed in the opening 17e, and the opening 17e is filled with the conductor 20. The conductor 21 is deposited so as to fit into the hole (see FIGS. 4(A) and 4(B)). It is preferable that the conductive film be formed with good coverage so as to cover the inner wall and bottom surface of the opening 17e. It is preferable that the conductive body 20 contacts the insulator 14b at the edge of the opening 17e. The opening formed in the insulating body 13a and the insulating body 14b is closed along the opening by the conductor 20. As described above, the openings 17ea in the insulators 13a and 14b The edge of the opening 17ea of ​​the insulator 14b is tapered, and the upper part of the edge of the opening 17ea of ​​the insulator 14b is rounded. By doing so, the coverage of the conductor 20 can be further improved.

[0073] The conductor 20 is preferably made of a conductor that is less permeable to hydrogen than the conductor 21 . The conductor 20 is preferably a metal nitride such as tantalum nitride or titanium nitride, particularly tantalum nitride. By providing such a conductor 20, it is possible to prevent the flow of hydrogen, water, etc. It is possible to suppress the diffusion of impurities into the conductor 21. Furthermore, Prevents the diffusion of metal components contained in the conductive material 21, prevents oxidation of the conductive material 21, and prevents the conductive material 21 from being oxidized. In addition, the conductor 20 is formed by laminating layers. In this case, for example, titanium, tantalum, titanium nitride, or tantalum nitride may be used. In addition, when forming a film of tantalum nitride as the conductor 20, RTA (Rapid Thermal Atomic (RTA)) is performed after the film formation. Heat treatment may be performed using a thermal annealing device.

[0074] The conductor 20 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, the film formation of the conductor 20 can be performed by a method that provides good coverage. It is preferable to carry out the deposition by, for example, a collimated sputtering method, an MCVD method, or an ALD method. It is preferable to use the following.

[0075] Here, the collimated sputtering method involves placing a collimator between the target and the substrate. This allows for directional deposition. The sputtered particles pass through the collimator and reach the substrate. This allows for high aspect ratios. Since sputtered particles can easily reach the bottom of the opening 17ea, As described above, the inner walls of the openings 17ea and 17eb can be sufficiently formed. By forming the opening 17ea and the opening 17eb in a tapered shape, a film is sufficiently formed on the inner walls of the opening 17ea and the opening 17eb. It is possible.

[0076] Furthermore, by forming the conductor 20 by the ALD method, the conductor 20 can be well coated. The film can be formed with good adhesion, and the formation of pinholes or the like in the conductor 20 can be suppressed. By forming the conductor 20 in this manner, impurities such as hydrogen and water can pass through the conductor 20. It is possible to further suppress the diffusion of the metal ions into the conductor 21. For example, when the ALD method is used, When tantalum nitride is deposited as the conductor 20, pentakis(dimethylamino)tantalum is used. Ta (structural formula: Ta[N(CH3)2]5) can be used as a precursor.

[0077] The conductor 21 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Sodium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sodium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductor 2 may be used in a single layer or a multilayer structure containing one or more of tungsten and Zn. The film formation of 1 is performed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the conductor 21 is deposited so as to fill the opening 17e. Therefore, it is preferable to use the CVD method (particularly the MCVD method).

[0078] Next, the conductor 21, the conductor 20, the hard mask 16a, and the insulator 15b are subjected to a polishing process. Thus, the conductors 20a and 21a are formed in the openings 17f (FIG. 4(C)). (See (D).) Polishing processes include mechanical polishing, chemical polishing, and chemical mechanical polishing (Chemical Polishing). This can be achieved by performing a technique such as mechanical polishing (CMP). For example, by performing CMP processing, the insulator 15b, the upper and side surfaces of the conductors 21 and 20 are removed. The hard mask 16a is removed, and the insulator 15c, the conductor 21a, and the conductor 21b are removed. 20a can be formed.

[0079] Here, the opening 17f is located at the bottom and serves as a via hole, a contact hole, or the like. The opening 17fa functions as a groove for embedding wiring patterns, etc., located at the top. The opening 17fa can be seen as being made up of the insulator 13a and the opening 17fb. An opening 17fb is formed in the insulator 14b, and an opening 17fb is formed in the insulator 15c. The portion of the conductor 21a embedded in the opening 17fa functions as a plug, and the conductors 20a and The portion of the conductor 21a embedded in the opening 17fb functions as a wiring or the like.

[0080] The conductor 20a is preferably in contact with the insulator 14b at the edge of the opening 17fa. The body 20a contacts the insulator 14b at the rounded portion at the top of the opening 17fa, and The insulators 13a and 14b are connected to the tapered edge of the opening 17fa. It is more preferable that the upper surface of the insulating body 14b is in contact with the upper surface of the insulating body 14b. Furthermore, the conductor 20a contacts the inner wall of the opening 17fa of the insulator 13a, and the It is preferable that the opening 17fb is in contact with the inner wall of the opening 17fb.

[0081] As shown in this embodiment, the insulating film 10 functions as a via hole or a contact hole. and an opening 17eb which functions as a groove for embedding a wiring pattern or the like. After forming the opening 17e, the conductor 20 is deposited, forming the wiring of the conductor 20a. The part that functions as a seal and the part that functions as a plug are integrated together. For example, the conductor 20a is not interrupted near the boundary between the opening 17ea and the opening 17eb. Since the film is formed quickly, it can further improve the blocking function against hydrogen and water. In addition, when forming the wiring and plug using the single damascene method, the shape of the plug The formation of the conductive film and the formation of the wiring each require one conductor deposition and one polishing process such as CMP. However, in the method shown in this embodiment, the deposition of a conductor for forming wiring and plugs and the CMP process are performed. Since polishing processes such as grinding can be completed in one step, the process can be shortened.

[0082] Here, the semiconductor device described in this embodiment has a semiconductor substrate over which an oxide semiconductor is provided. The stacked insulator and the oxide semiconductor are disposed between the semiconductor substrate and the oxide semiconductor. and a conductor that functions as a wiring and a plug and is embedded in the opening formed in the insulating film. The semiconductor device described in this embodiment has a transistor formed using an oxide semiconductor. An element layer including the transistor is formed over an element layer including a semiconductor substrate. A transistor may be formed in an element layer including a semiconductor substrate. For example, an element layer including a capacitor element may be formed on an element layer including an oxide semiconductor. The semiconductor layer may be formed on an element layer including a semiconductor substrate and an element layer including an oxide semiconductor. It may be formed between.

[0083] In the semiconductor device having such a configuration, as shown in FIGS. 4(C) and 4(D), the insulator 14b The conductor 20a is in contact with the insulator 14b at the edge of the opening 17fa formed in the In other words, it is preferable to close the opening 17fa formed in the insulator 14b with the conductor 20a. It is preferable that the shape is

[0084] Here, the insulator 14b has a function of blocking the diffusion of hydrogen and water. Impurities such as hydrogen and water pass from the body 13a through the insulator 14b and reach the element layer including the oxide semiconductor. Furthermore, the conductor 20a can block the diffusion of hydrogen and water. The conductor 20a is provided so as to close the opening 17f of the insulator 14b. As a result, the oxygen passes through the conductor 21a at the opening 17f of the insulator 14b. This can prevent impurities such as hydrogen and water from diffusing into the element layer including the nitride semiconductor.

[0085] In this way, the semiconductor substrate and the oxide semiconductor are separated by the insulator 14b and the conductor 20a. By this, impurities such as hydrogen or water contained in the element layer including the semiconductor substrate can be isolated. The upper surface is electrically connected to the plug (conductor 21) or the via hole (opening 17fa) formed in the insulator 14b. This can prevent diffusion into the layer. In this case, hydrogen is used to terminate the dangling bonds of the silicon substrate, The amount of hydrogen contained in the element layer including the substrate is large, and hydrogen diffuses to the element layer including the oxide semiconductor. However, by using the structure described in this embodiment, This can prevent hydrogen from diffusing into the element layer.

[0086] As will be described in detail later, oxide semiconductors reduce impurities such as hydrogen and water and It is preferable to reduce the density and use an oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic. It is preferable that a transistor be formed using such an oxide semiconductor. The electrical characteristics of the sintered body can be stabilized. By using an oxide semiconductor, which is a In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor can be used. This can improve the reliability of the transistor.

[0087] The shapes of the wiring and plugs shown in this embodiment are not limited to those shown in FIGS. 4(C) and 4(D). The following shows wires and plugs with shapes different from those shown in Figures 4(C) and (D).

[0088] The shapes of the wiring and plug shown in FIG. 6(A) are different from those of the opening 17g and the opening 17f. The opening 17g is located at the bottom and is different from the shape shown in FIG. An opening of 17 ga that functions as a contact hole, etc., and a wiring pattern, etc., located at the top. It can be seen as consisting of an opening 17gb that functions as a groove into which the The opening 17ga is formed in the lower part of the insulator 13a and the insulator 14b, and the opening 17gb is formed in the insulator 15. c and the insulator 14b. The portions of the body 20a and the conductor 21a that function as wiring or the like are embedded in the upper part of the insulator 14b. Here, the inner wall of the opening formed in the insulator 14b is formed so as to be enclosed by the opening 17g. It is formed in a stepped shape by the inner wall of a and the inner wall of opening 17gb.

[0089] The shapes of the wiring and plug shown in FIG. 6(B) are different from those of the opening 17f in that the shape of the opening 17h is different from that of the opening 17f. The opening 17h is located at the bottom and is different from the shape shown in FIG. The opening of 17ha functions as a contact hole, etc., and the upper part is located on the wiring pattern. It can be seen as consisting of an opening 17hb that functions as a groove into which the The opening 17ha is formed in the lower part of the insulator 13a, and the opening 17hb is formed in the insulators 15c and 14b. and is formed on the upper part of the insulator 13a. Therefore, in the configuration shown in FIG. The portions of the conductor 20a and the conductor 21a that function as wiring or the like are embedded in the upper part of the insulator 13a. Here, the inner wall of the opening formed in the insulator 13a is formed so as to be parallel to the opening 17ha. It is formed in a stepped shape by the inner wall of the opening 17hb and the inner wall of the opening 17hb.

[0090] The shapes of the wiring and plug shown in FIG. 6(C) are different from those of the opening 17i and the opening 17f. The opening 17i is located at the bottom and is different from the shape shown in FIG. An opening 17ia that functions as a contact hole, etc., and a wiring pattern, etc., located at the top The opening 17ib functions as a groove for embedding the The opening 17ia is formed in the insulator 13a, and the opening 17ib is formed in the insulators 15c and 14b. Therefore, in the configuration shown in FIG. 6(C), the arrangement of the conductor 20a and the conductor 21a The portion that functions as a wire or the like is provided so as to be embedded in the insulator 14b. The inner wall of the opening of the edge body 14b is formed in a gentle tapered shape.

[0091] The shapes of the wiring and plug shown in FIG. 7(A) are different from those of the opening 17f in that the opening 17j has a different shape. The opening 17j is located at the bottom and is different from the shape shown in FIG. An opening 17ja that functions as a contact hole, etc., and a wiring pattern, etc., located at the top It can be seen that the opening 17jb functions as a groove for embedding the The opening 17ja is formed in the insulator 13a and the insulator 14b, and the opening 17jb is formed in the insulator 15c. Therefore, in the configuration shown in FIG. 7(A), the arrangement of the conductor 20a and the conductor 21a The portion that functions as a wire or the like is provided so as to be embedded in the insulator 15c. The inner wall of the opening 17ja formed in the insulator 14b and the edge 13a is substantially perpendicular to the conductor 12. The inner wall of the opening 17jb formed in the insulator 15c is directly connected to the insulator 14b. In addition, when the inner wall of the opening is provided substantially perpendicularly, In order to form the conductor 20a on the inner wall with a sufficient thickness, the conductor 20 is formed by using an ALD method or the like. It is preferable to form a film of

[0092] In the shapes of the wiring and plug shown in FIGS. 7(B) and (C), the shape of the opening 17k is different from that of the opening 17j. 7(A) in that respect. The opening 17k is located at the bottom, and the via hole Or an opening 17ka that functions as a contact hole or the like, and a wiring pattern located at the top. It can be seen as consisting of a 17kb opening that functions as a groove for embedding the The shape of the wiring and plug shown in Figure 7(B)(C) is such that the maximum width of the opening 17k is 1. This is approximately equal to the minimum width of 7 kb. For example, the X1 of the 17 kb aperture shown in Figure 7(B)(C) The width in the -X2 direction is approximately equal to the width in the X1-X2 direction of the opening 17kb. This reduces the area occupied by the wiring. For example, the width of the opening 17a in the hard mask 16 in the X1-X2 direction shown in FIGS. 1(A) and 1(B) and The width of the opening 17b in the X1-X2 direction of the resist mask 18a shown in FIG. You can set it to match.

[0093] The configuration of the wiring and plug shown in FIG. 8(A)(B) is such that the conductor 24 is connected to the conductor 21a and the conductor 4(C)(D) in that it is provided on 20a. The conductor 24 may be made of any conductor that can be used for the conductor 20a, for example, nitride. By using such a structure, the conductor 21a can be The hydrogen-impermeable conductor 20a and the conductor 24 can be wrapped around the hydrogen-impermeable conductor 20a. By adopting this structure, hydrogen diffused from the conductor 12, the insulator 13a, etc. can be more effectively This blocks hydrogen from penetrating into the upper layers through the conductor 21a.

[0094] The conductor 24 may be patterned using lithography or the like, or may be formed by insulating Alternatively, an insulator having an opening similar to that of the body 15c may be provided and embedded in the opening.

[0095] The method for manufacturing the wiring and plug shown in this embodiment is not limited to the above method. A different method for fabricating wiring and plugs from the above method is shown below.

[0096] A method for fabricating wiring and plugs that is different from the above method will be described below with reference to FIGS. 9 to 12. The process from the step shown in FIG. 12(A)(B) onwards is the same as that shown in FIG. 3(A)(B). Just continue with the process.

[0097] First, a conductor 12 is formed in the same manner as in the above process, and an insulator 13 is formed on the conductor 12. Then, an insulator 14 is formed on the insulator 13, and an insulator 15 is formed on the insulator 14. do.

[0098] Next, a hard mask is formed on the insulator 15 in the same manner as in the formation of the material for the hard mask 16. A mask material 16b is formed as a film (see FIGS. 9(A) and 9(B)). 1B) is a cross-sectional view corresponding to the dashed line X1-X2 shown in FIG. It is shown corresponding to the dashed dotted line X1-X2.

[0099] Next, a resist mask 18b having an opening 17m is formed on the hard mask material 16b. The resist mask 18b is formed in the same manner as the resist mask 18a. The description can be taken into consideration.

[0100] Here, the opening 17m is an opening 17fa to be formed in a later step, that is, a via hole or a capacitor. Therefore, the top surface shape of the 17m opening is a via hole or contact hole. It will be compatible with contact holes.

[0101] The opening 17m has a circular top surface, but is not limited to this. For example, The upper surface may be elliptical, triangular, rectangular or other polygonal shape. In the case of a corner shape, the corners may be rounded.

[0102] Next, the hard mask material 16b is etched using the resist mask 18b to form an opening. A hard mask 16c having a thickness of 17n is formed (see FIGS. 9(C) and (D)). Etching is performed at opening 17n until the upper surface of insulator 15 is exposed. For etching, it is preferable to use dry etching. Various types of materials can be used.

[0103] Next, the insulator 15 is etched using the resist mask 18b to form an opening 17p. In this case, the upper surface of the insulator 14 is exposed in the opening 17p. It is preferable to use dry etching for the etching. The dry etching device may be the same as that described above.

[0104] Next, the insulator 14 is etched using the resist mask 18b to form an opening 17q. Insulator 14a is formed (see FIGS. 10(A) and 10(B)). The etching is continued until the upper surface of the insulator 13 is exposed. It is preferable to use a dry etching apparatus similar to that described above. It is possible.

[0105] Next, the resist mask 18b is removed (see FIGS. 10(C) and 10(D)). The removal of the resist mask 18b can be performed in the same manner as described above for removing the resist mask 18a. .

[0106] Next, a resist mask 26a having an opening 17r is formed on the hard mask 16c. The formation of the resist mask 26a is the same as that of the resist mask 18a. When the opening 17r is formed, the resist 26b is formed in the opening 17r. q and opening 17p.

[0107] Here, the opening 17r is an opening 17fb to be formed in a later step, that is, an opening to fill a wiring pattern. Therefore, the top surface shape of the opening 17r corresponds to the groove in which the wiring pattern is embedded. The opening 17q corresponding to the via hole or contact hole is It is preferable that the wiring pattern is formed in an opening 17r corresponding to the groove in which the wiring pattern is to be embedded. In this case, the minimum width of the opening 17r is equal to or greater than the maximum width of the opening 17q. The width of the opening 17r in the X1-X2 direction shown in FIGS. 11(A) and 11(B) is The width of the opening 17q in the X1-X2 direction is larger than that of the via hole 17q. In this case, the contact holes can be formed with a margin relative to the grooves of the wiring pattern. Cut.

[0108] Next, the hard mask 16c is etched using the resist mask 26a to form an opening 17. A hard mask 16d having an opening s is formed (see FIGS. 12(A) and 12(B)). In 17s, etching is performed until the upper surface of the insulator 15a is exposed. For etching, it is preferable to use dry etching. Various types of materials can be used.

[0109] Next, the resist mask 26a is removed. The description of removing the mask 18a can be referred to. If the resist mask 26a remains in the opening 17p, the resist mask 26a is removed at the same time. It is preferable to remove the resist 26b.

[0110] After removing the resist mask 18b, the openings 17q and 17p are filled with a filler. The filler may be removed at the same time as the resist mask 26a is removed. Any material that can be removed by dry etching such as the above-mentioned ashing may be used. Such fillers can be, for example, amorphous fillers. A carbon-based material may be used.

[0111] By removing the resist mask 26a, the shape shown in FIGS. 3(A) and 3(B) is obtained. The following steps are performed to form wiring and plugs in accordance with the steps shown in FIG. 3(C)(D) and subsequent steps. .

[0112] <Structure of Transistor Having Oxide Semiconductor Film> 13A and 13B show transistors formed in an element layer including an oxide semiconductor. 13A shows an example of the configuration of the transistor 60a. 13B is a cross-sectional view corresponding to the channel width direction A3 of the transistor 60a. The channel length direction of the transistor is the direction parallel to the substrate. In the same plane, the source (source region or source electrode) and the drain (drain region or The channel width direction is the direction in which carriers move between the source and drain electrodes. It means a direction perpendicular to the channel length direction in a plane parallel to the substrate.

[0113] In the cross-sectional views of FIGS. 13(A) and 13(B), the patterned conductive Although the edges of electric conductors, semiconductors, insulators, etc. are shown at right angles in the drawings, The semiconductor device shown in FIG. 1 is not limited to this, and the end portions may be rounded.

[0114] The transistor 60a includes a conductor 62a, a conductor 62b, an insulator 65, and an insulator 63. , an insulator 64, an insulator 66a, a semiconductor 66b, a conductor 68a, and a conductor 68b. , insulator 66c, insulator 72, and conductor 74. and conductor 62b serves as the back gate of transistor 60a, and insulator 65, insulating The body 63 and the insulator 64 serve as gate insulating films for the back gate of the transistor 60a. In addition, the conductor 68a and the conductor 68b are connected to the source or drain of the transistor 60a. The insulator 72 also functions as a gate insulating film for the transistor 60a. However, conductor 74 functions as the gate of transistor 60a.

[0115] As will be described later in detail, when the insulators 66a and 66c are used alone, In some cases, a material that can function as a semiconductor or an insulator is used. However, when a transistor is formed by stacking the semiconductor 66b, electrons pass through the semiconductor 66b and the semiconductor 66c. The vicinity of the interface between the conductor 66b and the insulator 66a, and the vicinity of the interface between the semiconductor 66b and the insulator 66c Therefore, the insulators 66a and 66c do not function as the channel of the transistor. Therefore, in this specification and the like, the insulators 66a and 66c are referred to as Instead of describing them as conductors and semiconductors, they will be described as insulators or oxide insulators.

[0116] In this embodiment and the like, the term "insulator" can be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be rephrased as "semiconductor film" or "semiconductor layer."

[0117] Below the transistor 60a, an insulator 67 having an opening is provided on the insulator 61. A conductor 62a is provided in the opening, and a conductor 62b is provided on the conductor 62a. At least a portion of the conductor 62a and the conductor 62b is covered with an insulator 66. a, semiconductor 66b, and insulator 66c overlap. The conductors 62a and 62b functioning as gates are the same as the wiring and plugs described above. The functional conductors 21a and 20a can be fabricated in parallel. The conductor 61 is connected to the insulator 14b, the insulator 67 is connected to the insulator 15c, and the conductor 62a is connected to the conductor 20a. The conductor 62b corresponds to the conductor 21a.

[0118] The upper surfaces of the conductors 62a and 62b are in contact with the conductors 62a and 62b. An insulator 65 is provided to cover the insulating material 63. An insulator 64 is provided on the body 63 .

[0119] Here, one end of the conductor 62a and the conductor 62b in the channel length direction is a part of the conductor 68a. The other ends of the conductors 62a and 62b in the channel length direction overlap with a part of the conductor 68b. By providing the conductors 62a and 62b in this manner, , the region between the conductors 68a and 68b of the semiconductor 66b, i.e., the channel of the semiconductor 66b. The conductive material 62a and the conductive material 62b can sufficiently cover the conductive material forming area. Conductor 62a and conductor 62b provide more effective control of the threshold voltage of transistor 60a. can be done.

[0120] An insulator 66a is provided on the insulator 64, and a conductive material is connected to at least a part of the upper surface of the insulator 66a. 13(A) and 13(B), the insulator 66 The insulator 66a and the semiconductor 66b are formed so that the ends of the insulator 66a and the semiconductor 66b are approximately aligned. However, the structure of the semiconductor device described in this embodiment mode is not limited to this.

[0121] A conductor 68a and a conductor 68b are formed in contact with at least a part of the upper surface of the semiconductor 66b. The conductor 68a and the conductor 68b are formed apart from each other, as shown in FIG. It is preferable that the electrodes are formed facing each other with the conductor 74 interposed therebetween.

[0122] An insulator 66c is provided in contact with at least a portion of the upper surface of the semiconductor 66b. c is formed so as to cover a part of the upper surface of the conductor 68a and a part of the upper surface of the conductor 68b. It is preferable that the conductor 68a and the conductor 68b contact a part of the upper surface of the semiconductor 66b. stomach.

[0123] An insulator 72 is provided on the insulator 66c. The insulator 72 is provided between the conductor 68a and the conductor 68b. It is preferable that the insulating member 66c contacts a part of the upper surface of the insulating member 66c between the insulating member 66c and the insulating member 66b.

[0124] A conductor 74 is provided on the insulator 72. The conductor 74 is made up of the conductors 68a and 68b. It is preferable that the insulator 72 contacts a part of the upper surface thereof between the points b.

[0125] An insulator 79 is provided to cover the conductor 74. However, the insulator 79 is not necessarily provided. There is no need to

[0126] However, the transistor 60a is not limited to the configuration shown in FIGS. 13(A) and 13(B). For example, the side surfaces of the insulator 66c, the insulator 72, and the conductor 74 in the A1-A2 direction are aligned. For example, the insulator 66c and / or the insulator 72 may be provided so as to covers the insulator 66a, the semiconductor 66b, the conductor 68a and the conductor 68b, and It may be configured so as to be in contact with the upper surface.

[0127] The conductor 74 is made up of the insulators 72, 66c, 64, 63, and 66b. 5, etc., may be connected to the conductor 62b through an opening formed therein.

[0128] An insulator 77 is provided on the insulator 64, the conductor 68a, the conductor 68b, and the conductor 74. Furthermore, an insulator 78 is provided on the insulator 77.

[0129] <Oxide semiconductor> The oxide semiconductor used for the semiconductor 66b will be described below.

[0130] The oxide semiconductor preferably contains at least indium or zinc. It is preferable that the alloy contains aluminum and zinc. It is preferable that the alloy contains boron, silicon, or yttrium. , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from aluminum, neodymium, hafnium, tantalum, tungsten, or magnesium. The composition may contain one or more of the above-mentioned compounds.

[0131] Here, a case where the oxide semiconductor contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. The elements that can be used for M include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum However, the element M may be a combination of multiple of the above elements. There are cases where it is acceptable to combine them.

[0132] First, with reference to FIGS. 26(A), 26(B), and 26(C), the oxidation method according to the present invention will be explained. The preferred range of the atomic ratio of indium, element M, and zinc contained in the compound semiconductor will be explained. Note that the atomic ratio of oxygen is not shown in FIG. 26. The atomic ratios of indium, element M, and zinc are expressed as [In], [M], and and [Zn].

[0133] In Figures 26(A), 26(B), and 26(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3 is n]:[M]:[Zn]=(1+α):(1-α):4, and The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0134] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β, the line where [In ]:[M]:[Zn]=1:3:β, the atomic ratio is [In]:[M]:[Zn ]=1:4:β, and the atomic ratio of [In]:[M]:[Zn]=2:1:β. The line where the atomic ratio is [In]:[M]:[Zn]=5:1:β Represents in.

[0135] In addition, the atomic ratio of [In]:[M]:[Zn]=0:2:1 shown in FIG. 26 or Oxide semiconductors with values ​​close to this range tend to have a spinel-type crystal structure.

[0136] 26A and 26B show the in-situ structure of the oxide semiconductor of one embodiment of the present invention. 1 shows an example of a preferred range of the atomic ratio of sodium, the element M, and zinc.

[0137] As an example, FIG. 27 shows InMZn where [In]:[M]:[Zn]=1:1:1. Figure 27 shows the crystal structure of InMZ when observed from a direction parallel to the b axis. The crystal structure of nO4 is shown in FIG. 27. The metal element in the (Zn) layer represents element M or zinc. The ratio of lead is equal. The element M and zinc are interchangeable and the arrangement is random. do.

[0138] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 27. The layer containing element M, zinc, and oxygen (hereinafter referred to as the In layer) is 1. The (M,Zn) layer containing oxygen becomes 2.

[0139] In addition, indium and element M can be substituted for each other. Therefore, the element of the (M, Zn) layer The element M can be replaced with indium, and the layer can be expressed as (In,M,Zn). In this case, In It has a layered structure with one layer and two (In, M, Zn) layers.

[0140] In the oxide semiconductor with the atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is In other words, the (M,Zn) layer is three. When [Zn] is large, when the oxide semiconductor crystallizes, the (M,Zn) ) layer proportion increases.

[0141] However, in the oxide semiconductor, the number of (M, Zn) layers is non-uniform for one In layer. When the number of layers is one, the number of layers is an integer. For example, when [In]:[M]:[Zn]=1:1:1.5 , a layered structure with one In layer and two (M,Zn) layers, and a layered structure with three (M,Zn) layers. In some cases, the layer structure may be a mixture of a layer structure and a layer structure.

[0142] For example, when forming an oxide semiconductor film using a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the target The [Zn] of the film may be smaller than the [Zn] of the substrate.

[0143] Furthermore, multiple phases may coexist in an oxide semiconductor (such as two-phase coexistence or three-phase coexistence). For example, at an atomic ratio close to the atomic ratio of [In]:[M]:[Zn]=0:2:1, In [In], two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist. At atomic ratios close to the atomic ratio of [M]:[Zn]=1:0:0, Two phases, a crystalline structure with a layered structure and a crystalline structure with a crystalline structure with a layered structure, tend to coexist. When these coexist, grain boundaries form between different crystal structures. may be formed.

[0144] In addition, by increasing the indium content, the carrier mobility (electron transfer rate) of the oxide semiconductor can be improved. This is because the oxide semiconductor containing indium, element M, and zinc can In conductors, the s orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the indium content, the overlapping area of ​​the s orbitals becomes larger. Oxide semiconductors with a high indium content have a higher carrier mobility than oxide semiconductors with a low indium content. This is because the

[0145] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0, and In the atomic ratios near this value (for example, region C shown in FIG. 26(C)), the insulating properties become high. .

[0146] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 26(A), which is likely to form a layered structure with a good atomic ratio. It's nice.

[0147] In addition, in the region B shown in FIG. 26(B), [In]:[M]:[Zn]=4:2:3 to 4 .1 and its neighboring values. For example, the atomic ratio [In]:[M ]:[Zn]=5:3:4. Oxide semiconductors having the atomic ratio shown in region B is an excellent oxide semiconductor having particularly high crystallinity and high carrier mobility.

[0148] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the forming conditions, a layered structure may or may not be formed. Therefore, the illustrated region is a region showing the atomic ratio in which the oxide semiconductor has a layered structure, and the region The boundaries between areas A and C are not strict.

[0149] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0150] Note that by using the oxide semiconductor in a transistor, carrier scattering at grain boundaries and other problems can be prevented. This allows for a reduction in the field-effect mobility of transistors. Furthermore, a highly reliable transistor can be realized.

[0151] In addition, an oxide semiconductor with low carrier density is preferably used for the transistor. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3Less than 1x1 0 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0152] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a carrier generation source. In addition, the carrier density can be reduced because the Intrinsic oxide semiconductors have a low density of defect states, and therefore a low density of trap states. There are cases where this happens.

[0153] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel region is formed in a thin oxide semiconductor may have unstable electrical characteristics. There is a match.

[0154] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, it is effective to reduce It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0155] Here, the influence of each impurity in an oxide semiconductor will be described.

[0156] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, they are oxidized. Defect levels are formed in semiconductors, which is why defects in silicon and carbon in oxide semiconductors The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0157] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, the defect level is Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, it is preferable to use an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0158] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor Therefore, the oxide semiconductor is likely to have a normally-on characteristic. For example, the nitrogen concentration in the oxide semiconductor is In SIMS, 5 × 10 19 atoms / cm 3 Less than 5 x 10 18 at oms / cm3 Less than 1×10, more preferably 18 atoms / cm 3 Below are some more preferred Or 5 x 10 17 atoms / cm 3 The following applies.

[0159] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, resulting in the formation of chiral ions. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the amount of Si in the oxide semiconductor is as small as possible. The hydrogen concentration obtained by MS was 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Less than.

[0160] By using an oxide semiconductor with sufficiently reduced impurities in a channel formation region of a transistor, This allows stable electrical properties to be imparted. The intrinsic oxide semiconductor has a significantly small off-state current and a channel width W of 1×10 6 μm Even if the channel length L of the device is 10 μm, the voltage between the source electrode and the drain electrode (drain The off-state current is measured in the range of 1V to 10V. below the measurement limit, i.e., 1×10 -13 It can achieve a characteristic of A or below.

[0161] The following describes a case where a semiconductor 66b, which is an oxide semiconductor, is formed in a two-layer structure or a three-layer structure in a transistor 60a. The layer structure is described below. The band diagram of the insulator in contact with the stacked structure and the band diagram of the semiconductor 66b and the insulator 66c in contact with the stacked structure are shown in Fig. The band diagram of the insulator will be explained with reference to FIG.

[0162] FIG. 28(A) shows an insulator I1, an insulator 66a (S1), a semiconductor 66b (S2), an insulator 66c(S3) and an example of a band diagram in the film thickness direction of a stacked structure having an insulator I2. FIG. 28(B) shows an insulator I1, a semiconductor 66b (S2), an insulator 66c (S3), and 1 is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I1 and an insulator I2. For ease of understanding, the insulator I1, the insulator 66a, the semiconductor 66b, the insulator 66c, and the insulator The energy level (Ec) at the bottom of the conduction band of the insulator I2 is shown.

[0163] The insulators 66a and 66c have a lower energy level at the bottom of the conduction band than the semiconductor 66b. The energy level is close to the empty level, typically the energy level at the bottom of the conduction band of the semiconductor 66b and the energy level at the bottom of the insulator 66 a, the difference between the energy level of the insulator 66c and the bottom of the conduction band is 0.15 eV or more, or 0 It is preferable that the insulator is 0.5 eV or more and 2 eV or less, or 1 eV or less. The electron affinity of the semiconductor 66b is greater than that of the insulator 66a and the insulator 66c. The difference between the electron affinity of the insulator 66a and the insulator 66c and the electron affinity of the semiconductor 66b is 0.1 It is preferably 5 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less. I wish.

[0164] As shown in FIGS. 28(A) and 28(B), an insulator 66a, a semiconductor 66b, an insulating In the region 66c, the energy level of the conduction band minimum changes gradually. It can also be said that the band diagram is a continuous change or a continuous junction. The interface between the insulator 66a and the semiconductor 66b, or the interface between the semiconductor 66b and the insulator 66c It is preferable to reduce the defect level density of the mixed layer formed on the surface.

[0165] Specifically, the insulator 66a and the semiconductor 66b, and the semiconductor 66b and the insulator 66c are connected to each other. By having a common element (main component) in both layers, a mixed layer with a low defect level density can be formed. For example, when the semiconductor 66b is an In-Ga-Zn oxide semiconductor, the insulator 66 a, as the insulator 66c, an In-Ga-Zn oxide semiconductor, a Ga-Zn oxide semiconductor, an oxide Gallium nitride or the like may be used.

[0166] At this time, the main path of the carriers is the semiconductor 66b. and the interface between the semiconductor 66b and the insulator 66c. Therefore, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained. can be.

[0167] However, when a high gate voltage is applied, the insulator 66a and the semiconductor 66b are in the vicinity of the interface, and Current may also flow near the interface between the insulator 66c and the semiconductor 66b.

[0168] As described above, when the insulators 66a and 66c are used alone, they are conductors, semiconductors, and the like. However, semiconductor 66b is made of a material that can function as an insulator. When a transistor is formed by stacking these, electrons flow through the semiconductor 66b, the semiconductor 66b and the insulator The current flows near the interface between the semiconductor 66b and the insulator 66c, and flows through the insulator 66a. The insulator 66c has a region that does not function as the channel of the transistor. Therefore, in this specification and the like, the insulators 66a and 66c are not described as semiconductors. The insulator 66a and the insulator 66 are referred to as an insulator or an oxide insulator. The reason why c is described as an insulator or oxide insulator is simply because it is a transistor compared to semiconductor 66b. Since the resistor has a function similar to that of an insulator, the insulator 66a or the insulator 66c In some cases, a material that can be used for the semiconductor 66b is used.

[0169] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the insulating layer 66c, the trap level can be kept away from the semiconductor 66b. This configuration allows the threshold voltage of the transistor to shift in the positive direction. It can be prevented.

[0170] The insulators 66a and 66c are made of a material having a sufficiently low conductivity compared to the semiconductor 66b. At this time, the semiconductor 66b, the interface between the semiconductor 66b and the insulator 66a, and the semiconductor The interface between the insulator 66b and the insulator 66c mainly functions as a channel region. 6a, and the insulator 66c has the atomic number shown in region C where the insulating property is high in FIG. 26(C). The region C shown in FIG. 26C is an oxide semiconductor having a ratio of [In]:[M ]:[Zn]=0:1:0 or a value close to that.

[0171] In particular, when an oxide semiconductor having the atomic ratio shown in region A is used for the semiconductor 66b, the insulator The insulator 66a and the insulator 66c are made of an acid having an [M] / [In] ratio of 1 or more, preferably 2 or more. It is preferable to use a compound semiconductor as the insulator 66c. [M] / ([Zn]+[In]) is 1 or more. It is preferable that:

[0172] The insulator 66a, the semiconductor 66b, and the insulator 66c are formed by sputtering, CVD, or M The film can be formed using the BE method, PLD method, ALD method, or the like.

[0173] In addition, the insulator 66a, the semiconductor 66b, and the insulator 66c are subjected to a substrate heating process during film formation. Alternatively, it is preferable to perform heat treatment after the film formation. By performing such heat treatment, the insulating The water or hydrogen contained in the body 66a, the semiconductor 66b, the insulator 66c, etc. is further reduced. In addition, excess oxygen can be supplied to the insulator 66a, the semiconductor 66b, and the insulator 66c. The heat treatment is carried out at a temperature of 250°C to 650°C, preferably 3 The heating temperature is preferably 350°C or higher and 400°C or lower. Heat treatment is carried out in an inert gas atmosphere or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 1 The heat treatment is carried out in an atmosphere containing 0% or more of HCl. The heat treatment may be carried out under reduced pressure. After heat treatment in an inert gas atmosphere, oxidizing gas was added at 10ppm to compensate for the desorbed oxygen. The heat treatment may be carried out in an atmosphere containing at least m, at least 1%, or at least 10% of An RTA device using lamp heating can also be used. Heat treatment using an RTA device is performed in a furnace and This takes less time than conventional methods, making it effective for increasing productivity.

[0174] The conductor 62a serving as the back gate of the transistor, the plug and the wiring shown in FIG. When tantalum nitride is used for the conductor 20a, the heat treatment temperature is set to 350° C. or higher. The temperature range is 410°C or less, preferably 370°C or more and 400°C or less. By carrying out the heat treatment at this temperature, it is possible to suppress the release of hydrogen from the tantalum nitride film.

[0175] In addition, the area in contact with the conductor 68a or the conductor 68b, such as the semiconductor 66b or the insulator 66c, A low resistance region may be formed in the conductive region where the semiconductor 66b is in contact. Oxygen is extracted by the conductor 68a or the conductor 68b, or oxygen is extracted by the conductor 68a or the conductor 68 The conductive material contained in b bonds with the elements in the semiconductor 66b. By forming such a low resistance region, the conductor 68a or the conductor 68b and the semiconductor 66b Since the contact resistance with the transistor 60a can be reduced, the on-current of the transistor 60a can be increased. It is possible.

[0176] In addition, the semiconductor 66b has a conductor 68a or a conductor 68b between the conductors 68a and 68b. conductors 68a and 68b may have a region that is thinner than the region that overlaps them. When forming the conductor 68b, a part of the upper surface of the semiconductor 66b is removed. On the upper surface of the semiconductor 66b, a film of a conductor that becomes the conductor 68a and the conductor 68b is formed. In this case, a region with low resistance similar to the low resistance region may be formed. By removing the area located between the conductors 68a and 68b on the top surface of the conductor 66b, This prevents a channel from being formed in a low-resistance region on the top surface of the semiconductor 66b. do.

[0177] The above-described three-layer structure of the insulator 66a, the semiconductor 66b, and the insulator 66c is an example. For example, a two-layer structure may be used in which either the insulator 66a or the insulator 66c is not provided. Alternatively, a single layer structure may be used in which neither the insulator 66a nor the insulator 66c is provided. Alternatively, the insulator, semiconductor or Alternatively, the layer structure may be an n-layer structure (n is an integer of 4 or more) having any of the following conductors:

[0178] <Insulators, conductors> The components of the transistor 60a other than the semiconductor will be described in detail below.

[0179] The insulator 61 is made of an insulator having a function of blocking hydrogen or water. The hydrogen and water in the insulator provided near the semiconductor 66b and the insulator 66c are mixed with the oxide semiconductor. Insulator 66a, semiconductor 66b, and insulator 66c function as carriers. This may result in a decrease in the reliability of the transistor 60a. When silicon or the like is used for the semiconductor substrate 91, the dangling bonds of the semiconductor substrate are Since hydrogen is used for termination, the hydrogen can be used in a transistor including an oxide semiconductor. Insulators 6 that have the function of blocking hydrogen or water are used to deal with this. By providing the insulating layer 1, hydrogen or water can be diffused from the lower layer of the transistor having an oxide semiconductor. This can suppress the generation of oxide semiconductor particles, thereby improving the reliability of the transistor including the oxide semiconductor. The insulator 61 is preferably less permeable to hydrogen or water than the insulator 65 or the insulator 64. It's nice.

[0180] It is also preferable that the insulator 61 has a function of blocking oxygen. By blocking oxygen diffusing from the insulator 64, the insulator 66a and the semiconductor Oxygen can be effectively supplied to the conductor 66b and the insulator 66c.

[0181] The insulator 61 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride or the like can be used. By using these as the insulator 61, It can function as an insulating film that blocks the diffusion of oxygen, hydrogen, or water. The insulator 61 may be made of, for example, silicon nitride or silicon nitride oxide. By using these as the insulator 61, the diffusion of hydrogen and water can be blocked. The insulator 61 can function as an insulating film that exhibits the effect. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0182] The insulator 67 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, The insulator 67 may be formed by a sputtering method, a CVD method, or the like. The method can be carried out by using a method such as MBE, PLD, or ALD.

[0183] At least a portion of the conductor 62a and the conductor 62b is sandwiched between the conductor 68a and the conductor 68b. It is preferable that the conductor 62a and the semiconductor 66b overlap in the area where the conductor 62a and the semiconductor 66b are included. b functions as the back gate of the transistor 60a. The conductor 62b is provided to control the threshold voltage of the transistor 60a. By controlling the threshold voltage, the gate (conducting When the voltage applied to the transistor (74) is low, for example, when the applied voltage is below 0 V, This prevents the transistor 60a from being turned on. This makes it easier to shift the thermal characteristics more in the normally-off direction.

[0184] Furthermore, the conductors 62a and 62b functioning as back gates are supplied with a predetermined potential. For example, the conductor 62a and the conductor 62b may be connected to a wiring or terminal to which the conductor 62 is supplied. b may be connected to a wiring to which a constant potential is supplied. The constant potential may be a high power supply potential or , and may be a low power supply potential such as ground potential.

[0185] The conductor 62a may be made of any conductor that can be used for the conductor 20. The conductor 62b may be made of any conductor that can be used for the conductor 21.

[0186] The insulator 65 is provided to cover the conductor 62a and the conductor 62b. An insulator similar to the insulator 64 or the insulator 72 described below can be used.

[0187] The insulator 63 is provided to cover the insulator 65. The insulator 63 blocks oxygen. By providing such an insulator 63, it is preferable that the insulator 64 This prevents the conductors 62a and 62b from extracting oxygen. By effectively supplying oxygen from the insulator 64 to the insulator 66a, the semiconductor 66b, and the insulator 66c, In addition, by increasing the covering property of the insulator 63, it is possible to draw more from the insulator 64. The amount of oxygen removed is further reduced, and the insulator 64 is divided into the insulator 66a, the semiconductor 66b, and the insulator 66c. This allows oxygen to be supplied more effectively to the

[0188] The insulator 63 may be boron, aluminum, silicon, scandium, titanium, or gallium. Sm, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium The oxide or nitride containing niobium or thallium is preferably hafnium oxide. The insulator 63 is formed by a sputtering method, a C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0189] In the insulators 65, 63, and 64, the insulator 63 forms an electron capture region. It is preferable that the insulators 65 and 64 have a function of suppressing electron emission. When the electrons are trapped in the insulator 63, they behave like fixed negative charges. 63 functions as a floating gate.

[0190] The insulator 64 preferably has a small amount of water or hydrogen contained in the film. The insulator 64 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Nitride, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, di a single layer of an insulator containing zinc, lanthanum, neodymium, hafnium or tantalum; For example, the insulator 64 may be made of aluminum oxide, magnesium oxide, or the like. Nesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gas oxide Sodium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Neodymium oxide, hafnium oxide or tantalum oxide may be used. Preferably, silicon oxide is used. The insulator 64 is formed by a sputtering method, a C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0191] Also, the insulator 64 is preferably an insulator having excess oxygen. By providing 64, the insulator 64 is connected to the insulator 66a, the semiconductor 66b, and the insulator 66c. Oxygen can be supplied to the insulator 66a, which is an oxide semiconductor, and the semiconductor This reduces oxygen deficiencies that can cause defects in the insulating layer 66b and the insulating layer 66c. The insulator 66a, the semiconductor 66b, and the insulator 66c are made of an oxide having a low defect level density and stable properties. The semiconductor may be a nitride semiconductor.

[0192] In this specification and the like, excess oxygen refers to oxygen contained in excess of the stoichiometric composition. Alternatively, the excess oxygen refers to oxygen that is released by heating, for example. This refers to oxygen released from a film or layer. Excess oxygen may be released, for example, by moving inside the film or layer. The movement of excess oxygen can occur between atoms in the film or layer, or between oxygen atoms that make up the film or layer. In some cases, the two move in a domino effect, replacing each other.

[0193] The insulator 64 having excess oxygen has a thermal desorption spectroscopy (TDS) analysis of 100 Desorption of oxygen molecules occurs in the surface temperature range of ℃ to 700℃ or 100℃ to 500℃. The separation is 1.0 x 10 14 molecules / cm 2 Over 1.0 x 10 16 molecu les / cm 2 or less, more preferably 1.0 × 10 15 molecules / cm 2 Below Upper 5.0×10 15 molecules / cm 2 The following is the result.

[0194] Regarding the method for measuring the amount of released molecules using TDS analysis, the amount of released oxygen is as follows: will be explained.

[0195] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated by the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can be calculated.

[0196] For example, the TDS analysis results of a silicon substrate containing a specified density of hydrogen as a standard sample, and From the TDS analysis results of the measurement sample, the amount of oxygen molecules released from the measurement sample (N O2 ) is shown below Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis can be calculated using the formula: We assume that all of the carbon atoms are derived from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but It is not considered here as it is unlikely. Also, the mass number of the isotope of the oxygen atom is 17. The existence of oxygen atoms with mass number 18 and oxygen molecules with mass number 18 in nature is also Not considered as the ratio is extremely small.

[0197] N O2 =N H2 / S H2 ×S O2 ×α

[0198] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is the standard This is the integrated value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. Details of the above formula For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. Measurements are made using a silicon substrate containing a fixed amount of hydrogen atoms.

[0199] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The atomic ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, evaluating the amount of released oxygen molecules can be used to estimate the amount of released oxygen atoms. It is also possible to estimate.

[0200] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount of offspring released.

[0201] Alternatively, insulators that release oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (E In SR (Electron Spin Resonance), the g value is around 2.01. It may also have an asymmetric signal.

[0202] The insulator 64 or the insulator 63 has a function of preventing the diffusion of impurities from the lower layer. That's fine.

[0203] As mentioned above, it is preferable that the upper or lower surface of the semiconductor 66b is highly flat. Therefore, the top surface of the insulator 64 is subjected to a planarization process such as CMP to improve the flatness. That's fine.

[0204] Conductor 68a and conductor 68b are the source or drain electrodes of transistor 60a, respectively. It functions as one of the rain electrodes.

[0205] The conductors 68a and 68b may include, for example, boron, nitrogen, oxygen, fluorine, silicon, etc. Copper, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc , Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium, Silver, Indium, Conductors containing one or more of tin, tantalum, and tungsten are used in a single layer or multilayer. For example, when the conductor 68a and the conductor 68b have a laminated structure, tantalum nitride Alternatively, tungsten may be laminated on the conductor 68a. For example, the conductive material may be an alloy or compound, and may be a conductor containing aluminum, copper, and titanium. Conductors containing copper and manganese, Conductors containing indium, tin and oxygen Alternatively, a conductor containing titanium and nitrogen may be used. The film 8b is formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. This can be done using

[0206] The insulator 72 functions as a gate insulating film of the transistor 60a. The insulator 72 may be an insulator having excess oxygen, similar to the insulator 64. By this, oxygen is supplied from the insulator 72 to the insulator 66a, the semiconductor 66b, and the insulator 66c. It is possible.

[0207] The insulators 72 and 77 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, or magnesium. Nesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, Insulators containing yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum The insulators may be used in a single layer or in a laminated layer. For example, the insulators 72 and 77 may be , aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, silicon dioxide If lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide is used, The insulators 72 and 77 may be formed by sputtering, CVD, or MBE. Alternatively, it can be performed using a PLD method, an ALD method, or the like.

[0208] In addition, the insulator 77 is preferably an insulator having excess oxygen. By providing 77, the insulator 77 is connected to the insulator 66a, the semiconductor 66b, and the insulator 66c. Oxygen can be supplied to the insulator 66a, which is an oxide semiconductor, and the semiconductor This reduces oxygen deficiencies that can cause defects in the insulating layer 66b and the insulating layer 66c. The insulator 66a, the semiconductor 66b, and the insulator 66c are made of an oxide having a low defect level density and stable properties. The semiconductor may be a nitride semiconductor.

[0209] The insulator 77 having excess oxygen was analyzed by thermal desorption spectroscopy (TDS) and found to have a 100 Desorption of oxygen molecules occurs in the surface temperature range of ℃ to 700℃ or 100℃ to 500℃. The separation is 1.0 x 10 14 molecules / cm 2 Over 1.0 x 10 16 molecu les / cm 2 or less, more preferably 1.0 × 10 15 molecules / cm 2 Below Upper 5.0×10 15 molecules / cm 2 The following is the result.

[0210] Insulator 77 also contains hydrogen, water, and nitrogen oxides (NO x For example, nitric oxide, nitrogen dioxide, etc. It is preferable that the amount of impurities such as SiO 2 and SiO 2 is small. By using such an insulator 77, Impurities such as hydrogen, water, and nitrogen oxides are transported from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulating layer 66c. The diffusion of the ions into the semiconductor 66c is suppressed, and the semiconductor 66b has a low defect level density and stable characteristics. The oxide semiconductor may be an oxide semiconductor.

[0211] Here, the insulator 77 is subjected to TDS analysis in the surface temperature range of 200°C to 560°C. , the number of H2O molecules released is 3.80 × 10 15molecules / cm 2 The following is more preferred: Or 2.40 x 10 15 molecules / cm 2 The following is true. Also, the insulator 77 In TDS analysis, the amount of H2O molecules desorbed was 7% in the surface temperature range of 0°C to 400°C. .00×10 14 molecules / cm 2 It is more preferable that: TDS analysis of insulator 77 showed that the amount of desorbed NO2 molecules was 1.80 x 10 13 molecul es / cm 2 It is preferable that the following be true:

[0212] The conductor 74 functions as the gate electrode of the transistor 60a. Any conductor that can be used as the conductor 62b may be used.

[0213] Here, as shown in FIG. 13(B), the conductors 62a, 62b, and 74 The electric field of the semiconductor 66b can electrically surround the semiconductor 66b (the electric field generated by the conductor The structure of the transistor that electrically surrounds the semiconductor is called the surrounded c This is called the s-channel structure.) Therefore, the entire semiconductor 66b ( In the s-channel structure, the transistor is A large current can be passed between the source and drain of the transistor, and the current (on-state current) when the transistor is turned on is increased. It can be made easier.

[0214] In addition, when the transistor has an s-channel structure, the side surface of the semiconductor 66b is also A channel is formed. Therefore, the thicker the semiconductor 66b, the larger the channel region. That is, the thicker the semiconductor 66b, the higher the on-current of the transistor. In addition, the thicker the semiconductor 66b, the greater the proportion of the region with high carrier controllability. The threshold swing value can be reduced, for example, to 10 nm or more, preferably The semiconductor 66b has a region with a thickness of 20 nm or more, more preferably 30 nm or more. However, since this may decrease the productivity of semiconductor devices, for example, The semiconductor 66b may have a region of lower thickness.

[0215] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. Preferably, the transistor has a channel width of 20 nm or less. or 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has a region.

[0216] It is preferable that the insulator 79 be an insulator that can be used for the insulator 63. For example, For example, the insulator 79 may be gallium oxide or aluminum oxide formed by ALD. By providing such an insulator 79 to cover the conductor 74, the insulation The conductor 74 takes away excess oxygen supplied to the body 77, preventing the conductor 74 from being oxidized. This can be done.

[0217] The thickness of the insulator 78 may be, for example, 5 nm or more, or 20 nm or more. In addition, it is preferable that at least a portion of the insulator 78 be formed in contact with the upper surface of the insulator 77. It's nice.

[0218] The insulator 78 may be, for example, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium Insulators containing sulphur, lanthanum, neodymium, hafnium or tantalum, either in a single layer or The insulator 78 may be formed of oxygen, hydrogen, water, alkali metals, alkaline earth metals, or the like. It is preferable that the insulating material has the effect of blocking the above. Examples of such insulating materials include nitrogen. The nitride insulating film may be a silicon nitride or silicon oxynitride. Silicon, aluminum nitride, aluminum oxide nitride, etc. Alternatively, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of insulating films include aluminum oxide, aluminum oxynitride, gallium oxide, and oxynitride. Gallium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride The insulator 78 may be used as the insulator 66a or the insulator 66c. The insulator 78 may be formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0219] Here, the insulator 78 is preferably formed by sputtering. It is more preferable to carry out the sputtering method in an atmosphere containing By forming the insulating film 78, the surface of the insulating film 77 (insulating film 78) is simultaneously formed. Then, oxygen is added to the vicinity of the interface between the insulator 77 and the insulator 78. For example, sputtering Then, an aluminum oxide film can be formed on top of it using the ALD method. It is preferable to form a film of aluminum. By using the ALD method, the formation of pinholes Therefore, oxygen, hydrogen, water, alkali metals, alkaline earth metals in the insulator 78 can be suppressed. The effect of blocking the above can be further improved.

[0220] It is preferable to perform heat treatment during or after the formation of the insulator 78. By performing the heat treatment, the oxygen added to the insulator 77 is diffused, and the insulator 66a and the semiconductor The oxygen can be supplied to the insulator 66b and the insulator 66c. The current is supplied to the insulator 66a, the semiconductor 66b, and the insulator 66c via the semiconductor 72 or the insulator 64. The heat treatment is carried out at a temperature of 250°C to 650°C, preferably 350°C to 45°C. The heat treatment can be carried out at 0°C or below. The heat treatment is carried out in an inert gas atmosphere or in an atmosphere containing 10 ppm of oxidizing gas. The heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of the above. Heat treatment can also be performed using an RTA device that uses lamp heating.

[0221] The conductor 62a serving as the back gate of the transistor, the plug and the wiring shown in FIG. When tantalum nitride is used for the conductor 20a, the heat treatment temperature is set to 350° C. or higher. The temperature range is 410°C or less, preferably 370°C or more and 400°C or less. By carrying out the heat treatment at this temperature, it is possible to suppress the release of hydrogen from tantalum nitride.

[0222] The insulator 78 is an insulator that is less permeable to oxygen than the insulator 77, and blocks oxygen. By providing such an insulator 78, the insulator 77 When oxygen is supplied from the insulating layer 66a to the semiconductor layer 66b and the insulating layer 66c, the oxygen This can prevent the heat from being released to the outside above the edge 78.

[0223] Aluminum oxide has a film that is resistant to both impurities such as hydrogen and moisture, and oxygen. It is preferable to apply it to the insulator 78 because it has a high blocking effect of preventing transmission.

[0224] Next, a modified example of the transistor 60a will be described with reference to FIGS. 13(C) and (D) show the channel of the transistor 60a in the same manner as in FIG. 13(A) and (B). 10A and 10B are cross-sectional views in the channel length direction and the channel width direction of the transistor 60a.

[0225] The transistor 60b shown in FIGS. 13(C) and 13(D) includes an insulator 64, a conductor 68a, and a conductor An insulator 77 is provided on the conductor 68b, and the insulator 77, the conductor 68a, and the conductor The insulator 66c, the insulator 72 and the conductive material 68b are embedded in the openings formed in the insulator 66c, the insulator 72 and the conductive material 68b. 13A and 13B in that a body 74 is provided. Note that other configurations of the transistor 60b shown in FIGS. 13(C) and 13(D) are the same as those shown in FIG. 3(A) and 3(B) can be taken into consideration.

[0226] In addition, the transistor 60b has an insulator 76 provided on an insulator 77. In this case, the insulator 76 may be used for the insulator 77. In addition, the transistor 60b is provided with an insulator 79. However, the present invention is not limited to this configuration, and an insulator 79 may be provided.

[0227] However, the transistor 60b is not limited to the configuration shown in FIGS. 13(C) and 13(D). For example, the side surfaces of the insulator 66c, the insulator 72, and the conductor 74 may be in contact with the upper surface of the semiconductor 66b. Alternatively, the tapered shape may be inclined at an angle of 30° or more and less than 90° with respect to the surface.

[0228] <Capacitor element configuration> 14A shows an example of the configuration of a capacitor 80a. The capacitor 80a has a conductor 82 and 14(A), the insulator 81 has an insulator 83 and a conductor 84. A conductor 82 is provided on the conductor 82, an insulator 83 is provided to cover the conductor 82, and the insulator 8 A conductor 84 is provided to cover the electrode 3, and an insulator 85 is provided on the conductor 84.

[0229] Here, the insulator 83 is provided so as to contact the side surface of the conductor 82, and the conductor 84 is provided so as to contact the side surface of the insulator. It is preferable that the conductive material 82 is provided so as to contact the side surface of the protrusion of the conductive material 83. Not only the top surface but also the side surface of the conductor 82 can function as a capacitance element. The value can be increased.

[0230] The conductors 82 and 84 may be, for example, boron, nitrogen, oxygen, fluorine, or silicon. , phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium Sodium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin When a conductor containing one or more of tantalum and tungsten is used in a single layer or a multilayer, For example, the material may be an alloy or compound, and may be a conductor containing aluminum, copper, and titanium. Conductors containing tin, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductor 82 and conductor containing titanium and nitrogen may be used. The film formation of 84 is performed by sputtering, CVD, MBE, PLD, ALD, etc. This can be done using

[0231] The insulator 83 may be, for example, aluminum oxide, aluminum oxynitride, or magnesium oxide. Sium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide ammonium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, nickel oxide An insulator containing one or more selected from the group consisting of oxydimium, hafnium oxide, tantalum oxide, etc. is used. For example, silicon oxynitride may be laminated on aluminum oxide. , hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped Huff HfSi x O y N z (x>0, y>0, z>0)), nitrogen is added Hafnium aluminate (HfAl x O y N z (x>0, y>0, z>0)), oxide ha It is preferable to use a high-k material such as fluorine or yttrium oxide. In addition, when a high-k material is used as the insulator 83, the capacitance value can be increased by performing heat treatment. By using such high-k materials, it is possible to reduce the Even if the insulator 83 is made thick, the capacitance value of the capacitive element 80a can be sufficiently secured. By doing so, it is possible to suppress the leakage current occurring between the conductor 82 and the conductor 84. The insulator 83 is formed by sputtering, CVD, MBE, or PLD. , ALD method, etc.

[0232] The insulators 81 and 85 are made of an insulator that can be used as the insulator 77. The insulator 85 may be an organic silane gas (for example, TEOS (Tetra-Ethylene Oxide)). Alternatively, a film may be formed using tetraethyl-ortho-silicate, etc.

[0233] Next, modified examples of the capacitive element 80a will be described with reference to FIGS. 14(B) and 14(C).

[0234] In the capacitance element 80b shown in FIG. 14(B), the conductor 84 is in contact with the side surface of the protrusion of the insulator 83. 14(A) in that the upper surface of the conductor 82 is formed so as to overlap the upper surface of the conductor 82 without any gap. 14B, the side end of the conductor 84 and the conductor The side end portions of the body 82 are arranged to overlap, but the capacitive element 80b is not limited to this. It's not that.

[0235] In the capacitance element 80c shown in FIG. 14(C), an insulator 86 having an opening is provided on the insulator 81. The conductor 82 is provided in the opening, which is the same as that shown in FIG. Here, the opening in the insulator 86 and the upper surface of the insulator 81 are regarded as a groove. It is preferable that the conductor 82 is provided along the groove. As shown in FIG. 4(C), the upper surface of the insulator 86 is formed so as to be approximately flush with the upper surface of the conductor 82. It may be made.

[0236] An insulator 83 is provided on the conductor 82, and a conductor 84 is provided on the insulator 83. Here, the conductor 84 is located in the groove in a region facing the conductor 82 via the insulator 83. In addition, it is preferable that the insulator 83 is provided so as to cover the upper surface of the conductor 82. By providing the insulator 83 in this manner, a leakage current does not flow between the conductor 82 and the conductor 84. In addition, the side edge of the insulator 83 and the side edge of the conductor 84 are approximately In this way, the capacitor element 80c may be provided in a concave shape. Alternatively, it is preferable that the capacitor element 80c has a cylindrical shape. The upper surfaces of the conductor 82, the insulator 83, and the conductor 84 may have a polygonal shape other than a square. Alternatively, it may be a circular shape including an ellipse.

[0237] <Configuration of transistors formed on a semiconductor substrate> 15(A) and 15(B) show transistors included in an element layer having a semiconductor substrate. 15A shows an example of the configuration of the transistor 90a. 15B is a cross-sectional view corresponding to the channel width direction B3 of the transistor 90a. FIG. 10 is a cross-sectional view corresponding to line B4.

[0238] A plurality of protrusions are formed on the semiconductor substrate 91, and grooves (trenches) are formed between the protrusions. An element isolation region 97 is formed in the semiconductor substrate 91. An insulator 94 is formed on the region 97, and a conductor 96 is formed on the insulator 94. An insulator 95 is formed in contact with the side surfaces of the insulator 94 and the conductor 96. An insulator 99 is provided on the plate 91, the element isolation region 97, the insulator 95, and the conductor 96. An insulator 98 is further provided thereon.

[0239] As shown in FIG. 15A, at least an insulator is formed on the protruding portion of the semiconductor substrate 91. The low resistance region 93a and the low resistance region 93b are formed so as to overlap with a part of the low resistance region 95. The low resistance region 92a and the low resistance region 92b are formed outside the low resistance region 93a and the low resistance region 93b. The low resistance region 92a and the low resistance region 92b are the same as the low resistance region 93a and the low resistance region 93b. It is preferable that the resistance is lower than that of 93b.

[0240] Here, conductor 96 serves as the gate of transistor 90a, and insulator 94 serves as the The low-resistance region 92a functions as a gate insulating film for the transistor 90a. The low resistance region 92b functions as either the source or drain of the transistor 90a. Insulator 95 also functions as the other of the source and drain of transistor 90a. The low resistance region 93a and the low resistance region 93b function as a gate wall insulating film. The LDD (Lightly Doped Drain) region of the transistor 90a is In addition, in the convex portion of the semiconductor substrate 91, the conductor 96 overlaps and the low resistance region 93a The region between the low-resistance region 93b and the low-resistance region 93c is the channel forming region of the transistor 90a. It functions as such.

[0241] In the transistor 90a, as shown in FIG. 15B, the convex portion in the channel forming region The side and top of the conductive material 96 overlap with the insulator 94 sandwiched therebetween, forming a channel. Carriers flow over a wide area, including the sides and top of the region. The area occupied by the transistor 90a on the substrate is kept small while the moving As a result, the amount of carriers in the transistor 90a increases. In particular, the convex portion in the channel forming region is The length of the channel width direction (channel width) of the part is W, and the height of the convex part in the channel formation region is If T is the aspect ratio, which corresponds to the ratio of the height T of the convex part to the channel width W (T / W), When θ is high, the range over which carriers can flow is wider, so the on-current of transistor 90a For example, the field effect mobility can be increased by In the case of the transistor 90a using the solid substrate 91, the aspect ratio is required to be 0.5 or more. It is preferable that the number be 1 or more, and more preferable that the number be 1 or more.

[0242] The transistor 90a shown in FIGS. 15A and 15B is formed by trench isolation (STI) method. This shows an example of device isolation using low trench isolation. However, the semiconductor device described in this embodiment mode is not limited to this.

[0243] The semiconductor substrate 91 may be, for example, a single semiconductor substrate such as silicon or germanium, or or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A semiconductor substrate such as gallium oxide may be used. A single crystal silicon substrate is used as the semiconductor substrate 91. A semiconductor substrate having a region, such as SOI (Silicon On Insulator) A substrate or the like may also be used.

[0244] The semiconductor substrate 91 is, for example, a semiconductor substrate containing impurities that impart p-type conductivity. However, the semiconductor substrate 91 is a semiconductor substrate containing impurities that impart n-type conductivity. Alternatively, the semiconductor substrate 91 may be an i-type.

[0245] The low resistance regions 92a and 92b provided in the semiconductor substrate 91 are formed of phosphorus or Elements that provide n-type conductivity, such as arsenic, or p-type conductivity, such as boron or aluminum Similarly, the low resistance region 93a and the low resistance region 93b also contains elements that give n-type conductivity, such as phosphorus and arsenic, or boron and aluminum. However, it is preferable that the low resistance region 93a and the low resistance region 93b contain an element that imparts p-type conductivity. Since it is preferable that the low resistance region 93a and the low resistance region 93b function as LDDs, The concentration of the element that provides conductivity contained in the low resistance region 93b is It is preferable that the concentration of the element that provides conductivity contained in the resistive region 92b is lower than that of the element that provides conductivity. The resistance region 92a and the low resistance region 92b may be formed using silicide or the like.

[0246] The insulators 94 and 95 are made of, for example, aluminum oxide, aluminum oxynitride, or oxide. Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Uses an insulator containing one or more selected from neodymium oxide, hafnium oxide, tantalum oxide, etc. Also, hafnium silicate (HfSi x O y (x>0, y>0) , nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z> 0)), nitrogen-doped hafnium aluminate (HfAl x Oy N z (x>0, y> 0, z>0), hafnium oxide, or yttrium oxide. The insulators 94 and 95 may be formed by a sputtering method, a CVD method, an M method, or the like. This can be carried out using a BE method, a PLD method, an ALD method, or the like.

[0247] The conductor 96 may be tantalum, tungsten, titanium, molybdenum, chromium, or niobium. Metals selected from the above, or alloy materials or compound materials containing these metals as the main components It is preferable to use polycrystalline silicon doped with impurities such as phosphorus. The conductor 96 may also be formed from a laminated structure of a metal nitride film and the above-mentioned metal film. As the metal nitride, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing a metal nitride film, the adhesion of the metal film can be improved, and peeling can be prevented. The conductor 96 can be formed by a sputtering method, a CVD method, or the like. This can be done using the MBE method, PLD method, ALD method, or the like.

[0248] The insulators 98 and 99 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, ma, or the like. Magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium , including yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum The insulator may be a single layer or a stacked layer. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0249] As the insulator 98, silicon carbonitride de), silicon oxycarbide, etc. Also available are USG (Undoped Silicate Glass) and BPSG. (Boron Phosphorus Silicate Glass), BSG(Bo USG, BPSG, etc. can be used. It may be formed by atmospheric pressure CVD. For example, HSQ (hydrogen silsesquioxane) ) may be formed by a coating method.

[0250] However, it may be preferable for the insulator 99 to contain hydrogen. For example, Silicon nitride containing hydrogen may be used. The conductive substrate 91 may reduce defects and improve the characteristics of the transistor 90a. For example, when a material containing silicon is used as the semiconductor substrate 91, the silicon This allows the termination of defects such as dangling bonds.

[0251] Next, a modified example of the transistor 90a will be described with reference to FIGS. 15(C) and (D) show the channel of the transistor 90a in the same manner as in FIG. 15(A) and (B). 10A and 10B are cross-sectional views in the channel length direction and the channel width direction of the transistor 90a.

[0252] The transistor 90b shown in FIGS. 15(C) and 15(D) has a semiconductor substrate 91 on which a protrusion is formed. 15A and 15B in that the transistor 90a shown in FIG. 5(C)(D) are other configurations of the transistor 90b shown in FIGS. 15(A)(B). The structure of the transistor 90a shown in FIG.

[0253] In the transistors 90a and 90b, the area in contact with the bottom surface of the conductor 96 However, the semiconductor device shown in this embodiment is not limited to this. For example, the insulator 94 may be provided so as to contact the bottom and side surfaces of the conductor 96. It may also be possible to use the following.

[0254] <Configuration example of semiconductor device> An element layer including an oxide semiconductor is formed on an element layer including a semiconductor substrate (hereinafter referred to as element layer 50). A layer (hereinafter referred to as an element layer 30) including a capacitance element is provided on the element layer 30. An example of the configuration of a semiconductor device provided with a layer 40 is shown in FIG. 1 is a cross-sectional view of the transistor 60a and the transistor 90a along the channel length direction C1-C2. In FIG. 16, the channel length direction of the transistor 60a and the transistor 90a is are parallel to each other, but are not limited to this and can be set appropriately.

[0255] The element layer 50 is provided with a transistor 90a shown in FIG. A substrate 91, an element isolation region 97, an insulator 98, an insulator 99, an insulator 94, an insulator 95, a conductor The conductive body 96, the low resistance region 93a and the low resistance region 93b, the low resistance region 92a and the low resistance region 9 Regarding 2b, the above description can be taken into consideration.

[0256] The element layer 50 includes a conductor 51a and a conductor 52a, a conductor 51b and a conductor 52b, and a conductor 51c. The conductor 51c and the conductor 52c are provided with portions that function as plugs. The lower surface of the conductor 51a is in contact with the low resistance region 92a, and the insulator 98 and formed in the openings of the insulator 99. The conductors 51b and 52b are The lower surface of 51b is in contact with the conductor 96 and is formed in the opening of the insulator 98. The lower surface of the conductor 51c is in contact with the low resistance region 92b, and the insulator 98 and formed in an opening in the insulator 99.

[0257] Here, the conductors 51a to 51c are the same as the conductor 20a shown in FIGS. 4(C) and 4(D). The conductors 52a to 52c may have the same structure as that shown in FIGS. However, the present invention is not limited to this, and may be applied to, for example, a single The plug and the wiring may be formed separately using a damascene method or the like.

[0258] As shown in FIG. 16, the conductors 51a to 51c and the conductors 52a to 52c are It is preferable that the conductors 51a to 51c have a laminated structure. For example, titanium, tantalum, titanium nitride, tantalum nitride, etc. may be used in a single layer or a laminated layer. A metal nitride such as tantalum nitride or titanium nitride, particularly tantalum nitride, is used as the conductor 51. By using the conductors 51a to 51c, impurities such as hydrogen and water contained in the element layer 50 and the like can be removed. Diffusion into the conductors 51a to 51c and migration to upper layers are suppressed. This can be done not only for the conductors 51a to 51c but also for other plugs and wirings. Therefore, the conductor 111 located below the element layer 30 Similarly, the conductors 111a to 111c and the conductors 121a to 121c also have a stacked structure. The layer may be made of a metal nitride, such as tantalum nitride or titanium nitride, and in particular tantalum nitride. This prevents impurities such as hydrogen and water from diffusing into the element layer 30 located above. By adopting such a configuration, the oxide semiconductor contained in the element layer 30 can be made highly pure. The oxide semiconductor may be a highly intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0259] An insulator 102a and an insulator 102b are provided on the insulator 98. The conductors 51a, 52a, 51b and 52c are inserted into openings formed in the insulator 102b. The portions that function as wirings of the conductors 51a, 51b, 52b, 51c, and 52c are embedded. For example, the conductors 52a to 52c are provided so as to be embedded in a material that is easily diffused, such as copper. When using metal, use an insulator that copper cannot easily penetrate, such as silicon nitride or silicon carbide nitride. This prevents impurities such as copper from diffusing into the transistor 90a. In addition, it is preferable to use an insulator having a lower hydrogen concentration than the insulator 98, etc. for the insulator 102a. It is also preferable that the insulator 102b has a lower dielectric constant than the insulator 102a. In FIG. 16, the insulator 102a and the insulator 102b are stacked, but this is not limitative. It may be a single layer insulator without any insulation.

[0260] An insulator 104 is provided on the insulator 102b, and an insulator 106 is provided on the insulator 104. The insulator 102a is provided on the insulator 106, and the insulator 108 is provided on the insulator 106. b. Insulator 104, insulator 106, and insulator 108 can be used for insulator 98. Insulators may be used. Either the insulating layer 106 or the insulating layer 108 has a function of blocking impurities such as hydrogen and oxygen. It is preferable to use an insulator having the following properties: Examples of insulators having the formula include boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used alone. It may be used in layers or laminates, for example, silicon nitride.

[0261] Furthermore, when a metal that easily diffuses, such as copper, is used for the conductors 52a to 52c, an insulator By using an insulator such as silicon nitride or silicon nitride carbonitride, which is difficult for copper to penetrate, This prevents impurities such as copper from diffusing into the oxide semiconductor film included in the element layer 30. can be done.

[0262] The insulators 104 and 106 are provided with the conductors 111a and 112a, and the conductors 111b and 112c. 1b and conductor 112b, and conductor 111c and conductor 112c. The insulator 108 includes a conductor 111a, a conductor 112a, and a As wiring for the conductors 111b and 112b, and the conductors 111c and 112c, The conductor 111a and the conductor 112a are provided with a functional portion. The lower surface of the insulator 104, the insulator 106, and the insulator 108 are in contact with the conductor 52a. The conductor 111b and the conductor 112b are formed in such a manner that the lower surface of the conductor 111b is conductive. The insulating material 104, the insulating material 106, and the insulating material 108 are formed in the openings in contact with the conductive material 52b. The conductor 111c and the conductor 112c are connected such that the lower surface of the conductor 111c is connected to the conductor 52c. , and are formed in the openings of the insulators 104, 106 and 108.

[0263] Here, the conductors 111a to 111c are the conductors 20a shown in FIGS. The conductors 112a to 112c may have a structure similar to that shown in FIG. The conductor 21a may have a structure similar to that of the conductor 21a shown in (D). However, the present invention is not limited to this, and may be, for example, The plug and the wiring may be formed separately using a single damascene method or the like.

[0264] An insulator 110 is provided on the insulator 108. The insulator 110 has the same structure as the insulator 106. Any insulator that can withstand such temperatures may be used.

[0265] The element layer 30 on the insulator 110 is provided with a transistor 60a shown in FIG. The insulator 61, the insulator 67, the conductor 62a, the conductor 62b, the insulator 65, the insulator 6 ...6, the insulator 66, the insulator 66, the insulator 66, the insulator 66 Insulator 63, insulator 64, insulator 66a, semiconductor 66b, insulator 66c, conductor 68a, conductor Regarding conductor 68b, insulator 72, conductor 74, insulator 79, insulator 77, and insulator 78 The above description can be taken into consideration.

[0266] The insulators 61 and 110 are provided with the conductors 121a and 122a, and the conductors 121 b and the conductor 122b, the conductor 121c and the conductor 122c, The insulator 67 is provided with a conductor 121a, a conductor 122a, and a conductor The conductive material 121b and the conductive material 122b, and the conductive material 121c and the conductive material 122c function as wiring. The conductor 121a and the conductor 122a are provided with a portion below the conductor 121a. The surface is in contact with the conductor 112a and is formed in the openings of the insulators 67, 61, and 110. The conductor 121b and the conductor 122b are formed such that the lower surface of the conductor 121b is in contact with the conductor 122b. 12b, and formed in the openings of the insulators 67, 61, and 110. The conductor 121c and the conductor 122c are connected such that the bottom surface of the conductor 121c is in contact with the conductor 112c. , and are formed in the openings of the insulators 67, 61 and 110.

[0267] Here, the conductors 121a to 121c are the conductors 20a shown in FIGS. The conductors 122a to 122c may have a structure similar to that shown in FIG. It may have a structure similar to that of the conductor 21a shown in D).

[0268] In addition, the conductors 62a and 62b are connected to the conductors 121a and 122a, and the conductors The conductors 121b and 122b, the conductors 121c and 122c are formed in the same layer. The conductors 62a and 62b, the conductors 121a and 122a, The process of simultaneously producing the above will be described in detail later.

[0269] As shown in FIG. 16, the insulator 61 and the conductor 12 are disposed between the semiconductor substrate 91 and the semiconductor 66b. The conductors 121a to 121c are separated by hydrogen. and the function of blocking the diffusion of water. Impurities such as water may be introduced into the conductors that function as via holes or plugs formed in the insulator 61. Diffusion into the semiconductor 66b through the conductors 122a to 122c can be prevented.

[0270] FIG. 17 shows a cross-sectional view corresponding to the C3-C4 cross section near the scribe line 138. As shown in Figure 17, in the vicinity of the area overlapping with the scribe line 138, the insulator 6 7, openings are formed in the insulators 65, 63, 64 and 77, and the insulator 67 An insulator 78 is formed to cover the side surfaces of the insulators 65, 63, 64 and 77. It is preferable that the insulator 78 and the insulator 61 are in contact with each other at the opening.

[0271] By adopting such a shape, the insulator 78 and the insulator 61 are 5, the insulators 63, 64 and 77 can be covered up to the side surfaces. The insulator 61 has a function of blocking hydrogen and water, and therefore, the semiconductor shown in this embodiment Even if the body device is scribed, the insulators 67, 65, 63, 64 and Preventing hydrogen or water from penetrating from the side of the body 77 and diffusing into the transistor 60a can be done.

[0272] As described above, excess oxygen may be supplied to the insulator 77 during the formation of the insulator 78. At this time, since the side surface of the insulator 77 is covered with the insulator 78, oxygen is insulated. Diffusion of oxygen from the insulator 77 to the insulator 6 is prevented. Oxygen can be supplied to the semiconductor 66a, the semiconductor 66b, and the insulator 66c. It is possible to reduce oxygen deficiencies that cause defects in the insulator 66a, the semiconductor 66b, and the insulator 66c. As a result, the semiconductor 66b becomes an oxide semiconductor having a low defect state density and stable characteristics. It is possible.

[0273] An insulator 81 is provided on the insulator 78. The insulator 81 can be used for the insulator 77. Any suitable insulator can be used.

[0274] The insulators 81, 78, 77, 65, 63, and 64 are Conductors 31a and 32a, 31b and 32b functioning as plugs; Conductor 31c and conductor 32c, conductor 31d and conductor 32d, conductor 31e and conductor The conductor 31a and the conductor 32a are provided with a conductive member 32e. In contact with the insulator 122a, the insulator 81, the insulator 78, the insulator 77, the insulator 64, and the insulator 63 and formed in the openings of the insulator 65. The conductors 31b and 32b are The lower surface of 31b contacts the conductor 68a, and the openings of the insulators 81, 78, and 77 are The conductor 31c and the conductor 32c are formed in such a manner that the lower surface of the conductor 31c is in contact with the conductor 6. The conductive member 8b is formed in the openings of the insulators 81, 78 and 77. The lower surface of the conductor 31d is in contact with the conductor 122b, and the insulating 81, insulator 78, insulator 77, insulator 64, insulator 63 and insulator 65 are formed in the openings. The conductor 31e and the conductor 32e are configured such that the lower surface of the conductor 31e is in contact with the conductor 122c. In contact with the insulator 81, the insulator 78, the insulator 77, the insulator 64, the insulator 63 and the insulator 6 It is formed in the opening of 5.

[0275] Here, the conductors 31a to 31e are the same as the conductor 20a shown in FIGS. 4(C) and 4(D). The conductors 31a to 31e can be formed in such a structure. By this structure, the via holes formed in the insulator 78 are connected to the conductors 31a to 31b. The conductors 31a to 31e can be shaped to block the diffusion of hydrogen and water. Since it has a blocking function, the via hole formed in the insulator 78 and the conductor 32 Impurities such as hydrogen or water diffuse into the transistor 60a through the conductors 32a to 32e. In addition, the conductors 32a to 32e can be prevented from being broken down into the following two types of conductors. Any conductor that can be used for the conductor 21a shown in FIG.

[0276] On the insulator 81, the conductors 33a, 33b, 82, and 33e are formed. Here, the conductor 82 is one of the electrodes of the capacitance element 80a of the element layer 40. The conductor 33a is in contact with the upper surfaces of the conductors 31a and 32a, and the conductor 33b is in contact with the upper surfaces of the conductors 31b. and the upper surface of the conductor 32b, and the conductor 82 is in contact with the conductors 31c, 32c, and the conductor The conductor 33e contacts the upper surfaces of the conductors 31d and 32d. It is in contact with the top surface of

[0277] Here, the conductors 33a, 33b, and 33e can be used as the conductor 82. Any suitable conductor may be used.

[0278] In the cross-sectional view shown in FIG. 16, the conductor 74, the wiring and the plug connected to the conductor 62b are Although not shown, a separate device may be provided.

[0279] The element layer 40 is provided with the capacitance element 80a shown in FIG. 14(A), and the insulator 8 1, the conductor 82, the insulator 83, the conductor 84, and the insulator 85 are described above. It is possible.

[0280] The element layer 40 includes a conductor 41a, a conductor 42a, and a conductor 41b that function as plugs. and conductor 42b, conductor 41c and conductor 42c, conductor 41d and conductor 42d are provided. The conductor 41a and the conductor 42a are connected such that the lower surface of the conductor 41a is connected to the conductor 33a. The conductor 41b and the conductor 41c are formed in the openings of the insulators 83 and 85. The lower surface of the conductor 41b is in contact with the conductor 33b, and the insulators 83 and 85 are in contact with each other. The conductors 41c and 42c are formed in the openings. The lower surface of the conductor 41c is conductive. The conductor 41d is formed in the opening of the insulator 85 in contact with the conductor 84. 2d is the opening of the insulator 83 and the insulator 85 when the lower surface of the conductor 41d contacts the conductor 33e. is formed inside.

[0281] Here, the conductors 41a to 41d are the same as the conductor 20a shown in FIGS. 4(C) and 4(D). Conductors 42a to 42d may be made of any suitable material. Any conductor that can be used for the conductor 21a shown in (C) and (D) may be used.

[0282] The conductors 43a to 43d functioning as wirings are formed on an insulator 85. The conductor 43a is in contact with the upper surfaces of the conductors 41a and 42a, and the conductor 43b is in contact with the upper surfaces of the conductors 41a and 42a. The conductor 43c is in contact with the upper surfaces of the conductors 41b and 42b, and the conductor 43c is in contact with the upper surfaces of the conductors 41c and 42c. The conductor 43d is in contact with the upper surfaces of the conductors 41d and 42d.

[0283] Here, the conductors 43a to 43d are the conductors 33a, 33b, and 33c. Conductors that can be used for the conductors 43a to 43d may be used. Since the conductors 43a to 43d are formed on the element layer 30, they are heated at high temperatures after the conductors 43a to 43d are formed. Therefore, the conductors 43a to 43d may not need to be subjected to the heat treatment. For example, by using metal materials such as aluminum and copper, which have low heat resistance but low resistance, This allows the wiring resistance to be reduced.

[0284] An insulator 134 is formed on the insulator 85 to cover the conductors 43a to 43d. The insulator 134 may be any insulator that can be used for the insulator 85 .

[0285] The insulator 134 is provided with a conductor 131 and a conductor 132 that function as plugs. The conductor 131 and the conductor 132 are arranged such that the lower surface of the conductor 131 contacts the conductor 43a, It is formed in an opening in the insulator 134 .

[0286] Here, the conductor 131 can be used for the conductor 20a shown in FIGS. 4(C) and 4(D). The conductor 132 may be the conductor 21a shown in FIGS. Any suitable conductor may be used.

[0287] The conductor 133, which functions as a wiring, is formed on the insulator 134. 3 is in contact with the upper surfaces of the conductors 131 and 132. Here, the conductor 133 is Any conductor that can be used for the conductor 33a, the conductor 33b, and the conductor 33e may be used.

[0288] An insulator 136 is formed on the insulator 134 so as to have an opening above the conductor 133. The insulator 136 may be an insulator that can be used for the insulator 134. The insulator 136 may be an organic insulating film such as polyimide.

[0289] In the semiconductor device shown in FIG. 16, the layers above the element layer 30 are interconnects and plugs. However, the semiconductor device according to the present embodiment is not limited to this. For example, as shown in FIG. 18, even in the layers above the element layer 30, the same structure as in FIGS. The wiring and the plug can be integrally formed by using the method shown in .

[0290] The conductor 31a and the conductor 32a shown in FIG. 18 are the same as the conductor 31a and the conductor 32a shown in FIG. 18 correspond to the conductors 2a and 33a. The conductors 31b and 32b shown in FIG. 18 corresponds to the conductors 31b, 32b, and 33b shown in FIG. 31f and the conductor 32f are the same as the conductors 31c, 32c, 31d, and The conductors 31e and 32e shown in FIG. , correspond to the conductor 31e, the conductor 32e, and the conductor 33e shown in FIG.

[0291] In FIG. 18, the conductors 31a, 31b, 31f, 31e, The conductors 32a, 32b, 32f, and a part of the conductor 32e are provided in the insulator 81. The sensor is embedded in a recessed opening.

[0292] 16. The conductor 41a and the conductor 42a shown in FIG. 18 are the same as the conductor 41a and the conductor 42a shown in FIG. The conductors 41b and 42b shown in FIG. 16. The conductor 41c and the conductor 42c are the same as the conductor 41c, the conductor 42c, and the conductor 42c shown in FIG. The conductors 41d and 42d shown in FIG. 18 correspond to the conductors 43c shown in FIG. 41d, conductor 42d and conductor 43d.

[0293] An insulator 135 is provided between the insulator 85 and the insulator 134. In FIG. The conductors 41a, 41b, 41c, 41d, 42a, and The conductors 42b, 42c, and 42d are partially filled in the openings in the insulator 135. The insulator 135 is made of a material that can be used for the insulator 134. That's fine.

[0294] Next, using the structure shown in FIG. 16 as an example, the wiring and plugs (the conductors 121a and 122a ) and a back gate (conductors 62a and 62b) are fabricated in parallel. 19 to 22 show cross-sectional views of a transistor. 6 shows a cross-sectional view corresponding to C5-C6 parallel to the channel length direction C1-C2 of 60a. 19 to 22 are exaggerated with a different aspect ratio from that of FIG.

[0295] The conductor 112a and the conductor 111a are formed in the openings, and the insulator 108 is formed. The insulator 110a is formed on the insulating film 110a after the opening is formed. Here, the insulator 110a corresponds to the insulator 13 shown in FIG.

[0296] An insulator 61a is formed on the insulator 110a. For example, the insulator 61a may be a sputtering material. Aluminum oxide film formed by the deposition method and acid film formed on it by the ALD method. It is preferable to use a laminated structure of aluminum oxide formed by the ALD method. By using aluminum, the formation of pinholes can be prevented, so that the insulator 61 The blocking performance against hydrogen and water can be further improved. After being formed, it becomes the insulator 61. Here, the insulator 61a corresponds to the insulator 14 shown in FIG.

[0297] An insulator 67a is formed on the insulator 61a. The insulator 67a is made of an insulator that can be used for the insulator 67 after the opening is formed. Here, the insulator 67a corresponds to the insulator 15 shown in FIG.

[0298] First, a film of the material of the hard mask 146 is formed on the above-mentioned insulating layer structure. The material of the hard mask 146 may be a conductor such as a metal material, or an insulator. For example, titanium, tantalum, tungsten, titanium nitride, or tantalum nitride may be used. The material for the hard mask 146 may be formed as a single layer or as an insulating layer. The material of the hard mask 146 may be deposited by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0299] Next, a hard mask is formed using a resist mask formed by lithography or the like. The material of 146 is etched to form a hard mask 14 having openings 147a and 149a. 6 is formed (see FIG. 19(A)). Here, in the opening 147a and the opening 149a, The etching is continued until the upper surface of the insulator 67a is exposed. This corresponds to the hard mask 16 shown in FIG.

[0300] Here, the opening 147a is a hole for opening 147fb to be formed in a later step, that is, a hole for forming a wiring pattern. Therefore, the top surface shape of the opening 147a corresponds to the wiring pattern. Furthermore, the opening 147a is set so that at least a portion thereof overlaps with the conductor 112a. It is preferable to do so.

[0301] The opening 149a is used to fill an opening 149c, that is, a back gate, which will be formed in a later step. Therefore, the upper surface shape of the opening 149a corresponds to the back gate. It becomes.

[0302] The etching for forming the hard mask 146 is preferably dry etching. For example, the dry etching may be performed using C4F6 gas, C4F8 gas, CF4 gas, S F6 gas, CHF3 gas, Cl2 gas, BCl3 gas, or SiCl4 gas may be used alone or in combination. Or, two or more gases can be mixed and used. Or, the above gases can be mixed with oxygen gas, helium gas, or the like. Gas such as argon, hydrogen, or the like may be added as needed. The above-mentioned device can be used as the measuring device.

[0303] Next, a resist mask having an opening 147b is formed on the insulator 67a and the hard mask 146. A resist mask 148 is formed (see FIG. 19(B)). It is preferable that the mask 146 is covered with the insulating film 146. In particular, the insulating film 146 is formed on the hard mask 146. A resist mask 148 is formed to cover the opening 149a. 8 corresponds to the resist mask 18a shown in FIG.

[0304] In addition, by applying an organic coating film before applying the resist for the resist mask 148, This can improve the adhesion between the resist mask 148 and the insulator 67b. When a coating film is used, it is necessary to etch the organic coating film before etching the insulator 67a. be.

[0305] Here, the opening 147b is an opening 147fa, that is, a via hole or Therefore, the top surface shape of the opening 147b is the same as that of a via hole. Also, it corresponds to a via hole or a contact hole. The opening 147b corresponding to the groove in which the wiring pattern is to be embedded is formed in the opening 147a. In this case, it is preferable that the maximum width of the opening 147b is equal to or less than the width of the opening 147a. For example, when the width of the opening 147b in the C5-C6 direction shown in FIG. 19(B) is large, The size is equal to or smaller than the width of the opening 147a in the C5-C6 direction shown in FIG. By doing so, the via hole or contact hole can be aligned with the groove of the wiring pattern. It can be formed with a margin.

[0306] Next, the insulator 67a is etched using the resist mask 148 to form an opening 147c. An insulator 67b having the opening 147c is formed (see FIG. 20(A)). The etching is continued until the upper surface of the insulator 61a is exposed. It is preferable to use dry etching. For example, C4F6 gas is used for the dry etching. , C4F8 gas, CF4 gas, SF6 gas, or CHF3 gas, etc., may be used singly or in combination. Gases can be mixed and used. Alternatively, oxygen gas, nitrogen gas, helium gas, etc. can be added to the above gases. Gas such as argon gas or hydrogen gas may be added as needed. The device can be the same as that described above. For example, a parallel plate electrode is provided around the It is preferable to use a dry etching device that is configured to connect high frequency power sources with different frequency. The conditions for dry etching, such as the selection of etching gas, depend on the insulating layer used for the insulator 67a. You can adjust it to suit your body.

[0307] Next, the insulator 61a is etched using the resist mask 148 to form an opening 147d. Insulator 61b having the above structure is formed (see FIG. 20(B)). The etching is continued until the top surface of the insulator 110a is exposed. For example, dry etching using C4F6 gas is used. Gases such as C4F8 gas, CF4 gas, SF6 gas, or CHF3 gas, either singly or in combination Alternatively, the above gases may be mixed with oxygen gas, nitrogen gas, helium gas, or the like. Gas such as argon, hydrogen, or the like may be added as needed. The same device as above can be used. For example, It is preferable to use a dry etching device that is configured to connect high frequency power sources with different frequencies. The conditions for dry etching, such as the selection of etching gas, depend on the insulating material used for the insulator 61a. This may be set appropriately according to the edge.

[0308] Furthermore, when forming the opening 147d, etching is not necessarily stopped on the top surface of the insulator 110a. For example, the opening 147d is formed and then a portion of the insulator 110a is etched away. A recess may be formed at a position overlapping with the opening 147d by cutting.

[0309] Next, the resist mask 148 is removed (see FIG. 21(A)). If an organic coating film is formed under the resist mask 148, it can be removed together with the resist mask 148. The resist mask 148 is preferably removed by dry etching such as ashing. Or, wet etching is performed, or wet etching is performed in addition to dry etching. wet etching or dry etching in addition to wet etching This can be done by doing the following.

[0310] 5(B) and 5(C), after removing the resist mask 148, an opening By-products may form around the upper edge of 147c.

[0311] Next, using a hard mask 146, the insulators 110a, 61b, and 67b are The insulator 110 and the insulator 61 are etched to form the openings 147e and 149b. and an insulator 67c is formed (see FIG. 21(B)). Etching is performed until the upper surface of the conductor 112a is exposed. The edges of the openings 147a and 149a of the hard mask 146 are also etched. In the hard mask 146a, the edge of the opening 147a may be tapered. and the upper edge of the opening 147a is rounded.

[0312] It is preferable to use dry etching for the etching. For example, C4F6 gas, C4F8 gas, CF4 gas, SF6 gas or CHF The above gases can be used alone or in combination of two or more gases. Oxygen gas, nitrogen gas, helium gas, argon gas, hydrogen gas, etc. are added appropriately to The dry etching equipment can be the same as that described above. For example, a dry etching method using a configuration in which high-frequency power supplies with different frequencies are connected to parallel plate electrodes is used. It is preferable to use a dry etching device. Regarding the conditions for dry etching, such as the selection of etching gas, The thickness may be appropriately set in accordance with the insulators used for the insulators 61a and 110a.

[0313] Here, the opening 147e is located at the bottom and is an opening formed using the insulator 61b as a mask. 147ea and an opening 147 located thereon and formed using the hard mask 146 as a mask. The opening 147ea will be used as a via hole in a later process. The opening 147eb functions as a wiring pattern or a contact hole in a later process. It functions as a groove for embedding.

[0314] The insulator 67c is formed on the edge of the opening 147eb (or the inner wall of the opening 147eb). It is also preferable that the edge of the opening 149b has a tapered shape.

[0315] The insulators 110 and 61 are disposed on the edge of the opening 147ea (the inner wall of the opening 147ea). It is also possible to use the opening 147e of the insulator 61. It is preferable that the upper edge of the opening 147ea is rounded. As a result, in a later process, the conductor 121 having high blocking performance against hydrogen is formed with good coverage. It is possible.

[0316] In order to etch the opening 147ea into such a shape, the above-mentioned dry etching The etching rate of the insulator 110a is set to be higher than the etching rate of the insulator 61a. For example, if the etching rate of the insulator 110a is The etching rate of 61a is 8 times or less, preferably 6 times or less, more preferably 4 times or less. This can be done as follows.

[0317] By carrying out the dry etching under these conditions, a tape is formed on the edge of the opening 147ea. Furthermore, the by-products shown in Figures 5(B) and (C) are formed. Even if the opening 147ea in the insulator 61 is not rounded at the top, the by-products must be removed. The shape can be such that:

[0318] However, the shapes of the openings 147e and 149b are not necessarily limited to the above shapes. For example, the inner walls of the openings 147ea, 147eb, and 149b are made of an insulator 61. The opening may be formed substantially perpendicular to the conductor 112a. The opening 147eb and the opening 149b may be formed in the insulator 67c and the insulator 61. The openings 147eb and 149b may be formed between the insulators 67c, 61, and 110. The second electrode 12 may be formed as follows.

[0319] Next, the conductor 121 is formed in the opening 147e and the opening 149b, and then the conductor 12 A conductor 122 is formed on the insulating film 1 so as to fill the openings 147e and 149b. 22(A). Here, the conductor 121 and the conductor 122 are the conductors shown in FIG. 20 and conductor 21.

[0320] Here, the conductor 121 is coated so as to cover the inner walls and bottom surfaces of the openings 147e and 149b. It is preferable that the conductor 121 is formed with good coverage. It is preferable that the insulators 110 and 61 are in contact with each other at their edges. It is more preferable that the conductor 121 has a shape that closes the opening along the opening. The edges of the opening 147ea of ​​the insulator 110 and the insulator 61 are tapered. The upper edge of the opening 147ea is rounded to improve the covering property of the conductor 121. can be further improved.

[0321] The conductor 121 is preferably a conductor that is less permeable to hydrogen than the conductor 122. The conductor 121 may be a metal nitride such as tantalum nitride or titanium nitride, particularly nitride. It is preferable to use tantalum. By providing such a conductor 121, hydrogen, It is possible to prevent impurities such as water from diffusing into the conductor 122. Prevents the diffusion of metal components contained in the conductor 122, prevents oxidation of the conductor 122, and It is possible to obtain an effect of improving the adhesion to the opening 147e. When 121 is formed by lamination, for example, titanium, tantalum, titanium nitride or tantalum nitride may be used. Alternatively, a layered structure in which titanium nitride is formed on tantalum nitride may be used. In addition, when a tantalum nitride film is formed as the conductor 121, the RTA apparatus Heat treatment may be carried out by

[0322] The conductor 121 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an AL method, or the like. Here, the conductor 121 can be formed by a method with good coating properties. It is preferably carried out by a method such as collimated sputtering, MCVD or ALD. It is preferable to use a method such as the above.

[0323] By using the collimated sputtering method, the bottom of the high aspect ratio opening of 147ea can be Since the sputtered particles can reach the bottom of the opening 147ea, a sufficient film can be formed on the bottom of the opening 147ea. As described above, the inner walls of the openings 147ea, 147eb, and 149b can be treated with a tape. By forming the opening 147ea, the opening 147eb, and the opening 149b in a rectangular shape, the inner walls of the opening 147ea, the opening 147eb, and the opening 149b It is possible to form a film sufficiently even in this case.

[0324] Furthermore, by forming the conductor 121 by the ALD method, the conductor 121 can be formed in a good condition. The film is formed with good coating properties and the formation of pinholes or the like in the conductor 121 can be suppressed. By forming the conductor 121 in this manner, impurities such as hydrogen and water can be absorbed into the conductor. It is possible to further suppress diffusion through the conductive material 121 to the conductive material 122. For example, When a tantalum nitride film is formed as the conductor 121 by the ALD method, pentakis(dimethylamino) (triamino)tantalum (structural formula: Ta[N(CH3)2]5) is used as a precursor. This can be done.

[0325] The conductor 122 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, Thorium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more of tungsten and cerium may be used in a single layer or a multilayer. , tungsten, etc. can be used.

[0326] The conductor 122 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an AL method, or the like. The conductor 122 can be formed by filling the opening 147e. Since the process is performed by embedding, it is preferable to use the CVD method (particularly the MCVD method).

[0327] In addition, when a conductor that suppresses copper diffusion is used for the conductor 121, the conductor 122 is For example, copper having low line resistance can be used as the conductor 121. Tantalum nitride may be used, and copper may be used for the conductor 122. In this case, the tantalum nitride may be used, and copper may be used for the conductor 122. It is preferable to form a film of tantalum nitride so as to cover the upper surface of the conductor 122a. By adopting such a configuration, a conductive layer that functions as a back gate of the transistor 60a is formed. The conductive body 62b may be made of copper and the conductive body 62a may be made of tantalum nitride.

[0328] Next, the conductor 122, the conductor 121, the hard mask 146a, and the insulator 67c are subjected to a polishing process. The conductors 121a and 122a embedded in the openings 147f and the openings 147c are then removed. Conductors 62a and 62b embedded in 9c are formed (see FIG. 22(B)). Polishing processes include mechanical polishing, chemical polishing, and chemical mechanical polishing. For example, CMP processing can be performed. By performing the treatment, the insulator 67c, the upper part of the conductor 122 and the conductor 121, and the hard The disk 146a is removed, and the insulator 67, the conductor 122a, the conductor 121a, and the conductor 122b are removed. Conductor 62a and conductor 62b can be formed.

[0329] Here, the opening 147f is located at the bottom and serves as a via hole, a contact hole, or the like. and an opening 147fa located at the top, which functions as a groove for embedding wiring patterns, etc. The opening 147fa is made up of an insulator 147b. 10 and the insulator 61, and the opening 147fb is formed in the insulator 67. 1a and the portion of the conductor 122a embedded in the opening 147fa function as a plug. The portions of the conductor 121a and the conductor 122a embedded in the opening 147fb are used as wiring or the like. It works.

[0330] In this way, the method shown in FIGS. 1 to 4 can be used to form conductive layers that function as plugs and interconnects. In parallel with forming the conductor 122a and the conductor 121a, the buffer is formed by the transistor 60a. Conductors 62a and 62b that function as gates can be formed. Without increasing the number of steps, the back gate of the transistor 60a and the back gate The wiring and the plug can be formed in the same layer. By providing the conductors 62a and 62b, the threshold voltage of the transistor 60a is By controlling the threshold voltage, the transistor 6 The voltage applied to the gate (conductor 74) of OA is low, e.g., the applied voltage is 0V or less. In this case, the transistor 60a can be prevented from being turned on. The transistor 60a can be a transistor having normally-off electrical characteristics.

[0331] The shapes of the wiring and plugs shown in this embodiment are limited to those shown in FIG. 22(B). Typical examples of wiring and plugs with shapes different from those shown in FIG. 22(B) are shown below.

[0332] In the wiring and plug shown in FIG. 23(A), the shape of the opening 147g is different from that of the opening 147f. 22(B) in that the shape of the opening 149d is different from that of the opening 149c. Here, the opening 147g consisting of the opening 147ga and the opening 147gb is different from the opening 147g shown in FIG. ) and can be taken into consideration. d is formed on the insulator 67 and the insulator 61. Therefore, in the configuration shown in FIG. In this case, the conductors 62a and 62b functioning as a back gate are connected to the insulator 67 and the insulator It is provided so as to be embedded in the upper part of the edge body 61.

[0333] In the wiring and plug shown in FIG. 23(B), the shape of the opening 147h is different from that of the opening 147f. 22B in that the shape of the opening 149e is different from that of the opening 149c. Here, the opening 147h consisting of the opening 147ha and the opening 147hb is different from the opening 147h shown in FIG. ) and can be used as a reference. e is formed on the top of the insulator 67, the insulator 61, and the insulator 110. In the structure shown in FIG. 1, the conductors 62a and 62b functioning as back gates are insulated. The edge member 67 is provided so as to be embedded in the upper part of the insulator 61 and the insulator 110 .

[0334] Next, the conductor 62a and the conductor 62b functioning as the back gate of the transistor 60a shown in FIG. The method of forming transistor 60a on conductor 62b is shown in FIGS. 24 and 25. The following explanation will be given using cross-sectional views of Fig. 24(A), Fig. 24(C), Fig. 24(E), Fig. 25(A). 25(C) and 25(E) are diagrams showing the channel length direction A1-A2 of the transistor 60a. 24(B), 24(D), 24(F), 25(B), and 2 5(D) and 25(F) correspond to the channel width direction A3-A4 of the transistor 60a. Cross-sectional view.

[0335] First, the insulator 65 is formed on the insulator 67, the conductor 62a, and the conductor 62b. The insulator 65 may be formed by a sputtering method. This can be done using a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 65 is formed of silicon oxide or silicon oxynitride by the PECVD method. Just film it.

[0336] Next, the insulator 63 is formed on the insulator 65. The insulator 63 is made of the above-mentioned material. The insulator 63 may be formed by sputtering, CVD, MBE, or PLD. For example, the insulator 63 can be formed by the ALD method. For this purpose, a film of hafnium oxide or aluminum oxide may be formed.

[0337] Next, an insulator 64 is formed on the insulator 63 (see FIGS. 24(A) and 24(B)). The insulator 64 may be formed by sputtering, CV This can be done using the D method, MBE method, PLD method, ALD method, etc. As the body 64, a film of silicon oxide or silicon oxynitride is formed by using the PECVD method. In addition, the insulators 65, 63, and 64 are formed without being exposed to the atmosphere. It may also be carried out continuously using the LD method.

[0338] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 65 and the insulator 6 The water or hydrogen in the insulator 64 can be further reduced. 4. It may be possible to have excess oxygen in the material. Heat treatment is carried out at temperatures between 250°C and 650°C. The temperature is preferably 350° C. or higher and 450° C. or lower. When tantalum nitride is used for the conductor 62a that becomes the gate, the heat treatment temperature is set to 350 The temperature may be set to 370°C or higher and 410°C or lower, preferably 370°C or higher and 400°C or lower. By performing the heat treatment within this temperature range, it is possible to suppress the release of hydrogen from tantalum nitride. Heat treatment is carried out in an inert gas atmosphere or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or The heat treatment is carried out in an atmosphere containing 10% or more of fluorine. The heat treatment may be carried out under reduced pressure. After heat treatment in an inert gas atmosphere, an oxidizing gas was introduced for 10 minutes to compensate for the oxygen that was released. The heat treatment may be carried out in an atmosphere containing at least pm, at least 1%, or at least 10% of Zn. This allows impurities such as hydrogen and water to be removed. The heat treatment using an RTA device is shorter than that using a furnace. This is effective in increasing productivity because it requires only a small amount of time.

[0339] Next, an insulator 69a that will become the insulator 66a is formed. Any insulator or semiconductor may be used as the insulator 66a. The film of a is formed by the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. The insulator 69a is preferably formed while the substrate is heated. The temperature for heating the substrate may be the same as that for the heat treatment described below.

[0340] Next, a semiconductor 69b that will become the semiconductor 66b is formed. The semiconductor 66b may be any semiconductor that can be used as the semiconductor 66b. The film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. It is also preferable to form the semiconductor 66b while heating the substrate. The temperature for heating the substrate may be the same as that for the heat treatment described later. The deposition of the semiconductor 9a and the deposition of the semiconductor 66b are carried out continuously without exposure to the atmosphere. This can reduce the amount of impurities entering the film and at the interface.

[0341] Next, it is preferable to perform a heat treatment on the insulator 69a and the semiconductor 69b. By doing so, it may be possible to reduce the hydrogen concentration in the insulator 66a and the semiconductor 66b. In addition, oxygen vacancies in the insulator 66a and the semiconductor 66b may be reduced. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. Furthermore, tantalum nitride may be used for the conductor 62a that serves as the back gate of the transistor. When using, the heat treatment temperature is 350°C or higher and 410°C or lower, preferably 370°C or higher and 40 By performing heat treatment in this temperature range, tantalum nitride The heat treatment can be carried out in an inert gas atmosphere or an oxidizing gas atmosphere. The heat treatment is carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more. Alternatively, the heat treatment may be performed in an inert gas atmosphere, followed by desorption of the desorbed fluorine. In an atmosphere containing oxidizing gases of 10 ppm or more, 1% or more, or 10% or more to supplement oxygen Heat treatment may be performed. The heat treatment can improve the crystallinity of the insulator 66a and the semiconductor 66b. The heat treatment can be performed by using a lamp. An RTA device can also be used. Heat treatment using an RTA device is more efficient than a furnace. This is effective in increasing productivity because it takes a short time. When CAAC-OS is used as described below, the peak intensity increases by heat treatment. That is, the crystallinity of CAAC-OS increases with heat treatment. .

[0342] By this heat treatment, oxygen is supplied from the insulator 64 to the insulator 69a and the semiconductor 69b. By subjecting the insulator 64 to a heat treatment, it is possible to insulate oxygen very easily. The insulating material can be applied to the body 66a, and the semiconductor material can be applied to the semiconductor 66b.

[0343] Here, the insulator 63 functions as a barrier film that blocks oxygen. By providing the insulating material 64 under the insulating material 64, oxygen diffused into the insulating material 64 is This can prevent the material from diffusing into the lower layers.

[0344] In this way, oxygen is supplied to the insulator that becomes the insulator 66a and the semiconductor that becomes the semiconductor 66b. By reducing oxygen vacancies, high purity intrinsic or substantially high purity silicon with low defect level density can be obtained. A pure intrinsic oxide semiconductor can be obtained.

[0345] Next, a conductor 68 that will become the conductor 68a and the conductor 68b is formed (FIG. 24(C)(D) ) The conductor 68 can be used as the conductor 68a and the conductor 68b described above. The conductor 68 can be formed by a sputtering method, a CVD method, an MBE method, or the like. Alternatively, it can be performed by using a PLD method, an ALD method, or the like. A tantalum nitride film is formed using the sputtering method, and then a tungsten film is formed on top of it. That's fine.

[0346] Next, a resist or the like is formed on the conductor 68, and the resist or the like is used to form an insulator 69a The semiconductor 69b and the conductor 68 are processed into an island shape, and the island-shaped conductor 68, the semiconductor 66b and the insulating layer 68 are formed. The edge body 66a is formed.

[0347] Next, heat treatment may be performed. By the heat treatment, the insulators 64, 63, and Further reducing water or hydrogen in the insulator 65, the insulator 66a, and the semiconductor 66b The heat treatment is carried out at a temperature of 250°C to 650°C, preferably 350°C to 450°C. Furthermore, nitride nitride is formed on the conductor 62a that serves as the back gate of the transistor. When tantalum is used, the heat treatment temperature is set to 350°C or higher and 410°C or lower, preferably 370°C or lower. By performing heat treatment in this temperature range, the nitride film can be The heat treatment can be performed in an inert gas atmosphere. The heat treatment may be carried out in an atmosphere containing an oxidizing gas. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by heating to replenish the desorbed oxygen. Therefore, heat treatment is carried out in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. Heat treatment can also be performed using an RTA device that uses lamp heating. Heat treatment by a station takes less time than by using a furnace, and is therefore effective in increasing productivity.

[0348] The heat treatment carried out up to this point removes impurities such as water and hydrogen that affect oxide semiconductors. The oxide semiconductor can be reduced before the oxide semiconductor is formed. By blocking the via holes formed in the insulating layer 1 with the conductor 121a or the like, The insulator 61 is formed of a material that prevents impurities such as hydrogen contained in the lower layer from diffusing into the upper layer. Furthermore, the temperature of the process performed after the oxide semiconductor film formation can be controlled by adjusting the temperature of the conductor 121a and the like. By keeping the temperature below the temperature at which hydrogen is released, the influence of impurity diffusion can be reduced. This can be done.

[0349] The insulator 66a and the semiconductor 66b are formed, and the surface of the insulator 64 is exposed. By carrying out the treatment, the supply of water and hydrogen to the insulator 66a and the semiconductor 66b is suppressed. While the water or hydrogen in the insulators 64, 63 and 65 is further reduced, It is possible.

[0350] In addition, when forming the insulator 66a and the semiconductor 66b, impurities such as hydrogen and carbon are When using an etching gas containing a pure substance, hydrogen is introduced into the insulator 66a and the semiconductor 66b. In this way, impurities such as carbon may be introduced into the insulator 66a and the semiconductor Further heat treatment after the formation of 66b can remove hydrogen and Impurities such as iron and carbon can be desorbed.

[0351] Next, a resist or the like is formed on the island-shaped conductor 68, and processing is performed using the resist or the like. Then, the conductors 68a and 68b are formed (see FIGS. 24(E) and 24(F)).

[0352] In addition, in the region of the semiconductor 66b that contacts the conductor 68a or the conductor 68b, a low resistance In addition, the semiconductor 66b may be formed between the conductor 68a and the conductor 68b. The thickness of the area overlapping the conductor 68a or the conductor 68b may be smaller than that of the area overlapping the conductor 68a or the conductor 68b. This is because when the conductors 68a and 68b are formed, the upper surface of the semiconductor 66b is It is formed by removing a portion.

[0353] Next, on the insulator 64, the insulator 66a, the semiconductor 66b, the conductor 68a and the conductor 68b The insulator 69c is formed on the insulating film 66c. The insulator or semiconductor that can be used as the insulator 66 may be used. The film c is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Before forming the insulator film that will become the insulator 66c, the surface of the semiconductor 66b or the like is The surface may be etched, for example, by using a plasma containing a rare gas. Thereafter, an insulator that will become the insulator 66c is continuously formed without being exposed to the atmosphere. This reduces the amount of impurities entering the interface between the semiconductor 66b and the insulator 66c. Impurities present at the interface between films may be more easily diffused than impurities within the film. Therefore, by reducing the amount of impurities mixed in, a stable current can be obtained in the transistor. It can be given a special characteristic.

[0354] Next, an insulator 72a that will become the insulator 72 is formed on the insulator 69c. The insulator 72 may be any insulator that can be used as the insulator 72 described above. The film of a is formed by the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. For example, the insulator 69c can be formed by using a PECVD method. The insulator 69c and the insulator 72a may be formed by depositing a film of silicon or the like. By performing this process continuously without exposing it to the atmosphere, the incorporation of impurities into the film and at the interface is reduced. It is possible.

[0355] Next, a conductor that will become the conductor 74 is formed on the insulator 72. The conductor 74 may be any conductor that can be used as the conductor 74. The conductive film to be formed is made by sputtering, CVD, MBE or PLD, AL This can be done using Method D or the like. For example, a titanium nitride film is formed as the conductor 74 by the ALD method, and then A tungsten film may be formed on the substrate by sputtering.

[0356] Next, a resist or the like is formed on the conductor that will become the conductor 74, and The metal is processed to form a conductor 74 (see FIGS. 25(A) and 25(B)).

[0357] Next, an insulator that will become the insulator 79 is formed on the insulator 72a. The insulating material may be any insulating material that can be used as the insulator 79 described above. The insulator film to be formed is made by sputtering, CVD, MBE or PLD method, A For example, the insulator 79 can be formed by ALD. A film of gallium oxide or aluminum oxide may be formed by using this method.

[0358] Next, a resist or the like is formed on the insulator that will become the insulator 79. The insulating material 79 is formed by processing (see FIGS. 25(C) and (D)).

[0359] Next, the insulator 7 is applied on the insulator 64, the insulator 79, the conductor 68a, the conductor 68b, etc. The insulator 77 may be any of the insulators described above. It is preferable that the insulator 77 contains few impurities such as hydrogen, water, and nitrogen oxides. The method can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, silicon oxynitride or the like can be formed as the insulator 77 by using the PECVD method. A film may be formed.

[0360] Next, it is preferable to improve the flatness of the upper surface of the insulator 77 by using a CMP method or the like. .

[0361] Here, as shown in FIG. 17, a scribe line 13 is formed by using a lithography method or the like. In the vicinity of the region overlapping with the insulating film 8, the insulating film 67, the insulating film 65, the insulating film 63, the insulating film 64, and the insulating film 8 are Preferably, the rim 77 has an opening formed therein.

[0362] Next, an insulator 78 is formed on the insulator 77. The insulator 78 is made of the above-mentioned material. The insulator 78 may be formed by sputtering, CV This can be done by using the D method, MBE method, PLD method, ALD method, etc. In the vicinity of the scribe line 138 shown in FIG. 1, the insulator 67, the insulator 65, An insulator 78 is formed to cover the side surfaces of the insulators 63, 64, and 77, and the opening Insulator 78 and insulator 61 come into contact with each other at this point.

[0363] The insulator 78 is preferably formed by plasma deposition, using a sputtering method. It is more preferable to carry out the process by sputtering in an atmosphere containing oxygen. Even more preferable.

[0364] The sputtering method uses a direct current (DC) power supply for the sputtering power supply. Current sputtering method, and pulsed DC sputtering method, which applies a bias in a pulsed manner. RF (Radio Frequency) sputtering method, which uses a high frequency power supply for sputtering. A sputtering method may also be used. A magnetron having a magnet mechanism inside the chamber may also be used. bias sputtering, which applies voltage to the substrate during film formation; reactive A reactive sputtering method performed in a gas atmosphere may also be used. The oxygen gas flow rate and film formation power for sputtering may be adjusted depending on the amount of oxygen. The amount may be determined appropriately depending on the amount added, etc.

[0365] Here, the insulator 78 is a material that blocks oxygen, hydrogen, water, etc., such as aluminum oxide. For example, a sputtered oxide insulating film is used as the insulator 78. The aluminum oxide film can be formed using the ring method. It is preferable to form an aluminum oxide film. By using the ion implantation method, it is possible to prevent the formation of pinholes, and therefore the hydrogen in the insulator 61 can be prevented. The blocking performance against water can be further improved.

[0366] By forming the insulator 78 by sputtering, the surface of the insulator 77 is simultaneously formed. Oxygen is added near the surface (the interface between the insulator 77 and the insulator 78 after the insulator 78 is formed). In this case, oxygen is added to the insulator 77 as, for example, oxygen radicals. The state of oxygen is not limited to this. Oxygen is insulating in the form of oxygen atoms or oxygen ions. The oxygen may be added to the insulator 77. When oxygen is added, oxygen is stoichiometrically added to the insulator 77. Oxygen may be contained in excess of the composition, and in this case, it can be called excess oxygen.

[0367] It is preferable to heat the substrate when forming the insulator 78. The temperature may be 0°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. When tantalum nitride is used for the conductor 62a that serves as the back gate of the transistor, the above-mentioned The treatment temperature is set to 350°C or higher and 410°C or lower, preferably 370°C or higher and 400°C or lower. By performing heat treatment within this temperature range, hydrogen is released from tantalum nitride. This can suppress the following.

[0368] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 64 or the insulating film The oxygen added to the insulator 77 is diffused and supplied to the insulator 66a, the semiconductor 66b, and the insulator 66c. The heat treatment can be carried out at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. The heat treatment should be carried out at 50°C or less. The heat treatment should be carried out in an inert gas atmosphere or in an oxidizing gas atmosphere at 10ppm. The heat treatment is carried out in an atmosphere containing more than m, more than 1%, or more than 10%. Heat treatment can also be performed using an RTA device that uses lamp heating.

[0369] The temperature of this heat treatment is preferably lower than that of the heat treatment performed after the semiconductor 66b is formed. The temperature difference between the heat treatment after the semiconductor 66b formation and the heat treatment after the semiconductor 66b formation is 20° C. or more and 150° C. or less, preferably 40° C. or less. ℃ or more and 100℃ or less. This prevents excess oxygen (oxygen) from being released from the insulator 64, etc. The heat treatment after the formation of the insulator 78 can be performed by the same heating method. When the heating process can be performed by heating each layer during the deposition process (for example, when the insulator 78 is deposited), In some cases, this may not be necessary (if equivalent heating is performed).

[0370] By this heat treatment, the oxygen added to the insulators 64 and 77 is converted into the insulators 64 and 77. The oxygen is diffused into the insulator 72. The insulator 78 is an insulator that is less permeable to oxygen than the insulator 77. This insulator 78 functions as a barrier film that blocks oxygen. Since the insulating layer 77 is formed on the insulating layer 77, oxygen diffusing through the insulating layer 77 does not diffuse above the insulating layer 77. The insulating material 77 is diffused mainly in the lateral direction or downward direction. When the insulator 78 is heated, oxygen is diffused into the insulators 64 and 77 at the same time as the addition. This can be done.

[0371] Oxygen diffusing through the insulator 64 or the insulator 77 penetrates the insulators 66a, 66c and the semiconductor At this time, the insulator 63 having the function of blocking oxygen is supplied to the insulator 66b. By providing the insulating material 64 below the insulating material 64, oxygen diffused into the insulating material 64 can be easily absorbed by the insulating material 64. Furthermore, in the vicinity of the scribe line 138 shown in FIG. In this case, the side surfaces of the insulator 77 are covered with the insulators 78 and 61. This prevents oxygen from diffusing out of the insulator 78, fills the insulator 77 with oxygen, and Oxygen can be supplied from the semiconductor 66b to the insulator 66a, the semiconductor 66b, and the insulator 66c.

[0372] Furthermore, during the heat treatment, impurities such as hydrogen and water diffused from the lower layer are removed by the insulator 61 and The via hole of the insulator 61 is blocked by a conductor 121a or the like provided therein, and the upper surface of the insulator 77 is blocked by a conductor 121b or the like provided therein. The insulator 78 blocks impurities such as hydrogen and water that diffuse from the surface and sides. As a result, the insulators 61 and 78 are wrapped around the insulators 77 and 78. The amount of impurities such as hydrogen and water in the insulator 66a, the insulator 66c, and the semiconductor 66b is Furthermore, impurities such as hydrogen can be reduced by bonding with oxygen in the insulator 77. Therefore, in the insulator 77, hydrogen, By reducing the amount of impurities such as water, the supply of oxygen can be promoted.

[0373] In this way, the insulator 66a, the insulator 66c and the semiconductor 66b, especially the semiconductor 66b The diffusion of impurities such as water and hydrogen is suppressed in the region where the channel is formed, and oxygen is effectively introduced. In this way, oxygen can be supplied to the insulator 66a, the insulator 66c, and the semiconductor 66b. By supplying oxygen and reducing oxygen vacancies, high-purity intrinsic or real silicon with low defect level density can be obtained. A qualitatively high-purity intrinsic oxide semiconductor can be obtained.

[0374] The heat treatment after the formation of the insulator 78 may be performed at any time after the formation of the insulator 78.

[0375] In this manner, the transistor 60a can be formed.

[0376] In this manner, by using the manufacturing method of a semiconductor device described in this embodiment mode, a stable A semiconductor device having a transistor with good electrical characteristics can be provided. By using the manufacturing method of the semiconductor device shown in the embodiment, a transistor with a small leakage current when non-conducting can be obtained. A semiconductor device having a transistor can be provided. By using the method for fabricating a semiconductor device, a transistor having normally-off electrical characteristics can be obtained. In addition, a semiconductor device can be provided by the method for manufacturing the semiconductor device described in this embodiment. By using this method, a semiconductor device having a highly reliable transistor can be provided. do.

[0377] The structure and method described in this embodiment mode may be combined as appropriate with the structure and method described in other embodiment modes. It is possible.

[0378] (Embodiment 2) In this embodiment, the oxide semiconductor included in the semiconductor device of one embodiment of the present invention will be described in detail. The following explains this.

[0379] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0380] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor be.

[0381] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0382] Amorphous structures are generally isotropic and have no heterogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The position is not fixed, the bond angle is flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0383] That is, a stable oxide semiconductor is completely amorphous. s) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, a periodic structure in a small area) An oxide semiconductor having an amorphous structure cannot be called a completely amorphous oxide semiconductor. ike OS is not isotropic, but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. stomach.

[0384] <caac-os> First, let me explain about CAAC-OS.

[0385] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0386] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystal structure was analyzed by the out-of-plane method. As shown in FIG. 29(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so it is In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface, or approximately perpendicular to the upper surface. In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferable that the C-OS does not exhibit such a peak.

[0387] On the other hand, in-pl, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the ane method, a peak appears at 2θ around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. The sample is then rotated around the normal vector of the sample surface as the axis (φ axis) for analysis (φ scan). Even if this is done, no clear peak appears as shown in Figure 29(B). When 2θ is fixed at around 56° and φ is scanned for ZnO4, the As shown, six peaks attributable to the crystal plane equivalent to the (110) plane are observed. Structural analysis using XRD revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0388] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was performed parallel to the surface on which the CAAC-OS was formed. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This diffraction pattern may contain I The spots due to the (009) plane of the nGaZnO4 crystal are included. Diffraction also shows that the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is formed On the other hand, for the same sample, the direction of the sample surface is perpendicular to the sample surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly to the ) is shown. From Figure 29(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a beam diameter of 300 nm also revealed that the pea contained in CAAC-OS It can be seen that the a-axis and b-axis of the lattice do not have any orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Figure 29(E) is thought to be due to the (110) plane. It is thought that...

[0389] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. It may not be possible to clearly identify the boundary. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0390] Figure 30(A) shows a high-resolution image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. For high-resolution TEM observation, spherical aberration correction (SCA) was used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0391] From Figure 30(A), it is possible to confirm the pellet, which is the region where metal atoms are arranged in layers. The size of a single pellet can be over 1 nm or over 3 nm. Therefore, the pellets can be called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with CAA It reflects the unevenness of the surface on which the C-OS is formed or the top surface, and the unevenness of the surface on which the CAAC-OS is formed or It is parallel to the top surface.

[0392] 30(B) and 30(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Figures 30(D) and 30(E) show Cs-corrected high-resolution TEM images of the C-OS surface. 30(B) and 30(C) are processed images, respectively. First, the processing method of FIG. 30(B) is performed using a fast Fourier transform (FFT). Then, the FFT image is obtained by Fourier Transform (FFT). In the acquired FFT image, the origin is used as the reference point, and the -1 to 5.0 nm -1 The range between Next, the masked FFT image is subjected to inverse fast Fourier transform (IFFT) : Inverse Fast Fourier Transform) processing The image thus obtained is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. This shows the child array.

[0393] In Figure 30(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the broken line is the connection between the pellets. The broken line indicates the hexagonal shape of the pellet. The shape of the let is not limited to a regular hexagon, but is often a non-regular hexagon.

[0394] In FIG. 30(E), a grid is formed between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The dotted lines indicate the changes in the orientation of the child array, and the dashed lines indicate the changes in the orientation of the lattice array. Even near the dotted line, no clear grain boundaries can be seen. When you connect the surrounding lattice points around the center, you can see the formation of distorted hexagons, pentagons, and / or heptagons. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction. The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is thought to be because it is possible to

[0395] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor with lane-anchored crystals. Cut.

[0396] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0397] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0398] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 traps hydrogen and becomes a carrier generation source.

[0399] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than Such an oxide semiconductor can be a high-purity intrinsic or The CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0400] <nc-os> Next, we will explain nc-OS.

[0401] We will explain the analysis of nc-OS by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0402] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in 1(A) was observed. In addition, the diffraction pattern ( The nanobeam electron diffraction pattern is shown in Figure 31(B). Therefore, the nc-OS probe diameter is 50 nm. However, when an electron beam with a probe diameter of 1 nm is incident, the order is not observed. Order is confirmed by injecting light.

[0403] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 31(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is possible to assume that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals have highly ordered regions, i.e., crystals. Therefore, there are some areas where a regular electron diffraction pattern is not observed.

[0404] FIG. 31(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film is formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. How to identify the crystal areas and areas where no clear crystal areas can be identified The crystal parts contained in the nc-OS have a size of 1 nm to 10 nm. The size of the crystal is often between 1 nm and 3 nm. An oxide semiconductor with a size of greater than 10 nm and less than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called a polycrystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as pellets below.

[0405] In this way, nc-OS can be used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the SiO2 film, there is no regularity in the crystal orientation between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0406] In addition, since there is no regularity in the crystal orientation between the pellets (nanocrystals), nc-OS , oxidation with RANC (Random Aligned nanocrystals) semiconductors or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0407] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0408] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0409] Figure 32 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 electrons (e - ) a-like OS after irradiation These are high-resolution cross-sectional TEM images. Figures 32(A) and 32(B) show that a-like O It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is assumed to be a density region.

[0410] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0411] As samples, a-like OS, nc-OS, and CAAC-OS were prepared. Both samples are In-Ga-Zn oxides.

[0412] First, high-resolution cross-sectional TEM images of each sample are acquired. All of the materials have crystalline parts.

[0413] The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers along the c-axis. The distance between these adjacent layers is determined by the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is referred to as InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0414] Figure 33 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. e The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 33, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was left behind (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, it can be seen that the size of the crystals grows to about 1.9 nm in the case of n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of Fig. 33. Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is constant regardless of the cumulative electron irradiation dose. , and are approximately 1.3 nm and 1.8 nm, respectively. The Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0415] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0416] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the nc-OS. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0417] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0418] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density corresponding to a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions combined. However, the density can be estimated by using as few types of single crystals as possible. It is preferable to estimate them together.

[0419] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0420] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0421] (Embodiment 3) In this embodiment, a semiconductor device using a transistor according to one embodiment of the present invention will be described. An example of the circuit of the device will be described.

[0422] <Circuit> An example of a circuit of a semiconductor device using a transistor according to one embodiment of the present invention will be described below. This article explains:

[0423] <CMOSインバータ> The circuit diagram shown in FIG. 34A includes a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The circuit shown in FIG. 34(A) is a circuit diagram of an OS inverter. 2200 is formed using the transistor 60a or the transistor 60b shown in FIG. 15. The transistor 2100 may be replaced by the transistor 90a shown in FIG. It can be formed using the heater 90b.

[0424] The semiconductor device shown in FIG. 34(A) is a semiconductor substrate having a p-channel transistor. By fabricating a thin film transistor and fabricating an n-channel transistor above it, the area occupied by the element can be reduced. In other words, the degree of integration of the semiconductor device can be increased. Fabrication of p-channel transistors and p-channel transistors using the same semiconductor substrate The process can be simplified compared to the conventional method, thereby increasing the productivity of semiconductor devices. In addition, the yield of the semiconductor device can be increased. The type transistor has an LDD (Lightly Doped Drain) region, a shallow In some cases, complex processes such as trench structure and strain design can be omitted. Compared to fabricating a silicon-type transistor using a semiconductor substrate, productivity and yield are improved. It may be possible to increase the

[0425] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 34B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called CMOS analog switch. ) can be implemented by replacing transistor 2200 with transistor 60a shown in FIG. 15. The transistor 2100 can be formed using the transistor 60b. It can be formed using a transistor 90a or a transistor 90b.

[0426] <Storage device 1> A memory device using a transistor according to one embodiment of the present invention and capable of storing stored contents even when power is not supplied An example of a semiconductor device (memory device) that can retain data and has no limit on the number of times it can be written is shown in Figure 3. Shown in 5.

[0427] The semiconductor device shown in FIG. 35A includes a transistor 3200 using a first semiconductor and a second semiconductor. The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 is the same as the transistor 2100 described above. Here, the transistor 3200 is configured with the above-mentioned element layer 50, and the transistor The capacitor 3300 is formed by the element layer 30, and the capacitor 3400 is formed by the element layer 40. As a result, the circuit shown in FIG. 35A can be formed using the semiconductor device shown in FIG. 16 or the like. do.

[0428] The transistor 3300 is preferably a transistor with low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor 300. The low off-state current of the STAR 3300 allows for long-term storage of specific nodes in the semiconductor device. It is possible to retain the stored contents, i.e., no refresh operation is required, and This allows for extremely low frequency refresh operations, resulting in low power consumption. It becomes a conductor device.

[0429] In FIG. 35A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 3 005 is electrically connected to the other electrode of the capacitor 3400 .

[0430] The semiconductor device shown in FIG. 35A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. be.

[0431] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and The voltage is applied to a node FG electrically connected to one electrode of the capacitor 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). The charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) ) is given. Then, the potential of the fourth wiring 3004 is given to the transistor. The potential is set to a level at which the transistor 3300 is in a non-conducting state. As a result, charge is held (retained) at node FG.

[0432] Since the off-state current of the transistor 3300 is small, the charge of the node FG is maintained for a long period of time. Retained.

[0433] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the second wiring The line 3002 takes on a potential corresponding to the amount of charge held in the node FG. If the transistor 3200 is an n-channel type, a high level voltage is applied to the gate of the transistor 3200. The apparent threshold voltage V under load th_H is a transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate of th_L Here, the apparent threshold voltage is the voltage at which the transistor 3200 The potential of the fifth wiring 3005 required to make the fifth wiring 3005 in a "conductive state" is referred to as the potential of the fifth wiring 3005. Then, the potential of the fifth wiring 3005 is V th_H and V th_L The potential between For example, in a write operation, the charge applied to node FG can be determined by When a high level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 ( >V th_H ), transistor 3200 is in a "conducting state." Meanwhile, node F When a low level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 (< V th_L ), transistor 3200 remains in a "non-conducting state." Therefore, by determining the potential of the second wiring 3002, the data stored in the node FG can be read. It can be seen.

[0434] When memory cells are arranged in an array, the information of a desired memory cell is read out. For example, in a memory cell that does not read information, The transistor 3200 is in a "non-conducting state" regardless of the charge applied to the FG terminal. Electric potential, i.e., V th_H By applying a lower potential to the fifth wiring 3005, a desired memory Alternatively, the memory cell may be configured so that only the information in the memory cell can be read. In this case, the transistor 3200 is in a "conducting state" regardless of the charge applied to the node FG. ", that is, V th_L By applying a higher potential to the fifth wiring 3005, In this way, it is possible to read out only the information from the desired memory cell.

[0435] In the above, an example in which two types of charges are held at node FG is shown. The semiconductor device according to the present invention is not limited to this. For example, the node FG of the semiconductor device It is also possible to have a configuration in which three or more types of charges can be held in the electrode. The semiconductor device can be made multi-valued to increase the storage capacity.

[0436] <Storage device 2> The semiconductor device shown in FIG. 35B is different from the semiconductor device shown in FIG. 35A in that it does not include the transistor 3200. This is different from the semiconductor device shown in FIG. This allows writing and holding of information. Here, the circuit shown in FIG. , the transistor 3300 is replaced with the transistor 60a or the transistor 60b shown in FIG. The capacitor element 3400 can be formed using the capacitor element 80a shown in FIG. Furthermore, a sense amplifier can be formed in the lower layer of the semiconductor device shown in FIG. In this case, the transistor 90a or the transistor 90b shown in FIG. It can be formed using the transistor 90b.

[0437] How to read data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 340, which are in a floating state, 0 is electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is The potential of one of the electrodes of the capacitor 3400 (or the charge stored in the capacitor 3400) and take different values.

[0438] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the The capacitance component of the third wiring 3003 is CB, and the capacitance of the third wiring 3003 before the charge is redistributed is If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+CV) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), , the potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+CV1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=( It can be seen that this is higher than (CB×VB0+CV0) / (CB+C)).

[0439] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0440] In this case, the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied as the transistor 3300. may be stacked on the drive circuit.

[0441] The semiconductor device described above includes a transistor using an oxide semiconductor and having low off-state current. By using this function, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store it for a long period of time. The content can be preserved.

[0442] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate Since there is no injection or extraction of electrons from the floating gate, there is no degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is a problem in the past, and reliability has improved dramatically. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0443] <Storage device 3> Regarding a modification of the semiconductor device (memory device) shown in FIG. 35(A), a circuit diagram shown in FIG. This will be used to explain.

[0444] The semiconductor device shown in FIG. 36 includes transistors 4100 to 4400 and capacitors The transistor 4100 includes an element 4500 and a capacitor 4600. A transistor similar to the transistor 3200 can be used, and the transistor 420 0 to 4400 can be transistors similar to the transistor 3300 described above. Although not shown in FIG. 36, the semiconductor device shown in FIG. 36 can be implemented in a matrix. The semiconductor device shown in FIG. 36 includes a wiring 4001, a wiring 4003, and a wiring 400 5 to 4009, the writing and reading of the data voltage is controlled according to the signal or potential applied to 36, the transistor 4100 shown in FIG. It can be formed using transistor 90a or transistor 90b. The transistors 4200, 4300 and 4400 are the transistors shown in FIG. The capacitor element 4500 and the transistor 60b can be formed using the capacitor element 4500 and the transistor 60a. The capacitor 4600 can be formed using the capacitor 80a shown in FIG.

[0445] One of the source and the drain of the transistor 4100 is connected to a wiring 4003. The other of the source and drain of the transistor 4100 is connected to a wiring 4001. 36, the conductivity type of the transistor 4100 is shown as a p-channel type, but it is an n-channel type. Good too.

[0446] The semiconductor device shown in FIG. 36 has two data holding units. For example, the first data holding unit is one of the source and drain of the transistor 4400 connected to the node FG1, Between one electrode of the element 4600 and one of the source and drain of the transistor 4200 The second data storage unit stores the charge in the transistor connected to node FG2. the gate of the transistor 4100, the other of the source or drain of the transistor 4200, A charge is transferred between one of the source or drain of 4300 and one electrode of the capacitor element 4500. Hold.

[0447] The other of the source and the drain of the transistor 4300 is connected to a wiring 4003. The other of the source and drain of the transistor 4400 is connected to a wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4300 is connected to a wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the element 0 is connected to a wiring 4009.

[0448] The transistors 4200 to 4400 control writing of data voltages and retention of electric charges. The transistors 4200 to 4400 function as switches. In this case, a transistor with a low current (off-state current) that flows between the source and drain is used. As a transistor with a low off-state current, it is preferable to use a transistor having an oxide layer in the channel formation region. Preferably, the transistor is an OS transistor having an oxide semiconductor. The advantage of silicon-based transistors is that they have low off-state current and can be stacked with silicon-based transistors. In FIG. 36, the conductivity types of the transistors 4200 to 4400 are n-channel. However, it may be a p-channel type.

[0449] The transistors 4200, 4300, and 4400 are oxidized. Even if the transistor uses a compound semiconductor, it is preferable to provide it in a separate layer. The semiconductor device shown in FIG. 6 includes a first layer 4 having a transistor 4100 as shown in FIG. 021, and a second layer 4022 having transistors 4200 and 4300. and a third layer 4023 having a transistor 4400. By stacking layers having transistors, the circuit area can be reduced, and The device can be made smaller.

[0450] Next, the operation of writing information into the semiconductor device shown in FIG. 36 will be described.

[0451] First, the data voltage is written to the data storage unit connected to node FG1 (hereinafter referred to as This will be referred to as write operation 1. The data voltage to be written to the connected data storage unit is V D1 and the threshold voltage of the transistor 4100 is The voltage is Vth.

[0452] In write operation 1, the wiring 4003 is connected to V D1 After setting the wiring 4001 to ground potential, , and are electrically floating. Also, the wirings 4005 and 4006 are set to high level. 4007 to 4009 are set to a low level. Then, the node FG The potential of the wiring 4 rises, and a current flows through the transistor 4100. The potential of 001 rises. Also, the transistor 4400 and the transistor 4200 are in a conducting state. Therefore, as the potential of the wiring 4001 increases, the potentials of the nodes FG1 and FG2 The potential of the node FG2 rises, and the potential between the gate and source of the transistor 4100 rises. When the voltage (Vgs) of the transistor 4100 reaches the threshold voltage Vth of the transistor 4100, the transistor 41 Therefore, the potential of the wiring 4001 and the nodes FG1 and FG2 The rise of V stopped. D1 Vth has dropped from D1 -Vth" and becomes constant.

[0453] In other words, the V given to wire 4003 D1 is generated by the current flowing through transistor 4100. The potential is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 increase. The potential of node FG2 becomes "V D1 -Vth" and the Vgs of the transistor 4100 becomes Vth, and the current stops.

[0454] Next, a data voltage write operation (hereinafter, This will be called write operation 2. The data voltage written to the memory is V D2 It will be explained as follows.

[0455] In write operation 2, wire 4001 is connected to V D2 After setting the wiring 4003 to ground potential, , and are electrically floating. The wiring 4007 is set to a high level. 4006, 4008, and 4009 are set to low level. Transistor 4300 is set to the conductive state. Therefore, the potential of the node FG2 is also set to low level. The voltage of the wiring 4003 decreases, and a current flows through the transistor 4100. The potential rises. In addition, the transistor 4300 is turned on. As the potential at node FG2 rises, the potential at node FG3 rises. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, the transistor Therefore, the current flowing through the wiring 4003 and the node FG2 is increased. The rise stops, V D2 Vth has dropped from D2 -Vth" and becomes constant.

[0456] In other words, the V given to wire 4001 D2 is generated by the current flowing through transistor 4100. is applied to the wiring 4003, and the potential of the node FG2 increases. The potential of FG2 is "V D2 -Vth", the Vgs of transistor 4100 is Vth At this time, the potential of the node FG1 is 4400 are in a non-conducting state, and the "V D1 -Vth" is maintained will be done.

[0457] In the semiconductor device shown in FIG. 36, after writing data voltages to a plurality of data holding units, The line 4009 is set to a high level, and the potentials of the nodes FG1 and FG2 are raised. The transistor is turned off, preventing the transfer of charge and maintaining the written data voltage. do.

[0458] By the above-described operation of writing data voltages to the nodes FG1 and FG2, multiple data The data voltage can be held in the data holding section. D1 -Vth" and "V D2 -Vth" was used as an example, but these are multi-value devices. Therefore, each data storage unit stores 4 bits of data. When holding data, 16 values ​​of "V D1 -Vth" and "V D2 -Vth" can be used.

[0459] Next, the operation of reading information from the semiconductor device shown in FIG. 36 will be described.

[0460] First, the data voltage is read from the data storage unit connected to node FG2 (hereinafter referred to as (This is called read operation 1.) will now be described.

[0461] In the read operation 1, the wiring 400 is precharged and then brought into an electrically floating state. 3 is discharged. The wirings 4005 to 4008 are set to a low level. The wiring 4009 is set to a low level. The potential of the electrically floating node FG2 is set to low level. D2 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. The flow of current reduces the potential of the wiring 4003, which is in an electrically floating state. As the potential decreases, the Vgs of transistor 4100 decreases. When the Vgs of the transistor 4100 becomes the Vth of the transistor 4100, the current flowing through the transistor 4100 That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2, D2 -Vth " is a value that is larger than Vth by "V D2 The potential of this wiring 4003 is This corresponds to the data voltage of the data storage section connected to FG2. The data voltage undergoes A / D conversion and the data is acquired from the data storage section connected to node FG2. do.

[0462] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching from high to low allows current to flow through transistor 4100. As a result, the potential of the floating wiring 4003 drops to "V D2 " Tiger In Transistor 4100, the "V D2 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D 2" is read out.

[0463] After acquiring the data from the data storage section connected to node FG2, transistor 4300 is in a conducting state, and "V D2 -Vth" is discharged.

[0464] Next, the charge held at node FG1 is distributed to node FG2, and the charge held at node FG1 is transferred to node FG3. The data voltage of the data storage unit connected to node FG1 is transferred to the data storage unit connected to node FG2. Then, the wirings 4001 and 4003 are set to low level, and the wiring 4006 is set to high level. In addition, the wiring 4005 and the wirings 4007 to 4009 are set to low level. When node FG1 is in a conductive state, the charge of node FG1 is shared with node FG2.

[0465] Here, the potential after the charge distribution is the written potential "V D1 -Vth". Therefore, the capacitance value of the capacitor 4600 is set to be larger than the capacitance value of the capacitor 4500. Alternatively, the potential "V D1 -Vth" is the same The potential "V D2 It is preferable to set the capacitance to be larger than "-Vth". By changing the ratio of the values ​​and increasing the potential to be written in advance, the potential after the charge distribution The change in potential due to the distribution of charge will be described later.

[0466] Next, the data voltage is read from the data storage unit connected to the node FG1 (hereinafter, This will be referred to as read operation 2.

[0467] In the read operation 2, the wiring 400 is precharged and then brought into an electrically floating state. 3 is discharged. The wirings 4005 to 4008 are set to a low level. The wiring 4009 is The line 4009 is set to a high level during precharge and then set to a low level. By using this as a bell, the electrically floating node FG2 is set to the potential "V D1 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. The flow of current reduces the potential of the electrically floating wiring 4003. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When Vgs becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D1 -Vth" Vth is larger than Vth. D1 The potential of the wiring 4003 is The data voltage of the data storage section connected to G1 corresponds to the data of the analog value that is read out. The voltage of the capacitor undergoes A / D conversion and acquires data from the data storage section connected to node FG1. This completes the read operation of the data voltage to the data storage unit connected to node FG1. .

[0468] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching from high to low allows current to flow through transistor 4100. As a result, the potential of the floating wiring 4003 drops to "V D1 " Tiger In Transistor 4100, the "V D1 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D "1" is read out.

[0469] By the above-described operation of reading the data voltages from the nodes FG1 and FG2, a plurality of The data voltage can be read from the data storage unit. For example, the node FG1 and the node FG2 stores 4 bits (16 values) of data, for a total of 8 bits (256 values) In FIG. 36, the first layer 4021 to the third layer 4022 can store data. However, by forming further layers, the surface of the semiconductor device can be It is possible to increase the storage capacity without increasing the product.

[0470] The potential to be read is a voltage that is Vth higher than the written data voltage. Therefore, the "V D1 -Vth" and "V D2 As a result, the Vth of the memory cell This improves the storage capacity per unit and makes the read data closer to the correct data. Therefore, the reliability of the data can be improved.

[0471] <Storage device 4> The semiconductor device shown in FIG. 35C includes a transistor 3500 and a sixth wiring 3006. This differs from the semiconductor device shown in FIG. It is possible to write and store information in the same way as in a semiconductor device. The transistor 3500 may be the same as the transistor 3200 described above. . Here, the transistor 3200 and the transistor 3500 are configured in the element layer 50. The transistor 3300 is formed by the element layer 30, and the capacitor 3400 is formed by the element layer 40. By constructing the circuit shown in FIG. 35(A), the semiconductor shown in FIG. 10(A) or FIG. 10(B) can be realized. The circuit shown in FIG. 35C can be formed by a single device. 15. The transistor 3500 is a transistor 90a or a transistor 90b shown in FIG. 13. The transistor 3300 can be formed using transistor 60b, 14. The capacitor element 3400 can be formed using transistor 60a or transistor 60b. The capacitor 80a shown in FIG.

[0472] The sixth wiring 3006 is electrically connected to the gate of the transistor 3500. One of the source and drain of the transistor 3500 is electrically connected to the drain of the transistor 3200. The other of the source and drain of the transistor 3500 is electrically connected to a third wiring 3003. is connected to.

[0473] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0474] (Fourth embodiment) In this embodiment, a circuit configuration to which the OS transistor described in the above embodiment can be applied is described. An example of the configuration will be described with reference to FIGS.

[0475] FIG. 37A shows a circuit diagram of an inverter. An inverter 800 receives a voltage at an input terminal IN. The inverter 800 outputs a signal obtained by inverting the logic of a signal from the output terminal OUT. The signal S BG Switching the electrical characteristics of OS transistors It is a signal that can be used.

[0476] FIG. 37B shows an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be fabricated using CMOS (Complementary Metal Oxide Semiconductor) transistors, Metal Oxide Semiconductor inverter (CMOS inverter) It can be produced at a lower cost than when producing a conventional photodiode (photodiode).

[0477] The inverter 800 having the OS transistor is a C inverter made of Si transistors. The inverter 800 can be placed on a CMOS circuit. Therefore, it is possible to suppress an increase in the circuit area due to the addition of the inverter 800.

[0478] The OS transistors 810 and 820 have a first gate that functions as a front gate and a back gate. The second gate acts as a lock gate and the first gate acts as either a source or a drain. It has one terminal and a second terminal that functions as the other of the source or drain.

[0479] The first gate of OS transistor 810 is connected to the second terminal. The second gate of 10 is the signal S BG The OS transistor 810 is connected to a wiring that supplies The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The terminal is connected to the output terminal OUT.

[0480] A first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. is connected to the wiring that gives

[0481] FIG. 37C is a timing chart for explaining the operation of the inverter 800. In the timing chart of Figure 37(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are Signal waveform, signal S BG The signal waveform and the threshold voltage of the OS transistor 810 (FET 810) The change in the voltage is shown.

[0482] signal S BG is applied to the second gate of the OS transistor 810, The threshold voltage of 810 can be controlled.

[0483] signal S BG is the voltage V for shifting the threshold voltage negatively BG_A , threshold voltage Voltage V for shifting the phase BG_B The second gate has a voltage V BG_A Give Thus, the OS transistor 810 has a threshold voltage V TH_A can be negatively shifted to Also, the second gate is connected to a voltage V BG_B By providing Voltage value V TH_B can be shifted positively to

[0484] To visualize the above explanation, Figure 38(A) shows one of the electrical characteristics of a transistor. 1 shows a Vg-Id curve.

[0485] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A of By increasing the value of the curve, the curve is shifted to the curve indicated by the dashed line 840 in FIG. 38(A). The electrical characteristics of the OS transistor 810 can be expressed as follows: Voltage V BG_B By making it smaller, the curve represented by the solid line 841 in FIG. 38(A) As shown in FIG. 38A, the OS transistor 810 signal S BG voltage V BG_A Or voltage V BG_B By switching like this, the threshold The value voltage can be shifted either positively or negatively.

[0486] The threshold voltage is V TH_B By shifting it to the positive side, the OS transistor 810 This state can be visualized in Figure 38(B). As shown in FIG. 38B, the current I B Mastering Therefore, when the signal applied to the input terminal IN is high level, the OS trigger When the transistor 820 is in the ON state (ON), it causes the voltage at the output terminal OUT to drop sharply. It is possible.

[0487] As shown in FIG. 38B, the current flowing through the OS transistor 810 is difficult. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 831 can be changed sharply. Since it is possible to reduce the through current flowing between the wiring that supplies S, it is possible to achieve low power consumption. The action can be performed.

[0488] Also, the threshold voltage is V TH_A By shifting the OS transistor The capacitor 810 can be set in a state where current can easily flow. As shown in Figure 38(C), the current I A At least Flow I B Therefore, the signal applied to the input terminal IN is low level. When the OS transistor 820 is in the OFF state, the voltage of the output terminal OUT is rapidly increased. can be increased to.

[0489] As shown in FIG. 38C, the current easily flows through the OS transistor 810. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 832 can be changed sharply.

[0490] In addition, signal S BG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of the controller 820 is switched, that is, before time T1 or T2. For example, as shown in FIG. 37(C), when the signal applied to the input terminal IN is at a high level, Before the switching time T1, the threshold voltage V TH_A to threshold voltage V TH_B OS Tra It is preferable to switch the threshold voltage of the transistor 810. As shown in the figure, the threshold voltage Vth is set to 0 V before the time T2 when the signal applied to the input terminal IN is switched to low level. Voltage V TH_B to threshold voltage V TH_A The threshold voltage of the OS transistor 810 is switched to It is preferable that

[0491] In the timing chart of FIG. 37(C), the signal S BG However, other configurations may be used. For example, a configuration for controlling the threshold voltage The voltage for this purpose is held at the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. Shown below.

[0492] 39A, in addition to the circuit configuration shown in FIG. 37B, an OS transistor 850 The first terminal of OS transistor 850 is connected to the second gate of OS transistor 810. The second terminal of the OS transistor 850 is connected to a voltage V BG_B (or electricity Pressure V BG_A The first gate of the OS transistor 850 is connected to a wiring that provides a signal No. S F The second gate of the OS transistor 850 is connected to a line that supplies a voltage V BG _B (or voltage V BG_A ) is connected to the wiring that provides

[0493] The operation of FIG. 39(A) will be explained using the timing chart of FIG. 39(B).

[0494] The voltage for controlling the threshold voltage of the OS transistor 810 is determined by the signal applied to the input terminal IN. Before time T3 when the signal is switched to a high level, the second gate of OS transistor 810 The signal S F is set to a high level to turn on the OS transistor 850. Then, node N BG Voltage V for controlling the threshold voltage BG_B Give.

[0495] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current and can be kept in an off state. Then, node N BG is set to a state close to floating, and then the node N BG To be protected The voltage V BG_B Therefore, the OS transistor 850 Voltage V applied to the second gate BG_B The number of operations to give the voltage V BG_B Rewriting Therefore, the power consumption required for the above can be reduced.

[0496] In the circuit configurations of FIGS. 37B and 39A, the second transistor of OS transistor 810 We have shown a configuration in which the voltage applied to the gate is controlled externally, but we will also consider other configurations. For example, the voltage for controlling the threshold voltage may be set based on the signal applied to the input terminal IN. and provide it to the second gate of the OS transistor 810. An example of a realizable circuit configuration is shown in FIG.

[0497] In FIG. 40(A), the input terminal IN and the OS transistor are connected in the circuit configuration shown in FIG. 37(B). A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal is connected to the second gate of OS transistor 810 .

[0498] The operation of FIG. 40(A) will be explained using the timing chart of FIG. 40(B). In the timing chart of Figure 40(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are 8, the output waveform IN_B of the CMOS inverter 860, and the OS transistor 810 The change in threshold voltage of the FET 810 is shown.

[0499] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is It can be a signal that controls the threshold voltage of the transistor 810. As described in (a) to (c), the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 40(B), the signal applied to the input terminal IN is at a high level. At this time, the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be made to be in a state where it is difficult for current to flow. The voltage at the output terminal OUT can be dropped sharply.

[0500] At time T5 in FIG. 40(B), the signal applied to the input terminal IN is low level. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be made to be in a state where current can easily flow. , the voltage at the output terminal OUT can be increased sharply.

[0501] As described above, in the configuration of this embodiment, the inverter having the OS transistor The back gate voltage is switched according to the logic of the signal at the input terminal IN. By using this configuration, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor with the signal given to It is possible to change the voltage sharply. It is also possible to reduce the through current between the wiring that supplies the power supply voltage. Therefore, it is possible to reduce power consumption.

[0502] (Embodiment 5) In this embodiment, a plurality of circuits each having an OS transistor described in the above embodiment are An example of a semiconductor device having the above structure will be described with reference to FIGS.

[0503] FIG. 41A is a block diagram of a semiconductor device 900. The semiconductor device 900 is A circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has a path 906.

[0504] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, Instead of a single voltage, multiple voltages may be used. Voltage V ORG is external to the semiconductor device 900. The semiconductor device 900 can generate the voltage V based on the voltage V0 given from the external The voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without applying multiple power supply voltages from the outside.

[0505] The circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the circuit 902 is V ORG and voltage V SS (V ORG >V SS ) and applied based on For example, the power supply voltage of the circuit 904 is a voltage V POG and voltage V SS (V POG >V ORG ) is a voltage applied based on the power supply voltage of the circuit 906. is the voltage V ORG and voltage V SS and voltage V NEG (V ORG >V SS >V NEG ) and based on The voltage V SS is equivalent to the ground potential (GND), Therefore, the number of types of voltages generated by the power supply circuit 901 can be reduced.

[0506] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG can be generated. The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage applied from the outside. It can be made.

[0507] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG can be generated. The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage applied from the outside. It can be made.

[0508] Figure 41(B) shows the voltage V POG FIG. 41C shows an example of a circuit 904 that operates in the 10 is an example of a waveform of a signal for operating the

[0509] FIG. 41B shows a transistor 911. The applied signal is, for example, a voltage V POG and voltage V SS The signal is generated based on the When transistor 911 is in the conducting state, the voltage V POG , the voltage when operating in a non-conducting state V SS Voltage V POG As shown in Figure 41(C), the voltage V ORG Bigger Therefore, the transistor 911 is in a conductive state between the source (S) and the drain (D). As a result, the circuit 904 can operate more reliably. The circuit can be made as follows.

[0510] Figure 41(D) shows the voltage V NEG FIG. 41(E) shows an example of a circuit 906 that operates in the 10 is an example of a waveform of a signal for operating the

[0511] FIG. 41D shows a transistor 912 having a back gate. The signal applied to the gate of the gate electrode 912 is, for example, a voltage V ORG and voltage V SS Generated based on This signal is applied to the voltage V ORG , non-guided When the voltage V SS Also, the back of the transistor 912 The signal applied to the gate is voltage V NEG It is generated based on the voltage V NEG Figure 41(E) As shown in the figure, the voltage V SS (GND). Therefore, the The threshold voltage can be controlled to be positively shifted. 12 can be more reliably made non-conductive, and the As a result, the circuit 906 has reduced malfunctions and low power consumption. This can result in a circuit with improved power.

[0512] Furthermore, the voltage V NEG may be directly applied to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a voltage is applied to the gate of the transistor 912. and supplying the signal to the back gate of the transistor 912. stomach.

[0513] Also, FIGS. 42(A) and (B) show modified examples of FIGS. 41(D) and (E).

[0514] In the circuit diagram shown in FIG. 42(A), a control circuit is provided between the voltage generating circuit 905 and the circuit 906. The transistor 922 has a conduction state that can be controlled by a path 921. is an n-channel OS transistor. BG is a signal that controls the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors like transistor 922.

[0515] In the timing chart of FIG. 42(B), the control signal S BG The change in the potential of the transformer The state of the potential of the back gates of the resistors 912A and 912B is connected to the node N BG The change in potential is shown by Control signal S BG When is at a high level, the transistor 922 is in a conductive state, and the node N BG is the voltage V NEG Then, the control signal S BG When is low, node N B G The transistor 922 is an OS transistor. Therefore, the off-state current is small. BG Even if is electrically floating, Once the voltage V is applied NEG can be held.

[0516] FIG. 43A shows an example of a circuit configuration applicable to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. 43A includes diodes D1 to D5 and a capacitor C The charge pump is a five-stage circuit having C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 directly or via an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS The voltage applied based on voltage, by applying a clock signal CLK, the voltage V ORG to a positive voltage five times greater than The boosted voltage V POG It should be noted that the forward currents of the diodes D1 to D5 are The voltage is set to 0 V. By changing the number of stages in the charge pump, the desired voltage V PO G can be obtained.

[0517] FIG. 43B shows an example of a circuit configuration applicable to the voltage generating circuit 905 described above. The voltage generating circuit 905 shown in FIG. 43B includes diodes D1 to D5 and a capacitor C The charge pump is a four-stage circuit having C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 directly or via an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS The voltage applied based on voltage, the clock signal CLK is applied to the ground, i.e., the voltage V SS to voltage V ORG The voltage V is stepped down to a negative voltage four times that of NEG You can get The forward voltage of the diodes D1 to D5 is set to 0V. By changing the number, the desired voltage V NEG can be obtained.

[0518] The circuit configuration of the voltage generating circuit 903 described above is not limited to the configuration of the circuit diagram shown in FIG. Modifications of the voltage generating circuit 903 are shown in FIGS. 44(A) to 44(C), 45(A) and 45(B). Shown below.

[0519] The voltage generating circuit 903A shown in FIG. 44A includes transistors M1 to M10, a capacitor The clock signal CLK is supplied to the inverters C11 to C14 and the inverter INV1. The voltage Vcc is applied directly to the gates of the transistors M1 to M10 or via an inverter INV1. By applying a clock signal CLK, the voltage V ORG is boosted to a positive voltage four times higher than the The voltage V POG By changing the number of stages, the desired voltage V POG The voltage generating circuit 903A shown in FIG. By using OS transistors for M11 to M10, the off-state current can be reduced. This can suppress leakage of the charge stored in C14. Therefore, the voltage V ORG to voltage V POG It is possible to boost the voltage to

[0520] The voltage generating circuit 903B shown in FIG. 44B includes transistors M11 to M14, The clock signal CLK is generated by: The voltage is applied to the gates of the transistors M11 to M14 directly or via an inverter INV2. By applying a clock signal CLK, the voltage V ORG rises to twice the positive voltage The applied voltage V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. Therefore, leakage of the electric charge held in the capacitors C15 and C16 can be suppressed. Pressure V ORG to voltage V POG It is possible to boost the voltage to

[0521] The voltage generating circuit 903C shown in FIG. 44(C) includes an inductor I11 and a transistor M 15, diode D6, and capacitor C17. Transistor M15 is controlled The conduction state is controlled by the signal EN. ORG is boosted The applied voltage V POG The voltage generating circuit 903C shown in FIG. Since the inductor I11 is used to boost the voltage, it is possible to boost the voltage with high conversion efficiency. can be done.

[0522] 45A is the same as the voltage generating circuit 903D shown in FIG. The diodes D1 to D5 of the O3 are placed in diode-connected transistors M16 to M20. The voltage generating circuit 903D shown in FIG. By using OS transistors M16 to M20, the off-state current can be reduced. Therefore, the leakage of the charge held in C5 can be suppressed. ORG Voltage from V POG It is possible to boost the voltage to

[0523] 45(B) is the same as the voltage generating circuit 903E shown in FIG. The transistors M16 to M20 of the first embodiment are replaced with transistors M21 to M20 having back gates. The voltage generating circuit 903E shown in FIG. Since the same voltage can be applied to the gate as to the clock gate, the amount of current flowing through the transistor Therefore, the voltage V ORG to voltage V POG Figure 1 shows the boost to It is possible.

[0524] The modified example of the voltage generating circuit 903 is also applicable to the voltage generating circuit 905 shown in FIG. 43(B). The circuit configuration in this case is shown in FIGS. 46(A) to 46(C), 47(A), and 47(B). The voltage generating circuit 905A shown in FIG. 46A supplies a clock signal CLK. By this, the voltage V SS is stepped down from the voltage V ORG to the voltage V NEG which is three times the negative voltage of V, and the obtained voltage can be obtained. Also, the voltage generation circuit 905B shown in FIG. 46(B) can obtain the voltage V by applying the clock signal CLK SS from the voltage V ORG which is stepped down to the negative voltage twice that of V NEG [[ID=

[19] ]]

[0525] In the voltage generation circuits 905A to 90 5E shown in FIGS. 46(A) to (C) and FIGS. 47(A) and (B), it corresponds to a configuration in which the voltage applied to each wiring is changed or the arrangement of elements is changed, similar to the voltage generation circuits 903A to 903E shown in FIGS. 44(A) to (C) and FIGS. 45(A) and (B). In the voltage generation circuits 905A to 905E shown in FIGS. 46(A) to (C) and FIGS. 47(A) and (B), the voltage can be efficiently stepped down from the voltage V to the voltage V ss to the voltage V NEG

[0526]

[0527] As described above, in the configuration of this embodiment, the necessary voltage for the circuit of the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the types of power supply voltages supplied from the outside.

[0527] (Embodiment 6) 0]In this embodiment, an example of a CPU including a semiconductor device such as a transistor according to an aspect of the present invention and the above-described memory device will be described.

[0528] <000 CPU Configuration> FIG. 48 is a block diagram showing the configuration of an example of a CPU using a part of the above-described transistor. The CPU configuration shown below is formed using, for example, the semiconductor device shown in FIG. It is possible.

[0529] The CPU shown in FIG. 48 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 1199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in FIG. 48 is merely an example of a simplified configuration, and an actual CPU may differ from the For example, the CPU or the arithmetic circuit shown in Figure 48 A configuration including a path is considered to be one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is , for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0530] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0531] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0532] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals that control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generator generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0533] In the CPU shown in FIG. 48, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as memory cells of the memory cell 1196. Cut.

[0534] In the CPU shown in FIG. 48, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 6, data is held by a flip-flop or a capacitance element. If data is held by a flip-flop, the data is held by the flip-flop. If selected, the power supply voltage is supplied to the memory cells in the register 1196 . If data retention in the capacitor is selected, data rewriting to the capacitor is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0535] FIG. 49 shows a circuit diagram of a storage element 1200 that can be used as a register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is turned off, and a power supply A circuit 1202, a switch 1203, and a switch 1204 that prevent the stored data from volatilizing when cut off. 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1201. 210. The memory element 1200 may include a diode, a resistor, etc., as needed. , and may further include other elements such as an inductor.

[0536] Here, the above-described memory device can be used for the circuit 1202. When the supply of power supply voltage to GND is stopped, the gate of transistor 1209 in circuit 1202 is GND (0V) or a potential that turns off the transistor 1209 is continuously input. For example, if the gate of the transistor 1209 is grounded via a load such as a resistor, do.

[0537] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 3 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of (i.e., the conductive or non-conductive state of transistor 1213) The first terminal of the switch 1204 is connected to the source of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 connects the input to the gate of the transistor 1214. The control signal RD determines whether the first terminal and the second terminal are electrically connected or disconnected (i.e., , the conductive or non-conductive state of transistor 1214) is selected.

[0538] One of the source and drain of the transistor 1209 is connected to one of the pair of electrodes of the capacitor 1208. The gate of the transistor 1210 is electrically connected to one of the gates of the transistor 1210. The part is designated as node M2. One of the source and drain of the transistor 1210 is connected to the low power supply voltage. The other is electrically connected to a wiring (for example, a GND line) that can supply a voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (one of the terminals of the transistor 1214) is electrically connected to the The other of the source and drain) is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) the input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207. , are electrically connected. Here, the connection point is a node m1. The other electrode of the pair may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND The capacitor element 12 may be configured to receive a high power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.). The other of the pair of electrodes 08 is connected to a wiring (e.g., GN D line).

[0539] The capacitors 1207 and 1208 are formed by using parasitic capacitances of transistors and wirings. It is also possible to omit this by actively using

[0540] A control signal WE is input to the gate of the transistor 1209. and the switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal of one switch is selected. When the first and second terminals of the other switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. It becomes a state.

[0541] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 49, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0542] In FIG. 49, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is passed through the logic element 1206 and the circuit 1220. Although an example of inputting the signal to the circuit 1201 is shown, this is not limiting. The signal output from the other of the source and drain of the transistor 1213 is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0543] In addition, in FIG. 49, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 11 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon film or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is

[0544] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0545] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0546] Further, a transistor whose channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 12 Even when power supply voltage is not supplied to 00, the signal held in the capacitor 1208 is retained for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0547] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operation, after the power supply voltage is supplied again, the circuit 1201 This can shorten the time it takes to restore the original data.

[0548] In the circuit 1202, the signal held by the capacitor 1208 is transferred to the transistor. Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the capacitor 1208 is opened, the transistor 1210 The state (conducting or non-conducting) is determined and can be read out from the circuit 1202 Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original It is possible to accurately read out the signal.

[0549] Such a storage element 1200 may be a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one of the components of the processor, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. can be suppressed.

[0550] Although the memory element 1200 has been described as being used in a CPU, the memory element 1200 may also be used in a DSP. (Digital Signal Processor), Custom LSI, PLD(P LSIs such as programmable logic devices, RF (Radio It can also be applied to (frequency) devices.

[0551] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0552] (Embodiment 7) In this embodiment, an imaging device including a transistor according to one embodiment of the present invention will be described. An example of this will be described.

[0553] <Imaging device> An imaging device according to one aspect of the present invention will be described below.

[0554] 50(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral The pixel section 210 has a pixel circuit 270, a peripheral circuit 280, and a peripheral circuit 290. It has a plurality of pixels 211 arranged in a matrix of columns (p and q are integers of 2 or more). The peripheral circuits 260, 270, 280, and 290 are respectively The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification and the like, the peripheral circuits 260, 270, 280, and The peripheral circuit 290 and the like may be referred to as the "peripheral circuit" or the "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0555] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light. It can emit P1.

[0556] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel section 210 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits are peripheral circuits 260, 270, 280, and 29. One or more of the 0s may be omitted.

[0557] Also, as shown in FIG. 50(B), in the pixel section 210 of the imaging device 200, The pixels 211 may be arranged at an angle. By arranging the pixels 211 at an angle, the pixel This allows the pixel interval (pitch) in the column direction to be shortened. This can further improve the quality of imaging in the imaging device.

[0558] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each Sub-pixel 212 is combined with a filter (color filter) that transmits light in a specific wavelength range. By doing so, it is possible to obtain information for realizing a color image display.

[0559] FIG. 51(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 51(A) is provided with a color filter that transmits light in the red (R) wavelength range. The subpixel 212 (hereinafter also referred to as "subpixel 212R") emits light in the green (G) wavelength range. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a transparent color filter ) and a sub-pixel 212 (hereinafter referred to as a sub-pixel 213) provided with a color filter that transmits light in the blue (B) wavelength range. The subpixel 212 functions as a photosensor. It can be done.

[0560] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 2 31, and are electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The subpixels 212R, 212G, and 212B are each connected to an independent wiring 2 53. In this specification, for example, the pixel connected to the n-th row pixel 211 is The wiring 248 and the wiring 249 are respectively referred to as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as wiring 253[m In FIG. 51A, the sub-pixel 212 of the pixel 211 in the m-th column is written as The wiring 253 connected to R is the wiring 253[m]R, and the wiring 253 connected to the subpixel 212G is the wiring 253[m]R. The wiring 253[m]G and the wiring 253 connected to the subpixel 212B are referred to as wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0561] In addition, the imaging device 200 uses color filters that transmit light in the same wavelength range for adjacent pixels 211. The sub-pixels 212 provided with the filters are electrically connected to each other via switches. In Figure 51(B), there are n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). The sub-pixel 212 of the pixel 211 and the pixel 211 adjacent to the pixel 211 in the n+1th row and the mth column are 51B shows an example of connection of sub-pixels 212 included in the arranged pixel 211. In FIG. The sub-pixel 212R arranged in the row and column m and the sub-pixel 212R arranged in the row and column n+1 are switched. The sub-pixels 212G and 212H are connected via a switch 201. The sub-pixels 212G and 212H are arranged in n rows and m columns. The sub-pixel 212G arranged in the +1 row and the m column is connected via the switch 202. , the sub-pixel 212B arranged in the nth row and the mth column, and the sub-pixel 212B arranged in the n+1th row and the mth column They are connected via a switch 203 .

[0562] The color filters used for the subpixel 212 are limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 211 may have sub-pixels that detect light in three different wavelength ranges. By providing 212, a full color image can be obtained.

[0563] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are used. In addition to the sub-pixel 212, a color filter that transmits yellow (Y) light is provided. Alternatively, a pixel 211 having sub-pixels 212 may be used. The sub-pixel 212 is provided with a color filter that transmits light of blue (Y) and magenta (M). In addition, a pixel 212 having a sub-pixel 212 provided with a color filter that transmits blue (B) light is One pixel 211 may have four sub-pixels 211 for detecting light in different wavelength ranges. By providing the lens 12, the color reproducibility of the acquired image can be further improved.

[0564] Also, for example, in FIG. 51(A), the sub-pixel 212 detects light in the red wavelength range, The sub-pixels 212 for detecting light in the blue wavelength range and the sub-pixels 212 for detecting light in the blue wavelength range are The pixel ratio (or light receiving area ratio) does not have to be 1:1:1. The light area ratio may be a Bayer array of red:green:blue=1:2:1. The numerical ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0565] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. For example, by providing two or more sub-pixels 212 that detect light in the same wavelength range, redundancy can be increased and the image can be captured more efficiently. This can improve the reliability of the imaging device 200.

[0566] In addition, IR (Infrared) filters absorb or reflect visible light and transmit infrared light. ) filter, an imaging device 200 that detects infrared light can be realized.

[0567] In addition, ND (Neutral Density) filters (light-reducing filters) are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, The dynamic range of the device can be increased.

[0568] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using the cross-sectional view of the pixel 211. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 52(A), a lens 255 and a filter 256 are formed in the pixel 211. 54 (filter 254R, filter 254G and filter 254B), and pixel circuit A structure can be adopted in which light 256 is incident on the photoelectric conversion element 220 through 230 or the like.

[0569] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is connected to the wiring 257. Therefore, as shown in Figure 52(B), the light is blocked by a part of the A lens 255 and a filter 254 are arranged on the photoelectric conversion element 220 side. A structure in which the light 256 is efficiently received by the photoelectric conversion element 220 is preferable. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity can be provided. This can be done.

[0570] As the photoelectric conversion element 220 shown in FIG. 52, a pn-type junction or a pin-type junction is formed. Alternatively, a photoelectric conversion element may be used.

[0571] The photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be: Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy There is money etc.

[0572] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, such as X-rays and gamma rays 20 can be achieved.

[0573] Here, one pixel 211 included in the imaging device 200 is added to a sub-pixel 212 shown in FIG. In addition, there may be a subpixel 212 having a first filter.

[0574] <Pixel configuration example 2> Below, a transistor using silicon, a transistor using an oxide semiconductor, and An example of forming a pixel using the transistors shown in the above embodiment will be described. A transistor similar to that used in the first embodiment can be used.

[0575] Fig. 53 is a cross-sectional view of an element constituting an imaging device. The imaging device shown in Fig. 53 is made of silicon. A silicon-based transistor 351 is provided on a silicon substrate 300. The transistor 352 and the transistor 35 using an oxide semiconductor are stacked on each other. 3, and a photodiode 360 ​​provided on the silicon substrate 300. The resistors and photodiodes 360 are electrically connected to various plugs 370 and wiring 371. The anode 361 of the photodiode 360 ​​has a low resistance region 363. 370 and has electrical connection therewith.

[0576] The imaging device also includes a transistor 351 and a photodiode 352 provided on a silicon substrate 300. A layer 310 having a diode 360 ​​and a layer 371 provided in contact with the layer 310. 320, and a transistor 352 and a transistor 353 are provided in contact with the layer 320. a layer 330 having a wiring 372 and a wiring 373 provided in contact with the layer 330; It is equipped with 340.

[0577] In the example of the cross section of FIG. 53, the transistor 351 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the opposite side of the surface on which the light receiving surface is formed. By configuring it in this way, it is possible to ensure an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light receiving surface of the transistor 351 may be the same as the surface on which the transistor 351 is formed.

[0578] When a pixel is configured using only transistors including an oxide semiconductor, layer 3 Alternatively, the layer 310 may be a layer including a transistor using an oxide semiconductor. Alternatively, the pixel may be formed using only a transistor including an oxide semiconductor.

[0579] The silicon substrate 300 may be an SOI substrate. Instead of germanium, silicon germanium, silicon carbide, gallium arsenide, and arsenic carbide, a substrate having aluminum gallium, indium phosphide, gallium nitride or an organic semiconductor; It can also be used.

[0580] Here, a la...

Claims

1. a semiconductor substrate having a channel formation region of a first transistor; a first insulator having a region over the semiconductor substrate; a second insulator having an area above the first insulator; a third insulator having an area above the second insulator; a fourth insulator having an area above the third insulator; and an oxide semiconductor having a region on the fourth insulator; a first conductor; a second conductor; and a third conductor; the oxide semiconductor includes a channel formation region of a second transistor; the first transistor is electrically connected to the first conductor and the second conductor; the first insulator and the second insulator have a first opening; the third insulator has a second opening; the fourth insulator has a third opening; the second opening penetrates from an upper surface of the third insulator to a lower surface of the third insulator, the third opening penetrates from an upper surface of the fourth insulator to a lower surface of the fourth insulator, The width of the second opening is greater than the width of the first opening, the first opening overlaps the second opening; the second opening overlaps with the third opening; the first conductor and the second conductor are embedded in the first opening and the second opening, the third conductor is embedded in the third opening; the first conductor is in contact with the first to third insulators, the second conductor is in contact with the first conductor; the third conductor has a region in contact with the first conductor, a region in contact with the second conductor, a region in contact with the third insulator, and a region in contact with the fourth insulator; the portions of the first conductor and the second conductor embedded in the first opening have regions that function as plugs; the portions of the first conductor and the second conductor embedded in the second opening have regions that function as wiring; the second insulator is less permeable to hydrogen than the first insulator; The semiconductor device, wherein the first conductor and the third conductor are less permeable to hydrogen than the second conductor.

2. In claim 1, The semiconductor device, wherein the first conductor and the third conductor contain tantalum and nitrogen.

3. In claim 1 or claim 2, The second insulator comprises aluminum and oxygen.

4. In any one of claims 1 to 3, The oxide semiconductor includes indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen.

5. In any one of claims 1 to 4, The semiconductor substrate is a semiconductor device having silicon.

Images