Duplicate registers in chiplet processing units

Abstract

A system, apparatus and method are disclosed for implementing duplicate registers for access by initiators across multiple semiconductor dies. The system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One semiconductor die is a master die, and the master die has copies of registers accessible by multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die, and a particular duplicate copy of the register is maintained for the given secondary die. From a software perspective, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, and flash registers are one type of register.

Description

[Background technology]

[0001] Description of Related Art Computing devices such as mobile phones, tablets, personal digital assistants (PDAs), digital cameras, portable players, gaming devices, laptops, and other devices need to integrate more performance and functionality into a smaller space. This has led to an increase in processor die density and the number of dies integrated into a single integrated circuit (IC) package. Some conventional multi-chip modules include two or more semiconductor chips mounted side-by-side on a carrier substrate, or in some cases, on an interposer (so-called "2.5D") that is mounted on the carrier substrate.

[0002] The advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of one embodiment of a computing system. [Figure 2] FIG. 1 is a block diagram of a processing system employing GPU chiplets, according to some embodiments. [Figure 3] FIG. 2 is a block diagram of another embodiment of a computing system. [Figure 4] FIG. 1 is a block diagram of another embodiment of a computing system with a chiplet GPU. [Figure 5] FIG. 1 is a block diagram of one embodiment of a master die. [Figure 6] FIG. 10 is a block diagram of one embodiment of a control unit on a master die. [Figure 7] FIG. 2 is a block diagram of one embodiment of a secondary die. [Figure 8] FIG. 1 illustrates one embodiment of a register copy mapping table. [Figure 9]FIG. 1 is a generalized flow diagram illustrating one embodiment of a method for determining which copy of a register to access based on an initiator index. [Figure 10] FIG. 1 is a generalized flow diagram illustrating one embodiment of a method for maintaining multiple copies of registers for initiators from multiple semiconductor dies. [Figure 11] FIG. 1 is a generalized flow diagram illustrating one embodiment of a method for tagging register accesses with a semiconductor ID. DETAILED DESCRIPTION OF THE INVENTION

[0004] In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, those skilled in the art should recognize that various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the approaches described herein. It will be understood that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements.

[0005] Disclosed herein are various systems, apparatus, and methods for implementing duplicate registers for access by initiators across multiple semiconductor dies. In one embodiment, the system includes multiple initiators on multiple semiconductor dies. In this embodiment, one of the semiconductor dies is a master die, and the master die maintains multiple copies of each register, with each copy accessible by initiators on the corresponding semiconductor die. That is, each semiconductor die has its own copy of a given register to access. For example, in a system with a four-die chiplet graphics processing unit (GPU), the master die maintains four separate copies of a given register, one for each die. This allows multiple initiators on multiple dies to access a given register without conflicting with each other. From the perspective of a particular initiator on a secondary die, only that initiator can access a given register. From a software perspective, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator.

[0006] An initiator may be a compute unit, a command processor, a direct memory access (DMA) engine, or other type of hardware or software agent. When a given initiator on a given secondary die generates a register access, the access is routed to the master die, which executes the access on the copy of the register corresponding to the given secondary die. A master die may maintain multiple types of registers, where a flash register is any type of register. A write to any copy of a flash register causes any outstanding memory transaction to be flushed (i.e., discarded without being executed). A master die may also maintain copies of other types of registers.

[0007] 1, a block diagram of one embodiment of computing system 100 is shown. In one embodiment, computing system 100 includes at least processors 105A-105N, input / output (I / O) interface 120, bus 125, memory controller 130, network interface 135, memory device(s) 140, display controller 150, and display 155. In other embodiments, computing system 100 includes other components and / or is arranged differently. Processors 105A-105N represent any number of processors included in system 100.

[0008] In one embodiment, processor 105A is a general-purpose processor such as a central processing unit (CPU). In this embodiment, processor 105A executes drivers 110 (e.g., graphics drivers) for communicating with and / or controlling the operation of one or more of the other processors in system 100. Note that, depending on the embodiment, driver 110 may be implemented using any suitable combination of hardware, software, and / or firmware. In one embodiment, processor 105N is a data-parallel processor with a highly parallel architecture, such as a chiplet graphics processing unit (GPU), that processes data, performs parallel processing of workloads, renders pixels for display controller 150 to drive display 155, and / or executes other workloads.

[0009] A chiplet GPU is a complex integrated circuit that performs graphics processing tasks across multiple semiconductor dies. GPUs perform graphics processing tasks required by end-user applications, such as video game applications. Increasingly, GPUs are also being used to perform other non-graphics related tasks. Other data parallel processors that may be included in system 100 include digital signal processors (DSPs), field programmable gate arrays (FPGAs), and application specific integrated circuits (ASICs). In some embodiments, processors 105A-105N include multiple data parallel processors.

[0010] Memory controller(s) 130 represent any number and type of memory controllers accessible by processors 105A-105N. While memory controller 130 is shown as separate from processors 105A-105N, it should be understood that this represents only one contemplated embodiment. In other embodiments, memory controller 130 may be incorporated into one or more of processors 105A-105N and / or memory controller 130 may be located on the same semiconductor die as one or more of processors 105A-105N. Memory controller(s) 130 couple to any number and type of memory device(s) 140.

[0011] Memory device(s) 140 represent any number and type of memory devices. For example, types of memory in memory device(s) 140 may include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc. Memory device(s) 140 store program instructions 145, which may include a first set of program instructions for an application, a second set of program instructions for a driver component, etc. Alternatively, program instructions 145, or portions thereof, may be stored in memory or a cache device local to processor 105A and / or processor 105N.

[0012] I / O interface 120 represents any number and type of I / O interface (e.g., Peripheral Component Interconnect (PCI) bus, PCI-Extended (PCI-X), PCI Express (PCIE) bus, Gigabit Ethernet (GBE) bus, Universal Serial Bus (USB). Various types of peripheral devices (not shown) are coupled to I / O interface 120. Such peripheral devices include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks, other types of game controllers, media recording devices, and external storage devices. Network interface 135 can receive and send network messages over a network.

[0013] In various embodiments, computing system 100 may be a computer, a laptop, a mobile device, a game console, a server, a streaming device, a wearable device, or any of a variety of other types of computing systems or devices. Note that the number of components in computing system 100 may vary from embodiment to embodiment. For example, in other embodiments, more or fewer components may be present than those shown in FIG. 1 . Note also that in other embodiments, computing system 100 may include other components not shown in FIG. 1 . Additionally, in other embodiments, computing system 100 may be constructed in a manner other than that shown in FIG. 1 .

[0014] Referring to FIG. 2, a block diagram illustrating a processing system 200 employing GPU chiplets according to some embodiments is shown. In the illustrated example, system 200 includes a central processing unit (CPU) 205 for executing instructions and an array of one or more GPU chiplets, such as GPU chiplets 250A, 250B, 250B, 250C, 250D, 250E, 250F, 250G, 250H ...

[0015] In various embodiments, CPU 205 connects to system memory 230, such as dynamic random access memory (DRAM), via bus 240. In various embodiments, system memory 230 may be implemented using other types of memory, including static random access memory (SRAM), non-volatile RAM, etc. In the illustrated embodiment, CPU 205 communicates with system memory 230 and also with GPU chiplets 250 via bus 240, which may be implemented as a Peripheral Component Interconnect (PCI) bus, PCI-E bus, or other type of bus. However, some embodiments of system 200 include GPU chiplets 250 that communicate with CPU 205 through a direct connection or through other buses, bridges, switches, routers, etc.

[0016] As illustrated, CPU 205 includes multiple processes, such as executing one or more application(s) 210 to generate graphics commands and user-mode driver 220 (or other drivers, such as kernel-mode drivers). In various embodiments, one or more applications 210 include applications that utilize the capabilities of GPU chiplet 250, such as applications that generate workloads in system 200 or operating system (OS) 215. Application 210 may include one or more graphics instructions that instruct GPU chiplet 250 to render a graphical user interface (GUI) and / or a graphics scene. For example, the graphics instructions may include instructions that define a set of one or more graphics primitives to be rendered by GPU chiplet 250.

[0017] In some embodiments, application 210 utilizes a graphics application programming interface (API) to invoke user-mode driver 220 (or a similar GPU driver). In one embodiment, user-mode driver 220 issues one or more commands to an array of one or more GPU chiplets to render one or more graphics primitives into a displayable graphics image. Based on the graphics instructions issued by application 210 to user-mode driver 220, user-mode driver 220 generates one or more graphics commands that specify one or more operations of the GPU chiplets to perform the rendering of the graphics. In some embodiments, user-mode driver 220 is part of application 210 running on CPU 205. For example, user-mode driver 220 may be part of a gaming application running on CPU 205. Similarly, a kernel-mode driver (not shown) may be part of OS 215 running on CPU 205.

[0018] In the embodiment shown in FIG. 2 , communication links 260 (e.g., crosslinks 260) connect GPU chiplets 250 (i.e., GPU chiplets 250A-250N) to one another. In such an embodiment, each chiplet (250) includes an interface (252A-252N) configured to enable the chiplets to communicate over links 260. Note that the number of GPU chiplets in a chiplet array is a matter of design choice and may vary from embodiment to embodiment. In various embodiments, links 260 are interconnect chips such as buses, high-density link (HDCL) die interposers, or other inter-chiplet communication mechanisms.

[0019] Referring to FIG. 3, a block diagram of another embodiment of a computing system 300 is shown. As seen in FIG. 3, computing system 300 includes a central processing unit (CPU) 310, a route complex 320, a switch 330, and a graphics processing unit (GPU) 340. In one embodiment, GPU 340 is a chiplet GPU including dies 350A-350D, which represent any number of semiconductor dies. Note that computing system 300 may include any number of other components (e.g., voltage regulators, memory devices, network interfaces, peripheral devices) not shown to avoid obscuring the diagram. Computing system 300 may be any of the devices or systems listed above, such as a computer, laptop, server, supercomputer, mobile device, etc. Computing system 300 may also be a subsystem incorporated into another device or system. Many other types of devices, systems, or subsystems are envisioned and contemplated.

[0020] CPU 310 represents any type of CPU or other type of processor. Depending on the embodiment, CPU 310 may include multiple cores or a single core. In one embodiment, CPU 310 executes control software (e.g., an operating system (OS)) for system 300. The operating system controls the operation of system 300 to achieve the desired functionality of the system. The operating system may include and / or interact with various software programs, such as drivers, control software, etc. Root complex 320 connects switch 330 to CPU 310 as well as any number and types of other components not shown in FIG. 3 to avoid obscuring the diagram. In one embodiment, switch 330 is a Peripheral Component Interconnect Express (PCIE) switch. In other embodiments, switch 330 is any of a variety of other types of switches.

[0021] As shown in FIG. 3 , chiplet GPU 340 includes four dies 350A-350D. In other embodiments, chiplet GPU 340 can include other numbers of dies (e.g., 8, 10, 16, 25, 32). As shown, each die 350A-D includes an initiator 365A-D, respectively, which represents any number and type of agent, component, or other unit that generates register accesses targeted to register 355A. While each die 350A-D is shown as including one initiator, it should be understood that this is for illustrative purposes only. In other embodiments, each die 350A-350D can include other numbers of initiators. It should also be understood that various dies can have different numbers of initiators. For example, a first die may have one initiator, a second die may have two initiators, a third die may have three initiators, and so on.

[0022] Although each die 350A-350D is shown as having a corresponding register 355A-350D, in one embodiment, only die 350A has enabled register 355A. In some cases, die 350B-350D also have registers 355B-355D, respectively, but these registers are disabled. For example, in one embodiment, each die 350A-350D are identical, with only one die having enabled registers and copies thereof, and the other die having disabled registers and copies thereof. The enabled registers and copies on master die 350A are intended to provide access from all die 350A-350D.

[0023] Register accesses from initiators 365B-365D to register 355A are routed from die 350B-350D to copies 360B-360D, respectively. That is, to prevent register accesses from various dies from conflicting with each other, there is a copy 360B-360D for each die 350B-350D, respectively. In one embodiment, when a register access is generated by an initiator on a secondary die (e.g., die 350B-350D), the register access traverses a link (e.g., communication link 260 in FIG. 2) to master die 350A. In one embodiment, a die ID is added to the register access to identify the origin of the register access. This die ID allows die 350A to route the register access to the appropriate copy 360B-360D.

[0024] In one embodiment, register 355A is a flush register that controls when memory transactions are flushed. For example, in this embodiment, when an initiator writes to register 355A, this causes all outstanding memory transactions to be flushed from the memory subsystem (e.g., system memory 230 of FIG. 2). When initiator 365B generates a write access to register 355A, this write access is tagged with the die ID of die 350B, and then the write access with the die ID of die 350B is sent to die 350A. Because the access includes the die ID of die 350B, the write access is performed on copy 360B. At a later point in time, when initiator 365C generates a write access targeting register 355A, this write access is tagged with the die ID for die 350C and sent to die 350A. When die 350A receives this write access, the write is performed on copy 360C. Note that the write accesses of initiators 365B and 365C both involve the same register address in register 355A. Die 350A distinguishes between these write accesses based on their corresponding die IDs. Note that in other embodiments, register 355A can be other types of registers besides a flash register.

[0025] Referring to FIG. 4, a block diagram of another embodiment of a computing system 400 including a chiplet GPU 440 is shown. Chiplet GPU 440 is similar to chiplet GPU 340 (of FIG. 3) in that chiplet GPU 440 includes four dies 450A-450D, with die 450A being the master die. It should be understood that dies 450A-450D represent any number of dies, and the example of four dies 450A-450D illustrates only one particular embodiment. Other embodiments may have other numbers of dies within the chiplet GPU. Die 450A connects to CPU 410 via switch 430 and route complex 420. It should be noted that system 400 may include any number and types of other components not shown to avoid obscuring the diagram.

[0026] Chiplet GPU 340 has homogeneous dies 350A-350D, while chiplet GPU 440 has heterogeneous dies 450A-450D. Thus, die 450A has register 455A and register copies 460A-460D, while dies 450B-450D do not have corresponding registers and register copies. As with chiplet GPU 340, initiator 465A on master die 450A couples to copy 460A, initiator 465B on secondary die 450B couples to copy 460B, initiator 465C on secondary die 450C couples to copy 460C, and initiator 465D on secondary die 450D couples to copy 460D. The functionality of master die 450A is similar to that described for master die 350A of chiplet GPU 340.

[0027] Referring to FIG. 5, a block diagram of one embodiment of a master die 500 is shown. Note that the master die 500 can be part of a chiplet GPU (e.g., chiplet GPU 440 of FIG. 4) with any number of other semiconductor dies. A control unit 530 handles accesses to copies 520B-520N of register 510 by off-die initiators (not shown). Copies 520A-520N of register 510 allow individual dies to access individual copies of register 510. This also allows initiators on different dies to target register 510 using the same address without blocking initiators from other dies.

[0028] In one embodiment, initiator 550 is hardwired to access copy 520A of register 510 without intervention from control unit 530. In other embodiments, control unit 530 routes accesses by initiator 550 to copy 520A. For the purposes of this discussion, it is assumed that initiator 550 is located on the same master die as control unit 530. In one embodiment, control unit 530 includes a mapping table 540 for mapping off-die initiators to copies 520B-520N. In this embodiment, control unit 530 obtains a die ID or other identifying characteristic from the register access to use as an index into mapping table 540. In other embodiments, control unit 530 uses other techniques to map off-die initiators to copies 520B-520N.

[0029] Referring to FIG. 6, a block diagram of one embodiment of a control unit 650 on a master die 600 is shown. While the above-described example of a master die shows a single register with multiple copies, the master die 600 includes multiple registers 610A-610N, each with its own set of copies for different initiators on other secondary dies (not shown) of the chiplet GPU (e.g., chiplet GPU 440 of FIG. 4). In one embodiment, the master die 600 includes an initiator 670 that is directly coupled to a given copy of copies 620A-620N, 630A-630N, and 640A-640N. In another embodiment, the initiator 670 couples to the control unit 650, which routes access to the appropriate copy of copies 620A-620N, 630A-630N, and 640A-640N. The initiator 670 represents any number and type of initiator.

[0030] For example, copies 620A-620N are maintained for register 610A accessed by initiators from other dies, copies 630A-630N are maintained for register 610B accessed by initiators from other dies, and copies 640A-640N are maintained for register 610N accessed by initiators on other dies. In one embodiment, the number of copies may be based on the number of different semiconductor dies. In other embodiments, the number of copies may vary, such as having two copies per die, three copies per die, etc. In such embodiments, different initiators on a die may have their own copies separate from other initiators on the same die. Control unit 650 maintains mapping tables 660 for mapping different initiators on other dies to copies 620A-620N, 630A-630N, and 640A-640N. In one embodiment, there is a separate mapping table 660 for each register 610A-610N.

[0031] Referring to FIG. 7 , a block diagram of one embodiment of a secondary die 700 is shown. In one embodiment, the secondary die 700 is part of a multi-die chiplet processor (e.g., chiplet GPU 440 of FIG. 4 ). As shown, the secondary die 700 includes a control unit 710 coupled to a communication link 720. The communication link 720 represents a link, bus, or other communication channel for connecting multiple dies of a chiplet to one another. When the control unit 710 detects a register access by an on-die initiator (not shown), the control unit 710 tags the register access with a semiconductor ID 730 and forwards the register access to the master die (not shown) via the communication link 720. The control unit 710 can be implemented using any suitable combination of circuits, processing elements, and / or executable program instructions. By tagging the register access with the semiconductor ID 730, the register access can be performed by the master die on the appropriate copy of the target register. This allows the secondary die 700 to operate as if it had exclusive access to the target register.

[0032] Referring to FIG. 8, a diagram of one embodiment of a register copy mapping table 800 is shown. In one embodiment, the entries of table 800 are included in table 540 (of FIG. 5). In one embodiment, the entries of table 800 include two fields: an initiator ID field 810 and a register copy ID field 820. Any number of entries may be included in table 800, and entries are illustrated for initiator IDs "001" and "111" and register copies 520B and 520N, respectively. In other embodiments, the entries of table 800 may include other numbers and / or types of fields and may be structured in other suitable manners. It should be understood that the initiator ID field 810 having three bits is merely illustrative of one embodiment. The initiator ID field 810 and the register copy field 820 may be encoded with any number of bits, and the number may vary depending on the embodiment. Further, it should be noted that the initiator ID field 810 may also be referred to as the semiconductor die ID field 810, and in one particular embodiment, the semiconductor die ID acts as the initiator ID. In one embodiment, when a control unit (e.g., control unit 530) receives a register access from an initiator, the control unit performs a lookup in table 800 with the initiator ID to determine which register copy to access. The control unit then accesses the identified register copy on behalf of the initiator.

[0033] Referring to FIG. 9, one embodiment of a method 900 for determining which copy of a register to access based on an initiator index is shown. For purposes of illustration, the steps in this embodiment and in FIGS. 10-11 are shown sequentially. However, it should be noted that in various embodiments of the described method, one or more of the described elements may be performed simultaneously, in a different order than shown, or omitted entirely. Other additional elements may also be performed, as desired. Any of the various systems or devices described herein may be configured to perform method 900 (and methods 1000-1100).

[0034] A control unit (e.g., control unit 530 of FIG. 5 ) on a master semiconductor die of a multi-die chiplet processor receives a register access from a predetermined initiator targeting a predetermined register (block 905). The control unit obtains an initiator ID from the register access (block 910). The control unit then identifies a copy of the predetermined register to access based on the obtained initiator ID (block 915). The control unit then performs the access to the identified copy of the predetermined register (block 920). After block 920, method 900 ends. Alternatively, after block 920, the multi-die chiplet processor performs one or more actions as a result of the access to the predetermined register (optional block 925). For example, in one embodiment, the predetermined register is a flash register, and a control unit or other agent on the master die causes a memory subsystem to flush memory requests targeted to the flash register as a result of writing to the flash register. In other embodiments, other types of actions may be taken as a result of the access to the predetermined register.

[0035] 10, one embodiment of a method 1000 for maintaining multiple copies of a register for an initiator from multiple semiconductor dies is shown. A master semiconductor die maintains multiple copies of a given register (block 1005). When the master semiconductor die receives a register access targeting the given register, the master semiconductor die obtains an initiator ID from the register access (block 1010). The master semiconductor die then determines which copy to access based on the obtained initiator ID (block 1015). The master semiconductor die then performs the register access to the identified copy (block 1020). After block 1020, the method 1000 ends.

[0036] Referring to FIG. 11 , one embodiment of a method 1100 for tagging a register access with a semiconductor ID is shown. A control unit (e.g., control unit 710 of FIG. 7 ) on a secondary semiconductor die of a chiplet processor (e.g., chiplet GPU 340 of FIG. 3 ) detects a register access targeting a predetermined register (block 1105). The control unit tags the register access with the semiconductor ID of the secondary semiconductor die (block 1110). In another embodiment, the control unit tags the register access with the initiator ID of the initiator that generated the register access. The control unit then transmits the register access tagged with the semiconductor ID over a communication link to a master semiconductor die (block 1115). The master semiconductor die then accesses a predetermined copy of the predetermined register, the predetermined copy being identified based on the semiconductor ID of the secondary semiconductor die (block 1120). After block 1120, method 1100 ends.

[0037] In various embodiments, program instructions of a software application are used to implement the methods and / or mechanisms described herein. For example, program instructions executable by a general-purpose or special-purpose processor are contemplated. In various embodiments, such program instructions are expressed in a high-level programming language. In other embodiments, the program instructions are compiled from the high-level programming language into binary, intermediate, or other format. Alternatively, program instructions that describe the behavior or design of hardware are written. Such program instructions are expressed in a high-level programming language such as C. Alternatively, a hardware design language (HDL) such as Verilog® is used. In various embodiments, the program instructions are stored on any of a variety of non-transitory computer-readable storage media. The storage medium is accessible by a computing system during use to provide the program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors configured to execute the program instructions.

[0038] It should be emphasized that the above-described embodiments are merely non-limiting examples of embodiments. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. 1. An apparatus comprising: an interface configured to communicate with the one or more semiconductor dies via a communication link; a first control unit; The first control unit receiving a register access via the interface, the register access targeting a register; responsive to determining that a first initiator generated the register access, performing the register access to a first copy of the register; and in response to determining that a second initiator generated the register access, performing the register access to a second copy of the register that is different from the first copy. Device.

2. the first control unit is configured to determine which copy of the register to access based on an identifier (ID) received with the register access.

10. The apparatus of claim 1.

3. the ID is a semiconductor die ID; 3. The apparatus of claim 2.

4. the ID is added to the access request by the semiconductor die that generated the register access; 3. The apparatus of claim 2.

5. the control unit is configured to determine, based on the ID, which of the first initiator and the second initiator generated the access request.

5. The apparatus of claim 4.

6. the control unit is configured to flush any outstanding memory requests to a memory subsystem in response to performing the register access.

10. The apparatus of claim 1.

7. the first control unit is configured to maintain multiple copies of the register, each copy corresponding to a different semiconductor die; 10. The apparatus of claim 1.

8. 1. A method comprising: receiving, by a control unit, a register access directed to a target register of a first semiconductor die of the plurality of semiconductor dies; In response to determining that a first initiator generated a given register access, performing the register access to a first copy of the target register of the first semiconductor die; in response to determining that a second initiator generated the predetermined register access, performing the register access to a second copy of the target register of the first semiconductor die, the second copy being different from the first copy. method.

9. determining which copy of the register to access based on a predetermined identifier (ID) communicated with the given register access; 9. The method of claim 8.

10. the predetermined ID is a semiconductor die ID; 10. The method of claim 9.

11. A second control unit on a second semiconductor die adds an identifier (ID) of the second semiconductor die to the register access generated by the second initiator before transmitting the register access to the first semiconductor die over a communication link.

9. The method of claim 8.

12. a first access request including a first identifier (ID) that identifies the first initiator, and a second access request including a second ID that identifies the second initiator, the method including distinguishing between the first access request and the second access request based on the first ID and the second ID; 9. The method of claim 8.

13. and flushing any outstanding memory requests to a memory subsystem in response to performing the predetermined register access.

9. The method of claim 8.

14. maintaining multiple copies of the target register, each copy corresponding to a different semiconductor die; 9. The method of claim 8.

15. 1. A system comprising: a plurality of semiconductor dies; Memory subsystem and a first control unit for a first semiconductor die of the plurality of semiconductor dies; The first control unit receiving a register access directed to a target register; In response to determining that a first initiator generated a given register access, performing the register access to a first copy of the target register; responsive to determining that a second initiator generated the given register access, performing the register access on a second copy of the target register, the second copy being different from the first copy; configured to: system.

16. the first control unit is configured to determine which copy of the register to access based on a predetermined identifier (ID) communicated with the given register access.

16. The system of claim 15.

17. the predetermined ID is a semiconductor die ID; 17. The system of claim 16.

18. A second control unit on a second semiconductor die; the second control unit is configured to add an identifier (ID) of the second semiconductor die to the register access generated by the second initiator before communicating the register access to the first semiconductor die over a communication link.

16. The system of claim 15.

19. the first access request includes a first identifier (ID) that identifies the first initiator, and the second access request includes a second ID that identifies the second initiator, and the first control unit is configured to distinguish between the first access request and the second access request based on the first ID and the second ID.

16. The system of claim 15.

20. the first control unit is configured to flush any outstanding memory requests to the memory subsystem in response to performing the predetermined register access.

16. The system of claim 15.

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