Semiconductor integrated circuit and receiving device

Abstract

To provide a semiconductor integrated circuit capable of suitably reproducing data on the basis of a reception signal, and a receiving device.SOLUTION: A semiconductor integrated circuit of an embodiment comprises: a converter which converts an analog signal to a digital signal on the basis of a clock signal; a determination circuit which determines first data having a first number of bit data per symbol and second data having a second number of bit data less than the first number per symbol on the basis of the digital signal; a recovery circuit which reproduces a clock signal; and a control circuit configured so as to input the digital signal and the first data to the recovery circuit when conditions are not met and input the digital signal and the second data to the recovery circuit when the conditions are met.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor integrated circuit and a receiving device. [Background technology]

[0002] The transmitting device and receiving device are connected via a transmission path. The receiving device receives a received signal that has passed through the transmission path. The receiving device includes a semiconductor integrated circuit that processes the received signal. The receiving device regenerates a clock signal based on the received signal. The receiving device regenerates data from the received signal based on the regenerated clock signal. The receiving device includes a clock data recovery circuit that regenerates the clock signal and data based on the received signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6849903 [Patent Document 2] Patent No. 6912702 [Patent Document 3] Patent No. 6518836 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor integrated circuit and a receiving device are provided that suitably reproduce data based on a received signal. [Means for solving the problem]

[0005] A semiconductor integrated circuit according to an embodiment includes a converter, a decision circuit, a recovery circuit, and a control circuit. The converter converts an analog signal into a digital signal based on a clock signal. The decision circuit determines, based on the digital signal, whether first data has a first number of bits per symbol or second data has a second number of bits per symbol that is less than the first number. The recovery circuit recovers the clock signal. The control circuit recovers the clock signal when a condition is met. R inputting the digital signal and the first data to the recovery circuit when the condition is met; do not have In this case, the digital signal and the second data are input to the recovery circuit. Satisfying the above condition includes the time elapsed since the start of reception of the analog signal being equal to or greater than a threshold, or the phase of the clock signal recovered by the recovery circuit being locked. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a receiving device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a receiving circuit according to the first embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the configuration of a digital processing circuit and a tap coefficient updating circuit of the receiving circuit according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing an example of the functional configuration of a data compression circuit of the digital processing circuit according to the first embodiment. [Figure 5] FIG. 2 is a block diagram showing an example of the configuration of a clock data recovery circuit of the receiving circuit according to the first embodiment. [Figure 6] FIG. 2 is a block diagram showing an example of the configuration of a phase detector of the clock data recovery circuit according to the first embodiment. [Figure 7] 5 is a flowchart showing an example of a receiving operation in the receiving device according to the first embodiment. [Figure 8] 4 is a diagram showing an example of an output of a phase detector in PAM4 mode in the receiving device according to the first embodiment. [Figure 9]4 is a diagram showing an example of an output of a phase detector in NRZ mode in the receiving device according to the first embodiment. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a receiving circuit according to a second embodiment. [Figure 11] FIG. 10 is a block diagram showing an example of the configuration of a digital processing circuit and a tap coefficient updating circuit of a receiving circuit according to a second embodiment. [Figure 12] 10 is a flowchart showing an example of a receiving operation in the receiving device according to the second embodiment. [Figure 13] FIG. 10 is a block diagram showing an example of the configuration of a receiving circuit according to a third embodiment. [Figure 14] FIG. 11 is a block diagram showing an example of the configuration of a digital processing circuit and a tap coefficient updating circuit of a receiving circuit according to a third embodiment. [Figure 15] FIG. 11 is a diagram showing an example of the functional configuration of a pattern filter in an inactive state of the digital processing circuit according to the third embodiment. [Figure 16] FIG. 11 is a diagram showing an example of the functional configuration of a pattern filter in an active state of the digital processing circuit according to the third embodiment. [Figure 17] FIG. 11 is a block diagram showing an example of the configuration of a phase detector of a clock data recovery circuit according to a third embodiment. [Figure 18] 10 is a flowchart showing an example of a receiving operation in the receiving device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. First embodiment A first embodiment will be described.

[0010] 1.1 Configuration The configuration according to the first embodiment will be described.

[0011] 1.1.1 Information Processing Systems First, a description will be given of the configuration of an information processing system including a receiving device according to the first embodiment. Fig. 1 is a block diagram showing an example of the configuration of an information processing system including a receiving device according to the first embodiment.

[0012] The information processing system 1 is a system that transmits information by serial communication. The information processing system 1 includes a host device 2 and a memory system 3. The memory system 3 is connectable to the host device 2 via a host bus BUS.

[0013] The host device 2 is an information processing device external to the memory system 3. The host device 2 is, for example, a personal computer or a server installed in a data center. The host device 2 transmits various requests to the memory system 3. When transmitting requests to the memory system 3, the host device 2 functions as a transmitting device.

[0014] The memory system 3 is a storage device. For example, the memory system 3 is TM The memory system 3 may be a memory card such as a card, a universal flash storage (UFS) device, or a solid state drive (SSD). The memory system 3 performs data write, read, and erase operations in response to a request from the host device 2. When receiving a request from the host device 2, the memory system 3 functions as a receiving device.

[0015] 1.1.2 Memory System The internal configuration of the memory system according to the first embodiment will be described.

[0016] The memory system 3 includes a memory device 4 and a memory controller 5 .

[0017] The memory device 4 is, for example, a nonvolatile memory. The memory device 4 is, for example, a NAND flash memory. The memory device 4 stores data in a nonvolatile manner.

[0018] The memory controller 5 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 5 controls the memory device 4 based on a request from the host device 2. Specifically, for example, the memory controller 5 writes write data to the memory device 4 based on a write request from the host device 2. The memory controller 5 also reads read data from the memory device 4 based on a read request from the host device 2. The memory controller 5 then transmits the read data to the host device 2.

[0019] Next, we will explain the internal configuration of the memory controller 5. The memory controller 5 includes a control unit 6, a buffer memory 7, a host interface circuit 8 (host I / F), and a memory interface circuit 9 (memory I / F). The functions of the memory controller 5 described below can be realized either by a hardware configuration or by a combination of hardware resources and firmware.

[0020] The control unit 6 is a circuit that controls the entire memory controller 5. The control unit 6 includes, for example, a processor such as a CPU (central processing unit) and a ROM (read only memory).

[0021] The buffer memory 7 is, for example, an SRAM (static random access memory). The buffer memory 7 buffers data transmitted between the host device 2 and the memory device 4. The buffer memory 7 temporarily stores write data and read data.

[0022] The host interface circuit 8 includes a semiconductor integrated circuit. The host interface circuit 8 controls communication between the memory controller 5 and the host device 2. When receiving a request from the host device 2, a part of the circuit of the host interface circuit 8 functions as a receiving circuit. The host interface circuit 8 is connected to the host device 2 via a host bus BUS. The host bus BUS is, for example, TM Interface: SAS (serial attached SCSI (small computer system interface)), SATA (serial ATA (advanced technology attachment)), or PCIe TM (Peripheral Component Interconnect Express) compliant.

[0023] The memory interface circuit 9 includes a semiconductor integrated circuit. The memory interface circuit 9 controls communication between the memory device 4 and the memory controller 5. The memory interface circuit 9 is connected to the memory device 4 via a memory bus. The memory bus conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0024] 1.1.3 Host interface circuit (receiving circuit) Next, a description will be given of the internal configuration of a portion corresponding to the receiving circuit provided in the host interface circuit according to the first embodiment. Fig. 2 is a block diagram showing an example of the configuration of the receiving circuit of the receiving device according to the first embodiment.

[0025] The host interface circuit 8 includes pads P1 and P2, an analog processing circuit 10, a TI-ADC 20, a digital processing circuit 30, a CDR 40, a tap coefficient update circuit 50, and a control circuit 60.

[0026] Each of the pads P1 and P2 is a terminal connected to the host bus BUS. In the example of Fig. 2, the pads P1 and P2 receive signals S0 and / S0, respectively, from the host device 2 via the host bus BUS.

[0027] The signals S0 and / S0 are differential signals. Before passing through the host bus BUS, the signals S0 and / S0 are, for example, pulse signals including multiple pulses. Data from the host device 2 is modulated onto each pulse of the signals S0 and / S0. The voltage level of each pulse of the signals S0 and / S0 corresponds to one or multiple bits of data. In the following explanation, it is assumed that two bits of data are modulated per pulse. This type of data transmission method is also called PAM4 (Four-level Pulse Amplitude Modulation).

[0028] By passing through the host bus BUS, the signals S0 and / S0 are subject to loss due to the transmission characteristics (for example, frequency characteristics) of the host bus BUS. As a result, inter-symbol interference (ISI) occurs in the signals S0 and / S0 that have passed through the host bus BUS. For this reason, the signals S0 and / S0 that have passed through the host bus BUS are processed as analog signals.

[0029] The analog processing circuit 10 is an AFE (Analog Front End). The analog processing circuit 10 includes, for example, a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE is an amplifier circuit with frequency characteristics that compensate for the frequency characteristics of the host bus BUS. The VGA is an amplifier circuit with variable gain. Signals S0 and / S0 are input to the analog processing circuit 10 from pads P1 and P2, respectively. The analog processing circuit 10 performs analog processing on the signals S0 and / S0 using the CTLE and VGA. The analog processing circuit 10 generates signals S1 and / S1 based on the signals S0 and / S0. The analog processing circuit 10 outputs the signals S1 and / S1 to the TI-ADC 20.

[0030] The TI-ADC 20 is a time-interleaved AD converter. The TI-ADC 20 receives signals S1 and / S1 from the analog processing circuit 10 and receives a signal CLK from the CDR 40. The TI-ADC 20 converts the signals S1 and / S1 into a signal X0 based on the signal CLK. The TI-ADC 20 outputs the signal X0 to the digital processing circuit 30.

[0031] The signal CLK includes n clock signals, where n is an integer equal to or greater than 1 (e.g., 32). The n clock signals of the signal CLK differ in phase by, for example, at least 360° / n. The frequency of the signal CLK may be equal to the frequency of the clock signals embedded in the signals S0 and / S0 by the host device 2. The frequency of the signal CLK may be different from the frequency of the clock signals embedded in the signals S0 and / S0 by the host device 2.

[0032] The signal X0 is a digital signal. The signal X0 includes a plurality of consecutive digital values. The bit value of one digital value included in the signal X0 is sampled from one symbol of the signals S1 and / S1 based on one clock signal of the signal CLK. One digital value is, for example, 7-bit data. The bit values ​​of each of n consecutive digital values ​​included in the signal X0 are sampled from n consecutive symbols of the signals S1 and / S1 based on n clock signals of the signal CLK. Hereinafter, the generation period of the n consecutive digital values ​​included in the signal X0 by the TI-ADC 20 will also be simply referred to as a "period." Furthermore, the n consecutive digital values ​​included in the signal X0 will also be referred to as "one period of the signal X0."

[0033] The digital processing circuit 30 includes, for example, a feed forward equalizer (FFE), a decision feedback equalizer (DFE), and a data decision circuit. The configuration of the digital processing circuit 30 will be described later. A signal X0 is input to the digital processing circuit 30. The digital processing circuit 30 performs digital processing on the signal X0 using the FFE, DFE, and data decision circuit. Specifically, the digital processing circuit 30 generates signals X1 and Xf and data A1 and Af based on the signal X0. The digital processing circuit 30 outputs the signal X1 and the data A1 to the CDR 40. The digital processing circuit 30 outputs the signals X0 and X1 and the data A1 to the tap coefficient update circuit 50. The digital processing circuit 30 outputs the signal Xf and the data Af to the tap coefficient update circuit 50 and subsequent circuits (not shown). The signals X1 and Xf and the data A1 and Af will be described in detail later.

[0034] The CDR 40 is a clock data recovery circuit. The signal X1 and data A1 are input to the CDR 40 every cycle. The CDR 40 calculates a phase correction amount for the signal CLK based on the signal X1 and data A1. The CDR 40 regenerates the signal CLK based on the calculated phase correction amount. The CDR 40 outputs the regenerated signal CLK to the TI-ADC 20 every cycle. In this way, the CDR 40 regenerates the signal CLK, which serves as a reference for the sampling timing of the signal X0 for one cycle, based on the signal X1 and data A1 generated from one cycle of the signal X0. This cycle-by-cycle cyclic processing by the TI-ADC 20, the digital processing circuit 30, and the CDR 40 is also called a "CDR loop."

[0035] The tap coefficient update circuit 50 is an arithmetic circuit. The tap coefficient update circuit 50 generates a signal TAP based on a set of signals X0 and X1 and data A1 received from the digital processing circuit 30, and a set of signals X0 and Xf and data Af. The signal TAP is a signal that controls information (e.g., tap coefficients) related to the arithmetic functions of the FFE and DFE of the digital processing circuit 30.

[0036] The control circuit 60 includes, for example, a processor such as a CPU, and a ROM. The control circuit 60 controls the entire host interface circuit 8. Specifically, for example, the control circuit 60 controls the digital processing circuit 30 and the tap coefficient update circuit 50 based on signals CNT1 and CNT2, respectively. The signal CNT1 is a signal that controls the value of data A1 output from the digital processing circuit 30. The signal CNT2 is a signal that controls whether or not the signal TAP output from the tap coefficient update circuit 50 is updated.

[0037] 1.1.4 Digital processing circuit and tap coefficient update circuit Next, a description will be given of the internal configuration of the digital processing circuit and tap coefficient updating circuit of the receiving circuit according to the first embodiment. Fig. 3 is a block diagram showing an example of the configuration of the digital processing circuit and tap coefficient updating circuit of the receiving circuit according to the first embodiment.

[0038] First, a description will be given of the configuration of the digital processing circuit 30. The digital processing circuit 30 includes an FFE 31, a data determination circuit 32, a data compression circuit 33, a multiplexer 34, an FFE 35, a DFE 36, and a data determination circuit 37.

[0039] The signal X0 is input to the FFE31. For each of n digital values ​​included in one cycle of the signal X0, the FFE31 performs arithmetic processing using the digital value to be calculated and digital values ​​for several symbols before and after the digital value to be calculated. The arithmetic processing by the FFE31 uses tap coefficients based on a portion of the signal TAP input from the tap coefficient update circuit 50. The FFE31 generates a signal X1 as a result of the arithmetic processing. In other words, the signal X1 is a digital signal like the signal X0. One cycle of the signal X1 is a collection of n digital values. The FFE31 outputs the signal X1 to the data decision circuit 32 and the FFE35. The signal X1 is also output to the CDR 40 and the tap coefficient update circuit 50.

[0040] The signal X1 is input to the data determination circuit 32. Based on the signal X1, the data determination circuit 32 determines the data encoded by the host device 2 as data A1a. Specifically, when PAM4 is applied, the data determination circuit 32 determines 2 bits of data for each n digital values ​​included in one cycle of the signal X1. That is, the data A1a has 2 bits of data for each n digital values ​​included in one cycle of the signal X1. The 2 bits of data correspond to, for example, any of "-3", "-1", "+1", and "+3". The data determination circuit 32 outputs the data A1a to the data compression circuit 33 and the multiplexer 34.

[0041] The data compression circuit 33 receives the data A1a. The data compression circuit 33 compresses the data A1a into data A1b. The data A1b has one bit of data for each of n digital values ​​included in one cycle of the signal X1. The one bit of data corresponds to either "-3" or "+3", for example. The data compression circuit 33 outputs the data A1b to the multiplexer 34.

[0042] Fig. 4 is a diagram showing an example of the functional configuration of a data compression circuit in the digital processing circuit according to the first embodiment. Fig. 4 shows the relationship between a value A1a[i] included in data A1a to be compressed and a value A1b[i] included in data A1b compressed by the data compression circuit 33. The value A1a[i] is a digital value corresponding to the i-th symbol of n pieces of 2-bit data included in data A1a (0≦i≦n-1). The value A1b[i] is a digital value corresponding to the i-th symbol of n pieces of 1-bit data included in data A1b, and corresponds to the value A1a[i].

[0043] As shown in FIG. 4, when the value A1a[i] indicates "-3", the data compression circuit 33 outputs a value A1b[i] indicating "-3". When the value A1a[i] indicates "-1", the data compression circuit 33 outputs a value A1b[i] indicating "-3". When the value A1a[i] indicates "+1", the data compression circuit 33 outputs a value A1b[i] indicating "+3". When the value A1a[i] indicates "+3", the data compression circuit 33 outputs a value A1b[i] indicating "+3". With the above configuration, the data compression circuit 33 can compress the 2-bit data A1a into the 1-bit data A1b.

[0044] The data decision circuit 32 and the data compression circuit 33 may be regarded as a single decision circuit that decides the data A1a and A1b based on the signal X1 and outputs the decision result.

[0045] Returning to FIG. 3, the configuration of the digital processing circuit 30 will be described.

[0046] The multiplexer 34 receives data A1a and A1b from the data decision circuit 32 and data compression circuit 33, respectively. The multiplexer 34 also receives a signal CNT1 from the control circuit 60. The multiplexer 34 outputs either data A1a or A1b based on the signal CNT1. The output of the multiplexer 34 is output to the CDR 40 and the tap coefficient update circuit 50. That is, the multiplexer 34 switches between data A1a and data A1b as the data to be output to the CDR 40 and the tap coefficient update circuit 50 in accordance with the signal CNT1.

[0047] In the following description, when data A1a is output as data A1, the digital processing circuit 30 is also referred to as being in a "PAM4 mode." When data A1b is output as data A1, the digital processing circuit 30 is also referred to as being in a "Non-Return to Zero (NRZ) mode."

[0048] A signal X1 is input to the FFE35. Note that the signal input to the FFE35 may be a signal X1' (not shown) different from the signal X1 input to the data decision circuit 32 and the CDR 40. In this case, the signal X1' input to the FFE35 is generated based on the signal X1. For each n digital values ​​included in one cycle of the signal X1, the FFE35 performs arithmetic processing using the digital value to be calculated and digital values ​​for several symbols before and after the digital value to be calculated. The arithmetic processing by the FFE35 uses tap coefficients based on a portion of the signal TAP input from the tap coefficient update circuit 50. Note that the tap coefficients applied to the FFE35 may be different from the tap coefficients applied to the FFE31. The FFE35 generates a signal X2 as a result of the arithmetic processing. In other words, the signal X2 is a digital signal, like the signals X0 and X1. One cycle of the signal X2 is a collection of n digital values. The FFE35 outputs the signal X2 to the DFE36.

[0049] The signal X2 is input to the DFE 36. For each n digital values ​​included in one cycle of the signal X2, the DFE 36 performs arithmetic processing based on the digital value to be calculated and the digital values ​​of several symbols before and after the digital value to be calculated. The arithmetic processing by the DFE 36 uses tap coefficients based on a part of the signal TAP input from the tap coefficient update circuit 50. The DFE 36 generates and outputs a signal Xf as a result of the arithmetic processing. In other words, the signal Xf is a digital signal, similar to the signals X0, X1, and X2. The signal Xf for one cycle is a set of n digital values. The signal Xf generated by the DFE 36 is output to the data decision circuit 37, the tap coefficient update circuit 50, and subsequent circuits.

[0050] A signal Xf is input to the data determination circuit 37. Based on the signal Xf, the data determination circuit 37 determines the data encoded by the host device 2 as data Af. Specifically, when PAM4 is applied, the data determination circuit 37 determines 2-bit data for each n digital values ​​included in one cycle of the signal Xf. The data Af determined by the data determination circuit 37 is output to the tap coefficient update circuit 50 and subsequent circuits.

[0051] Next, a description will be given of the configuration of the tap coefficient updating circuit 50. The tap coefficient updating circuit 50 includes a first updating circuit 51 and a second updating circuit 52.

[0052] The first updating circuit 51 receives the signal X1 and data A1 from the FFE 31 and the multiplexer 34, respectively. The first updating circuit 51 also receives the signal X0 that was input to the digital processing circuit 30. The first updating circuit 51 generates a portion of the signal TAP based on the signals X0 and X1 and the data A1, and outputs it to the FFE 31. The portion of the signal TAP that is output from the first updating circuit 51 is applied to the FFE 31 as a tap coefficient.

[0053] Furthermore, the first updating circuit 51 receives a signal CNT2 from the control circuit 60. The first updating circuit 51 stops updating the signal TAP based on the signal CNT2. When the updating of the signal TAP is stopped, the first updating circuit 51 continues to output the signal TAP that was last updated when the updating of the signal TAP was not stopped, regardless of the signals X0 and X1 and the data A1 in the latest cycle.

[0054] The second updating circuit 52 receives the signal Xf and data Af from the DFE 36 and the data determination circuit 37, respectively. The second updating circuit 52 also receives the signal X0 that was input to the digital processing circuit 30. The second updating circuit 52 generates a portion of the signal TAP based on the signals X0 and Xf and the data Af, and outputs it to the FFE 35 and the DFE 36. The portion of the signal TAP that is output from the second updating circuit 52 is applied to the FFE 35 and the DFE 36 as a tap coefficient.

[0055] 1.1.5 Clock and data recovery circuits Next, a description will be given of the internal configuration of the clock data recovery circuit (CDR) of the receiver circuit according to the first embodiment. Fig. 5 is a block diagram showing an example of the configuration of the clock data recovery circuit of the receiver circuit according to the first embodiment.

[0056] The CDR 40 includes a PD 41 , an LF 42 , a PLL 43 , a PI 44 , and a clock generation circuit 45 .

[0057] PD41 is an MM baud rate phase detector (Mueller-Muller Baud-Rate Phase Detector). When detecting a phase shift related to the signal CLK, the MM baud rate phase detector uses one sampling result per symbol. When detecting a phase shift, the MM baud rate phase detector does not use the sampling results of the edges (boundaries) of pulses corresponding to the data encoded in the signals S0 and / S0. PD41 receives the signal X1 and data A1 from the digital processing circuit 30. PD41 calculates a value PDOUT based on the signal X1 and data A1. The value PDOUT is a value corresponding to the phase shift between the current sampling timing based on the signal CLK and the optimal sampling timing. PD41 outputs the value PDOUT to LP42.

[0058] The LF42 is a loop filter. The value PDOUT is input to the LF42. The LF42 calculates the value LFOUT based on the value PDOUT. The value LFOUT is a value corresponding to the amount of correction of the phase of the signal CLK. The LF42 outputs the value LFOUT to the PI44.

[0059] The PLL 43 is a phase locked loop circuit. The PLL 43 generates a signal REF. The signal REF is a reference signal having a reference frequency in the receiving circuit. The PLL 43 outputs the signal REF to the PI 44. In the following description, the difference between the reference frequency of the signal REF and the frequency of the clock signal embedded in the signals S0 and / S0 by the host device 2 is also referred to as "frequency deviation."

[0060] The PI44 is a phase interpolator. The value LFOUT is input to the PI44 from the LF42, and the signal REF is input to the PI44 from the PLL43. The PI44 generates a signal PIOUT from the signal REF based on the value LFOUT. The signal PIOUT is an n-phase signal whose phase has been corrected. The PI44 outputs the signal PIOUT to the clock generation circuit 45.

[0061] The signal PIOUT is input to the clock generation circuit 45. The clock generation circuit 45 generates a signal CLK based on the signal PIOUT. The clock generation circuit 45 uses, for example, a frequency divider circuit to generate the signal CLK. The signal CLK generated by the clock generation circuit 45 is output to the TI-ADC 20.

[0062] 1.1.6 Phase Detector Next, a description will be given of the internal configuration of the phase detector (PD) of the clock data recovery circuit according to the first embodiment. Fig. 6 is a block diagram showing an example of the configuration of the phase detector of the clock data recovery circuit according to the first embodiment.

[0063] The PD 41 includes a plurality of multipliers 411, a plurality of adders 412, a plurality of sign function circuits 413, and an adder 414. The plurality of multipliers 411 include 2n multipliers 411_1, 411_2, ..., 411_(2k-1) (not shown), 411_2k (not shown), ..., 411_(2n-1), and 411_2n. The plurality of adders 412 include n adders 412_1, ..., 412_k (not shown), ..., and 412_n. The plurality of sign function circuits 413 include n sign function circuits 413_1, ..., 413_k (not shown), ..., and 413_n, where k is an integer greater than or equal to 2 and less than or equal to (n-1) (2≦k≦n-1).

[0064] In FIG. 6, n digital values ​​included in one cycle of signal X1 are represented as values ​​X1[1], ..., and X1[n]. Similarly, n digital values ​​included in one cycle of data A1 are represented as values ​​A1[1], ..., and A1[n]. Values ​​X1[0] and A1[0] correspond to the symbols immediately preceding values ​​X1[1] and A1[1], respectively. For example, values ​​X1[0] and A1[0] are value X1[n] included in signal X1 and value A1[n] included in data A1 in the CDR loop one cycle ago, respectively. Values ​​X1[0] and A1[0] are pre-stored in a register (not shown) during the CDR loop one cycle ago, for example.

[0065] The multiplier 411_1 multiplies the value X1[0] by the value A1[1] and outputs the result of the operation, the value X1[0]A1[1], to the adder 412_1.

[0066] The multiplier 411_2 multiplies the value X1[1] by the value A1[0] and outputs the result of the operation, the value X1[1]A1[0], to the adder 412_1.

[0067] The adder 412_1 subtracts the value X1[1]A1[0] from the value X1[0]A1[1]. The adder 412_1 outputs the operation result (X1[0]A1[1]-X1[1]A1[0]) to the sign function circuit 413_1.

[0068] The sign function circuit 413_1 determines whether the value (X1[0]A1[1]-X1[1]A1[0]) is positive or negative. If the value (X1[0]A1[1]-X1[1]A1[0]) is positive, the sign function circuit 413_1 outputs "1" to the adder 414. If the value (X1[0]A1[1]-X1[1]A1[0]) is negative, the sign function circuit 413_1 outputs "-1" to the adder 414.

[0069] Furthermore, the multiplier 411_(2k-1) multiplies the value X1[k-1] by the value A1[k], and outputs the result of the operation, the value X1[k-1]A1[k], to the adder 412_k.

[0070] The multiplier 411_2k multiplies the value X1[k] by the value A1[k−1] and outputs the result of the operation, the value X1[k]A1[k−1], to the adder 412_k.

[0071] The adder 412_k subtracts the value X1[k]A1[k-1] from the value X1[k-1]A1[k]. The adder 412_k outputs the operation result (X1[k-1]A1[k]-X1[k]A1[k-1]) to the sign function circuit 413_k.

[0072] The sign function circuit 413_k determines whether the value (X1[k-1]A1[k]-X1[k]A1[k-1]) is positive or negative. If the value (X1[k-1]A1[k]-X1[k]A1[k-1]) is positive, the sign function circuit 413_k outputs "1" to the adder 414. If the value (X1[k-1]A1[k]-X1[k]A1[k-1]) is negative, the sign function circuit 413_k outputs "-1" to the adder 414.

[0073] The explanations regarding the multipliers 411_(2k-1) and 411_2k, the adder 412_k, and the sign function circuit 413_k apply to all k values ​​between 2 and (n-1).

[0074] Similarly, the multiplier 411_(2n-1) multiplies the value X1[n-1] by the value A1[n], and outputs the result of the operation, the value X1[n-1]A1[n], to the adder 412_n.

[0075] The multiplier 411_2n multiplies the value X1[n] by the value A1[n-1] and outputs the result of the operation, that is, the value X1[n]A1[n-1], to the adder 412_n.

[0076] The adder 412_n subtracts the value X1[n]A1[n-1] from the value X1[n-1]A1[n]. The adder 412_n outputs the operation result (X1[n-1]A1[n]-X1[n]A1[n-1]) to the sign function circuit 413_n.

[0077] The sign function circuit 413_n determines whether the value (X1[n-1]A1[n]-X1[n]A1[n-1]) is positive or negative. If the value (X1[n-1]A1[n]-X1[n]A1[n-1]) is positive, the sign function circuit 413_n outputs "1" to the adder 414. If the value (X1[n-1]A1[n]-X1[n]A1[n-1]) is negative, the sign function circuit 413_n outputs "-1" to the adder 414.

[0078] The adder 414 adds "1" or "-1" input from each of the n sign function circuits 413_1 to 413_n, and outputs the operation result to the LF 42 as a value PDOUT.

[0079] 1.2 Operation Next, the operation of the receiving device according to the first embodiment will be described.

[0080] 1.2.1 Receiving Operation First, the receiving operation in the receiving device according to the first embodiment will be described. Fig. 7 is a flowchart showing an example of the receiving operation in the receiving device according to the first embodiment. Fig. 7 shows a part of the receiving operation including a CDR loop.

[0081] When reception of the signals S0 and / S0 begins (START), the tap coefficient update circuit 50 initializes the tap coefficients included in the signal TAP (S1).

[0082] Based on the signal CLK, the TI-ADC 20 samples and AD converts the signals S1 and / S1 generated based on the signals S0 and / S0, generating a signal X0 for one period (S2).

[0083] The FFE 31 of the digital processing circuit 30 generates a signal X1 for one cycle based on the signal X0 for one cycle generated in the process of S2 and the tap coefficients initialized in the process of S1 (S3). The signal X1 is output to the CDR 40 and the tap coefficient update circuit 50.

[0084] The data decision circuit 32 of the digital processing circuit 30 decides the data A1a for one period based on the signal X1 for one period (S4).

[0085] The data compression circuit 33 of the digital processing circuit 30 compresses the data A1a for one period to generate data A1b (S5).

[0086] The control circuit 60 determines whether a condition is met (S6). The condition may be, for example, that the elapsed time since the start of reception of the signals S0 and / S0 is equal to or greater than a threshold value. The condition may be, for example, that the CDR 40 locks the phase of the signal CLK.

[0087] If it is determined that the condition is not satisfied (S6; no), the control circuit 60 outputs a signal CNT1 instructing the multiplexer 34 to select data A1b. The multiplexer 34 selects one cycle's worth of data A1b generated in the process of S5 in accordance with the signal CNT1 (S7). The data A1b selected in the process of S7 is output to the CDR 40 and the tap coefficient update circuit 50 as data A1.

[0088] Furthermore, if it is determined that the condition is not satisfied (S6; no), the control circuit 60 outputs a signal CNT2 instructing the first updating circuit 51 of the tap coefficient updating circuit 50 to stop updating the tap coefficients. In response to the signal CNT2, the first updating circuit 51 stops updating the tap coefficients based on the signals X0 and X1 and the data A1 (S8). Here, stopping the updating of the tap coefficients includes not performing the updating of the tap coefficients.

[0089] In this way, when the condition is not satisfied, the digital processing circuit 30 operates in NRZ mode. That is, when the condition is not satisfied, data A1 compressed to 1 bit data is input to the CDR 40 and the tap coefficient update circuit 50. Note that the tap coefficient update circuit 50 stops updating the tap coefficients while data A1 compressed to 1 bit data is being input.

[0090] If it is determined that the condition is satisfied (S6; yes), the control circuit 60 outputs a signal CNT1 instructing the selection of data A1a to the multiplexer 34. The multiplexer 34 selects one cycle's worth of data A1a generated in the process of S4 in accordance with the signal CNT1 (S9). The data A1a selected in the process of S9 is output to the CDR 40 and the tap coefficient update circuit 50 as data A1.

[0091] Furthermore, if it is determined that the condition is satisfied (S6; yes), the control circuit 60 outputs a signal CNT2 instructing an update of the tap coefficients to the first update circuit 51 of the tap coefficient update circuit 50. The first update circuit 51 updates the tap coefficients based on the signals X0 and X1 and the data A1 in response to the signal CNT2 (S10).

[0092] In this way, when the condition is satisfied, the digital processing circuit 30 operates in PAM4 mode. That is, when the condition is satisfied, data A1, which is 2-bit data, is input to the CDR 40 and the tap coefficient update circuit 50. Then, the tap coefficient update circuit 50 updates the tap coefficients while data A1, which is 2-bit data, is being input.

[0093] After the process of S7 and the process of S8, or after the process of S9 and the process of S10, the CDR 40 reproduces the signal CLK based on one cycle of the signal X1 and the data A1 (S11).

[0094] The host interface circuit 8 determines whether or not reception of the signals S0 and / S0 has finished based on whether or not the signals S1 and / S1 have been input (S12).

[0095] If reception of signals S0 and / S0 has not yet finished (S12; no), TI-ADC 20 generates signal X0 of the next cycle based on the recovered signal CLK (S2). This causes the processes of S2 to S12 to be repeated (CDR loop) until reception of signals S0 and / S0 has finished. Note that in the process of S3 in the second and subsequent CDR loops, if the updating of tap coefficients has stopped in the process of S8, the current tap coefficients continue to be used. If the tap coefficients have been updated in the process of S10, the updated tap coefficients are used.

[0096] When the reception of the signals S0 and / S0 is completed (S12; yes), the reception operation is completed (end).

[0097] 1.3 Effects of the First Embodiment According to the first embodiment, the TI-ADC 20, the digital processing circuit 30, and the CDR 40 execute a CDR loop to correct a phase shift in the signal CLK. The data decision circuit 32 of the digital processing circuit 30 decides on two-bit data A1a per symbol based on the signal X1. The data compression circuit 33 of the digital processing circuit 30 generates one-bit data A1b per symbol based on the data A1a. The control circuit 60 outputs a signal CNT1 indicating selection of either the data A1a or A1b depending on whether a condition is met. The multiplexer 34 outputs either the data A1a or A1b as data A1 depending on the signal CNT1. The PD 41 of the CDR 40 calculates a value PDOUT based on the signal X1 and the data A1. As a result, the CDR 40 can selectively use the data A1a based on the PAM4 mode and the data A1b based on the NRZ mode when recovering the signal CLK depending on whether a condition is met. Therefore, according to the first embodiment, data can be suitably reproduced based on the received signal.

[0098] More specifically, when the value PDOUT is positive, the CDR 40 delays the phase of the signal CLK. When the value PDOUT is negative, the CDR 40 advances the phase of the signal CLK. As a result, as the CDR loop repeats, the phase of the signal CLK converges toward the point where the value PDOUT switches from positive to negative along the direction of phase advance. This point is called the convergence point. The CDR 40 then locks the phase of the signal CLK based on the amount of phase shift at the convergence point. However, when the digital processing circuit 30 operates in PAM4 mode, the CDR 40 may lock the phase of the signal CLK at an incorrect convergence point.

[0099] FIG. 8 is a diagram showing an example of the output of a phase detector in PAM4 mode in the receiving device according to the first embodiment. FIG. 9 is a diagram showing an example of the output of a phase detector in NRZ mode in the receiving device according to the first embodiment. In the examples of FIGS. 8 and 9, the vertical axis indicates the value PDOUT, which is the output of the PD41 of the CDR 40. The horizontal axis indicates the amount of phase shift from the sampling timing in a certain CDR loop period in units of UI (Unit Interval). Here, the range from 0 UI to 1 UI corresponds to one symbol. In the examples of FIGS. 8 and 9, lines L1 and L2 respectively represent an example of the history of the value PDOUT when the amount of phase shift from the sampling timing in a certain CDR loop period is changed between 0 UI and 1 UI.

[0100] 8, when the signal X1 and data A1a are input to the CDR 40 based on the PAM4 mode, the value PDOUT of the line L1 may have three positive peaks and three negative peaks in the range from 0 UI to 1 UI, crossing 0 multiple times. Therefore, in addition to the true convergence point TL indicating the optimal phase shift amount, the line L1 may also have false convergence points FL1 and FL2 indicating non-optimal phase shift amounts. In other words, in the PAM4 mode, there is at least one phase at which the CDR 40 may falsely lock. Therefore, when the CDR 40 is caused to lock the phase of the signal CLK using the data A1 (i.e., data A1a) based on the PAM4 mode, the phase of the signal CLK may lock to the false convergence points FL1 and FL2, which is undesirable.

[0101] On the other hand, as shown in FIG. 9, when the signal X1 and data A1b are input to the CDR 40 based on the NRZ mode, the value PDOUT of the line L2 may have one positive peak and one negative peak in the range from 0 UI to 1 UI, crossing 0 twice. Therefore, the line L2 only has a true convergence point TL, and does not have a false convergence point. In other words, in the NRZ mode, the possibility of the CDR 40 false locking is smaller than in the PAM4 mode. Therefore, when the CDR 40 is made to lock the phase of the signal CLK using the data A1 (i.e., data A1b) based on the NRZ mode, the phase of the signal CLK is more likely to lock to the true convergence point TL, which is more preferable.

[0102] According to the first embodiment, the control circuit 60 determines whether a condition is satisfied based on whether the CDR 40 has locked the phase of the signal CLK. In one example, the control circuit 60 determines that the condition is satisfied when the CDR 40 has locked the phase of the signal CLK. In another example, the control circuit 60 determines that the condition is satisfied when the elapsed time since receiving the signals S0 and / S0 is equal to or exceeds a threshold. This allows the multiplexer 34 to switch between data A1a and data A1b to be output to the CDR 40 depending on whether the CDR 40 has locked the phase of the signal CLK.

[0103] Specifically, if the condition is not satisfied, the control circuit 60 outputs a signal CNT1 that instructs the selection of data A1b. This allows the CDR 40 to lock the phase of the signal CLK to the true convergence point TL. On the other hand, if the condition is satisfied, the control circuit 60 outputs a signal CNT1 that instructs the selection of data A1a. Therefore, after the CDR 40 locks the phase of the signal CLK to the true convergence point TL, it can obtain a larger gain (amount of change d(PDOUT) / d(UI)) by calculating the value PDOUT using data A1a.

[0104] Furthermore, if the condition is not satisfied, the control circuit 60 outputs a signal CNT2 instructing the first update circuit 51 to stop updating the tap coefficients. Furthermore, if the condition is satisfied, the control circuit 60 outputs a signal CNT2 instructing the first update circuit 51 to update the tap coefficients. This prevents the tap coefficients from becoming inappropriate values ​​when the first update circuit 51 updates the tap coefficients using data A1b based on the NRZ mode.

[0105] 2. Second embodiment Next, a second embodiment will be described.

[0106] The second embodiment differs from the first embodiment in that the update of the tap coefficients is not stopped. The following mainly describes the configuration and operation that are different from the first embodiment. Descriptions of the configuration and operation that are equivalent to those of the first embodiment will be omitted or simplified as appropriate.

[0107] 2.1 Host interface circuit (receiving circuit) configuration Fig. 10 is a block diagram showing an example of the configuration of a receiving circuit of a receiving device according to the second embodiment, which corresponds to Fig. 2 in the first embodiment.

[0108] The host interface circuit 8a according to the second embodiment includes pads P1 and P2, an analog processing circuit 10, a TI-ADC 20, a digital processing circuit 30a, a CDR 40, a tap coefficient updating circuit 50a, and a control circuit 60a. The configuration other than the digital processing circuit 30a, the tap coefficient updating circuit 50a, and the control circuit 60a is the same as the configuration shown in FIG. 2, and therefore a description thereof will be omitted.

[0109] The digital processing circuit 30a includes, for example, an FFE, a DFE, and a data decision circuit. The configuration of the digital processing circuit 30a will be described later. A signal X0 is input to the digital processing circuit 30a. The digital processing circuit 30a performs digital processing on the signal X0 using the FFE, DFE, and data decision circuit. Specifically, the digital processing circuit 30a generates signals X1 and Xf and data A1a, A1, and Af based on the signal X0. The digital processing circuit 30a outputs the signal X1 and the data A1 to the CDR 40. The digital processing circuit 30a outputs the signals X0, X1, and the data A1a to the tap coefficient update circuit 50a. The digital processing circuit 30a outputs the signal Xf and the data Af to the tap coefficient update circuit 50a and subsequent circuits (not shown).

[0110] The tap coefficient update circuit 50a is an arithmetic circuit. A set of signals X0, X1, and data A1a, and a set of signals X0, Xf, and data Af are input to the tap coefficient update circuit 50a from the digital processing circuit 30a. The tap coefficient update circuit 50a generates a signal TAP based on the set of signals X0, X1, and data A1a, and the set of signals X0, Xf, and data Af.

[0111] The control circuit 60a includes, for example, a processor such as a CPU and a ROM. The control circuit 60a controls the entire host interface circuit 8a. Specifically, for example, the control circuit 60a controls the digital processing circuit 30a based on a signal CNT1.

[0112] 2.2 Configuration of the digital processing circuit and tap coefficient update circuit Next, the internal configuration of the digital processing circuit and tap coefficient update circuit of the receiver circuit according to the second embodiment will be described. Fig. 11 is a block diagram showing an example of the configuration of the digital processing circuit and tap coefficient update circuit of the receiver circuit according to the second embodiment. Fig. 11 corresponds to Fig. 3 in the first embodiment.

[0113] First, the configuration of the digital processing circuit 30a will be described. The digital processing circuit 30a includes an FFE 31, a data determination circuit 32a, a data compression circuit 33, a multiplexer 34a, an FFE 35, a DFE 36, and a data determination circuit 37. The configuration other than the data determination circuit 32a and the multiplexer 34a is the same as the configuration shown in Fig. 3, so the description will be omitted or simplified.

[0114] The data decision circuit 32a receives the signal X1. Based on the signal X1, the data decision circuit 32a determines the data encoded by the host device 2 as data A1a. Specifically, when PAM4 is applied, the data decision circuit 32a determines 2-bit data for every n digital values ​​included in one cycle of the signal X1. The data decision circuit 32a outputs the data A1a to the data compression circuit 33 and the multiplexer 34a. The data A1a is also output to the tap coefficient update circuit 50a.

[0115] The multiplexer 34a receives data A1a and A1b from the data determination circuit 32a and data compression circuit 33, respectively. The multiplexer 34a also receives a signal CNT1 from the control circuit 60a. The multiplexer 34a outputs either the data A1a or A1b based on the signal CNT1. The output of the multiplexer 34a is also output to the CDR 40. That is, the multiplexer 34a switches the data to be output to the CDR 40 between the data A1a and the data A1b in accordance with the signal CNT1.

[0116] Next, the configuration of the tap coefficient update circuit 50a will be described. The tap coefficient update circuit 50a includes a first update circuit 51a and a second update circuit 52. The configuration other than the first update circuit 51a is the same as the configuration shown in FIG. 3, so the description will be omitted.

[0117] The first updating circuit 51a receives the signal X1 and data A1a from the FFE 31 and the data decision circuit 32a, respectively. The first updating circuit 51a also receives the signal X0 input to the digital processing circuit 30a. The first updating circuit 51a generates a portion of the signal TAP based on the signals X0 and X1 and the data A1a, and outputs it to the FFE 31. The portion of the signal TAP output from the first updating circuit 51a is applied to the FFE 31 as a tap coefficient.

[0118] 2.3 Receiving Operation Fig. 12 is a flowchart showing an example of a receiving operation in the receiving device according to the second embodiment, which corresponds to Fig. 7 in the first embodiment.

[0119] When reception of the signals S0 and / S0 begins (START), the tap coefficient update circuit 50a initializes the tap coefficients included in the signal TAP (S21).

[0120] Based on the signal CLK, the TI-ADC 20 samples and AD converts the signals S1 and / S1 generated based on the signals S0 and / S0, and generates a signal X0 for one cycle (S22).

[0121] The FFE 31 of the digital processing circuit 30a generates a signal X1 for one cycle based on the signal X0 for one cycle generated in the process of S22 and the tap coefficients initialized in the process of S21 (S23). The signal X1 is output to the CDR 40 and the tap coefficient update circuit 50a.

[0122] The data decision circuit 32a of the digital processing circuit 30a decides one period of data A1a based on one period of the signal X1 (S24).

[0123] The data compression circuit 33 of the digital processing circuit 30a compresses the data A1a for one period to generate data A1b (S25).

[0124] The control circuit 60a determines whether a condition is met (S26). The condition may be, for example, that the elapsed time since the start of reception of the signals S0 and / S0 is equal to or greater than a threshold value. The condition may be, for example, that the CDR 40 locks the phase of the signal CLK.

[0125] If it is determined that the condition is not satisfied (S26; no), the control circuit 60a outputs a signal CNT1 to the multiplexer 34a to instruct the selection of data A1b. The multiplexer 34a selects one cycle's worth of data A1b generated in the process of S25 in accordance with the signal CNT1 (S27). The data A1b selected in the process of S27 is output to the CDR 40 as data A1. In this way, if the condition is not satisfied, the digital processing circuit 30a operates in NRZ mode. In other words, if the condition is not satisfied, data A1 compressed to 1-bit data is input to the CDR 40.

[0126] If it is determined that the condition is met (S26; yes), the control circuit 60a outputs a signal CNT1 to the multiplexer 34a instructing the selection of data A1a. The multiplexer 34a selects one cycle's worth of data A1a generated in the process of S24 in accordance with the signal CNT1 (S28). The data A1a selected in the process of S28 is output to the CDR 40 as data A1. In this way, if the condition is met, the digital processing circuit 30a operates in PAM4 mode. In other words, if the condition is met, data A1, which is 2-bit data, is input to the CDR 40.

[0127] The first updating circuit 51a receives the signals X0 and X1 and the data A1a regardless of whether the condition is satisfied, and therefore updates the tap coefficients based on the signals X0 and X1 and the data A1a regardless of whether the condition is satisfied (S29).

[0128] The CDR 40 reproduces the signal CLK based on one cycle of the signal X1 and the data A1 (S30).

[0129] The host interface circuit 8a determines whether or not reception of the signals S0 and / S0 has finished based on whether or not the signals S1 and / S1 have been input (S31).

[0130] If reception of signals S0 and / S0 has not yet finished (S31; no), TI-ADC 20 generates signal X0 of the next cycle based on the recovered signal CLK (S22). This causes the processes of S22 to S31 to be repeated (CDR loop) until reception of signals S0 and / S0 finishes. Note that in the process of S23 in the second and subsequent CDR loops, the tap coefficients updated in the process of S29 are used.

[0131] When the reception of the signals S0 and / S0 is completed (S31; yes), the reception operation is completed (end).

[0132] 2.4 Effects of the Second Embodiment According to the second embodiment, the signals X0 and X1 and the data A1a are input to the first updating circuit 51a regardless of whether the condition is satisfied. This allows the first updating circuit 51a to update the tap coefficients even when the phase of the signal CLK is not locked or is in the middle of a locking operation. Therefore, the first updating circuit 51a can continue to update the tap coefficients regardless of whether the digital processing circuit 30a operates in PAM4 mode or NRZ mode.

[0133] 3. Third embodiment Next, a third embodiment will be described.

[0134] The third embodiment differs from the first and second embodiments in that data A1b based on the NRZ mode is not generated. The following mainly describes configurations and operations that differ from the first and second embodiments. Descriptions of configurations and operations equivalent to those of the first and second embodiments will be omitted or simplified as appropriate.

[0135] 3.1 Host interface circuit (receiving circuit) configuration Fig. 13 is a block diagram showing an example of the configuration of a receiving circuit of a receiving device according to the third embodiment, which corresponds to Fig. 2 in the first embodiment.

[0136] The host interface circuit 8b according to the third embodiment includes pads P1 and P2, an analog processing circuit 10, a TI-ADC 20, a digital processing circuit 30b, a CDR 40b, a tap coefficient updating circuit 50b, and a control circuit 60b. The configuration other than the digital processing circuit 30b, the CDR 40b, the tap coefficient updating circuit 50b, and the control circuit 60b is the same as the configuration shown in FIG. 2, and therefore description thereof will be omitted.

[0137] The digital processing circuit 30b includes, for example, an FFE, a DFE, and a data decision circuit. The configuration of the digital processing circuit 30b will be described later. The digital processing circuit 30b receives a signal X0. The digital processing circuit 30b performs digital processing on the signal X0 using the FFE, DFE, and data decision circuit. Specifically, the digital processing circuit 30b generates signals X1 and Xf and data A1_1, A1_2, A1a, and Af based on the signal X0. The digital processing circuit 30b outputs the signal X1 and the data A1_1 and A1_2 to the CDR 40b. The digital processing circuit 30b outputs the signals X0 and X1 and the data A1a to the tap coefficient update circuit 50b. The digital processing circuit 30b outputs the signal Xf and the data Af to the tap coefficient update circuit 50b and subsequent circuits (not shown). The data A1_1 and A1_2 will be described later in detail.

[0138] The CDR 40b is a clock data recovery circuit. The signal X1 and data A1_1 and A1_2 are input to the CDR 40b for each period. The CDR 40b calculates a phase correction amount for the signal CLK based on the signal X1 and data A1_1 and A1_2. The CDR 40b regenerates the signal CLK based on the calculated phase correction amount. The CDR 40b outputs the regenerated signal CLK to the TI-ADC 20 for each period. In this way, the CDR 40b regenerates the signal CLK, which serves as a reference for the sampling timing of the signal X0 for one subsequent period, based on the signal X1 and data A1_1 and A1_2 generated from the signal X0 for one period.

[0139] The tap coefficient update circuit 50b is an arithmetic circuit. A set of signals X0, X1, and data A1a, and a set of signals X0, Xf, and data Af are input to the tap coefficient update circuit 50b from the digital processing circuit 30b. The tap coefficient update circuit 50b generates a signal TAP based on the set of signals X0, X1, and data A1a, and the set of signals X0, Xf, and data Af.

[0140] The control circuit 60b includes, for example, a processor such as a CPU and a ROM. The control circuit 60b controls the entire host interface circuit 8b. Specifically, for example, the control circuit 60b controls the digital processing circuit 30b based on a signal CNT3. The signal CNT3 is a signal that controls the values ​​of the data A1_1 and A1_2 output from the digital processing circuit 30b.

[0141] 3.2 Configuration of the digital processing circuit and tap coefficient update circuit Next, the internal configuration of the digital processing circuit and tap coefficient update circuit of the receiver circuit according to the third embodiment will be described. Fig. 14 is a block diagram showing an example of the configuration of the digital processing circuit and tap coefficient update circuit of the receiver circuit according to the third embodiment. Fig. 14 corresponds to Fig. 3 in the first embodiment.

[0142] First, the configuration of the digital processing circuit 30b will be described. The digital processing circuit 30b includes an FFE 31, a data determination circuit 32b, an FFE 35, a DFE 36, a data determination circuit 37, and a pattern filter 38. The configuration other than the data determination circuit 32b and the pattern filter 38 is the same as the configuration shown in FIG. 3, so the description will be omitted or simplified.

[0143] The signal X1 is input to the data decision circuit 32b. Based on the signal X1, the data decision circuit 32b decides that the data encoded by the host device 2 is data A1a. Specifically, when PAM4 is applied, the data decision circuit 32b decides 2-bit data for every n digital values ​​included in one cycle of the signal X1. The data decision circuit 32b outputs the data A1a to the pattern filter 38. The data A1a is also output to the tap coefficient update circuit 50b.

[0144] The pattern filter 38 receives data A1a from the data determination circuit 32b. The pattern filter 38 generates data A1_1 and A1_2 based on the data A1a. The pattern filter 38 outputs the generated data A1_1 and A1_2 to the CDR 40b. The control circuit 60b also receives a signal CNT3 from the control circuit 60b. The pattern filter 38 is activated or deactivated according to the signal CNT3. When activated, the pattern filter 38 generates data A1_1 and A1_2 by filtering the data A1a with a predetermined pattern. The generated data A1_1 and A1_2 are output to the CDR 40b. When deactivated, the pattern filter 38 copies the data A1a to data A1_1 and A1_2 without filtering. The data A1a copied to data A1_1 and A1_2 are output to the CDR 40b.

[0145] FIG. 15 is a diagram illustrating an example of the functional configuration of a pattern filter in an inactive state of a digital processing circuit according to the third embodiment. FIG. 16 is a diagram illustrating an example of the functional configuration of a pattern filter in an active state of a digital processing circuit according to the third embodiment. FIGS. 15 and 16 illustrate the relationship between values ​​A1a[i] and A1a[i+1] included in data A1a and values ​​A1_2[i] and A1_1[i+1] included in data A1_2 and A1_1, respectively. Values ​​A1a[i] and A1a[i+1] are digital values ​​corresponding to two temporally adjacent symbols included in data A1a. Value A1_2[i] is a digital value corresponding to data A1a[i] in data A1_2. Value A1_1[i+1] is a digital value corresponding to data A1a[i+1] in data A1_1.

[0146] First, with reference to FIG. 15, the data A1_1 and A1_2 output from the inactive pattern filter 38 will be described.

[0147] 15, the pattern filter 38 copies the values ​​A1a[i] and A1a[i+1] to the values ​​A1_2[i] and A1_1[i+1], respectively, so that both the data A1_1 and A1_2 are essentially the same as the data A1a.

[0148] Next, with reference to FIG. 16, the data A1_1 and A1_2 output from the active pattern filter 38 will be described.

[0149] 16, when the value A1a[i] indicates "-3" and the value A1a[i+1] indicates "-3", "-1", or "+1", the pattern filter 38 outputs a value A1_2[i] indicating "0" and a value A1_1[i+1] indicating "0". When the value A1a[i] indicates "-3" and the value A1a[i+1] indicates "+3", the pattern filter 38 outputs a value A1_2[i] indicating "-3" and a value A1_1[i+1] indicating "+3". When the value A1a[i] indicates "-1" or "+1", the pattern filter 38 outputs a value A1_2[i] indicating "0" and a value A1_1[i+1] indicating "0". When the value A1a[i] indicates "+3" and the value A1a[i+1] indicates "-1," "+1," or "+3," the pattern filter 38 outputs a value A1_2[i] indicating "0" and a value A1_1[i+1] indicating "0." When the value A1a[i] indicates "+3" and the value A1a[i+1] indicates "-3," the pattern filter 38 outputs a value A1_2[i] indicating "+3" and a value A1_1[i+1] indicating "-3." In this way, the active pattern filter 38 selectively extracts transitions from "-3" to "+3" and transitions from "+3" to "-3" from among transitions between temporally adjacent symbols included in the data A1a.

[0150] Returning to Fig. 14, the configuration of the tap coefficient updating circuit 50b will be described. The tap coefficient updating circuit 50b includes a first updating circuit 51b and a second updating circuit 52. The configuration other than the first updating circuit 51b is the same as the configuration shown in Fig. 3, so description thereof will be omitted.

[0151] The first updating circuit 51b receives the signal X1 and data A1a from the FFE 31 and the data decision circuit 32b, respectively. The first updating circuit 51b also receives the signal X0 input to the digital processing circuit 30b. The first updating circuit 51b generates a portion of the signal TAP based on the signals X0 and X1 and the data A1a, and outputs it to the FFE 31. The portion of the signal TAP output from the first updating circuit 51b is applied to the FFE 31 as a tap coefficient.

[0152] 3.3 Phase detector configuration Next, the internal configuration of the phase detector (PD) of the clock data recovery circuit according to the third embodiment will be described. Fig. 17 is a block diagram showing an example of the configuration of the phase detector of the clock data recovery circuit according to the third embodiment. Fig. 17 corresponds to Fig. 6 in the first embodiment. The CDR 40b according to the third embodiment includes a PD 41b instead of the PD 41 shown in Fig. 5 in the first embodiment.

[0153] The values ​​X1[0] and A1_2[0] correspond to the symbols immediately preceding the values ​​X1[1] and A1_2[1], respectively. For example, the values ​​X1[0] and A1_2[0] are the value X1[n] included in the signal X1 and the value A1_2[n] included in the data A1_2 in the CDR loop one cycle before. The values ​​X1[0] and A1_2[0] are stored in advance in a register (not shown) during the CDR loop one cycle before, for example.

[0154] The PD 41b includes a plurality of multipliers 411b, a plurality of adders 412b, a plurality of sign function circuits 413b, and an adder 414b. The plurality of multipliers 411b include 2n multipliers 411b_1, 411b_2, ..., 411b_(2k-1) (not shown), 411b_2k (not shown), ..., 411b_(2n-1), and 411b_2n. The plurality of adders 412 include n adders 412_1, ..., 412_k (not shown), ..., and 412_n. The plurality of adders 412b include n adders 412b_1, ..., 412b_k (not shown), ..., and 412b_n. The plurality of sign function circuits 413b includes n sign function circuits 413b_1, . . . , 413b_k (not shown), .

[0155] The multiplier 411b_1 multiplies the value X1[0] by the value A1_1[1], and outputs the result of the operation, the value X1[0]A1_1[1], to the adder 412b_1.

[0156] The multiplier 411b_2 multiplies the value X1[1] by the value A1_2[0] and outputs the result of the operation, the value X1[1]A1_2[0], to the adder 412b_1.

[0157] The adder 412b_1 subtracts the value X1[1]A1_2[0] from the value X1[0]A1_1[1]. The adder 412b_1 outputs the value (X1[0]A1_1[1]-X1[1]A1_2[0]) as the calculation result to the sign function circuit 413b_1.

[0158] The sign function circuit 413b_1 determines whether the value (X1[0]A1_1[1]-X1[1]A1_2[0]) is positive or negative. If the value (X1[0]A1_1[1]-X1[1]A1_2[0]) is positive, the sign function circuit 413b_1 outputs "1" to the adder 414b. If the value (X1[0]A1_1[1]-X1[1]A1_2[0]) is negative, the sign function circuit 413b_1 outputs "-1" to the adder 414b. If the value (X1[0]A1_1[1]-X1[1]A1_2[0]) is "0", the sign function circuit 413b_1 outputs "0" to the adder 414b.

[0159] Furthermore, the multiplier 411b_(2k-1) multiplies the value X1[k-1] by the value A1_1[k], and outputs the result of the calculation, the value X1[k-1]A1_1[k], to the adder 412b_k.

[0160] The multiplier 411b_2k multiplies the value X1[k] by the value A1_2[k−1], and outputs the result of the operation, the value X1[k]A1_2[k−1], to the adder 412b_k.

[0161] The adder 412b_k subtracts the value X1[k]A1_2[k-1] from the value X1[k-1]A1_1[k]. The adder 412b_k outputs the operation result (X1[k-1]A1_1[k]-X1[k]A1_2[k-1]) to the sign function circuit 413b_k.

[0162] The sign function circuit 413b_k determines whether the value (X1[k-1]A1_1[k]-X1[k]A1_2[k-1]) is positive or negative. If the value (X1[k-1]A1_1[k]-X1[k]A1_2[k-1]) is positive, the sign function circuit 413b_k outputs "1" to the adder 414b. If the value (X1[k-1]A1_1[k]-X1[k]A1_2[k-1]) is negative, the sign function circuit 413b_k outputs "-1" to the adder 414b. If the value (X1[k-1]A1_1[k]-X1[k]A1_2[k-1]) is "0", the sign function circuit 413b_k outputs "0" to the adder 414b.

[0163] The explanations regarding the multipliers 411b_(2k-1) and 411b_2k, the adder 412b_k, and the sign function circuit 413b_k apply to all k values ​​between 2 and (n-1).

[0164] Similarly, the multiplier 411b_(2n-1) multiplies the value X1[n-1] by the value A1_1[n], and outputs the result of the operation, the value X1[n-1]A1_1[n], to the adder 412b_n.

[0165] The multiplier 411b_2n multiplies the value X1[n] by the value A1_2[n-1], and outputs the result of the operation, the value X1[n]A1_2[n-1], to the adder 412b_n.

[0166] The adder 412b_n subtracts the value X1[n]A1_2[n-1] from the value X1[n-1]A1_1[n]. The adder 412b_n outputs the operation result (X1[n-1]A1_1[n]-X1[n]A1_2[n-1]) to the sign function circuit 413b_n.

[0167] The sign function circuit 413b_n determines whether the value (X1[n-1]A1_1[n]-X1[n]A1_2[n-1]) is positive or negative. If the value (X1[n-1]A1_1[n]-X1[n]A1_2[n-1]) is positive, the sign function circuit 413b_n outputs "1" to the adder 414b. If the value (X1[n-1]A1_1[n]-X1[n]A1_2[n-1]) is negative, the sign function circuit 413b_n outputs "-1" to the adder 414b. If the value (X1[n-1]A1_1[n]-X1[n]A1_2[n-1]) is "0", the sign function circuit 413b_n outputs "0" to the adder 414b.

[0168] The adder 414b adds "1" or "-1" input from each of the n sign function circuits 413b_1 to 413b_n, and outputs the operation result to the LF 42 as a value PDOUT.

[0169] With the above configuration, when the pattern filter 38 is in an active state, the output from the corresponding sign function circuit 413b is “0” except when the value of the data A1a transitions from “−3” to “+3” or from “+3” to “−3” between temporally adjacent symbols.

[0170] 3.4 Receiving Operation Fig. 18 is a flowchart showing an example of a receiving operation in the receiving device according to the third embodiment, which corresponds to Fig. 7 in the first embodiment.

[0171] When reception of the signals S0 and / S0 begins (START), the tap coefficient update circuit 50b initializes the tap coefficients included in the signal TAP (S41).

[0172] Based on the signal CLK, the TI-ADC 20 samples and AD converts the signals S1 and / S1 generated based on the signals S0 and / S0, and generates a signal X0 for one cycle (S42).

[0173] The FFE 31 of the digital processing circuit 30b generates a signal X1 for one cycle based on the signal X0 for one cycle generated in the process of S42 and the tap coefficients initialized in the process of S41 (S43). The signal X1 is output to the CDR 40b and the tap coefficient update circuit 50b.

[0174] The data decision circuit 32b of the digital processing circuit 30b decides on one period of data A1a based on one period of the signal X1 (S44).

[0175] The control circuit 60b determines whether a condition is met (S45). The condition may be, for example, that the elapsed time since the start of reception of the signals S0 and / S0 is equal to or greater than a threshold value. The condition may be, for example, that the CDR 40b locks the phase of the signal CLK.

[0176] If it is determined that the condition is not satisfied (S45; no), the control circuit 60b outputs a signal CNT3 to the pattern filter 38 to activate the pattern filter 38. The pattern filter 38 becomes active in response to the signal CNT3. The active pattern filter 38 generates data A1_1 and A1_2 based on the data A1a (S46). The data A1_1 and A1_2 selected in the processing of S46 are output to the CDR 40b. In this way, if the condition is not satisfied, information regarding the transition from "-3" to "+3" and the transition from "+3" to "-3" out of the data transitions in PAM4 mode is selectively output as the data A1_1 and A1_2 output to the CDR 40b.

[0177] If it is determined that the condition is satisfied (S45; yes), the control circuit 60b outputs a signal CNT3 to the pattern filter 38 to deactivate the pattern filter 38. The pattern filter 38 is deactivated in response to the signal CNT3. The inactive pattern filter 38 generates data A1_1 and A1_2 by copying the data A1a (S47). The data A1_1 and A1_2 generated by the processing of S47 are output to the CDR 40b. In this way, when the condition is satisfied, all information related to data transitions in PAM4 mode is output to the data A1_1 and A1_2 output to the CDR 40b.

[0178] The first updating circuit 51b receives the signals X0 and X1 and the data A1a regardless of whether the condition is satisfied, and therefore updates the tap coefficients based on the signals X0 and X1 and the data A1a regardless of whether the condition is satisfied (S48).

[0179] The CDR 40b reproduces the signal CLK based on one cycle of the signal X1 and the data A1_1 and A1_2 (S49).

[0180] The host interface circuit 8b determines whether or not reception of the signals S0 and / S0 has finished based on whether or not the signals S1 and / S1 have been input (S50).

[0181] If reception of signals S0 and / S0 has not finished (S50; no), TI-ADC 20 generates signal X0 of the next cycle based on the recovered signal CLK (S42). This causes the processes of S42 to S50 to be repeated (CDR loop) until reception of signals S0 and / S0 finishes. Note that in the process of S43 in the second and subsequent CDR loops, the tap coefficients updated in the process of S48 are used.

[0182] If the reception of the signals S0 and / S0 has finished (S50; yes), the reception operation ends (end).

[0183] 3.5 Effects of the Third Embodiment According to the third embodiment, the control circuit 60b outputs a signal CNT3 instructing whether to activate the pattern filter 38, depending on whether a condition is satisfied. The active pattern filter 38 outputs data A1_1 and A1_2, obtained by filtering data A1a in accordance with transitions of bit data between symbols, to the CDR 40b. The inactive pattern filter 38 outputs data A1_1 and A1_2, which are substantially equivalent to data A1a, to the CDR 40b. This allows the CDR 40b to selectively use data A1a based on the PAM4 mode and filtered data A1_1 and A1_2 when recovering the signal CLK, depending on whether a condition is satisfied.

[0184] Specifically, the value A1_2[i] of the data A1_2 and the value A1_1[i+1] of the data A1_1 output by the active pattern filter 38 are both "0" except when the transition from the value A1a[i] to the value A1a[i+1] is from "-3" to "+3" or from "+3" to "-3." The value A1_2[i] of the data A1_2 and the value A1_1[i+1] of the data A1_1 output by the active pattern filter 38 are equal to the values ​​A1a[i] and A1a[i+1], respectively, when the transition from the value A1a[i] to the value A1a[i+1] is from "-3" to "+3" or from "+3" to "-3." This allows the output of the corresponding sign function circuit 413b_i to be set to "0" except when the transition from value A1a[i] to value A1a[i+1] is from "-3" to "+3" or from "+3" to "-3." Therefore, when the phase of signal CLK is not locked or is in the middle of a locking operation, PD 41b can prevent all transition patterns different from the transition pattern in NRZ mode (i.e., transitions from "-3" to "+3" or from "+3" to "-3") from being reflected in the value PDOUT. Therefore, it is possible to achieve effects equivalent to those of the first and second embodiments.

[0185] 4. Modifications, etc. The first, second, and third embodiments are not limited to the above examples, and various modifications can be applied.

[0186] In the first and second embodiments described above, the data compression circuits 33 and 33a generate data A1b containing one bit of data per symbol, but this is not limiting. If data A1a contains three or more bits of data per symbol, the data compression circuits 33 and 33a may generate data A1b containing fewer bits of data per symbol than the bits contained in data A1a.

[0187] In the first, second, and third embodiments described above, the host interface circuit 8 has been described as an example of the receiving circuit, but the receiving circuit is not limited to this. For example, the receiving circuit may be any semiconductor integrated circuit used for serial communication.

[0188] Note that part or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes. [Appendix 1] a converter that converts an analog signal into a digital signal based on a clock signal; a determination circuit that determines first data having two or more bit data per symbol based on the digital signal; a filter circuit that filters the first data in accordance with transitions of bit data between symbols to generate third data; a recovery circuit for recovering the clock signal; a control circuit configured to input the digital signal and the first data to the recovery circuit when a condition is not met, and to input the digital signal and the third data to the recovery circuit when the condition is met; A semiconductor integrated circuit comprising: [Appendix 2] Satisfying the condition includes that the elapsed time from the start of reception of the analog signal is equal to or greater than a threshold, or that the phase of the clock signal recovered by the recovery circuit is locked. 10. The semiconductor integrated circuit of claim 1. [Appendix 3] further comprising an update circuit that updates tap coefficients used in an operation on the digital signal regardless of whether the condition is satisfied. 10. The semiconductor integrated circuit of claim 1. [Appendix 4] the recovery circuit includes a phase detector that calculates a first value relating to a phase of the clock signal based on the digital signal and the first data or the third data; the digital signal includes a second value sampled at a first time and a third value sampled at a second time different from the first time; the first data includes a fourth value corresponding to the second value and a fifth value corresponding to the third value; the third data includes a sixth value corresponding to the second value and a seventh value corresponding to the third value; the phase detector calculates the first value based on a difference between a product of the second value and the fifth value and a product of the third value and the fourth value, or a difference between a product of the second value and the seventh value and a product of the third value and the sixth value. 10. The semiconductor integrated circuit of claim 1. [Appendix 5] The phase detector is a MM baud rate phase detector. 5. The semiconductor integrated circuit according to claim 4. [Appendix 6] when a transition between the fourth value and the fifth value is a first pattern, the sixth value is equal to the fourth value and the seventh value is equal to the fifth value; If the transition between the fourth value and the fifth value does not follow the first pattern, the sixth value and the seventh value are both 0. 5. The semiconductor integrated circuit according to claim 4. [Appendix 7] A semiconductor integrated circuit according to any one of Supplementary Note 1 to Supplementary Note 6; a data processing circuit that utilizes data output from the semiconductor integrated circuit; A receiving device comprising:

[0189] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0190] 1. Information processing system 2...Host device 3. Memory system 4...Memory device 5...Memory controller 6...Control section 7...Buffer memory 8, 8a, 8b...Host interface circuit 9...Memory interface circuit 10...Analog processing circuit 20...TI-ADC 30, 30a, 30b...Digital processing circuit 31,35…FFE 32, 32a, 32b, 37...Data judgment circuit 33...Data compression circuit 34, 34a...Multiplexer 36…DFE 38...Pattern filter 40,40b…CDR 41,41b…PD 42...LF 43...PLL 44...PI 45...Clock generation circuit 50, 50a, 50b...Tap coefficient update circuit 51,51a,51b...1st update circuit 52…Second update circuit 60, 60a, 60b...Control circuit 411,411b...multiplier 412, 412b, 414, 414b...adder 413, 413b...Sign function circuit

Claims

1. a converter that converts an analog signal into a digital signal based on a clock signal; a determination circuit that determines, based on the digital signal, whether first data has a first number of bits per symbol or second data has a second number of bits per symbol that is less than the first number; a recovery circuit for recovering the clock signal; a control circuit configured to input the digital signal and the first data to the recovery circuit when a condition is met, and to input the digital signal and the second data to the recovery circuit when the condition is not met; Equipped with The condition being satisfied includes that the elapsed time from the start of reception of the analog signal is equal to or greater than a threshold, or that the phase of the clock signal recovered by the recovery circuit is locked. Semiconductor integrated circuit.

2. an update circuit for updating tap coefficients used in an operation on the digital signal; the control circuit is configured to stop updating of the tap coefficients by the update circuit when the condition is not satisfied, and to update the tap coefficients by the update circuit when the condition is satisfied.

2. The semiconductor integrated circuit according to claim 1.

3. further comprising an update circuit that updates tap coefficients used in an operation on the digital signal regardless of whether the condition is satisfied.

2. The semiconductor integrated circuit according to claim 1.

4. the first data includes 2-bit data per symbol; the second data includes 1-bit data per symbol; 2. The semiconductor integrated circuit according to claim 1.

5. the recovery circuit includes a phase detector that calculates a first value relating to a phase of the clock signal based on the digital signal and the first data or the second data; the digital signal includes a second value sampled at a first time and a third value sampled at a second time different from the first time; the first data includes a fourth value corresponding to the second value and a fifth value corresponding to the third value; the second data includes a sixth value corresponding to the second value and a seventh value corresponding to the third value; the phase detector calculates the first value based on a difference between a product of the second value and the fifth value and a product of the third value and the fourth value, or a difference between a product of the second value and the seventh value and a product of the third value and the sixth value.

2. The semiconductor integrated circuit according to claim 1.

6. the phase detector is a MM baud rate phase detector; 6. The semiconductor integrated circuit according to claim 5.

7. a converter that converts an analog signal into a digital signal based on a clock signal; a determination circuit that determines first data having two or more bit data per symbol based on the digital signal; a filter circuit that filters the first data in accordance with transitions of bit data between symbols to generate third data; a recovery circuit for recovering the clock signal; a control circuit configured to input the digital signal and the first data to the recovery circuit when a condition is met, and to input the digital signal and the third data to the recovery circuit when the condition is not met; Equipped with The condition being satisfied includes that the elapsed time from the start of reception of the analog signal is equal to or greater than a threshold, or that the phase of the clock signal recovered by the recovery circuit is locked. Semiconductor integrated circuit.

8. A semiconductor integrated circuit according to any one of claims 1 to 7; a data processing circuit that utilizes data output from the semiconductor integrated circuit; A receiving device comprising:

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