Information processing system and memory system

Abstract

To provide an information processing system and a memory system for suppressing the increase in processing load at the time of reading data.SOLUTION: An information processing system 1 comprises a memory system including a non-volatile memory, and a host device including a host memory and a processor which executes software for accessing data stored in the non-volatile memory. The processor assigns a cache area for caching data stored in the non-volatile memory to the host memory and looks up the cache area when executing the software. When a cache hit occurs as a result of looking up, the processor accesses the cache area without accessing the non-volatile memory and caches data stored in the non-volatile memory into the cache area at a second frequency lower than a first frequency at which a cache miss occurs.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to an information processing system and a memory system. [Background technology]

[0002] An information processing system including a host device and a memory system is known. The memory system includes a NAND flash memory as a nonvolatile memory and a memory controller that controls the nonvolatile memory. The memory controller reads data from the nonvolatile memory in response to a request from the host device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,474,588 [Patent Document 2] U.S. Patent No. 10,552,329 [Patent Document 3] International Publication No. 2018 / 211749 [Non-patent literature]

[0004] [Non-Patent Document 1] Gil Einziger, et al., “TinyLFU: A Highly Efficient Cache Admission Policy,” arXiv:1512.00727v2, 2015 [Non-patent document 2] Xiaozhou Li, et al., “Be Fast, Cheap and in Control with SwitchKV,” 13th USENIX Symposium on Networked Systems Design and Implementation (NSDI '16), 2016 Summary of the Invention [Problem to be solved by the invention]

[0005] This suppresses the increase in processing load when reading data. [Means for solving the problem]

[0006] According to an embodiment, an information processing system includes a memory system including a nonvolatile memory, and a host device including a processor and a host memory that executes software that accesses data stored in the nonvolatile memory. The processor is configured to allocate a cache area in the host memory for caching data stored in the nonvolatile memory, look up the cache area when executing the software, and if a cache hit occurs as a result of the lookup, access the cache area without accessing the nonvolatile memory, and cache the data stored in the nonvolatile memory in the cache area at a second frequency that is lower than a first frequency at which cache misses occur. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of a hardware configuration of an information processing system according to a first embodiment. [Figure 2] FIG. 1 is a block diagram showing an example of the functional configuration of an information processing system according to a first embodiment. [Figure 3] FIG. 2 is a diagram showing an example of the arrangement of an access area of ​​the information processing system according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing an example of the arrangement of a cache area of ​​the information processing system according to the first embodiment. [Figure 5] 10 is a flowchart showing an example of a read access process in an application of the information processing system according to the first embodiment. [Figure 6] 10 is a flowchart showing an example of a read process in a read module of the information processing system according to the first embodiment. [Figure 7]10 is a flowchart showing an example of a mistake frequency collection process in the mistake frequency collection module of the information processing system according to the first embodiment. [Figure 8] 10 is a flowchart showing an example of a cache replacement process in a cache replacement module of the information processing system according to the first embodiment. [Figure 9] FIG. 4 is a diagram showing the relationship between the frequency of read access processing and the frequency of cache replacement processing in the information processing system according to the first embodiment. [Figure 10] FIG. 10 is a block diagram showing an example of the functional configuration of an information processing system according to a second embodiment. [Figure 11] 10A and 10B are diagrams showing an example of the configuration of a cache area and access frequency information in an information processing system according to a second embodiment. [Figure 12] 10 is a flowchart showing an example of a read access process in an application of the information processing system according to the second embodiment. [Figure 13] 10 is a flowchart showing an example of a cache replacement process in a cache replacement module of an information processing system according to the second embodiment. [Figure 14] FIG. 11 is a block diagram showing an example of the hardware configuration of an information processing system according to a third embodiment. [Figure 15] FIG. 10 is a block diagram showing an example of the functional configuration of an information processing system according to a third embodiment. [Figure 16] 11 is a flowchart showing an example of a read process in a read module of an information processing system according to the third embodiment. [Figure 17] FIG. 10 is a block diagram showing an example of the functional configuration of an information processing system according to a fourth embodiment. [Figure 18] 13 is a flowchart showing an example of a read access process in an application of the information processing system according to the fourth embodiment. [Figure 19] 13 is a flowchart showing an example of a read process in a read module of an information processing system according to the fourth embodiment. [Figure 20] FIG. 13 is a block diagram showing an example of the functional configuration of an information processing system according to a fifth embodiment. [Figure 21] FIG. 13 is a block diagram showing an example of the functional configuration of an information processing system according to a sixth embodiment. [Figure 22] 13 is a flowchart showing an example of a cache replacement process in a cache replacement module of an information processing system according to the seventh embodiment. [Figure 23] FIG. 10 is a block diagram showing an example of a hardware configuration of an information processing system according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be given the same reference numerals. Furthermore, when multiple components having the same reference numerals are to be distinguished from one another, a subscript will be added to the common reference numeral. In addition, when no particular distinction is required between multiple components, only the common reference numerals will be added to the multiple components, and no subscript will be added.

[0009] 1. First embodiment 1.1 Configuration The configuration of the information processing system according to the first embodiment will be described.

[0010] 1.1.1 Hardware configuration of information processing systems 1 is a block diagram showing the hardware configuration of an information processing system according to Embodiment 1. The information processing system 1 includes a host device 10 and a memory system 20.

[0011] The information processing system 1 is, for example, a personal computer or a server in a data center. The host device 10 includes a processor 11 and a host memory 12.

[0012] The processor 11 includes, for example, a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). The processor 11 requests data input / output (access) to the memory system 20. For example, the processor 11 requests data write processing and data read processing from the memory system 20. Hereinafter, the request processing related to the read processing in the host device 10 is also referred to as read access processing.

[0013] The host memory 12 is, for example, a dynamic random access memory (DRAM). The host memory 12 is used as a working area when the processor 11 executes an operating system (OS), application programs, etc. The host memory 12 is also used as a memory area for temporarily storing data read from the memory system 20.

[0014] The memory system 20 is a storage device configured to be connected to the host device 10. The memory system 20 is, for example, an SD TM The memory system 20 includes a memory controller 30 and a nonvolatile memory 40. The memory controller 30 may be a memory card, a Universal Flash Storage (UFS), or a Solid State Drive (SSD).

[0015] The memory controller 30 is configured as an integrated circuit such as an SoC (System-on-a-Chip). The memory controller 30 includes a controller control circuit 31, a host interface circuit (host I / F) 32, and a memory interface circuit (memory I / F) 33.

[0016] The controller control circuit 31 includes, for example, a processor such as a CPU, a ROM, and a RAM. The controller control circuit 31 controls the input and output of data between the host device 10 and the nonvolatile memory 40. For example, the controller control circuit 31 executes a data read process for the nonvolatile memory 40 in response to a read request from the host device 10.

[0017] The host interface circuit 32 controls communication between the host device 10 and the memory controller 30. The host interface circuit 32 is connected to the host device 10 via a host bus HB. The host bus HB is, for example, TM Interface: SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)), or PCIe TM (Peripheral Component Interconnect express) compliant.

[0018] The memory interface circuit 33 controls communication between the nonvolatile memory 40 and the memory controller 30. The memory interface circuit 33 is connected to the nonvolatile memory 40 via a memory bus MB. The memory bus MB conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0019] The nonvolatile memory 40 is, for example, a NAND flash memory. The nonvolatile memory 40 includes a plurality of memory chips CP_1, ..., CP_n (n is an integer equal to or greater than 2). Each of the plurality of memory chips CP_1 to CP_n includes a plurality of memory cells. Each of the plurality of memory cells stores data in a nonvolatile manner.

[0020] In the above example, the host device 10 and the memory system 20 are components in a personal computer or a server, but the present invention is not limited to this. For example, the host device 10 and the memory system 20 may be connected to each other via a network. In this case, the information processing system 1 is a cluster made up of multiple servers. The memory system 20 is, for example, a storage server. In this case, the host bus HB connecting the host device 10 and the memory system 20 may be, for example, an Ethernet TM , and InfiniBand, etc.

[0021] 1.1.2 Functional configuration of information processing system FIG. 2 is a block diagram showing the functional configuration of the information processing system according to the first embodiment.

[0022] The host device 10 functions as a buffer area 110, a cache area 120, a queue 130, an application 140, a miss frequency collection module 150, and a cache replacement module 160. The memory controller 30 functions as a read module 310. The non-volatile memory 40 functions as an access area 410.

[0023] The buffer area 110 is, for example, a memory area that functions as a DMA (Direct Memory Access) buffer in the host memory 12. The buffer area 110 temporarily stores, for example, data that is output from the memory system 20 in response to a read request.

[0024] The cache area 120 is, for example, a memory area that functions as a software cache in the host memory 12. The cache area 120 stores, for example, information about data that is to be cached in the medium to long term (i.e., data that is frequently accessed in the medium to long term) out of the data stored in the access area 410. The cache area 120 includes data fields 121a and 121b and tag fields 122a and 122b.

[0025] The data fields 121a and 121b store the actual data to be cached. The data fields 121a and 121b are associated with the tag fields 122a and 122b, respectively. The tag fields 122a and 122b store information for searching for the data stored in the data fields 121a and 121b, respectively. The data structures of the data fields 121a and 122a are the same as those of the data fields 121b and 122b. Details of the data structures in the cache area 120 will be described later.

[0026] The queue 130 includes SQ131 and CQ132. SQ131 is a submission queue. For example, various requests (e.g., read requests) to the memory system 20 are stored in SQ131. CQ132 is a completion queue. The results of various requests completed by the memory system 20 are stored in CQ132. For example, CQ132 stores a pointer indicating the address of the storage destination of data output from the memory system 20 in response to a read request.

[0027] The application 140 is a software program executed by the processor 11. For example, multithreading is implemented in the application 140. The application 140 determines whether the data to be accessed is stored in the cache area 120 in response to the occurrence of a read access process. The process of determining whether the data to be accessed is stored in the cache area 120 is also called a lookup process. That is, the application 140 looks up the cache area 120 in response to the occurrence of a read access process. If the data to be accessed is stored in the cache area 120, the application 140 accesses the data to be accessed in the data field 121 of the cache area 120. If the data to be accessed is not stored in the cache area 120, the application 140 stores a read request in the SQ 131. The application 140 accesses data output from the memory system 20 as a result of the read request based on the pointer stored in the CQ 132. The data output from the memory system 20 is stored, for example, in the buffer area 110.

[0028] The application 140 also stores reference count values ​​141a and 141b. The reference count value 141a is a counter value indicating how many threads of the application 140 are accessing the data field 121a and the tag field 122a of the cache area 120. The reference count value 141b is a counter value indicating how many threads of the application 140 are accessing the data field 121b and the tag field 122b of the cache area 120.

[0029] In the following description, the state in which the accessed data is stored in the cache area is also referred to as a "cache hit." The state in which the accessed data is not stored in the cache area is also referred to as a "cache miss."

[0030] The read access process is executed for either the pair of data field 121a and tag field 122a or the pair of data field 121b and tag field 122b. In the following description, the pair of data field 121a and tag field 122a for which the read access process is executed, or the pair of data field 121b and tag field 122b, is referred to as the "active cache area 120." The pair of data field 121a and tag field 122a for which the above-mentioned determination process in the application 140 is not executed, or the pair of data field 121b and tag field 122b, is referred to as the "inactive cache area 120." Furthermore, the reference count value 141a or 141b corresponding to the active cache area 120 is referred to as the "active reference count value 141." The reference count value 141a or 141b corresponding to the inactive cache area 120 is referred to as the "inactive reference count value 141."

[0031] The miss frequency collection module 150 is a module that executes the miss frequency collection process. The miss frequency collection process is a process that collects the frequency (miss frequency) of cache misses occurring during read access processing in association with the access area 410. For example, the miss frequency collection module 150 counts the number of read requests stored in SQ131 for each address (access destination) to be accessed each time a first period elapses. The first period is, for example, 10 milliseconds or less. In this case, the miss frequency collection process is executed asynchronously with the read access processing (lookup processing). Furthermore, the miss frequency collection module 150 may count the number of read requests stored in SQ131 for each address to be accessed each time the number of cache misses reaches a first number. The first number is, for example, 128 or less. In this case, the miss frequency collection process is executed synchronously with the read access processing (lookup processing). The miss frequency may or may not be reset each time the miss frequency collection process is executed. If the miss frequency is not reset each time the miss frequency collection process is executed, the miss frequency collection module 150 may, for example, uniformly halve the miss frequencies already collected as new miss frequencies. The miss frequency collection module 150 stores the collected miss frequencies as miss frequency information 151.

[0032] The miss frequency information 151 may include a Bloom filter, a CM sketch (Count-Min sketch), and a map structure. The Bloom filter is a data structure that can probabilistically determine whether or not a miss frequency occurs in a Boolean format. The CM sketch is a data structure that can probabilistically determine the number of miss frequency occurrences in an integer format. The map structure is a data structure that determines the number of miss frequency occurrences in an integer format. With the above configuration, the miss frequency collection module 150 performs probabilistic calculations for access targets with low miss frequencies, while selectively calculating access targets with high miss frequencies with high accuracy. This allows the miss frequency collection module 150 to operate with fewer memory resources than when strictly calculating all miss frequencies.

[0033] The cache replacement module 160 is a module that executes cache replacement processing. The cache replacement processing is processing in which data stored in the inactive cache area 120 is replaced with data that has a high miss frequency. For example, the cache replacement module 160 executes the cache replacement processing every time a second period longer than the first period elapses. The second period is, for example, several hundred milliseconds. In this case, the cache replacement processing is executed asynchronously with the read access processing. The cache replacement module 160 may also execute the cache replacement processing every time the number of cache misses reaches a second number that is greater than the first number. The second number is, for example, 1024. In this case, the cache replacement processing may be executed synchronously with the read access processing. The timer that counts up to the second period and the timer that counts up to the second number are reset every time the cache replacement processing is executed.

[0034] In the cache replacement process, the cache replacement module 160 determines which data has a high miss frequency among the data stored in the memory system 20, based on the miss frequency information 151. For example, the cache replacement module 160 determines that, among the data stored in the memory system 20, data with a cache miss count equal to or greater than a threshold value is data with a high miss frequency. Furthermore, for example, the cache replacement module 160 may determine that, among the data stored in the memory system 20, the top N data with the highest cache miss counts are data with a high miss frequency (N is a natural number).

[0035] The cache replacement module 160 randomly determines whether to replace data stored in the cache area 120 with data determined to have a high miss frequency. If it is determined to replace the data, the cache replacement module 160 replaces the data stored in the inactive cache area 120 with data determined to have a high miss frequency. If it is determined not to replace the data, the cache replacement module 160 does not replace the data. Note that the cache replacement module 160 may unconditionally replace data stored in the cache area 120 with data determined to have a high miss frequency.

[0036] The read module 310 is a module that executes read processing in response to a read request. Upon receiving a read request, the read module 310 reads the access target data from the nonvolatile memory 40 via the memory bus MB. Then, the read module 310 outputs the access target data read from the nonvolatile memory 40 to the host device 10 via the host bus HB. The output access target data is temporarily stored in the buffer area 110, for example.

[0037] The access area 410 is a memory area that stores data in a nonvolatile manner in the nonvolatile memory 40. The access area 410 stores data that is to be accessed in a read access process in a nonvolatile manner.

[0038] 1.1.3 Configuring the Access Area Fig. 3 is a diagram showing an example of the configuration of an access area of ​​the information processing system according to the first embodiment. As shown in Fig. 3, the access area 410 is divided into a plurality of sub-areas. Data DAT to be accessed is stored in each of the plurality of sub-areas.

[0039] Specifically, for example, each of the multiple sub-areas in the access area 410 is associated with a combination of one tag number out of x tag numbers and one group out of y groups (x and y are each an integer of 2 or greater). The example in Fig. 3 shows a case where data DAT((i-1)y+j) is stored in a sub-area associated with a combination of tag number "i" and group "j" for any combination of i between 1 and x, and j between 1 and y.

[0040] With the above configuration, among the multiple sub-areas in the access area 410, x sub-areas associated with the same group are assigned different tag numbers.

[0041] 1.1.4 Configuring the Cache Area Fig. 4 is a diagram showing an example of the configuration of a cache area of ​​the information processing system according to the first embodiment. Fig. 4 shows an example of the configuration of a set of data field 121a and tag field 122a. Note that the configuration of a set of data field 121b and tag field 122b is the same as the configuration of the set of data field 121a and tag field 122a, and therefore a description thereof will be omitted. However, data different from that stored in the set of data field 121a and tag field 122a may be stored in the set of data field 121b and tag field 122b.

[0042] The set of data field 121a and tag field 122a is divided into y sub-areas. The y sub-areas are associated with groups "1" to "y," respectively. That is, the sub-area of ​​the set of data field 121a and tag field 122a associated with group "j" is allocated as a cache area for the x sub-areas associated with group "j" in the access area 410.

[0043] The sub-area of ​​the data field 121a stores cache data CDAT The sub-area of ​​the tag field 122a stores a pair of a tag number and a validity flag.

[0044] The validity flag of the tag field 122a indicates whether valid cache data CDAT is stored in the corresponding data field 121a. Specifically, for example, if the validity flag V2 of the tag field 122a associated with group "2" is "true", the cache data CDAT2 of the data field 121a associated with group "2" is valid. If the validity flag V3 of the tag field 122a associated with group "3" is "false", the cache data CDAT3 of the data field 121a associated with group "3" is invalid.

[0045] The tag number of the tag field 122a indicates to which tag number in the access area 410 the cache data CDAT stored in the data field 121a is assigned. Specifically, for example, when the tag number T1 of the tag field 122a associated with group "1" is "3", the cache data CDAT1 stored in the data field 121a associated with group "1" is data DAT(2y+1). When the tag number Ty of the tag field 122a associated with group "y" is "x", the cache data CDATy stored in the data field 121a associated with group "y" is data DAT(xy).

[0046] With the above configuration, it is possible to identify which sub-area of ​​the access area 410 the cache data CDAT stored in the cache area 120 corresponds to. Such a data structure in the cache area 120 is also called a direct-mapped cache structure. While the examples in FIGS. 3 and 4 illustrate cases in which sub-areas are identified by a pair of a tag number and a group, this is not limiting. For example, the tag number and group may be calculated as the output when the address of the access area 410 is input to a hash function. Each sub-area may store variable-length data, not limited to fixed-length data. When the data stored in each sub-area is variable-length, the data is stored in each sub-area, for example, in a key-value store format. Here, when the data structure of the cache area 120 is a direct-mapped type, the cache area 120 has a configuration in which a corresponding entry is uniquely determined when a key is input.

[0047] 1.2 Operation Next, the operation of the information processing system according to the first embodiment will be described.

[0048] 1.2.1 Read access processing FIG. 5 is a flowchart showing an example of a read access process in an application of the information processing system according to the first embodiment.

[0049] When a read access occurs (start), the application 140 increments the reference count value 141 of the active state (S1). More specifically, the application 140 acquires the cache number (current number) of the active cache area 120. Then, the application 140 increments the reference count value 141 of the current number.

[0050] The application 140 determines whether or not the data to be accessed is stored in the current numbered cache area 120. In other words, the application 140 determines whether or not a cache hit has occurred (S2).

[0051] If a cache hit occurs (S2; yes), the application 140 accesses the data to be accessed that is stored in the data field 121 of the cache area 120 with the current number (S3). As a result, the application 140 uses the data to be accessed. Note that the switching of the active state of the cache area 120 is performed asynchronously with the application 140. For this reason, the active state of the cache area 120 may have changed between the time of processing S1 and the time of processing S3. For this reason, the application 140 acquires the current number at the time of processing S1 and stores it until the read access process is completed.

[0052] After the process of S3, the application 140 decrements the reference count value 141 of the current number (S4).

[0053] If a cache miss occurs (S2; no), the application 140 decrements the reference count value 141 of the current number (S5).

[0054] The application 140 causes the memory system 20 to execute a read process for the data to be accessed (S6). The data to be accessed that is output from the memory system 20 by the read process of S6 is stored in the buffer area 110.

[0055] The application 140 accesses the data to be accessed that is stored in the buffer area 110 (S7), and the application 140 then uses the data to be accessed.

[0056] When the process of S4 or the process of S7 ends, the read access process ends (ends).

[0057] In this way, the read access process branches into a process in which a cache hit occurs and the data field 121 of the cache area 120 is accessed, and a process in which a cache miss occurs and the access area 410 is accessed. Therefore, the frequency at which read access processes occur is the sum of the frequency at which a cache hit occurs (i.e., the frequency at which the data field 121 of the cache area 120 is accessed) and the frequency at which a cache miss occurs (i.e., the frequency at which the access area 410 is accessed).

[0058] 1.2.2 Lead Processing 6 is a flowchart showing an example of a read process in the read module of the information processing system according to Embodiment 1. The processes of S11 and S12 shown in FIG.

[0059] When a read request is stored in SQ131 (start), the read module 310 executes the read process of the data to be accessed from the access area 410 in the nonvolatile memory 40 (S11).

[0060] The read module 310 outputs the access target data read from the access area 410 by the process of S11 to the host device 10 (S12). The data output to the host device 10 is stored in the buffer area 110.

[0061] When the processing of S12 is completed, the read processing is completed (end).

[0062] 1.2.3 Miss frequency collection process FIG. 7 is a flowchart showing an example of the error frequency collection process in the error frequency collection module of the information processing system according to the first embodiment.

[0063] When the first period has elapsed or the number of occurrences of cache misses reaches the first number (start), the miss frequency collection module 150 selects the address to be accessed that is included in the read request in SQ131 (S21).

[0064] The miss frequency collection module 150 determines whether the address selected in the process of S21 has already been registered in the Bloom filter (S22).

[0065] If the selected address has not been registered in the Bloom filter (S22; no), the miss frequency collection module 150 registers the address selected in the process of S21 in the Bloom filter (S23). As a result, the miss frequency information 151 stores information for probabilistically determining whether or not a cache miss has occurred in a Boolean format for each address in the access area 410.

[0066] If the selected address is already registered in the Bloom filter (S22; yes), the miss frequency collection module 150 determines whether the count number by the CM sketch of the address selected in the process of S21 has reached the upper limit (S24). Note that the case where it is determined that the selected address is already registered in the Bloom filter includes a false positive. Therefore, even if the selected address is not already registered in the Bloom filter, the miss frequency collection module 150 may erroneously determine that it is already registered in the Bloom filter.

[0067] If the count number by the CM sketch of the selected address has not reached the upper limit (S24; no), the miss frequency collection module 150 increments the count number by the CM sketch of the address selected in the process of S21 (S25). As a result, the miss frequency information 151 stores information for probabilistically determining, in integer format, how often a cache miss has occurred for each address in the access area 410.

[0068] If the count number by the CM sketch of the selected address reaches the upper limit (S24; yes), the miss frequency collection module 150 increments the exact count number of the address selected in the process of S21 (S26).

[0069] Note that the determination that the count number of the selected address by the CM sketch has reached the upper limit includes a false positive case. Therefore, even if the count number of the selected address by the CM sketch has not reached the upper limit, the miss frequency collection module 150 may erroneously determine that the count number of the CM sketch has reached the upper limit.

[0070] After the process of S23, S25, or S26, the miss frequency collection module 150 determines whether or not the addresses included in all the read requests in SQ131 have been selected (S27).

[0071] If the addresses included in all the read requests in SQ131 have not been selected (S27; no), the miss frequency collection module 150 selects the addresses to be accessed included in the read requests in SQ131 (S21). Then, the subsequent processes of S22 to S27 are executed. As a result, the processes of S21 to S27 are repeated until the addresses included in all the read requests in SQ131 have been selected.

[0072] If the addresses included in all the read requests in SQ131 are selected (S27; yes), the miss frequency collection process ends (END).

[0073] 1.2.4 Cache Replacement Handling FIG. 8 is a flowchart showing an example of a cache replacement process in the cache replacement module of the information processing system according to the first embodiment.

[0074] When the second period has elapsed or the number of occurrences of cache misses reaches the second number (start), the cache replacement module 160 identifies the address of the data to be replaced from the access area 410 based on the miss frequency information 151 (S31).

[0075] The cache replacement module 160 switches the cache area 120 to be activated (S32). Specifically, if the set of data field 121a and tag field 122a is in the active state, the cache replacement module 160 deactivates the data field 121a and tag field 122a and activates the data field 121b and tag field 122b. If the set of data field 121b and tag field 122b is in the active state, the cache replacement module 160 deactivates the data field 121b and tag field 122b and activates the data field 121a and tag field 122a.

[0076] The cache replacement module 160 determines whether the reference count value 141 in the inactive state in the read access process is "0" (S33).

[0077] If the reference count value 141 in the inactive state is not "0" (S33; no), the cache replacement module 160 waits until the reference count value 141 in the inactive state becomes "0" (S34).

[0078] If the reference count value 141 in the inactive state is "0" (S33; yes), or after the processing of S34, the cache replacement module 160 determines whether or not to replace the data in the cache area 120 (S35). For example, the cache replacement module 160 randomly determines whether or not to replace the data in the cache area 120. Note that if the data in the cache area 120 is to be replaced unconditionally, in the processing of S35, the cache replacement module 160 determines to replace the data in the cache area 120 (S35; yes).

[0079] If it is determined that the data in the cache area 120 is to be replaced (S35; yes), the cache replacement module 160 causes the memory system 20 to execute a read process for the data to be replaced (S36).

[0080] The cache replacement module 160 stores the replacement target data in the inactive cache area 120 corresponding to the address identified in the process of S31 (S37). Accordingly, the data that has been stored in the inactive cache area 120 corresponding to the address identified in the process of S31 is discarded (evict).

[0081] If it is determined that the data in the cache area 120 is not to be replaced (S35; no), or when the processing of S37 is completed, the cache replacement processing is completed (end). Note that in the above-described cache replacement processing, the processing of S31 may be replaced in any order as long as it is completed before the processing of S35.

[0082] 1.2.5 Relationship between the frequency of various processes FIG. 9 is a diagram showing the relationship between the frequency of read access processing and the frequency of cache replacement processing in the information processing system according to the first embodiment.

[0083] As described above, the cache replacement process can be performed asynchronously or synchronously with respect to the read access process. However, whether the cache replacement process is performed asynchronously or synchronously with respect to the read access process, the frequency of the cache replacement process is lower than the frequency of the read access process.

[0084] 1.3 Effects of the First Embodiment According to the first embodiment, the cache replacement module 160 executes the cache replacement process at a frequency lower than the frequency of read access processes (i.e., the frequency at which it is determined whether the data to be read is cached in the cache area 120). Specifically, the cache replacement module 160 executes the cache replacement process when the number of times a cache miss occurs in a read access process reaches a second number. Alternatively, the cache replacement module 160 executes the cache replacement process when a second period has elapsed since the cache replacement process executed immediately before. This makes it possible to exclude the replacement process of the cache data CDAT from the read access process. This makes it possible to suppress an increase in the CPU processing load on the processor 11 during read access processes.

[0085] Additionally, the CPU processing load of the processor 11 during read access processing includes the load associated with the software cache and the load associated with inputting and outputting data from the memory system 20 when a cache miss occurs. When there are many accesses to data stored in the memory system 20 (specifically, for example, when the number of read accesses, including both cache hits and cache misses in one thread, exceeds 5 million times per second (5M Reads Per Second)), the load is large. When there are many software cache hits or when the memory system 20 has high IOPS (Input / Output Per Second) and is optimized to reduce the load associated with data input and output, the load associated with the software cache may not be negligible.

[0086] According to the first embodiment, the cache replacement process is executed less frequently than the miss frequency. This reduces the CPU processing load on the processor 11 associated with software caching compared to when the cache replacement process is executed every time a cache miss occurs. Therefore, even if the IOPS of the memory system 20 is sufficiently high, the load associated with software caching can be sufficiently reduced.

[0087] Furthermore, the frequency of cache replacement processing is lower than the miss frequency. This makes the cache replacement processing suitable for caching data that is frequently used over a medium to long term (e.g., several hundred milliseconds). This allows for a reduction in the frequency of data replacement for the cache area 120 over a medium to long term.

[0088] Furthermore, the miss frequency collection module 150 executes a miss frequency collection process. Specifically, the miss frequency collection module 150 executes the miss frequency collection process when the number of times a cache miss has occurred in a read access process reaches a first number, which is smaller than a second number. Alternatively, the miss frequency collection module 150 executes the miss frequency collection process when a first period, which is shorter than the second period, has elapsed since the miss frequency collection process executed immediately before. This makes it possible to exclude the miss frequency collection process from the read access process. This makes it possible to suppress an increase in the CPU processing load of the processor 11 in the read access process.

[0089] Furthermore, in the cache replacement process, the cache replacement module 160 randomly determines whether or not to replace data in the cache area 120 with replacement target data. This allows a low-load process to determine whether or not to replace data in the cache area 120. Furthermore, because the data in the cache area 120 is replaced randomly, it is possible to prevent specific data from remaining in the cache area 120.

[0090] 2. Second embodiment Next, an information processing system according to a second embodiment will be described. The second embodiment differs from the first embodiment in that, in a cache replacement process, whether or not to replace data in the cache area 120 with data to be replaced is determined based on the access frequency of the data in the cache area 120. In the following explanation, explanations of the configuration and operation equivalent to those of the first embodiment will be omitted, and the configuration and operation different from those of the first embodiment will be mainly explained.

[0091] 2.1 Functional configuration of information processing system Fig. 10 is a block diagram showing the functional configuration of an information processing system according to the second embodiment, which corresponds to Fig. 2 in the first embodiment.

[0092] The information processing system 1A includes a host device 10A and a memory system 20. The functional configuration of the memory system 20 is the same as that of the first embodiment, and therefore a description thereof will be omitted.

[0093] The host device 10A functions as a buffer area 110, a cache area 120A, a queue 130, an application 140A, a miss frequency collection module 150, and a cache replacement module 160A. The functional configurations of the buffer area 110, the queue 130, and the miss frequency collection module 150 are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0094] The cache area 120A includes data fields 121a and 121b and tag fields 122Aa and 122Ab. The configurations of the data fields 121a and 121b are the same as those in the first embodiment. The data fields 121a and 121b are associated with tag fields 122Aa and 122Ab, respectively. The tag fields 122Aa and 122Ab store information for searching for data stored in the data fields 121a and 121b, respectively. The data structures of the data field 121a and tag field 122Aa are the same as those of the data field 121b and tag field 122Ab. Details of the data structures in the cache area 120A will be described later.

[0095] In the cache area 120A, the frequency at which data is read from the cache area 120A in a read access process is stored for each address as access frequency information 142. Specifically, in the cache area 120A, an estimate of the frequency at which cache hits occur is stored for each address as access frequency information 142. The access frequency is, for example, the number of accesses per unit time. The access frequency information 142 may be initialized, for example, by the miss frequency information 151. The access frequency information 142 may or may not be reset each time a cache replacement process is executed. If the access frequency information 142 is not reset, the access frequency information 142 may, for example, not be updated after initialization, or may be updated. If the access frequency information 142 is updated, the access frequency information 142 may be halved at regular intervals or may be updated by an access count value 143. The access count value 143 is a counter value indicating the number of times a cache hit has occurred for data in the cache area 120A that can be the subject of an access count.

[0096] The cache replacement module 160A determines whether to replace data stored in the cache area 120A with data determined to have a high miss frequency, based on the access frequency information 142. Specifically, the cache replacement module 160A compares the miss frequency of the data determined to have a high miss frequency with the access frequency associated with the address of the cache area 120A that will replace the data. If the comparison shows that the miss frequency is higher than the access frequency, the cache replacement module 160A replaces the data stored in the inactive cache area 120A with the data that has a high miss frequency. If the miss frequency is lower than the access frequency, the cache replacement module 160A does not replace the data.

[0097] 2.2 Configuring the Cache Area Fig. 11 is a diagram showing an example of the configuration of a cache area and access frequency information of an information processing system according to the second embodiment. Fig. 11 corresponds to Fig. 4 in the first embodiment. Fig. 11 shows an example of the configuration of a set of a data field 121a and a tag field 122Aa. Note that the configuration of a set of a data field 121b and a tag field 122Ab is the same as the configuration of a set of a data field 121a and a tag field 122Aa, so a description thereof will be omitted.

[0098] The set of data field 121a and tag field 122Aa is divided into y sub-areas, which are associated with groups "1" to "y," respectively.

[0099] A sub-area of ​​the tag field 122Aa stores a set of a tag number, a valid flag, and an access count flag. The access count flag of the tag field 122Aa indicates whether or not to calculate the access count value 143 when data is read from the corresponding data field 121a. Specifically, for example, if the access count flag E1 of the tag field 122Aa associated with group "1" is "true," the access frequency information A1 corresponding to the cache data CDAT1 can be updated with the access count value. If the access count flag E1 is "false," the access frequency information A1 corresponding to the cache data CDAT1 is not updated with the access count value.

[0100] The access count flag is, for example, periodically switched between "true" and "false." This makes it possible to control the number of groups for which access count values ​​are calculated during a certain period. This reduces the management load of the access frequency information 142 imposed on the application 140A.

[0101] 2.3 Read access processing Fig. 12 is a flowchart showing an example of read access processing in an application of an information processing system according to the second embodiment, which corresponds to Fig. 5 in the first embodiment.

[0102] When a read access occurs (starts), the application 140A increments the reference count value 141 of the active state (S41). More specifically, the application 140A acquires the cache number (current number) of the active state cache area 120A. Then, the application 140A increments the reference count value 141 of the current number.

[0103] The application 140A determines whether a cache hit has occurred (S42).

[0104] If a cache hit occurs (S42; yes), the application 140A accesses the data to be accessed that is stored in the data field 121 of the cache area 120A of the current number (S43).

[0105] After the process of S43, the application 140A determines whether the access count flag corresponding to the cache area 120A in which the data to be accessed is stored is "true" (S44).

[0106] If the access count flag corresponding to the cache area 120A in which the data to be accessed is stored is "true" (S44; yes), the application 140A increments the corresponding access count value 143 (S45).

[0107] If the access count flag corresponding to the cache area 120A in which the data to be accessed is stored is "false" (S44; no), or after the processing of S45, the application 140A decrements the reference count value 141 of the current number (S46).

[0108] If a cache miss occurs (S42; no), the application 140A decrements the reference count value 141 of the current number (S47).

[0109] The application 140A causes the memory system 20 to execute a read process for the data to be accessed (S48). The data to be accessed that is output from the memory system 20 by the read process of S48 is stored in the buffer area 110.

[0110] The application 140A accesses the data to be accessed that is stored in the buffer area 110 (S49).

[0111] When the process of S46 or the process of S49 ends, the read access process ends (ends).

[0112] The cache replacement module 160A, for example, updates the access count value 143 to the corresponding access frequency information 142 at regular intervals, thereby updating the access frequency information 142 to the latest access frequency as appropriate.

[0113] 2.4 Cache Replacement Process Fig. 13 is a flowchart showing an example of cache replacement processing in the cache replacement module of the information processing system according to the second embodiment, which corresponds to Fig. 8 in the first embodiment.

[0114] When the second period has elapsed or the number of occurrences of cache misses reaches the second number (start), the cache replacement module 160A identifies (S51) the address of the data to be replaced from the access area 410 based on the miss frequency information 151. Specifically, for example, the cache replacement module 160A identifies the address in the access area 410 where the data with the highest miss frequency is stored.

[0115] The cache replacement module 160A switches the cache area 120A to be activated (S52).

[0116] The cache replacement module 160A judges whether or not the reference count value 141 in the inactive state in the read access process is "0" (S53).

[0117] If the inactive state reference count value 141 is not "0" (S53; no), the cache replacement module 160A waits until the inactive state reference count value 141 becomes "0" (S54).

[0118] If the reference count value 141 in the inactive state is “0” (S53; yes), or after the processing of S54, the cache replacement module 160A determines whether the miss frequency of the data to be replaced is higher than the access frequency of the inactive cache area 120A corresponding to the address identified in the processing of S51 (S55).

[0119] If the miss frequency of the data to be replaced is higher than the access frequency of the inactive cache area 120A corresponding to the address identified in the processing of S51 (S55; yes), the cache replacement module 160A causes the memory system 20 to execute a read process of the data to be replaced (S56).

[0120] The cache replacement module 160A stores the replacement target data in the inactive cache area 120A corresponding to the address identified in the processing of S51 (S57). Accordingly, the data stored up to that point in the inactive cache area 120A corresponding to the address identified in the processing of S51 is discarded.

[0121] If the miss frequency of the data to be replaced is lower than the access frequency of the inactive cache area 120A corresponding to the address identified in the processing of S51 (S55; no), or when the processing of S57 is completed, the cache replacement processing is completed (end).

[0122] 2.5 Effects of the Second Embodiment According to the second embodiment, the cache replacement module 160A stores the replacement target data in the inactive cache area 120A when the access frequency is lower than the miss frequency. This makes it possible to suppress the eviction of data from the cache area 120A when the access frequency of data already stored in the cache area 120A is high. This makes it possible to more accurately maintain a state in which data with a high mid- to long-term access frequency is cached.

[0123] 3. Third embodiment Next, an information processing system according to a third embodiment will be described. The third embodiment differs from the first embodiment in that a cache is implemented in the memory system. In the following explanation, explanations of the configuration and operation equivalent to those of the first embodiment will be omitted, and the configuration and operation different from those of the first embodiment will be mainly explained.

[0124] 3.1 Hardware configuration of information processing system Fig. 14 is a block diagram showing the hardware configuration of an information processing system according to the third embodiment, which corresponds to Fig. 1 in the first embodiment.

[0125] The information processing system 1B includes a host device 10 and a memory system 20B. The memory system 20B includes a memory controller 30B and a nonvolatile memory 40. The configurations of the host device 10 and the nonvolatile memory 40 are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0126] The memory controller 30B includes a controller control circuit 31, a host interface circuit 32, a memory interface circuit 33, and a cache memory 34. The configurations of the controller control circuit 31, the host interface circuit 32, and the memory interface circuit 33 are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0127] The cache memory 34 is, for example, a static random access memory (SRAM) or a DRAM, and is used as a memory area for temporarily storing data read from the nonvolatile memory 40.

[0128] 3.2 Functional configuration of information processing system Fig. 15 is a block diagram showing the functional configuration of an information processing system according to the third embodiment, which corresponds to Fig. 2 in the first embodiment.

[0129] The memory controller 30B functions as a read module 310B and a cache area 320.

[0130] The cache area 320 is a memory area that functions as a cache. The cache that constitutes the cache area 320 may be implemented in hardware or by using software on a processor in the memory controller 30B. The cache area 320 stores, for example, data that is accessed more frequently in the short term than the data stored in the cache area 120. For example, data that has experienced a cache miss may be cached in the cache area 320 as is.

[0131] When the read module 310B receives a read request, it determines whether the data to be accessed is stored in the cache area 320. If the data to be accessed is stored in the cache area 320, the read module 310B outputs the data to be accessed in the cache area 320 to the host device 10. If the data to be accessed is not stored in the cache area 320, the read module 310B reads the data to be accessed from the nonvolatile memory 40 via the memory bus MB. Then, the read module 310B outputs the data to be accessed read from the nonvolatile memory 40 to the host device 10 via the host bus HB. The read module 310B also stores the data to be accessed read from the nonvolatile memory 40 in the cache area 320.

[0132] 3.3 Lead Processing Fig. 16 is a flowchart showing an example of read processing in the read module of the information processing system according to the third embodiment. Fig. 16 corresponds to Fig. 6 in the first embodiment.

[0133] When a read request is stored in SQ131 (start), the read module 310B determines whether or not the data to be accessed is stored in the cache area 320. In other words, the read module 310B determines whether or not a cache hit has occurred (S61).

[0134] If a cache hit occurs (S61; yes), the read module 310B outputs the access target data that has been read from the cache area 320 to the host device 10 (S62).

[0135] If a cache miss occurs (S61; no), the read module 310B executes a read process from the access target in the access area 410 (S63).

[0136] The read module 310B stores the access target data that was read from the access area 410 by the processing of S63 in the cache area 320 (S64).

[0137] The read module 310B outputs the access target data read from the access area 410 by the processing of S63 to the host device 10 (S65).

[0138] When the process of S62 or the process of S65 ends, the read process ends (ends). The data output to the host device 10 is stored in the buffer area 110.

[0139] 3.4 Effects of the Third Embodiment According to the third embodiment, the memory controller 30B includes a cache memory 34. During a read process, the read module 310B determines whether or not the data to be accessed is stored in the cache area 320. As a result, even if the data to be accessed is not stored in the cache area 120, the read module 310B can output the data to be accessed to the host device 10 without accessing the access area 410 as long as the data is stored in the cache area 320. This makes it possible to reduce the processing load on the nonvolatile memory 40 when a cache miss occurs in the cache area 120, and also to reduce the latency until data is output from the memory system 20B.

[0140] As described above, the frequency of cache replacement processing is set lower than the frequency of read access processing. As a result, data that is frequently accessed over the medium to long term is likely to be stored in the cache area 120. For this reason, data that is frequently accessed over the short term may not be stored in the cache area 120.

[0141] According to the third embodiment, when a cache miss occurs in the cache area 320, the data to be accessed is read from the access area 410 and stored in the cache area 320. This makes it possible to store in the cache area 320 data that is accessed frequently in a short period of time and that is unlikely to be stored in the cache area 120. Therefore, access to the access area 410 can be avoided even for data that is accessed frequently in a short period of time.

[0142] 4. Fourth embodiment Next, an information processing system according to a fourth embodiment will be described. The fourth embodiment differs from the first embodiment in that a tag field is implemented in the memory system. In the following explanation, explanations of the configuration and operation equivalent to those of the first embodiment will be omitted, and the configuration and operation different from those of the first embodiment will be mainly explained.

[0143] 4.1 Functional configuration of information processing system Fig. 17 is a block diagram showing the functional configuration of an information processing system according to the fourth embodiment. Fig. 17 corresponds to Fig. 2 in the first embodiment. The information processing system 1C includes a host device 10C and a memory system 20C. The memory system 20C includes a memory controller 30C and a non-volatile memory 40. The configuration of the non-volatile memory 40 is the same as in the first embodiment, so a description thereof will be omitted.

[0144] The host device 10C functions as a buffer area 110, a cache area 120C, a queue 130, an application 140C, a miss frequency collection module 150, and a cache replacement module 160. The memory controller 30C functions as a read module 310C and tag fields 330a and 330b. The functional configurations of the buffer area 110, the queue 130, the miss frequency collection module 150, and the cache replacement module 160 are the same as those in the first embodiment, so description thereof will be omitted.

[0145] The cache area 120C includes data fields 121a and 121b but does not include a tag field. The data fields 121a and 121b correspond to tag fields 330a and 330b, respectively, in the memory controller 30C. The tag fields 330a and 330b have the same configuration as the tag fields 122a and 122b in the first embodiment.

[0146] In response to the occurrence of a read access process, the application 140C stores a read request in SQ 131. Based on the pointer stored in CQ 132, the application 140C acquires the data output from the memory system 20C as a result of the read request.

[0147] As described above, the application 140C acquires the current number in response to the occurrence of a read access process. The application 140C notifies the read module 310C of the current number (i.e., the cache number used in the read access process) by including the current number in SQ131.

[0148] When the read module 310C receives a read request, it determines whether to refer to the tag field 330a or 330b based on the current number in SQ131. The read module 310C determines whether the data to be accessed is stored in the cache area 120C by referencing the tag field 330a or 330b that it has determined to refer to as a result of this determination. If the data to be accessed is stored in the cache area 120C, the read module 310C outputs a pointer indicating the address of the cache area 120C in which the data to be accessed is stored to the host device 10C. As a result, the pointer indicating the address of the cache area 120C in which the data to be accessed is stored is stored in CQ132.

[0149] If the data to be accessed is not stored in the cache area 120C, the read module 310C reads the data to be accessed from the nonvolatile memory 40 via the memory bus MB. Then, the read module 310C outputs the data to be accessed read from the nonvolatile memory 40 to the host device 10C via the host bus HB. The output data to be accessed is stored in the buffer area 110. As a result, a pointer indicating the address of the buffer area 110 where the data to be accessed is stored is stored in the CQ132.

[0150] 4.2 Read access processing Fig. 18 is a flowchart showing an example of a read access process in an application of an information processing system according to the fourth embodiment. Fig. 18 corresponds to Fig. 5 in the first embodiment.

[0151] When a read access occurs (starts), the application 140C increments the reference count value 141 of the active state (S71). More specifically, the application 140C acquires the cache number (current number) of the active cache area 120C. Then, the application 140C increments the reference count value 141 of the current number.

[0152] The application 140C stores the read request for the data to be accessed in SQ131 (S72). SQ131 includes the current number acquired in the process of S71.

[0153] The application 140C waits until the result of the read request stored in SQ131 in the processing of S72 is stored in CQ132 (S73).

[0154] After the process of S73, the application 140C accesses the data indicated by the pointer stored in the CQ 132 as the data to be accessed (S74).

[0155] After the process of S74, the application 140C decrements the reference count value 141 of the current number (S75).

[0156] When the process of S75 ends, the read access process ends (END).

[0157] 4.3 Lead Processing Fig. 19 is a flowchart showing an example of a read process in a read module of an information processing system according to Embodiment 4. Fig. 19 corresponds to Fig. 6 in the first embodiment.

[0158] When a read request is stored in SQ131 (start), the read module 310C determines whether or not the data to be accessed is stored in the cache area 120C by referencing the tag field 330a or 330b of the current number in SQ131. In other words, the read module 310C determines whether or not a cache hit has occurred (S81).

[0159] If a cache hit occurs (S81; yes), the read module 310C outputs a pointer indicating the address of the data field 121a or 121b of the current number in which the data to be accessed is stored to the host device 10C (S82). As a result, the pointer indicating the address of the data field 121a or 121b of the current number in which the data to be accessed is stored is stored in CQ132.

[0160] If a cache miss occurs (S81; no), the read module 310C executes a read process for the data to be accessed from the access area 410 in the nonvolatile memory 40 (S83).

[0161] The read module 310C outputs the access target data read from the access area 410 by the processing of S83 to the host device 10C (S84). The data output to the host device 10C is stored in the buffer area 110. As a result, a pointer indicating the address of the buffer area 110 where the access target data is stored is stored in the CQ132.

[0162] When the processing of S82 or the processing of S84 ends, the read processing ends (ends).

[0163] 4.4 Effects of the Fourth Embodiment According to the fourth embodiment, the tag fields 330a and 330b are managed by the memory controller 30C, which reduces the management load of the cache area 120C in the host memory 12.

[0164] Additionally, when tag fields are managed by the host device 10C, tag fields with high access frequencies are cached in a hardware cache (not shown) in the host device 10C, which is not preferable because it reduces the memory area margin of the hardware cache in the host device 10C.

[0165] According to the fourth embodiment, the tag fields 330a and 330b are offloaded to the memory controller 30C, which makes it possible to avoid caching the tag fields in the memory area of ​​the hardware cache in the host device 10C.

[0166] 5. Fifth embodiment Next, an information processing system according to a fifth embodiment will be described. The fifth embodiment differs from the first embodiment in that an error frequency collection module is implemented in a memory system. In the following explanation, explanations of the configuration and operation equivalent to those of the first embodiment will be omitted, and the configuration and operation different from those of the first embodiment will be mainly explained.

[0167] 5.1 Functional configuration of information processing system Fig. 20 is a block diagram showing the functional configuration of an information processing system according to the fifth embodiment, which corresponds to Fig. 2 in the first embodiment.

[0168] The information processing system 1D includes a host device 10D and a memory system 20D. The memory system 20D includes a memory controller 30D and a nonvolatile memory 40. The functional configuration of the nonvolatile memory 40 is the same as that of the first embodiment, and therefore description thereof will be omitted.

[0169] The host device 10D functions as a buffer area 110, a cache area 120, a queue 130, an application 140, and a cache replacement module 160D. The memory controller 30D functions as a read module 310 and a miss frequency collection module 340. The functional configuration other than the cache replacement module 160D and the miss frequency collection module 340 is the same as in the first embodiment, and therefore description thereof will be omitted.

[0170] The miss frequency collection module 340 is a module that executes miss frequency collection processing. For example, the miss frequency collection module 340 counts the number of read requests for each address to be accessed each time it acquires a read request stored in SQ131. The miss frequency collection module 340 stores the collected miss frequencies as miss frequency information 341. The configuration of the miss frequency information 341 is the same as the miss frequency information 151 in the first embodiment.

[0171] The cache replacement module 160D determines which data has a high miss frequency among the data stored in the memory system 20D based on the miss frequency information 341. The cache replacement module 160D determines whether to replace the data stored in the cache area 120 with the data determined to have a high miss frequency. If it is determined that the data should be replaced, the cache replacement module 160D replaces the data stored in the inactive cache area 120 with the data with a high miss frequency. If it is determined that the data should not be replaced, the cache replacement module 160D does not replace the data.

[0172] 5.2 Effects of the Fifth Embodiment According to the fifth embodiment, the miss frequency collection module 340 is implemented in the memory controller 30D. This allows the load of the miss frequency collection process to be offloaded from the processor 11 to the memory controller 30D. This further reduces the CPU load for managing the cache area 120 in the host device 10D.

[0173] 6. Sixth embodiment Next, an information processing system according to a sixth embodiment will be described. The sixth embodiment differs from the fifth embodiment in that a cache replacement module is further implemented in the memory system in addition to the miss frequency collection module. In the following description, the same configuration and operation as the fifth embodiment will be omitted, and the configuration and operation different from the fifth embodiment will be mainly described.

[0174] 6.1 Functional configuration of information processing system Fig. 21 is a block diagram showing the functional configuration of an information processing system according to the sixth embodiment, which corresponds to Fig. 20 in the fifth embodiment.

[0175] The information processing system 1E includes a host device 10E and a memory system 20E. The memory system 20E includes a memory controller 30E and a nonvolatile memory 40. The functional configuration of the nonvolatile memory 40 is the same as that of the fifth embodiment, and therefore description thereof will be omitted.

[0176] The host device 10E functions as a buffer area 110, a cache area 120, a queue 130, and an application 140. The memory controller 30E functions as a read module 310, a miss frequency collection module 340, and a cache replacement module 350. The functional configuration except for the cache replacement module 350 is the same as in the fifth embodiment, and therefore description thereof will be omitted.

[0177] The cache replacement module 350 determines which data stored in the memory system 20E has a high miss frequency based on the miss frequency information 341. The cache replacement module 350 determines whether to replace the data stored in the cache area 120 with the data determined to have a high miss frequency. If it is determined that the data should be replaced, the cache replacement module 350 replaces the data stored in the inactive cache area 120 with the data with a high miss frequency. If it is determined that the data should not be replaced, the cache replacement module 350 does not replace the data.

[0178] 6.2 Effects of the Sixth Embodiment According to the sixth embodiment, the cache replacement module 350 is implemented in the memory controller 30E. This allows the load of cache replacement processing to be offloaded from the processor 11 to the memory controller 30E. This further reduces the CPU load for managing the cache area 120 in the host device 10E.

[0179] 7. Seventh embodiment Next, an information processing system according to a seventh embodiment will be described. The seventh embodiment differs from the first embodiment in that, during cache replacement processing, a memory chip (replacement target memory chip) in which replacement target data is stored is identified before identifying the replacement target data. In the following explanation, explanations of configurations and operations equivalent to those of the first embodiment will be omitted, and configurations and operations different from those of the first embodiment will be mainly explained.

[0180] 7.1 Cache Replacement Process Fig. 22 is a flowchart showing an example of cache replacement processing in a cache replacement module of an information processing system according to Embodiment 7. Fig. 22 corresponds to Fig. 8 in the first embodiment.

[0181] When the second period has elapsed or the number of occurrences of cache misses reaches the second number (start), the cache replacement module 160 identifies (S91) a memory chip to be replaced from the multiple memory chips CP_1 to CP_n based on the miss frequency information 151. Specifically, for example, the cache replacement module 160 identifies, from the multiple memory chips CP_1 to CP_n, a memory chip with the largest total number of cache misses.

[0182] The cache replacement module 160 identifies (S92) the address of the data to be replaced from the access area 410 in the memory chip to be replaced identified in the process of S91 based on the miss frequency information 151. Specifically, for example, the cache replacement module 160 identifies the address of the access area 410 in which the data with the highest miss frequency is stored.

[0183] The cache replacement module 160 switches the cache area 120 to be activated (S93).

[0184] The cache replacement module 160 determines whether the reference count value 141 in the inactive state in the read access process is "0" (S94).

[0185] If the reference count value 141 in the inactive state is not "0" (S94; no), the cache replacement module 160 waits until the reference count value 141 in the inactive state becomes "0" (S95).

[0186] If the reference count value 141 in the inactive state is "0" (S94; yes), or after the processing of S95, the cache replacement module 160 determines whether or not to replace the data in the cache area 120 (S96).

[0187] If it is determined that the data in the cache area 120 is to be replaced (S96; yes), the cache replacement module 160 causes the memory system 20 to execute a read process for the data to be replaced (S97).

[0188] The cache replacement module 160 stores the replacement target data in the inactive cache area 120 corresponding to the address identified in the process of S92 (S98). Accordingly, the data that has been stored in the inactive cache area 120 corresponding to the address identified in the process of S92 is discarded (evict).

[0189] If it is determined that the data in the cache area 120 is not to be replaced (S96; no), or when the processing of S98 ends, the cache replacement processing ends (END).

[0190] 7.2 Effects of the Seventh Embodiment According to the seventh embodiment, the cache replacement module 160 identifies a memory chip to be replaced from among the multiple memory chips CP_1 to CP_n based on the miss frequency information 151. Specifically, the cache replacement module 160 identifies the memory chip with the highest access frequency as the memory chip to be replaced. This makes it possible to prevent access from being concentrated on a specific memory chip. This makes it possible to shorten the period during which the memory controller 30 does not operate the multiple memory chips CP_1 to CP_n in parallel. This makes it possible to maximize the performance of the memory system 20.

[0191] 8. Modifications The first to seventh embodiments described above are not limited to the examples described above, and various modifications are applicable.

[0192] For example, the third to seventh embodiments described above are applied to the first embodiment, but are not limited to this. The third to seventh embodiments described above may be applied to the second embodiment. That is, in the cache replacement process of the third to seventh embodiments described above, whether to cache the replacement target data may be determined based on the magnitude relationship between the miss frequency of the replacement target data and the access frequency of the data to be replaced. Furthermore, the third to seventh embodiments described above may be combined with each other.

[0193] Furthermore, for example, the first to seventh embodiments have been described above in terms of a case where one memory system 20 is connected to the host device 10 via the host bus HB, but this is not limiting. A plurality of memory systems 20 may be connected to the host device 10 via the host bus HB.

[0194] Fig. 23 is a block diagram showing an example of a hardware configuration of an information processing system according to a modified example. Fig. 23 corresponds to Fig. 1 in the first embodiment. The information processing system 1F includes a host device 10 and a plurality of memory systems 20_1, ..., 20_m (m is an integer equal to or greater than 2).

[0195] The configuration of each of the plurality of memory systems 20_1 to 20_m is the same as the configuration of the memory system 20 in the first embodiment. Each of the plurality of memory systems 20_1 to 20_m is commonly connected to the host device 10 via a host bus HB.

[0196] When the above-described modification is applied to the fourth embodiment, each of the plurality of memory systems 20_1 to 20_m stores tag fields 330a and 330b associated with the data fields 121a and 121b corresponding to its own access area 410. In this case, the data fields 121a and 121b may be divided by the number of memory systems 20_1 to 20_m. This allows the application 140C to inquire whether a cache hit has occurred to a memory system among the plurality of memory systems 20_1 to 20_m from which the data to be accessed is read when a cache miss occurs.

[0197] When the above-described modification is applied to the fifth embodiment, the miss frequency collection module 340 of each of the plurality of memory systems 20_1 to 20_m stores miss frequency information 341 based on a read request to its own access area 410 stored in SQ 131. The cache replacement module 160D identifies the address of the data to be replaced based on the miss frequency information 341 stored in each of the plurality of memory systems 20_1 to 20_m.

[0198] When the above-described modification is applied to the sixth embodiment, a cache replacement module 350 may be provided in each of the plurality of memory systems 20_1 to 20_m. In this case, the cache area 120 is managed independently for each memory system. That is, the data fields 121a and 121b and the tag fields 122a and 122b are divided into independent areas for each memory system. Furthermore, switching between the active state and the inactive state of the cache area 120 is also controlled independently for each memory system. Then, the cache replacement module 350 of each of the plurality of memory systems 20_1 to 20_m identifies the address of the data to be replaced based on the miss frequency information 341 collected by its own miss frequency collection module 340.

[0199] Alternatively, when the above-described modification is applied to the sixth embodiment, the cache replacement module 350 may be provided in one of the memory systems 20_1 to 20_m. The cache replacement module 350 aggregates the miss frequency information 341 collected by the miss frequency collection modules 340 of the memory systems 20_1 to 20_m, and identifies the address of the data to be replaced. In this case, the cache area 120 does not need to be managed independently for each memory system.

[0200] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0201] 1, 1A, 1B, 1C, 1D, 1E, 1F...Information Processing System 10, 10A, 10C, 10D, 10E...Host device 11...Processor 12...Host memory 20...Memory system 30, 30B, 30C, 30D, 30E...Memory controller 31...Controller control circuit 32...Host interface circuit 33...Memory interface circuit 34...Cache memory 40...Non-volatile memory 110...Buffer area 120, 120A, 120C...Cache area 121a, 121b...Data field 122a, 122b, 122Aa, 122Ab, 330a, 330b...tag field 130...Queue 131…SQ 132…CQ 140, 140A, 140C...Applications 141a, 141b...Reference count value 142...Access frequency information 150,340…Miss frequency collection module 151,341...Mistake frequency information 160, 160A, 160D, 350...Cache replacement module 310, 310B, 310C... Lead modules 320...Cache area 410...Access area

Claims

1. a memory system including a non-volatile memory; a host device including a processor that executes software that accesses data stored in the non-volatile memory, and a host memory; Equipped with The processor: Allocating a cache area in the host memory for caching data stored in the nonvolatile memory; When the software is executed, looking up the cache area; If a cache hit occurs as a result of the lookup, the cache area is accessed without accessing the nonvolatile memory; The data stored in the nonvolatile memory is cached in the cache area at a second frequency lower than the first frequency at which a cache miss occurs. It was configured as follows: Information processing system.

2. the processor is configured to cache the data stored in the nonvolatile memory in the cache area asynchronously with the lookup; 2. The information processing system according to claim 1.

3. the processor is configured to cache the data stored in the nonvolatile memory in the cache area in synchronization with the lookup; 2. The information processing system according to claim 1.

4. The processor: calculating the first frequency for each access destination of the nonvolatile memory; Identifying data to be cached in the cache area based on the calculated first frequency for each of the access destinations. It was configured as follows:

2. The information processing system according to claim 1.

5. the host device further includes a queue; the processor is configured to calculate the first frequency for each of the access destinations based on the number of access requests to the nonvolatile memory stored in the queue; 5. The information processing system according to claim 4.

6. the processor is configured to identify data to be cached in the cache area based on a magnitude relationship of the first frequency for each of the access destinations; 5. The information processing system according to claim 4.

7. the nonvolatile memory includes a plurality of memory chips; The processor: identifying a first memory chip based on the magnitude relationship of the first frequency for each of the memory chips; Identifying data to be cached in the cache area based on a magnitude relationship for each of the access destinations in the first memory chip with the first frequency. It was configured as follows:

5. The information processing system according to claim 4.

8. the cache area has a direct-mapped data structure; 5. The information processing system according to claim 4.

9. the processor is configured to cache data stored in an access destination where the first frequency is equal to or greater than a threshold in the cache area; 5. The information processing system according to claim 4.

10. the processor is configured to cache, in the cache area, data stored in an access destination where the first frequency is higher than a third frequency; the third frequency is a frequency at which a cache hit occurs in a memory area of ​​the cache area corresponding to the access destination; 5. The information processing system according to claim 4.

11. the memory system further includes a control circuit; the control circuit is configured to calculate the first frequency for each access destination of the nonvolatile memory; The processor identifies data to be cached in the cache area based on the calculated first frequency for each of the access destinations. It was configured as follows:

2. The information processing system according to claim 1.

12. the host device further includes a queue; the control circuit is configured to calculate a first frequency for each of the access destinations based on the number of access requests to the nonvolatile memory stored in the queue; 12. The information processing system according to claim 11.

13. the processor is configured to identify data to be cached in the cache area based on a magnitude relationship of the first frequency for each of the access destinations; 12. The information processing system according to claim 11.

14. the nonvolatile memory includes a plurality of memory chips; The processor: identifying a first memory chip based on the magnitude relationship of the first frequency for each of the memory chips; Identifying data to be cached in the cache area based on a magnitude relationship for each of the access destinations in the first memory chip with the first frequency. It was configured as follows:

12. The information processing system according to claim 11.

15. the cache area has a direct-mapped data structure; 12. The information processing system according to claim 11.

16. the processor is configured to cache data stored in an access destination where the first frequency is equal to or greater than a threshold in the cache area; 12. The information processing system according to claim 11.

17. the processor is configured to cache, in the cache area, data stored in an access destination where the first frequency is higher than a third frequency; the third frequency is a frequency at which a cache hit occurs in a memory area of ​​the cache area corresponding to the access destination; 12. The information processing system according to claim 11.

18. the cache area includes a first memory area and a second memory area; The processor: one of the first memory area and the second memory area is in an active state while the other is in an inactive state; The data stored in the nonvolatile memory is cached in the inactive memory area of ​​the first memory area and the second memory area. It was configured as follows:

2. The information processing system according to claim 1.

19. the processor is configured to switch the memory area in an inactive state to an active state and the memory area in an active state to an inactive state every time data to be cached in the cache area is identified, 19. The information processing system according to claim 18.

20. a memory system including a control circuit and a non-volatile memory; a host device including: a host memory to which a cache area for caching data stored in the nonvolatile memory is allocated; and a processor that, when executing software that accesses data stored in the nonvolatile memory, looks up the cache area, and, if a cache hit occurs as a result of the lookup, accesses the cache area without accessing the nonvolatile memory; The memory system in an information processing system comprising: the control circuit is configured to cache data stored in the nonvolatile memory in the cache area at a second frequency that is lower than a first frequency at which a cache miss occurs; Memory system.

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