Switching Circuits and Power Converters

Abstract

To provide technique for enabling suppression of oscillation noise of a semiconductor device and suppression of mirror noise.SOLUTION: A switching circuit comprises: a switching device for conducting or opening a state between a drain terminal and a source terminal on the basis of voltage applied between the gate terminal and the source terminal; a drive circuit which includes a first switch element and a second switch element, opens and closes the first and second switch elements in accordance with a prescribed control signal and outputs drive voltage for driving the switching device to the gate terminal through an output terminal; a clamp circuit having a third switch element for conducting between a reference potential of the drive circuit and a connection point on the basis of a comparison result between a threshold potential generated on the basis of the reference potential of the drive circuit and a potential in the connection point of a path connecting the output terminal of the drive circuit and the gate terminal; and a ferrite inductor which is provided just near the output terminal of the drive circuit, whose one end is connected to the output terminal and whose the other end is connected to the connection point.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a switching circuit and a power converter that suppress noise accompanying the switching operation of a semiconductor device. [Background technology]

[0002] It is known that a conventional method of suppressing oscillation noise in semiconductor devices is to add ferrite beads or the like close to the gate terminal connected to the gate driver (for example, Patent Document 1). By adding ferrite beads or the like, it is possible to increase the impedance seen from the input side of the gate terminal, which is expected to suppress oscillation noise caused by parasitic capacitance (for example, gate-drain capacitance) of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6645924 Summary of the Invention [Problem to be solved by the invention]

[0004] However, adding ferrite beads or the like close to the gate terminal can cause voltage fluctuations due to noise (hereinafter also referred to as Miller noise) that accompanies turning on and off of the semiconductor device. Such voltage fluctuations become more pronounced as the switching speed increases, and for example, there is a risk that the voltage applied to the gate terminal will increase, causing malfunction or destruction of the semiconductor device.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique that makes it possible to suppress oscillation noise of a semiconductor device and also suppress mirror noise. [Means for solving the problem]

[0006] One aspect of the disclosed technology for solving the above problem is: a switching device that turns on or off the state between the drain terminal and the source terminal based on a voltage applied between the gate terminal and the source terminal; a drive circuit including a first switch element having one end connected to the positive side of a control power supply and the other end connected to an output terminal, and a second switch element having one end connected to the output terminal and the other end connected to a reference potential to which the negative side of the control power supply is connected, the drive circuit opening and closing the first switch element and the second switch element in accordance with a predetermined control signal, generating a drive voltage for driving the switching device, and outputting the generated drive voltage to a gate terminal of the switching device via the output terminal; a clamp circuit having a third switch element that, based on a comparison result between a threshold potential generated based on a reference potential of the drive circuit and a potential at a connection point of a path connecting an output end of the drive circuit and a gate terminal of the switching device, conducts between the reference potential of the drive circuit and the connection point; a ferrite inductor provided in close proximity to an output terminal of the drive circuit, one end of which is connected to the output terminal and the other end of which is connected to the connection point; The present invention is characterized by comprising:

[0007] As a result, in the switching circuit 100, a ferrite bead FB, which is a ferrite inductor, is provided immediately adjacent to the gate driver 101, which is a drive circuit. The switching circuit 100 can be configured such that a connection point T3, which is a connection point on the path connecting the ferrite bead FB and the gate terminal G of the semiconductor device 102, which is a switching device, is connected to the input terminal (connection point T4) of the Miller clamp circuit 103, which is a clamp circuit. In the switching circuit 100, a closed loop of the propagation path through which oscillation noise propagates via the GND potential can be separated from a closed loop of the propagation path of Miller noise accompanying the turn-on and turn-off of the semiconductor device 102. The ferrite bead FB can be placed in the propagation path through which the oscillation noise propagates, and the Miller clamp 103, which suppresses the Miller noise without the ferrite bead FB, can be placed in the propagation path through which the Miller noise propagates. As a result, the oscillation noise propagated via the GND potential is suppressed by the inductance of the ferrite bead FB, and the Miller clamp circuit 103's suppression effect on the Miller noise propagated via the connection point T3 can be sufficiently enhanced. This provides a technology that enables both the suppression of oscillation noise of a semiconductor device and the suppression of Miller noise.

[0008] In one aspect of the disclosed technology, a resistive element may be further provided between the output end of the drive circuit and the connection point, connected in series with the ferrite inductor. Adding a gate resistor Rg, which is a resistive element, makes it possible to change the rise time (slew rate) of the gate voltage applied to the gate terminal G, thereby changing the switching speed related to turn-on and turn-off of the semiconductor device 102. Changing the rise time of the gate voltage is expected to reduce switching noise (Miller noise) associated with turn-on and turn-off of the semiconductor device 102.

[0009] In addition, in one aspect of the disclosed technology, a diode element may be further provided, the anode of which is connected to the reference potential of the drive circuit and the cathode of which is connected to the connection point. This allows the Schottky diode Ds, which is the diode element, to be disposed between the connection point T3 and the GND potential in the path through which the mirror noise propagates, thereby reducing the impedance of the current path through which the switching noise (mirror noise) propagates. This further improves the effect of reducing the switching noise (mirror noise) that accompanies the turn-on and turn-off of the semiconductor device 102.

[0010] In one embodiment of the disclosed technology, a capacitor element may be connected in parallel to the resistor element connected in series with the ferrite inductor. This increases the switching speed for turning on and off the semiconductor device 102 by adding a capacitor Cp that is a capacitor element connected in parallel to the gate resistor Rg, and is therefore expected to reduce switching loss in the switching circuit.

[0011] In one embodiment of the disclosed technology, the ferrite inductor may be an equivalent circuit corresponding to the ferrite inductor. This allows the ferrite inductor to be appropriately configured using an inductor element and a resistor element depending on the characteristics of the oscillation noise to be suppressed, the circuit size, etc. Furthermore, in one embodiment of the disclosed technology, the switching device may be configured with a wide bandgap semiconductor including at least a SiC semiconductor and a GaN semiconductor. This allows for effective suppression of Miller noise associated with parasitic capacitance in a switching device configured with a wide bandgap semiconductor including a SiC semiconductor and a GaN semiconductor.

[0012] Another aspect of the disclosed technology may be a power converter comprising a switching circuit according to any one of claims 1 to 6. Even in this aspect, it is possible to separate the closed loop of the propagation path through which oscillation noise propagates via the GND potential from the closed loop of the propagation path of mirror noise accompanying the turn-on and turn-off of the semiconductor device 102. A ferrite bead FB is arranged in the propagation path through which oscillation noise propagates, and a ferrite bead FB is not interposed in the propagation path through which mirror noise propagates, thereby suppressing the noise. This allows the placement of the Miller clamp 103. This allows the inductance of the ferrite bead FB to suppress the oscillation noise propagated via the GND potential, thereby sufficiently enhancing the Miller clamp circuit 103's effect of suppressing the Miller noise propagated via the connection point T3. [Effects of the Invention]

[0013] According to the embodiments of the present disclosure, it is possible to provide a technique that can suppress oscillation noise of a semiconductor device and also suppress mirror noise. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a circuit diagram illustrating oscillation of a switching circuit that is a premise of the present invention. [Figure 2] 1 is a diagram illustrating the suppression of oscillation noise by ferrite beads in a switching circuit, which is a premise of the present invention. FIG. [Figure 3] FIG. 2 is a diagram illustrating a noise propagation path in a switching circuit that is a premise of the present invention. [Figure 4] 1 is a circuit diagram showing a circuit configuration of a switching circuit according to an embodiment of the present invention; [Figure 5] FIG. 2 is a diagram illustrating a noise propagation path in a switching circuit according to an embodiment of the present invention. [Figure 6] 10A and 10B are diagrams illustrating the results of an evaluation test of mirror noise suppression when the switching circuit according to the embodiment of the present invention is turned on. [Figure 7]10A and 10B are diagrams illustrating the results of an evaluation test of mirror noise suppression when a switching circuit according to a comparative example of the present invention is turned on. [Figure 8] 10A and 10B are diagrams illustrating the results of an evaluation test of Miller noise suppression when the switching circuit according to the embodiment of the present invention is turned off. [Figure 9] 10A and 10B are diagrams illustrating the results of an evaluation test of Miller noise suppression when a switching circuit according to a comparative example of the present invention is turned off. [Figure 10] FIG. 4 is a circuit diagram showing a circuit configuration of a switching circuit according to a first modified example of the present invention. [Figure 11] FIG. 10 is a circuit diagram showing a circuit configuration of a switching circuit according to a second modified example of the present invention. [Figure 12] FIG. 10 is a circuit diagram showing a circuit configuration of a switching circuit according to a third modified example of the present invention. [Figure 13] FIG. 10 is a circuit diagram showing a circuit configuration of a switching circuit according to a fourth modified example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] [Application example] Hereinafter, application examples of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing the circuit configuration of a switching circuit 100 according to an application example of the present invention. The switching circuit 100 according to this application example includes a gate driver 101 having a Miller clamp circuit 103 that suppresses Miller noise, a ferrite bead FB that suppresses oscillation noise, and a semiconductor device 102. The Miller clamp circuit 103 is a circuit that bypasses current due to charges stored in parasitic capacitances (capacitors Cgd, Cgs, and Cds) to the source terminal side, thereby suppressing an increase in gate potential due to Miller noise. In the switching circuit 100 according to this application example, a connection point T4 of the Miller clamp circuit 103 is configured to be connected to a connection point T3 that is connected to a gate terminal G of the semiconductor device 102. The ferrite bead FB in the switching circuit 100 according to this application example is configured to be provided immediately adjacent to the gate driver 101 on a path between a connection point T2 of the gate driver 101 and a connection point T3 to which the Miller clamp circuit 103 is connected. That is, one end of the ferrite bead FB is connected to a connection point T2 of the gate driver 101, and the other end is connected to a connection point T3.

[0016] As shown in FIGS. 5 to 9 , the switching circuit 100 according to this application example can separate the closed loop of the propagation path of oscillation noise propagating via the GND potential from the closed loop of the propagation path of Miller noise accompanying the turn-on and turn-off of the semiconductor device 102. The ferrite bead FB can be disposed in the propagation path of the oscillation noise, and the Miller clamp 103, which suppresses the Miller noise without the ferrite bead FB, can be disposed in the propagation path of the Miller noise. As a result, the oscillation noise propagating via the GND potential is suppressed by the inductor of the ferrite bead FB, and the Miller clamp circuit 103 can sufficiently enhance the suppression effect of Miller noise propagating via the connection point T3. This provides a technology that can suppress both oscillation noise of a semiconductor device and Miller noise.

[0017] Example 1 Hereinafter, specific embodiments of the present invention will be described in more detail with reference to the drawings. Note that the configurations of the embodiments shown below are examples, and the disclosed technology is not limited to the configurations of the embodiments.

[0018] <Circuit configuration> FIG. 1 is a diagram illustrating oscillation of a switching circuit according to an embodiment of the present invention. In FIG. 1, (a) illustrates a switching circuit 300 for oscillation evaluation, which includes a circuit configuration (a gate driver 301 and a semiconductor device 302) that is the target of oscillation suppression according to this embodiment, and (b) illustrates the state of oscillation measured by the switching circuit 300. The circuit configuration of the switching circuit 300 that is the target of oscillation suppression according to this embodiment constitutes, for example, a power converter such as a power conditioner (PCS) in a distributed power system that is operated in connection with a commercial power grid. The power converter performs, for example, a power conversion process for converting DC power stored in a storage battery unit or DC power generated by solar power generation into AC power synchronized with the commercial power grid, and a power conversion process for converting AC power supplied from a power grid or the like into DC power.

[0019] As shown in FIG. 1(a), a switching circuit 300 for oscillation evaluation comprises a gate driver 301, a semiconductor device 302, and a gate resistance adjustment circuit 303. The gate driver 301 includes a switch element S1, one end of which is connected to the positive side of a control power supply Vs, and a switch element S2, one end of which is connected to the negative side (GND) of the control power supply Vs. The other end of the switch element S1 is connected to the other end of the switch element S2 via a connection point T1. The gate driver 301 opens and closes the switch elements S1 and S2 in accordance with a control signal Vsig such as a PWM signal, and generates a gate voltage Vgs for driving the semiconductor device based on the voltage applied from the control power supply Vs. The gate voltage Vgs generated by the gate driver 301 is applied between the gate terminal G and the source terminal S of the semiconductor device 302 via the connection point T1 and GND.

[0020] The semiconductor device 302 is an IGBT (Insulated Gate Bipolar Transistor) capable of high-speed switching of large power, a wide band gap semiconductor, The semiconductor device 302 is a switching device made of a material such as a silicon carbide (SiC) semiconductor or a gallium nitride (GaN) semiconductor. In this embodiment, a gate injection transistor (GIT) made of a GaN semiconductor will be described as the semiconductor device 302. However, the semiconductor device 302 may be, for example, a FET (Field Effect Transistor) using a nitride semiconductor or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) using silicon carbide.

[0021] The semiconductor device 302 is connected to a gate terminal G and a source terminal S via a gate voltage Vg s, the semiconductor device 302 makes the drain terminal D and the source terminal S conductive (turn on) or open (turn off) in accordance with the gate voltage Vgs. For example, when the gate voltage Vgs is in a high state where it exceeds a predetermined threshold, the semiconductor device 302 makes the drain terminal D and the source terminal S conductive, and when the gate voltage Vgs is in a low state where it is equal to or lower than the predetermined threshold, the semiconductor device 302 opens the drain terminal D and the source terminal S. In the semiconductor device 302, the drain current Id flowing between the drain terminal D and the source terminal S is controlled in accordance with the state of the gate voltage Vgs.

[0022] 1(a), the diode D1 connected between the gate terminal G and the source terminal S is a parasitic diode of the semiconductor device, and the anode of the diode D1 is connected to the gate terminal G, and the cathode is connected to the source terminal S. Capacitors Cgd, Cgs, and Cds represent the parasitic capacitance between the gate terminal G and the drain terminal D, the parasitic capacitance between the gate terminal G and the source terminal S, and the parasitic capacitance between the drain terminal D and the source terminal S, respectively. These parasitic capacitances are factors that cause oscillation noise in the semiconductor device 302.

[0023] The gate resistance adjustment circuit 303 is composed of a resistor Rp, a resistor Rgoff, and a diode Dp. The resistor Rgoff and the diode Dp are connected in series and are connected in parallel to the resistor Rp. An input terminal of the gate resistance adjustment circuit 303, at which the cathode of the diode Dp and one end of the resistor Rp are connected, is connected to a connection point T1 of the gate driver 301. An output terminal of the gate resistance adjustment circuit 303, at which the other end of the resistor Rp is connected to the other end of the resistor Rgoff, one end of which is connected to the anode of the diode Dp, is connected to the gate terminal G of the semiconductor device 302.

[0024] In the switching circuit 300 for oscillation evaluation, the resistance value of resistor Rp was set to 1.5 kΩ and the resistance value of resistor Rgoff was set to 22 Ω, thereby adjusting the resistance value (gate resistance value) in the path where gate voltage Vgs is applied between gate driver 301 and semiconductor device 302 to 1.5 kΩ, and oscillation of semiconductor device 302 was evaluated. In the oscillation evaluation, the positive side of evaluation power supply Vin was connected to drain terminal D of semiconductor device 302, and the negative side of evaluation power supply Vin was connected to source terminal S, and a voltage of 100 VDC was applied between drain terminal D and source terminal S. Then, the pulse width of the evaluation signal applied from gate driver 301 to gate terminal G of semiconductor device 302 was set to a single pulse with a 2 μsec pulse width, and current fluctuations and voltage fluctuations related to the switching operation were measured. In this embodiment, the gate voltage Vgs of the semiconductor device 302, the voltage (terminal voltage) Vds applied between the drain terminal D and the source terminal S, the drain current Ids, and the gate current Ig are measured as current and voltage fluctuations related to the switching operation.

[0025] In FIG. 1(b), the vertical axis represents the relative magnitude of the measured current and voltage fluctuations, and the horizontal axis represents time. Graph G1 represents the change in gate voltage Vgs, graph G2 represents the change in drain current Ids, graph G3 represents the change in inter-terminal voltage Vds, and graph G4 represents the change in gate current Ig. The rectangular T represents the rising edge of the evaluation signal applied to gate terminal G. As shown in FIG. 1(b), the gate current Ig shown in graph G4 rises sharply with the rising edge of the evaluation signal and flows between gate terminal G and GND of semiconductor device 302. As shown in graphs G1 and G2, when gate voltage Vgs exceeds a predetermined threshold, semiconductor device 302 turns on, and drain current Ids flows between drain terminal D and source terminal S. As shown in graph G1, high-frequency oscillation noise caused by parasitic capacitance is superimposed upon turning on semiconductor device 302, causing large fluctuations in gate voltage Vgs. It can be seen that the fluctuation range of the gate voltage Vgs swings significantly to the negative side relatively from the potential state (rectangular frame 1) before the evaluation signal is input.

[0026] FIG. 2(a) is a diagram illustrating the suppression of oscillation noise using ferrite beads. 2(a) illustrates an example of a switching circuit 300 for evaluation that includes a ferrite bead FB. The configuration shown in FIG. 2(a) is a configuration in which, as indicated by a dashed rectangular frame 304, a ferrite bead FB is inserted into the path on the GND potential side connecting the source terminal S of the semiconductor device 302 and the switch element S2 of the gate driver 301 to the circuit configuration of FIG. 1(a). That is, one end of the ferrite bead FB is connected to the GND-side connection point of the switch element S2 of the gate driver 301, and the other end is connected to the source terminal S of the semiconductor device 302. The ferrite bead FB functions as an inductor that increases impedance in the high-frequency range, thereby suppressing noise superimposed on the gate voltage Vgs and suppressing sudden fluctuations in the gate voltage applied between the gate terminal G and the source terminal S of the semiconductor device 302. In this example, the ferrite bead FB is described as an inductor for suppressing oscillation noise. However, such an inductor may be an inductor with a hollow cylindrical ferrite core structure, or may have an equivalent circuit configuration of the ferrite bead FB composed of an inductor L and a resistor R.

[0027] FIG. 2(b) illustrates an example of an evaluation of oscillation in a switching circuit 300 equipped with a ferrite bead FB in the GND path. The evaluation measurement conditions are the same as those in FIG. 1. In FIG. 2(b), the vertical axis represents the relative magnitude of the measured current and voltage fluctuations, and the horizontal axis represents time. The rectangular T represents the rising edge of the evaluation signal applied to the gate terminal G. Graph G5 represents the transitions of the gate voltage Vgs, graph G6 represents the drain current Ids, and graph G7 represents the transitions of the inter-terminal voltage Vds. As shown in graph G5, the gate voltage Vgs suppresses high-frequency oscillation noise caused by parasitic capacitance upon turning on the semiconductor device 302. It can be seen that the fluctuation range of the gate voltage Vgs remains constant without swinging negatively relative to the potential state (rectangular frame 1) before the evaluation signal is input.

[0028] As explained with reference to FIGS. 1 and 2, in the switching circuit 300, it is found that providing a ferrite bead FB as an inductor that increases impedance is effective in suppressing high-frequency oscillation noise caused by the parasitic capacitance of the semiconductor device 302. However, adding the ferrite bead FB amplifies the charge stored in the parasitic capacitance (capacitors Cgd, Cgs, and Cds) when the semiconductor device 302 is turned on and off, which can increase noise (Miller noise) associated with switching operations. The increase in Miller noise becomes more pronounced as the switching speed increases, and this can, for example, increase the voltage applied to the gate terminal, potentially causing malfunction of the semiconductor device or destruction of other switching devices (e.g., arm destruction) that constitute the half-bridge circuit or full-bridge circuit.

[0029] Fig. 3 is a diagram illustrating noise propagation paths in a switching circuit 300. In Fig. 3, the path indicated by a thick arrow Z11 represents the propagation path of oscillation noise, and the path indicated by a thick dashed arrow Z12 represents the propagation path of Miller noise. Note that in the switching circuit 300 illustrated in Fig. 3, the ferrite bead FB is provided immediately adjacent to the gate terminal of the wiring path connecting the connection point T1 of the gate driver 301 and the gate terminal G of the semiconductor device 302.

[0030] As indicated by the thick arrow Z11, the oscillation noise propagates via a path of GND potential between the gate driver 301 and the semiconductor device 302, forming a closed loop of a propagation path consisting of the control power supply Vs → gate driver 301 → ferrite bead FB → gate terminal G → source terminal S → control power supply Vs. In the closed loop indicated by the thick arrow Z11, the inductor formed by the ferrite bead FB functions to increase the impedance to the oscillation noise, thereby suppressing the oscillation noise.

[0031] However, the Miller noise is generated by the parasitic capacitance (capacitor Cgd, The noise is caused by parasitic capacitances Cgs and Cds, and the charge stored in the parasitic capacitances propagates as the semiconductor device 302 is turned on and off. As a result, as indicated by the thick dashed arrow Z12, a closed loop is formed in the mirror noise propagation path consisting of the gate driver 301 (connection point T1) → ferrite bead FB → gate terminal G → source terminal S → gate driver 301 (GND-side switch element S2) → gate driver 301 (connection point T1).

[0032] 3, Miller noise propagates in both directions through the closed loop indicated by the thick dashed arrow Z12 as the semiconductor device 302 is turned on and off. As a result, the charge stored in the parasitic capacitances (capacitors Cgd, Cgs, and Cds) is amplified via the inductor of the ferrite bead FB, increasing the Miller noise as the semiconductor device 302 is turned on and off.

[0033] <Circuit configuration of Example 1> FIG. 4 is a circuit diagram showing the circuit configuration of a switching circuit 100 according to this embodiment. The switching circuit 100 according to this embodiment includes a gate driver 101 having a Miller clamp circuit 103 that suppresses Miller noise, a ferrite bead FB that suppresses oscillation noise, and a semiconductor device 102. The Miller clamp circuit 103 bypasses current due to charges stored in parasitic capacitances (capacitors Cgd, Cgs, and Cds) to the source terminal side, thereby suppressing an increase in gate potential due to Miller noise. In the switching circuit 100 according to this embodiment, a connection point T4 of the Miller clamp circuit 103 is configured to be connected to a connection point T3 that is connected to the gate terminal G of the semiconductor device 102. The ferrite bead FB in the switching circuit 100 according to this embodiment is configured to be located immediately adjacent to the gate driver 101 on a path between a connection point T2 of the gate driver 101 and a connection point T3 to which the Miller clamp circuit 103 is connected. That is, one end of the ferrite bead FB is connected to the connection point T2 of the gate driver 101, and the other end is connected to the connection point T3. In the switching circuit 100 according to this embodiment, the gate driver 101 corresponds to an example of a "drive circuit," and the semiconductor device 102 corresponds to an example of a "switching device." Similarly, the Miller clamp circuit 103 corresponds to an example of a "clamp circuit," and the ferrite bead FB corresponds to an example of a "ferrite inductor." Furthermore, the connection point T2 of the gate driver 101 according to this embodiment corresponds to an example of an "output terminal," and the connection point T3 to which the other end of the ferrite bead FB is connected corresponds to an example of a "connection point."

[0034] 4, the switching circuit 100 according to this embodiment can separate the closed loop of the propagation path of oscillation noise propagating via the GND potential from the closed loop of the propagation path of Miller noise accompanying the turn-on and turn-off of the semiconductor device 102. The switching circuit 100 according to this embodiment can suppress the oscillation noise propagating via the GND potential by the inductor of the ferrite bead FB, and can suppress the propagated Miller noise by the Miller clamp circuit 103 connected via the connection point T3.

[0035] 5A and 5B are diagrams illustrating noise propagation paths in a switching circuit 100 according to this embodiment. Fig. 5A illustrates a diagram illustrating the propagation paths in the switching circuit 100, and Figs. 5B and 5C illustrate diagrams illustrating the propagation paths in switching circuits 200a and 200b, which have different arrangement positions of ferrite beads FB. In Figs. 5A, 5B, and 5C, each of the thick arrows (Z1, Z3, and Z5) represents the propagation path of oscillation noise in each switching circuit, and each of the thick dashed arrows (Z2, Z4, and Z6) represents the propagation path of Miller noise in each switching circuit.

[0036] In the switching circuit 100 according to this embodiment, as indicated by the thick arrow Z1, oscillation noise propagates through a GND potential path between the gate driver 101 and the semiconductor device 102, forming a closed loop propagation path consisting of the control power supply Vs → gate driver 101 (connection point T2) → ferrite bead FB → connection point T3 → gate terminal G → source terminal S → control power supply Vs. As indicated by the thick dashed arrow Z2, the Miller noise propagation path is a closed loop consisting of the gate terminal G → connection point T3 → connection point T4 → Miller clamp circuit 103 → source terminal S → gate terminal G. In the switching circuit 100 according to this embodiment, the ferrite bead FB is not present in the closed loop path along which the Miller noise propagates. Therefore, in the semiconductor device 102, unlike the semiconductor device 302 shown in FIG. 3, the charge stored in the parasitic capacitances (capacitors Cgd, Cgs, and Cds) is not amplified via the inductor of the ferrite bead FB. In the switching circuit 100, it is possible to suppress both oscillation noise and mirror noise.

[0037] 5(b), a ferrite bead FB for suppressing oscillation noise is provided on the wiring path between the connection point T3 and the gate terminal G. In the switching circuit 200a, as indicated by the thick arrow Z3, oscillation noise propagates through a GND potential path between the gate driver 101 and the semiconductor device 102, forming a closed loop propagation path consisting of the control power supply Vs → gate driver 101 (connection point T2) → ferrite bead FB → gate terminal G → source terminal S → control power supply Vs. However, as indicated by the thick dashed arrow Z4, the propagation path of Miller noise becomes a closed loop consisting of the gate terminal G → ferrite bead FB → connection point T3 → connection point T4 → Miller clamp circuit 103 → source terminal S → gate terminal G, and the ferrite bead FB is included in the closed loop path along which Miller noise propagates. Therefore, when the ferrite bead FB is provided on the path between the connection point T3 and the gate terminal G, although the Miller clamp circuit 103 can provide some noise suppression effect, the charge stored in the parasitic capacitance (capacitors Cgd, Cgs, Cds) of the semiconductor device 102 is amplified via the inductor of the ferrite bead FB, and a sufficient noise suppression effect cannot be obtained.

[0038] 5(c), a ferrite bead FB for suppressing oscillation noise is provided on the path between the GND potential side of the Miller clamp circuit 103 and the source terminal S. In the switching circuit 200b, as indicated by the thick arrow Z5, oscillation noise propagates via the GND potential path between the gate driver 101 and the semiconductor device 102, forming a closed-loop propagation path consisting of the control power supply Vs → gate driver 101 (connection point T2) → gate terminal G → source terminal S → ferrite bead FB → control power supply Vs. However, as indicated by the thick dashed arrow Z6, the propagation path of Miller noise becomes a closed loop consisting of the gate terminal G → connection point T3 → connection point T4 → Miller clamp circuit 103 → ferrite bead FB → source terminal S → gate terminal G, and the ferrite bead FB is included in the closed-loop path along which the Miller noise propagates. For this reason, even in the switching circuit 200b, although the Miller clamp circuit 103 can provide some noise suppression effect, the charge stored in the parasitic capacitance (capacitors Cgd, Cgs, Cds) of the semiconductor device 102 is amplified via the inductor of the ferrite bead FB, and therefore a sufficient noise suppression effect cannot be expected.

[0039] Returning to FIG. 4, the gate driver 101 includes a switch element S3, one end of which is connected to the positive side of the control power supply Vs, and a switch element S4, one end of which is connected to the negative side (GND) of the control power supply Vs, and the other end of the switch element S3 is connected to the other end of the switch element S4 via a connection point T2. The gate driver 101 opens and closes the switch elements S3 and S4 in accordance with a control signal Vsig such as PWM, and generates a gate voltage Vgs for driving the semiconductor device based on the voltage applied from the control power supply Vs. The gate voltage Vgs generated by this is applied between the gate terminal G and the source terminal S of the semiconductor device 102 via a ferrite bead FB, one end of which is connected to the connection point T2, and GND. In this embodiment, the switch element S3 corresponds to an example of a "first switch element," and the switch element S4 corresponds to an example of a "second switch element." Note that the semiconductor device 102 is a switching device having a circuit configuration similar to that of the semiconductor device 302, and therefore a description thereof will be omitted.

[0040] The Miller clamp circuit 103 includes an internal reference potential Vth, a comparator COM, a clamp logic 103a, and a transistor Qs, which is an N-type MOSFET. The Miller clamp circuit 103 may be provided outside the gate driver 101. The transistor Qs may be replaced with another switch, such as a P-type MOSFET.

[0041] In the Miller clamp circuit 103, an internal reference potential Vth is input as a signal source to the inverting input terminal (-) of the comparator COM. A gate voltage Vgs propagated via a connection point T4 is input to the non-inverting input terminal (+) of the comparator COM. The comparator COM compares the internal reference potential Vth input to the inverting input terminal (-) with the gate voltage Vgs input to the non-inverting input terminal (+), and outputs the comparison result to the clamp logic 103a. The clamp logic 103a controls the gate voltage of the transistor Qs based on the comparison result output from the comparator COM, thereby controlling the conduction or open state between the drain and source. The drain of the transistor Qs is connected to the connection point T4, and the source is connected to a GND potential. In the Miller clamp circuit 103, for example, the gate voltage is controlled so that the drain-source of the transistor Qs is conductive when the switch element S4 is turned on (closed). As a result, Miller noise caused by the charge stored in the parasitic capacitances (capacitors Cgd, Cgs, Cds) of the semiconductor device 102 during turn-on and turn-off is suppressed. In the Miller clamp circuit 103 according to this embodiment, the GND potential corresponds to an example of a "reference potential," and the internal reference potential Vth corresponds to an example of a "threshold potential." Similarly, the transistor Qs of the Miller clamp circuit 103 corresponds to an example of a "third switch element that establishes conduction between the reference potential of the drive circuit and the connection point."

[0042] <Mirror noise suppression evaluation> Next, the results of an evaluation test of Miller noise suppression using the switching circuit 100 according to this embodiment will be described with reference to FIGS. 6 to 9. To perform a comparative evaluation, a comparative evaluation test was conducted on the switching circuit 200b illustrated in FIG. 5(c), i.e., a configuration in which a ferrite bead FB for suppressing oscillation noise is provided on the path between the GND potential side of the Miller clamp circuit 103 and the source terminal S. The evaluation conditions were: an input voltage of 50 V applied between the drain terminal D and the source terminal S of the semiconductor device 102; an output voltage of 90 V generated by the switching operation (turn-on, turn-off) of the semiconductor device 102; and a switching frequency of 50 kHz. Voltage fluctuations due to Miller noise associated with turn-on and turn-off were measured. In this embodiment, the voltage (inter-terminal voltage) Vds applied between the drain terminal D and the source terminal S and the gate voltage Vgs were measured as voltage fluctuations due to Miller noise.

[0043] First, the test results at turn-on will be described. Fig. 6 is a diagram illustrating the results of an evaluation test at turn-on using the switching circuit 100 according to this embodiment. Fig. 6(a) illustrates the circuit configuration of the switching circuit 100#1, and Fig. 6(b) illustrates the Miller noise state for the inter-terminal voltage Vds and the gate voltage Vgs measured under the evaluation conditions described above.

[0044] In FIG. 6(a), circuits 104 and 105 are gate resistance adjustment circuits. The circuit 104 is composed of resistors Rp, Rgon, Rgoff, a capacitor Cp, and a diode Dp. , is provided between a ferrite bead FB provided close to the gate driver 101 and the gate terminal G of the semiconductor device 102. The circuit 105 is composed of a resistor Rs and a capacitor Cs, and is provided on the path of GND potential between the source terminal S of the semiconductor device 102 and the gate driver 101. In FIG. 6(a), the dashed-dotted arrow indicates the propagation path of Miller noise propagated via the drain terminal D and gate terminal G when the semiconductor device 102 is turned on.

[0045] In Figure 6(b), the vertical axis represents the relative magnitude of the measured voltage fluctuation, and the horizontal axis represents time. The graph shown in rectangular frame 1 represents the transition of the voltage (terminal voltage) Vds applied between the drain terminal D and the source terminal S when the semiconductor device is turned on, and similarly, the graph shown in rectangular frame 2 represents the transition of the gate voltage Vgs.

[0046] The thick-circled area in FIG. 6(b) illustrates the transition of the gate voltage Vgs due to Miller noise. As shown by the transition of the gate voltage Vgs within the thick-circled area, it can be seen that the voltage fluctuation due to Miller noise is minimized. In the switching circuit 100 of this embodiment, the ferrite bead FB is provided close to the output terminal (connection point T2) of the gate driver 101, and a connection point T3 on the connection path between the ferrite bead FB and the gate terminal G is connected to a connection point T4 of the Miller clamp circuit 103. The Miller noise propagated via the connection point T3 propagates via the transistor Qs of the Miller clamp circuit 103 provided in the gate driver 101 to the GND potential to which the source terminal S of the semiconductor device 102 is connected. Because the ferrite bead FB does not exist in the path along which the Miller noise propagates (indicated by the dashed-dotted arrow), the Miller clamp circuit 103 can effectively suppress the Miller noise. As shown by the bold circle in Figure 6(b), the effect of Miller noise on the gate voltage Vgs (fluctuation range of the gate voltage) is minimized, preventing malfunctions and other problems caused by an increase in the gate voltage Vgs.

[0047] FIG. 7 illustrates the results of an evaluation test performed on the switching circuit 200b during turn-on. FIG. 7(a) illustrates the circuit configuration of the switching circuit 200b#1, and FIG. 7(b) illustrates the Miller noise versus the inter-terminal voltage Vds and gate voltage Vgs measured under the evaluation conditions described above. The circuits 104 and 105 in the switching circuit 200b#1 are similar to those in the switching circuit 100#1. The circuit 105 is located on the GND potential path between the ferrite bead FB and the source terminal S of the semiconductor device 102. The dashed-dotted arrow in FIG. 7(a) represents the propagation path of the Miller noise propagating via the drain terminal D and gate terminal G when the semiconductor device 102 is turned on. The vertical axis in FIG. 7(b) represents the relative magnitude of the measured voltage fluctuation, and the horizontal axis represents time. Similar to Figure 6(b), the graph shown in rectangular frame 1 represents the change in the voltage (terminal voltage) Vds applied between the drain terminal D and the source terminal S when the semiconductor device is turned on, and the graph shown in rectangular frame 2 represents the change in the gate voltage Vgs.

[0048] In FIG. 7(b), the transition of the gate voltage Vgs due to Miller noise is shown in the area circled by a thick line. In the switching circuit 200b, as already explained, a ferrite bead FB for suppressing oscillation noise is provided on the path between the GND potential side of the Miller clamp circuit 103 and the source terminal S. The Miller noise propagated via the connection point T3 propagates to the GND potential to which the source terminal S of the semiconductor device 102 is connected via the transistor Qs and ferrite bead FB of the Miller clamp circuit 103 provided in the gate driver 101. The Miller noise, whose voltage fluctuation range is once suppressed by the Miller clamp circuit 103, is increased by the inductor of the ferrite bead FB and propagates to the GND potential to which the source terminal S of the semiconductor device 102 is connected. For this reason, as shown in the transition of the gate voltage Vgs within the thick line circle in FIG. 7(b), the voltage fluctuation range due to Miller noise is larger than the voltage fluctuation shown in the transition of the gate voltage Vgs within the thick line circle in FIG. 6(b). It can be seen that the amplitude is relatively large compared to the oscillation width. When the ferrite bead FB for suppressing oscillation noise is located on the path between the GND potential side of the Miller clamp circuit 103 and the source terminal S, it is not possible to obtain a sufficient Miller noise suppression effect at turn-on.

[0049] Next, test results during turn-off will be described. FIG. 8 illustrates the results of an evaluation test performed on the switching circuit 100 according to this embodiment during turn-off. FIG. 8(a) illustrates the circuit configuration of the switching circuit 100#1, similar to that shown in FIG. 6(a), and FIG. 8(b) illustrates the Miller noise versus the inter-terminal voltage Vds and gate voltage Vgs measured under the evaluation conditions described above. The dashed-dotted arrow in FIG. 8(a) represents the propagation path of Miller noise propagating via the drain terminal D and gate terminal G during turn-off of the semiconductor device 102. The vertical axis of FIG. 8(b) represents the relative magnitude of the measured voltage fluctuation, and the horizontal axis represents time. The graph indicated by rectangular frame 1 represents the transition of the voltage (inter-terminal voltage) Vds applied between the drain terminal D and source terminal S during turn-off of the semiconductor device. Similarly, the graph indicated by rectangular frame 2 represents the transition of the gate voltage Vgs.

[0050] The thick-circled area in Figure 8(b) illustrates the transition of the gate voltage Vgs due to Miller noise during turn-off. As shown by the transition of the gate voltage Vgs within the thick-circled area, it can be seen that the voltage fluctuation due to Miller noise is minimized even during turn-off. This is because the ferrite bead FB does not exist in the path (indicated by the dashed-dotted arrow) along which Miller noise propagates, branching off at connection point T3, and therefore the Miller clamp circuit 103 provided on the path can fully suppress the noise.

[0051] 9A and 9B are diagrams illustrating the results of an evaluation test performed on the switching circuit 200b during turn-off. Fig. 9A illustrates the circuit configuration of the switching circuit 200b#1, and Fig. 9B illustrates the Miller noise versus the inter-terminal voltage Vds and gate voltage Vgs measured under the evaluation conditions described above. The dashed-dotted arrows in Fig. 9A, the vertical and horizontal axes in Fig. 9B, and the rectangular frames 1 and 2 are the same as those in Fig. 8.

[0052] In Figure 9(b), the thick-circled area illustrates the transition of the gate voltage Vgs due to Miller noise during turn-off. As shown by the transition of the gate voltage Vgs within the thick-circled area in Figure 9(b), the voltage fluctuation range due to Miller noise is relatively large compared to the voltage fluctuation range shown by the transition of the gate voltage Vgs within the thick-circled area in Figure 8(b). This is because, as with turn-on, sufficient Miller noise suppression effect cannot be obtained because the ferrite bead FB for suppressing oscillation noise is present on the path between the GND potential side of the Miller clamp circuit 103 and the source terminal S.

[0053] As described above, the switching circuit 100 according to this embodiment can be configured such that the ferrite bead FB is provided immediately adjacent to the gate driver 101, and the connection point T3 on the path connecting the ferrite bead FB and the gate terminal G of the semiconductor device 102 is connected to the input terminal (connection point T4) of the Miller clamp circuit 103. The switching circuit 100 according to this embodiment can separate the closed loop of the propagation path of the oscillation noise propagating via the GND potential from the closed loop of the propagation path of the Miller noise accompanying the turn-on and turn-off of the semiconductor device 102. As a result, the oscillation noise propagating via the GND potential is suppressed by the inductor of the ferrite bead FB, and the Miller clamp circuit 103 connected via the connection point T3 can sufficiently enhance the suppression effect of the Miller noise propagated. The switching circuit 100 according to this embodiment can provide a technology that suppresses both the oscillation noise of the semiconductor device and the Miller noise.

[0054] <Variation 1> FIG. 10 is a circuit diagram showing the circuit configuration of a switching circuit 100a according to Modification 1. The switching circuit 100a according to Modification 1 includes a gate resistor Rg connected in series with a ferrite bead FB. Specifically, one end of the ferrite bead FB, which is provided adjacent to the gate driver 101, is connected to a connection point T2 of the gate driver 101, and the other end is connected to one end of the gate resistor Rg. The other end of the gate resistor Rg is connected to a connection point T3 provided on a path connected to the gate terminal G. Therefore, Modification 1 can achieve the same effects as the switching circuit 100 according to Example 1. Furthermore, in Modification 1, the addition of the gate resistor Rg makes it possible to change the rise time (slew rate) of the gate voltage applied to the gate terminal G, thereby changing the switching speed related to the turn-on and turn-off of the semiconductor device 102. Changing the rise time of the gate voltage is expected to reduce switching noise (Miller noise) associated with the turn-on and turn-off of the semiconductor device 102.

[0055] <Variation 2> In the switching circuit 100a according to the first modification, the gate resistor Rg connected in series with the ferrite bead FB may be located on the gate driver 101 side. FIG. 11 is a circuit diagram showing the circuit configuration of a switching circuit 100b according to the second modification. In the switching circuit 100b according to the second modification, one end of the gate resistor Rg is connected to a connection point T2 of the gate driver 101, and the other end is connected to one end of the ferrite bead. The other end of the ferrite bead FB is connected to a connection point T3 provided in a path connected to the gate terminal G. The configuration of the switching circuit 100b shown in FIG. 11 can also achieve the same effects as those of the first modification. In the first and second modifications, the gate resistor Rg corresponds to an example of a "resistance element."

[0056] <Variation 3> FIG. 12 is a circuit diagram showing the circuit configuration of a switching circuit 100c according to Modification 3. The switching circuit 100c according to Modification 3 further includes a Schottky diode Ds in addition to the circuit configuration of the switching circuit 100a according to Modification 1. While FIG. 12 illustrates the circuit configuration of the switching circuit 100a according to Modification 1 including the Schottky diode Ds, the circuit configuration of the switching circuit 100b according to Modification 2 may also include the Schottky diode Ds. As shown in FIG. 12, the Schottky diode Ds is provided between the connection point T3 and a GND potential, with the anode of the Schottky diode Ds connected to the GND potential and the cathode connected to the connection point T3. This circuit configuration reduces the impedance of the current path through which switching noise (mirror noise) propagates, thereby further improving the effect of reducing switching noise (mirror noise) associated with turning on and off the semiconductor device 102. The cathode of the Schottky diode Ds may be connected to the path connecting the connection points T3 and T4. In the third modification, the Schottky diode Ds corresponds to an example of a "diode element."

[0057] <Variation 4> FIG. 13 is a circuit diagram showing the circuit configuration of a switching circuit 100d according to Modification 4. The switching circuit 100d according to Modification 4 further includes a capacitor Cp in addition to the circuit configuration of the switching circuit 100c according to Modification 3. As shown in FIG. 12, one end of the capacitor Cp is connected to a connection point T5 between the ferrite bead FB and the gate resistor Rg, and the other end is connected to a connection point T3. The addition of the capacitor Cp connected in parallel to the gate resistor Rg can increase the switching speed related to turning on and off the semiconductor device 102, which is expected to reduce switching loss in the switching circuit. In Modification 4, the capacitor Cp corresponds to an example of a "capacitor element."

[0058] (others) The above-described embodiment is merely an example, and the disclosure of the present embodiment may be appropriately modified and implemented without departing from the spirit thereof. The processes and means described in the present disclosure may be freely combined and implemented as long as no technical contradiction occurs.

[0059] Furthermore, a process described as being performed by one circuit or device may be shared and performed by multiple circuits or devices, or a process described as being performed by different circuits or devices may be performed by a single circuit or device.

[0060] In the following, the constituent elements of the present invention will be described with reference to the reference numerals in the drawings in order to make it possible to compare the constituent elements of the present invention with the configurations of the embodiments. <Invention 1> a switching device (102) that turns on or off a state between a drain terminal (102, D) and a source terminal (102, S) based on a voltage applied between a gate terminal (102, G) and a source terminal (102, S); a drive circuit (101) comprising: a first switch element (101, S3) having one end connected to the positive side of a control power supply (Vs) and the other end connected to an output terminal (101, T2); and a second switch element (101, S4) having one end connected to the output terminal (101, T2) and the other end connected to a reference potential (GND) to which the negative side of the control power supply (Vs) is connected, the drive circuit (101) opening and closing the first switch element (101, S3) and the second switch element (101, S4) in accordance with a predetermined control signal (Vsig), generating a drive voltage (Vgs) for driving the switching device (102), and outputting the generated drive voltage (Vgs) to a gate terminal (102, G) of the switching device (102) via the output terminal (101, T2); a clamp circuit (103) having a third switch element (103, Qs) that conducts between the reference potential (GND) of the drive circuit (101) and the connection point (T3) of a path connecting an output terminal (101, T2) of the drive circuit (101) and a gate terminal (G) of the switching device (102) based on a comparison result between a threshold potential (Vth) generated based on the reference potential (GND) of the drive circuit (101) and the connection point (T3) of the path connecting an output terminal (101, T2) of the drive circuit (101) and the gate terminal (G) of the switching device (102); a ferrite inductor (FB) provided in close proximity to the output terminal (101, T2) of the drive circuit (101), one end of which is connected to the output terminal (101, T2) and the other end of which is connected to the connection point (T3); A switching circuit (100) comprising: [Explanation of symbols]

[0061] 100, 100a, 100b, 100c, 100d, 100#1, 200a, 200b, 200ba#1, 300 switching circuit 101, 301 gate drivers 102, 302 Semiconductor devices (switching devices) 103 Miller clamp circuit 104, 105, 303 Gate resistance adjustment circuit FB ferrite beads T2, T3, T4, T5 Junctions D1 Parasitic diode Ds Schottky diode Qs transistor (third switch element) Rg Gate resistance Cp capacitor Cgd, Cgs, Cds capacitors (parasitic capacitance)

Claims

1. a switching device that turns on or off the state between the drain terminal and the source terminal based on a voltage applied between the gate terminal and the source terminal; a drive circuit including a first switch element having one end connected to the positive side of a control power supply and the other end connected to an output terminal, and a second switch element having one end connected to the output terminal and the other end connected to a reference potential to which the negative side of the control power supply is connected, the drive circuit opening and closing the first switch element and the second switch element in accordance with a predetermined control signal, generating a drive voltage for driving the switching device, and outputting the generated drive voltage to a gate terminal of the switching device via the output terminal; a clamp circuit having a third switch element that, based on a comparison result between a threshold potential generated based on a reference potential of the drive circuit and a potential at a connection point of a path connecting an output end of the drive circuit and a gate terminal of the switching device, conducts between the reference potential of the drive circuit and the connection point; a ferrite inductor provided in close proximity to an output terminal of the drive circuit, one end of which is connected to the output terminal and the other end of which is connected to the connection point; Equipped with the ferrite inductor is provided in series between an output terminal of the drive circuit and a gate terminal of the switching device; the clamp circuit is connected to the connection point on the gate terminal side of the ferrite inductor, A switching circuit, characterized in that the ferrite inductor and the clamp circuit are arranged so as to separate a propagation path of oscillation noise from a propagation path of Miller noise.

2. 2. The switching circuit according to claim 1, further comprising a resistive element connected in series with the ferrite inductor between the output terminal of the drive circuit and the connection point.

3. 3. The switching circuit according to claim 1, further comprising a diode element having an anode connected to a reference potential of the drive circuit and a cathode connected to the connection point.

4. 4. The switching circuit according to claim 2, wherein a capacitor element is connected in parallel to the resistor element connected in series with the ferrite inductor.

5. 5. The switching circuit according to claim 1, wherein the ferrite inductor is an equivalent circuit corresponding to the ferrite inductor.

6. The switching circuit according to claim 1 , wherein the switching device is made of a wide bandgap semiconductor including at least a SiC semiconductor and a GaN semiconductor.

7. A power converter comprising a switching circuit according to any one of claims 1 to 6.

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