Calculation program and calculation method

Abstract

To provide a calculation program to calculate a degree of degradation of an electrical characteristic of an amplifier circuit.SOLUTION: A calculation program, in an amplifier circuit comprising an input terminal to which a high-frequency signal is inputted, a transistor to amplify the inputted high-frequency signal, an output terminal to output the amplified high-frequency signal, and a matching circuit connected between the transistor and the output terminal, makes a computer execute a step S12 of calculating the high-frequency characteristics of the amplifier circuit based on the element values of the matching circuit by using the equivalent circuit of the transistor, a step S16 of calculating at least one of the current value and the voltage value at a specified point in the equivalent circuit based on the element values by using the equivalent circuit if the calculated high-frequency characteristics of the amplifier circuit are the desired characteristics, and a step S18 of calculating a degree of degradation of the electrical characteristics of the transistor based on the at least one of the values by using data that maps the at least one of the values to the degree of degradation of the electrical characteristics of the transistor.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a calculation program and a calculation method, and more particularly to a calculation program and a calculation method for calculating the degree of degradation of electrical characteristics of an amplifier circuit, for example. [Background technology]

[0002] Radio frequency power amplifier circuits are used in mobile communication base stations. Transistors such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) are used in the amplifier circuits. Several degradation modes are known in degradation tests of the electrical characteristics of GaN HEMTs (for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] IEEE TRANSACTIONS DEVICE AND MATERIALS RELIABIILITY, Vol. 15, No. 4, pp. 486-494 (2015) Summary of the Invention [Problem to be solved by the invention]

[0004] Amplifier circuits are designed to obtain desired high-frequency characteristics by adjusting the load impedance of the transistors. However, even if the desired high-frequency characteristics are obtained, the degradation of the electrical characteristics does not necessarily fall within the desired range.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a calculation program and a calculation method for calculating the degree of degradation of the electrical characteristics of an amplifier circuit. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a calculation program that causes a computer to execute the following steps in an amplifier circuit that includes an input terminal for inputting a high-frequency signal, a transistor for amplifying the input high-frequency signal, an output terminal for outputting the amplified high-frequency signal, and a matching circuit connected between the transistor and the output terminal: calculating high-frequency characteristics of the amplifier circuit using an equivalent circuit of the transistor based on element values ​​of the matching circuit; if the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, calculating at least one of a current value and a voltage value at a predetermined location within the equivalent circuit based on the element values ​​using the equivalent circuit; and calculating a degree of degradation of the electrical characteristics of the transistor based on the at least one value and data that associates the at least one value with a degree of degradation of the electrical characteristics of the transistor.

[0007] One embodiment of the present disclosure is a calculation method executed by a computer, in an amplifier circuit having an input terminal for inputting a high-frequency signal, a transistor for amplifying the input high-frequency signal, an output terminal for outputting the amplified high-frequency signal, and a matching circuit connected between the transistor and the output terminal, the method including the steps of: calculating high-frequency characteristics of the amplifier circuit using an equivalent circuit of the transistor based on element values ​​of the matching circuit; if the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, calculating at least one of a current value and a voltage value at a predetermined location within the equivalent circuit based on the element values ​​using the equivalent circuit; and calculating a degree of degradation of the electrical characteristics of the transistor based on the at least one value using data correlating the at least one value with a degree of degradation of the electrical characteristics of the transistor.

[0008] The present disclosure can be realized not only as such a characteristic calculation program and calculation method, but also as a calculation device that processes such characteristic steps, as a semiconductor integrated circuit that realizes part or all of the calculation device, or as a calculation system that includes the calculation device. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a calculation program and a calculation method for calculating the degree of degradation of the electrical characteristics of an amplifier circuit. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram of an amplifier circuit according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an equivalent circuit of a large signal model of an FET in the first embodiment. [Figure 3] FIG. 3 is a block diagram of a computer according to the first embodiment. [Figure 4] FIG. 4 is a flowchart illustrating a method for designing an amplifier circuit according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing the output power Pout, the gain Gain, and the PAE relative to the input power Pin. [Figure 6] FIG. 6 is a diagram showing a load line in a large signal model. [Figure 7] FIG. 7 is a schematic diagram showing the drain current Ids-drain voltage Vds characteristics and the degradation mode. [Figure 8] FIG. 8 is a schematic diagram showing the drain current Ids-drain voltage Vds characteristics and a load line. [Figure 9] FIG. 9 is a diagram showing parameters with respect to time in Mode A. [Figure 10] FIG. 10 is a diagram showing parameters with respect to time in Mode B. [Figure 11] FIG. 11 is a diagram showing parameters with respect to time in Mode C. [Figure 12] FIG. 12 is an Arrhenius plot showing MTTF versus temperature in Mode A. [Figure 13] FIG. 13 is an Arrhenius plot showing MTTF versus temperature for Mode B. [Figure 14]FIG. 14 is an Arrhenius plot showing MTTF versus temperature for Mode C. [Figure 15] FIG. 15 is a diagram showing data stored in the memory of a computer. [Figure 16] FIG. 16 is a flowchart illustrating an example of steps S16 and S18. [Figure 17] FIG. 17 is an Arrhenius plot showing the MTTF of modes A to D versus temperature. [Figure 18] FIG. 18 is an Arrhenius plot showing the MTTF of modes A to D versus temperature. DETAILED DESCRIPTION OF THE INVENTION

[0011] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a calculation program that causes a computer to execute the following steps in an amplifier circuit including an input terminal for inputting a high-frequency signal, a transistor for amplifying the input high-frequency signal, an output terminal for outputting the amplified high-frequency signal, and a matching circuit connected between the transistor and the output terminal: calculating high-frequency characteristics of the amplifier circuit using an equivalent circuit of the transistor based on element values ​​of the matching circuit; if the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, calculating at least one of a current value and a voltage value at a predetermined location in the equivalent circuit based on the element values ​​using the equivalent circuit; and calculating a degradation level of the transistor's electrical characteristics based on the at least one value and data correlating the at least one value with a degradation level of the transistor's electrical characteristics. This allows the degradation level of the amplifier circuit to be calculated. (2) It is preferable to have a computer execute a step of determining whether the calculated degree of degradation is a desired degree of degradation or not, and when it is determined that the calculated degree of degradation is not the desired degree of degradation, change the element value and calculate the high-frequency characteristics based on the changed element value, calculate at least one of the values, calculate the degree of degradation, and determine whether the degree of degradation is the desired degree of degradation or not. (3) It is preferable that the step of calculating at least one of the values ​​includes a step of calculating, as the at least one of the values, a current value at an end of a current source in the equivalent circuit and a voltage value across both ends of the current source. (4) The step of calculating the at least one value preferably includes a step of calculating at least two values ​​from the following: a first value of at least one of a voltage value and a current value at a first end of a load line where the voltage value is smallest in the current-voltage characteristic between the current value at an end of the current source in the equivalent circuit and the voltage values ​​at both ends of the current source; a second value of at least one of a voltage value and a current value at a second end of the load line where the voltage value is largest; and a third value of at least one of a DC current component and a DC voltage component on the load line; and the step of calculating the degradation degree preferably includes a step of calculating the degradation degree of at least two electrical characteristics of the transistor based on each of the at least two values. (5) The step of calculating the degradation degree preferably includes the step of calculating the worst degradation degree of the two electrical characteristics as the degradation degree of the electrical characteristics of the transistor. (6) It is preferable that the step of calculating at least one of the values ​​includes the steps of calculating the first value, the second value, and the third value, and that the step of calculating the degree of degradation includes the step of calculating the degree of degradation of each of the three electrical characteristics of the transistor based on each of the first value, the second value, and the third value. (7) Preferably, the transistor is an FET having a gate connected to the input terminal and a drain connected to the matching circuit, and the current source is a drain current source within the FET. (8) The step of calculating at least one of the values ​​preferably includes a step of calculating a fourth value of at least one of a current value at an end of at least one of a diode between the gate and source and a diode between the gate and drain in the equivalent circuit and a voltage value across both ends of the at least one of the diodes, and the step of calculating the degradation degree preferably includes a step of calculating a degradation degree of the electrical characteristics of the FET based on the fourth value. (9) It is preferable that the step of acquiring the operating temperature of the transistor by a computer and the step of calculating the degree of degradation of the electrical characteristics of the transistor include a step of calculating the degree of degradation of the electrical characteristics of the transistor based on the at least one value and the operating temperature using data correlating the at least one value and the operating temperature with the degree of degradation of the electrical characteristics of the transistor. (10) One embodiment of the present disclosure provides a calculation method executed by a computer, in an amplifier circuit including an input terminal for inputting a high-frequency signal, a transistor for amplifying the input high-frequency signal, an output terminal for outputting the amplified high-frequency signal, and a matching circuit connected between the transistor and the output terminal, the method including the steps of: calculating high-frequency characteristics of the amplifier circuit using an equivalent circuit of the transistor based on element values ​​of the matching circuit; if the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, calculating at least one of a current value and a voltage value at a predetermined point in the equivalent circuit based on the element values ​​using the equivalent circuit; and calculating a degradation level of the transistor's electrical characteristics based on the at least one value and data correlating the at least one value with a degradation level of the transistor's electrical characteristics, thereby enabling the degradation level of the amplifier circuit to be calculated. (11) One embodiment of the present disclosure is a calculation device for an amplifier circuit including an input terminal for inputting a high-frequency signal, a transistor for amplifying the input high-frequency signal, an output terminal for outputting the amplified high-frequency signal, and a matching circuit connected between the transistor and the output terminal, the calculation device including: a high-frequency characteristic calculation unit that calculates high-frequency characteristics of the amplifier circuit based on element values ​​of the matching circuit using an equivalent circuit of the transistor; a current value / voltage value calculation unit that, when the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, calculates at least one of a current value and a voltage value at a predetermined location in the equivalent circuit based on the element values ​​using the equivalent circuit; and a degradation degree calculation unit that calculates a degradation degree of the electrical characteristics of the transistor based on data correlating the at least one value with a degradation degree of the electrical characteristics of the transistor. (12) One embodiment of the present disclosure is a calculation device comprising: an amplifier circuit including an input terminal for inputting a high-frequency signal, a transistor for amplifying the input high-frequency signal, an output terminal for outputting the amplified high-frequency signal, and a matching circuit connected between the transistor and the output terminal; a processor that calculates high-frequency characteristics of the amplifier circuit based on element values ​​of the matching circuit using an equivalent circuit of the transistor; and, if the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, calculates at least one of a current value and a voltage value at a predetermined location in the equivalent circuit based on the element values ​​using the equivalent circuit; and calculates a degree of degradation of the electrical characteristics of the transistor based on the at least one value using data correlating the at least one value with a degree of degradation of the electrical characteristics of the transistor; and a memory that stores the data.

[0012] [Details of the embodiments of the present disclosure] Specific examples of a calculation program and a calculation method according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0013] At least some of the embodiments described below may be combined in any manner. The calculation device is configured with a computer, and each function of the calculation device is realized by a computer program stored in a storage device of the computer being executed by the CPU (Central Processing Unit) of the computer. The computer program can be stored in a storage medium such as a CD-ROM (Compact Disc Read Only Memory). [Example 1]

[0014] In the following description, the degree of degradation of the electrical characteristics of an amplifier circuit or a transistor, etc., refers to the degree to which the electrical characteristics of the amplifier circuit or transistor, etc., deteriorate when the amplifier circuit or transistor, etc., is continuously used under a certain environment, and is, for example, the lifespan of the amplifier circuit or transistor, etc., at a certain operating temperature. The degree of degradation of the electrical characteristics of the transistor, etc., can be calculated by performing a stress test that applies stress to the transistor, etc.

[0015] [Amplification circuit] In Example 1, an amplifier circuit to be designed will be described using an FET (Field Effect Transistor) as an example of a transistor. FIG. 1 is a circuit diagram of the amplifier circuit in Example 1. As shown in FIG. 1, an amplifier circuit 30 includes an FET 10 and matching circuits 12 and 14. The FET is, for example, a GaN HEMT. A source S of the FET 10 is connected to ground, and a gate G is connected to an input terminal Tin via the matching circuit 12. A drain D of the FET 10 is connected to an output terminal Tout via the matching circuit 14. The matching circuit 12 is connected between the input terminal Tin and the FET 10, and includes inductors L11 and L12 connected in series between the input terminal Tin and the gate G, and a capacitor C11 shunt-connected at a node between the inductors L11 and L12. The matching circuit 14 is connected between the FET 10 and the output terminal Tout, and includes inductors L21 and L22 connected in series between the drain D and the output terminal Tout, and a capacitor C21 shunt-connected at the node between the inductors L21 and L22.

[0016] A high-frequency signal input to the input terminal Tin is input to the gate G of the FET 10 via the matching circuit 12. The FET 10 amplifies the input high-frequency signal. The output terminal Tout outputs the amplified high-frequency signal. The matching circuit 12 matches the input impedance of the input terminal Tin to the input impedance of the gate G. The matching circuit 14 matches the output impedance of the drain D to the output impedance of the output terminal Tout. By designing the element values ​​of the matching circuits 12 and 14 (the inductances of inductors L11, L12, L21, and L22, and the capacitances of capacitors C11 and C21), the high-frequency characteristics of the amplifier circuit 30 can be adjusted to desired characteristics. In particular, by adjusting the element values ​​of the matching circuit 14, the load impedance of the FET 10 can be adjusted, and the high-frequency characteristics of the amplifier circuit 30 can be adjusted. The circuit configurations of the matching circuits 12 and 14 can be designed appropriately. The center frequency of the band of the amplifier circuit 30 is, for example, 0.5 GHz to 10 GHz.

[0017] [Large signal model equivalent circuit] A large signal model is used to design a high-frequency power amplifier circuit. The equivalent circuit of the large signal model used in the first embodiment will be described using a FET as an example. FIG. 2 is a circuit diagram showing the equivalent circuit of the large signal model of the FET in the first embodiment. As shown in FIG. 2, in the equivalent circuit 32, the drain-source current is represented by a drain current source Id. A node N1 on the source side of the current source Id is connected to the source S via a source resistance Rs and a source inductance Ls. A node N2 on the drain side of the drain current source Id is connected to the drain D via a drain resistance Rd and a drain inductance Ld. A drain-source capacitance Cds is connected in parallel with the drain current source Id between nodes N1 and N2. A node N3 is connected to the gate G via a gate resistance Rg and a gate inductance Lg. A gate-drain capacitance Cgd and a diode Dg1 are connected in parallel between nodes N2 and N3. A gate-source capacitance Cgs and a diode Dg2 are connected in parallel between nodes N3 and N4. A channel resistance Ri is connected between nodes N1 and N4. In the case of a GaN HEMT, the diode Dg1 corresponds to a Schottky diode between the gate G and the drain D, and the diode Dg2 corresponds to a Schottky diode between the gate G and the source S.

[0018] In the first embodiment, ammeters A1 to A3 and voltmeters V1 to V4 are provided in the equivalent circuit 32 to calculate high-frequency current and voltage values ​​at predetermined locations in the equivalent circuit 32. The ammeter A1 calculates the current value at the end of the drain current source Id. The ammeters A2 and A3 calculate the current values ​​at the ends of the diodes Dg1 and Dg2, respectively. The voltmeters V1 to V4 calculate the voltage values ​​at the nodes N1 to N4, respectively. The voltage difference between voltmeters V1 and V2 corresponds to the voltage across the drain current source Id. The voltage difference between voltmeters V2 and V3 corresponds to the voltage across the diode Dg1, and the voltage difference between voltmeters V3 and V4 corresponds to the voltage across the diode Dg2.

[0019] [Computer block diagram] FIG. 3 is a block diagram of a computer according to the first embodiment. The computer 20 functions as a calculation device in cooperation with software. The computer 20 executes a calculation program and performs a calculation method. The computer 20 includes a processor 22, a memory 24, an input / output device 26, and an internal bus 28. The processor 22 is, for example, a CPU, and calculates the degree of degradation of the high-frequency characteristics and electrical characteristics of the amplifier circuit 30 using a large-signal model equivalent circuit 32. The memory 24 is, for example, a volatile memory or a non-volatile memory, and stores data used by the processor 22 when calculating the degree of degradation of the high-frequency characteristics and electrical characteristics. The memory 24 may store a program executed by the processor 22. The input / output device 26 inputs data acquired by the processor 22 from an external device and outputs data output by the processor 22 to an external device. The internal bus 28 connects the processor 22, the memory 24, and the input / output device 26, transmitting data and the like. The calculation program is stored in a storage medium. The storage medium is, for example, a non-transitory tangible medium.

[0020] [flowchart] FIG. 4 is a flowchart showing a method for designing an amplifier circuit according to the first embodiment. As shown in FIG. 4, the user or computer 20 sets the element values ​​of the matching circuits 12 and 14 (step S10). For example, the inductances of the inductors L11, L12, L21, and L22 and the capacitances of the capacitors C11 and C21 in FIG. 1 are set. The computer 20 calculates the high-frequency characteristics of the amplifier circuit 30 based on the matching circuits 12 and 14 set using the equivalent circuit 32 (step S12). For example, the computer 20 calculates the output power Pout, gain, power added efficiency (PAE), etc. of the amplifier circuit 30. The user or computer 20 determines whether the calculated high-frequency characteristics are the desired characteristics (step S14). If the result is No, the process returns to step S10. In step S10, the element values ​​of the matching circuits 12 and 14 are reset, and steps S12 and S14 are performed. Steps S10 to S14 are repeated until the result is Yes in step S14. If the determination in step S14 is No, the user may set the element values ​​of the matching circuits 12 and 14 in step S10. Alternatively, the computer 20 may set the element values ​​of the matching circuits 12 and 14 in step S10. The element values ​​of the matching circuit 14 in the computer 20 may be changed using a program using machine learning or the like.

[0021] If the answer is Yes in step S14, the computer 20 calculates at least one of the current value and the voltage value at a predetermined point in the equivalent circuit 32 based on the element values ​​of the matching circuits 12 and 14 set in step S10 (step S16). For example, the computer 20 calculates the current value at the end of the drain current source Id using ammeter A1 of the equivalent circuit 32, and calculates the voltage across the drain current source Id using voltmeters V1 and V2. The computer 20 also calculates the current value at the end of diode Dg1 using ammeter A2, calculates the voltage across diode Dg1 using voltmeters V2 and V3, calculates the current value at the end of diode Dg2 using ammeter A3, and calculates the voltage across diode Dg2 using voltmeters V3 and V4.

[0022] The computer 20 calculates the degree of degradation of the electrical characteristics of the transistor based on the calculated current value and / or voltage value (step S18). For example, data in which the current value and / or voltage value at a predetermined point in the equivalent circuit 32 is associated with the degree of degradation of the electrical characteristics of the transistor is stored in the memory 24. The computer 20 calculates the degree of degradation of the electrical characteristics of the transistor based on the data. The degree of degradation of the electrical characteristics is, for example, the lifetime (e.g., mean time to failure (MTTF)) at the operating temperature of the transistor. The computer 20 determines whether the calculated degree of degradation is a desired degree of degradation (step S20). For example, the computer 20 determines Yes if the calculated lifetime is equal to or greater than the desired lifetime. If No, the process returns to step S10. In step S10, the element values ​​of the matching circuits 12 and 14 are reset, and steps S12 to S20 are performed. Steps S10 to S20 are repeated until the determination in step S20 is Yes. If the determination in step S20 is No, the user may set the element values ​​of the matching circuits 12 and 14 in step S10. The computer 20 may set the element values ​​of the matching circuits 12 and 14 in step S10. A program using machine learning or the like may be used to change the element values ​​of the matching circuit 14 in the computer 20. If the determination in step S20 is Yes, an amplifier circuit having desired high-frequency characteristics and a desired degree of degradation can be designed.

[0023] The processor 22 cooperates with the calculation program to function as a high-frequency characteristic calculation unit, a current / voltage value calculation unit, a degradation degree calculation unit, and a degradation degree determination unit. The high-frequency characteristic calculation unit calculates the high-frequency characteristics of the amplifier circuit 30 in step S12. The current / voltage value calculation unit calculates at least one of the current value and the voltage value at a predetermined location in the equivalent circuit 32 in step S16. The degradation degree calculation unit calculates the degradation degree of the electrical characteristics of the transistor in step S18. The degradation degree determination unit determines whether the calculated degradation degree of the transistor is a desired degradation degree in step S20.

[0024] [Example of high-frequency characteristics calculated in step S12] An example of the high-frequency characteristics calculated in step S12 of FIG. 4 will be described. FIG. 5 is a diagram showing the output power Pout, gain Gain, and PAE relative to the input power Pin. The upper diagram of FIG. 5 is an example of power matching in which the element values ​​of the matching circuits 12 and 14 are set to maximize the output power Pout, and the lower diagram of FIG. 5 is an example of efficiency matching in which the element values ​​of the matching circuits 12 and 14 are set to maximize the PAE. In the upper diagram of FIG. 5, the saturation power (the power at which the output power Pout saturates) and gain are larger than those in the lower diagram of FIG. 5. In the lower diagram of FIG. 5, the maximum PAE is larger than that in the upper diagram of FIG. 5. In this way, changing the element values ​​of the matching circuits 12 and 14 (particularly matching circuit 14) changes the high-frequency characteristics of the transistor. In steps S10 to S14, matching circuits 12 and 14 are designed so that the high-frequency characteristics of amplifier circuit 30 become the desired target high-frequency characteristics (e.g., power matching or efficiency matching).

[0025] [Example of current and voltage values ​​calculated in step S16] An example of the current and voltage values ​​at a predetermined point in the equivalent circuit calculated in step S16 of FIG. 4 will be described. FIG. 6 is a diagram showing a load line in a large-signal model. FIG. 6 shows the drain current Ids versus the drain voltage Vds (Ids-Vds characteristic). The load line shows the Ids-Vds curve when a high-frequency signal with a large amplitude is input as the input signal. FIG. 6 shows an example of a load line when, for example, the high-frequency signal has a frequency of 14 GHz, power matching is performed, and the input power is backed off by 3 dB from the input signal at which the saturation power is reached. The dashed line is the load line between the drain D and the source S, and the solid line is the load line at the end of the drain current source Id (between nodes N1 and N2 in FIG. 2). As shown in FIG. 6, the dashed load line has large hysteresis. This is due to the influence of reactance components such as Cds. The hysteresis in the solid load line is small. This is because, although small hysteresis occurs due to the nonlinearity of Cgs, it is not affected by large reactance components such as Cds. The load line that affects the degradation of the electrical characteristics is the solid load line LC at the end of the drain current source Id. Of the ends of the load line LC, the end with the smallest drain voltage Vds is designated E1, and the end with the largest drain voltage Vds is designated E2. The DC components (DC components of the current and DC components of the voltage) on the load line LC are designated E3. The current DC component corresponds to the DC component obtained when the current at the end of the current source Id with respect to time is Fourier transformed. The voltage DC component corresponds to the DC component obtained when the voltage at both ends of the current source Id with respect to time is Fourier transformed.

[0026] Figure 7 is a schematic diagram showing the drain current Ids-drain voltage Vds characteristics and degradation modes. The thin curve in Figure 7 shows the DC Ids-Vds characteristics when the gate voltage Vgs is changed. Vgs is changed from 1 V to -4 V in 1 V steps. As described in Non-Patent Document 1, there are multiple degradation modes for transistors, and the degradation mode that has the greatest impact varies depending on the values ​​of Vds and Ids. For example, in the case of a GaN HEMT, in the region where Vds is low and Ids is high, the transistor degradation mode is Mode A. Mode A is a mode in which the transistor degrades due to temperature, for example. For example, in the region where Vds is high and Ids is low, the transistor degradation mode is Mode B. Mode B is a mode in which the transistor degrades due to breakdown between the gate and drain, even without current flow, due to a high electric field between the gate and drain. For example, in the region where Vds and Ids are moderate, the transistor degradation mode is Mode C. Mode C is a mode in which the transistor deteriorates when, for example, electrons flowing through the channel become hot electrons and are trapped in traps in the semiconductor layer or insulating layer between the gate and drain.Even if the transistor is not a GaN HEMT, the transistor deteriorates due to different deterioration modes depending on the current and voltage values ​​at the ends of the current source.

[0027] FIG. 8 is a schematic diagram showing drain current Ids-drain voltage Vds characteristics and load lines. As shown in FIG. 8, load lines LCa to LCc are shown. The load lines LCa to LCc can be changed by changing the element values ​​of matching circuits 12 and 14. The Ids-Vds at the first end, second end, and DC component of load line LCa are defined as E1a, E2a, and E3a, respectively. The Ids-Vds at the first end, second end, and DC component of load line LCb are defined as E1b, E2b, and E3b, respectively. The Ids-Vds at the first end, second end, and DC component of load line LCc are defined as E1c, E2c, and E3c, respectively.

[0028] Comparing FIGS. 7 and 8, the degradation mode of the transistor at the first ends E1a to E1c is mainly Mode A. At the second ends E2a to E2c, the degradation mode of the transistor is mainly Mode B. At the DC components E3a to E3c, the degradation mode is mainly Mode C. Therefore, the degradation level in Mode A can be calculated using the current and voltage values ​​at the first ends E1a to E1c. The degradation level in Mode B can be calculated using the current and voltage values ​​at the second ends E2a to E2c. The degradation level in Mode C can be calculated using the current and voltage values ​​at the DC components E3a to E3c. Note that, depending on the degradation mode, when either the current or the voltage contributes to the degradation of the transistor, both the current and the voltage may contribute to the degradation of the transistor. Therefore, in step S16 of FIG. 4, for example, the current and / or voltage value of at least one of the first end E1, the second end E2, and the DC component E3 is calculated.

[0029] [Method of creating data used in step S18] A method for calculating the degradation level for each mode will be described in advance. Figures 9 to 11 are diagrams showing parameters versus time for modes A to C, respectively. In Figures 9 to 11, the horizontal axis represents the stress time during which a predetermined drain current Ids and drain voltage Vds are applied. Note that Ids can be changed by varying Vgs while maintaining the same Vds. The vertical axis represents parameter P, which is degraded by applying a predetermined drain current Ids and drain voltage Vds. Parameter P may be, for example, at least one of threshold voltage Vth, transconductance gm, and drain current Ids. The operating temperature of the transistor is set to one of T1 to T3, and the drain current Ids and drain voltage Vds are set to predetermined values. This applies temperature stress, current stress, and voltage stress to the transistor. Parameter P is measured at room temperature. Parameter P changes with stress time. Parameter P at time 0 (i.e., before applying the predetermined drain current Ids and drain voltage Vds) is defined as P0, and parameter P when the parameter P has changed by a predetermined amount from P0 is defined as P1. When the parameter P reaches P1, it is determined that the transistor has deteriorated. The time it takes for the parameter P to reach P1 varies depending on the temperatures T1 to T3.

[0030] As shown in Figure 9, in mode A, a stress test is performed with drain current Idsa1 and drain voltage Vdsa1 as drain current Ids and drain voltage Vds corresponding to first end E1. Times t1 to t3 are when parameter P becomes P1 at temperatures T1 to T3. A stress test is performed on multiple samples at the same temperature. The average value of time t1 for the multiple samples is the MTTF at temperature T1, the average value of time t2 is the MTTF at temperature T2, and the average value of time t3 is the MTTF at temperature T3.

[0031] As shown in FIG. 10, in Mode B, a stress test is performed with a drain current Idsb1 and a drain voltage Vdsb1, which are the drain current Ids and drain voltage Vds corresponding to the second end E2. Using multiple samples, the MTTF is calculated at temperatures T1 to T3. As shown in FIG. 11, in Mode C, a stress test is performed with a drain current Idsc1 and a drain voltage Vdsc1, which are the drain current Ids and drain voltage Vds corresponding to the DC component E3. Using multiple samples, the MTTF is calculated at temperatures T1 to T3.

[0032] 12 to 14 are Arrhenius plots showing the MTTF versus temperature in modes A to C, respectively. The horizontal axis scale corresponds to the logarithm of the MTTF, and the vertical axis scale corresponds to the reciprocal of the temperature. The dots in FIGS. 12 to 14 represent the temperature versus the MTTF determined in FIGS. 9 to 11. The straight lines are approximations of the dots. As shown in FIG. 12, approximate straight lines T-MTTFa1, T-MTTFa2, and T-MTTFa3 are determined for multiple drain currents and drain voltages (Idsa1, Vdsa1), (Idsa2, Vdsa2), and (Idsa3, Vdsa3) corresponding to the first end E1. As shown in Fig. 13, approximate straight lines T-MTTFb1, T-MTTFb2, and T-MTTFb3 are determined for the multiple drain currents and drain voltages (Idsb1, Vdsb1), (Idsb2, Vdsa2), and (Idsb3, Vdsb3) corresponding to the second end E2. As shown in Fig. 14, approximate straight lines T-MTTFc1, T-MTTFc2, and T-MTTFc3 are determined for the multiple drain currents and drain voltages (Idsc1, Vdsc1), (Idsc2, Vdsc2), and (Idsc3, Vdsc3) corresponding to the DC component E3.

[0033] FIG. 15 is a diagram showing data stored in a computer memory. As shown in FIG. 15, in Mode A, T-MTTF is stored in association with the drain current Idsa and drain voltage Vdsa corresponding to the first end E1. For example, T-MTTFa1, T-MTTFa2, and T-MTTFa3 are stored in association with (Idsa1, Vdsa1), (Idsa2, Vdsa2), and (Idsa3, Vdsa3), respectively. The measured Ids and Vds are the current and voltage between the source S and drain D in the equivalent circuit 32. Therefore, the measured Ids and Vds may be converted to the current and voltage at the end of the drain current source Id and stored in memory. For example, the slope and intercept of the approximation line in FIGS. 12 to 14 are stored as T-MTTF. In Mode B, T-MTTFb is stored in association with the drain current Idsb and drain voltage Vdsb corresponding to the second end E2. For example, T-MTTFb1, T-MTTFb2, and T-MTTFb3 are stored in association with (Idsb1, Vdsb1), (Idsb2, Vdsb2), and (Idsb3, Vdsb3), respectively. In Mode C, T-MTTFc is stored in association with the drain current Idsc and drain voltage Vdsc corresponding to the DC component E3. For example, T-MTTFc1, T-MTTFc2, and T-MTTFc3 are stored in association with (Idsc1, Vdsc1), (Idsc2, Vdsc2), and (Idsc3, Vdsc3), respectively.

[0034] Furthermore, in FETs such as GaN HEMTs, a degradation mode occurs due to the gate current. This degradation mode is referred to as Mode D. The gate current is changed and the MTTF is measured for each operating temperature as in Figures 9 to 11. As in Figures 12 to 14, T-MTTFd is measured for each gate current. In this way, in Mode D, T-MTTFd is stored in association with the gate current Ig. For example, T-MTTFd1 to T-MTTFd3 are stored in association with Ig1 to Ig3, respectively.

[0035] [Example of steps S16 and S18] An example of steps S16 and S18 in FIG. 4 will be described. FIG. 16 is a flowchart illustrating an example of steps S16 and S18. As shown in FIG. 16, steps S30 to S34 correspond to step S16 in FIG. 4, and steps S36 to S40 correspond to step S18 in FIG. 4. Using the equivalent circuit 32 in FIG. 2 and the element values ​​of the matching circuits 12 and 14 set in step S10, the computer 20 calculates a load line LC when the input power Pin used in the amplifier circuit 30 is input (step S30). The ammeter A1 and voltmeters V1 and V2 in FIG. 2 are used to calculate the load line LC. The current monitored by the ammeter A1 is Ids, and the difference in voltage monitored by the voltmeters V2 and V1 is Vds.

[0036] The computer 20 calculates the first end E1, the second end E2, and the DC component E3 of the calculated load line LC (step S32). The computer 20 calculates the gate current Ig (step S34). The gate current Ig is the sum of the currents monitored by the ammeters A2 and A3. The gate current Ig is, for example, the maximum gate current or the average gate current when the input power Pin is applied.

[0037] The computer 20 acquires the operating temperature T0 (step S36). The operating temperature T is the temperature at which the transistor operates. The operating temperature T0 may be input in advance by the user or may be calculated by the computer 20. The computer 20 calculates the degradation level for each of modes A to D based on E1, E2, E3, Ig, and T0 (step S38). For example, when calculating the degradation level for mode A, the computer 20 calculates T-MTTFa corresponding to E1 (Idsa, Vdsa) based on the table for mode A in FIG. 15. For example, when (Idsa, Vdsa)=(Idsa1, Vdsa1), the computer 20 calculates T-MTTFa1 as T-MTTFa. If E1 calculated in step S32 is not included in the table for mode A in FIG. 15, the T-MTTFa may be calculated using interpolation. In addition, the (Ids, Vds) plane is divided into multiple ranges in advance. The computer 20 may calculate T-MTTFa1 as T-MTTFa when (Idsa, Vdsa) is within a predetermined range among a plurality of ranges, and may calculate T-MTTFa2 as T-MTTFa when (Idsa, Vdsa) is within another predetermined range among a plurality of ranges. The computer 20 calculates the MTTFa for mode A based on T-MTTFa and T0. The computer 20 similarly calculates the T-MTTF for modes B to D.

[0038] 17 and 18 are Arrhenius plots showing the MTTF versus temperature for modes A to D. As shown in FIGS. 17 and 18, straight lines of the MTTF versus temperature for modes A to D are shown. In step S38 of FIG. 16, computer 20 calculates the mode among modes A to D that has the worst degree of degradation at operating temperature T0 (step S40). In FIGS. 17 and 18, mode C has the smallest MTTF at operating temperature T0. Therefore, computer 20 calculates the MTTF at operating temperature T0 of mode C as the worst degree of degradation.

[0039] In step S20 of Fig. 4, it is determined whether the MTTF at the operating temperature T0 of mode C satisfies a desired degree of deterioration (for example, t0). In Fig. 17, the MTTF at the operating temperature T0 of mode C is smaller than t0. Therefore, the computer 20 determines No in step S20. In Fig. 18, the MTTF at the operating temperature T0 of mode C is larger than t0. Therefore, the computer 20 determines Yes in step S20.

[0040] In the examples of Figures 15 to 18, the degree of degradation is calculated for modes A to D, but the number of modes may be one or more. In E1 to E3, the T-MTTF is stored in association with Ids and Vds, but there are cases where one of Ids and Vds does not affect degradation. In this case, the T-MTTF may be associated with one of Ids and Vds that affects degradation, and in step S32, only the one of Ids and Vds that affects degradation may be calculated. For example, in mode B, only Ids may be calculated, and in mode C, only Vds may be calculated.

[0041] Although the degree of degradation in Mode D is calculated based on the gate current Ig, there are cases where at least one of the current value and voltage value of diode Dg1 in equivalent circuit 32 affects degradation, and cases where at least one of the current value and voltage value of diode Dg2 affects degradation. The degree of degradation in Mode D can be calculated based on the values ​​that affect degradation.

[0042] If the operating temperature T is already determined, step S36 does not need to be performed. MTTF may be stored in the table of Fig. 15 instead of T-MTTF. While MTTF has been described as the degree of degradation, the degree of degradation may be something other than MTTF, as long as it is an index showing the degree of degradation of the electrical characteristics.

[0043] According to the first embodiment, computer 20 executes a program to calculate the high-frequency characteristics of amplifier circuit 30 based on the element values ​​of matching circuit 14 using equivalent circuit 32 of FET 10 (transistor) in amplifier circuit 30, as shown in step S12 of FIG. 4 . If the calculated high-frequency characteristics of amplifier circuit 30 are the desired characteristics, as shown in step S16, the computer calculates at least one of a current value and a voltage value at a predetermined location in equivalent circuit 32 based on the element values ​​of matching circuit 14 using equivalent circuit 32. As shown in step S18, the computer calculates the degradation level of the electrical characteristics of FET 10 based on the at least one of the current value and the voltage value and data correlating the at least one of the current value and the voltage value with the degradation level of the electrical characteristics of FET 10. This allows the computer to design amplifier circuit 30 taking the degradation level into consideration, since the degradation level of the electrical characteristics of FET 10 is calculated using element values ​​that provide the desired high-frequency characteristics.

[0044] The computer 20 further determines whether the calculated degradation degree is a desired degradation degree, as in step S20. If it is determined in step S20 that the calculated degradation degree is not a desired degradation degree, the computer 20 changes the element values ​​of the matching circuit 14 in step S10, and then executes steps S12, S16, S18, and S30. This allows the computer 20 to design the amplifier circuit 30 taking into account the degradation of the electrical characteristics.

[0045] In step S16, at least one of the current value at the end of the current source Id and the voltage value at both ends of the current source Id is calculated in the equivalent circuit 32. This makes it possible to calculate at least one of the current value and the voltage value without increasing the hysteresis due to the reactance component, as shown in FIG.

[0046] 16, at least two values ​​are calculated: a first value of at least one of the voltage value and the current value at the first end E1 where the voltage value of the load line LC is the smallest in the current-voltage characteristic between the current value at the end of the current source and the voltage value at both ends of the current source in the equivalent circuit 32; a second value of at least one of the voltage value and the current value at the second end E2 where the voltage value of the load line LC is the largest; and a third value of at least one of the DC current component and the DC voltage component at the load line LC. As in step S38, at least two degradation levels of the FET 10 in modes A to C are calculated based on each of at least two values ​​E1 to E3. This allows the degradation levels of at least two of the different degradation modes A to C in E1 to E3 to be calculated.

[0047] 16, the worst degradation degree among the degradation degrees of modes A to C is calculated as the degradation degree of the electrical characteristics of FET 10. In this way, the degradation degree of the electrical characteristics of FET 10 can be calculated from a plurality of modes.

[0048] In step S32, first, second, and third values ​​are calculated for E1, E2, and E3, respectively, and in step S38, the degradation levels of the three modes A to C of FET 10 are calculated based on the first, second, and third values, respectively. This allows the three degradation levels of the different degradation modes A to C for E1 to E3 to be calculated.

[0049] When the transistor is an FET 10 having a gate G connected to the input terminal Tin and a drain D connected to a matching circuit 14, the current source in the equivalent circuit is a drain current source Id. In the FET 10, different degradation modes A to C occur at the first end E1, the second end E2, and the DC component E3 of the load line FC. Therefore, when the transistor is an FET 10, it is preferable to calculate the degradation degrees of modes A to C based on E1 to E3. The transistor may be a transistor other than the FET 10, for example, a bipolar transistor.

[0050] When the FET 10 is a GaN HEMT, different degradation modes A to C occur at E1, E2, and E3 on the load line FC. When the FET 10 is a GaN HEMT, it is preferable to calculate the degradation levels of modes A to C based on E1 to E3. A GaN HEMT is a HEMT that uses a GaN-based semiconductor. In a GaN HEMT, a channel layer such as a GaN layer is stacked on a substrate such as a SiC substrate, and a barrier layer such as an AlGaN layer is stacked on the channel layer. A source electrode, a gate electrode, and a drain electrode are provided on the barrier layer.

[0051] In FET 10, degradation mode D occurs due to the gate current and / or gate voltage. Therefore, in step S34, a fourth value of at least one of the current value at the end of at least one of diodes Dg1 between the gate and source and diode Dg2 between the gate and drain in equivalent circuit 32 and the voltage value at both ends of at least one of the diodes is calculated. In step S38, the degradation degree of FET 10 in mode D is calculated based on the fourth value. This makes it possible to calculate the degradation degree of degradation mode D due to the gate current and / or gate voltage.

[0052] As in step S36, the operating temperature of FET 10 is acquired. In step S38, the degree of degradation of FET 10 is calculated based on data associating E1 to E3, Ig, and T0 with the degree of degradation, based on E1 to E3, Ig, and the operating temperature T0. This makes it possible to calculate the degree of degradation at the operating temperature T0.

[0053] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0054] 10FET 12, 14 matching circuit 20 Computer 22 processors 24 memory 26 Input / Output Devices 28 Internal Bus 30 Amplification circuit 32 Equivalent Circuit

Claims

1. an amplifier circuit including an input terminal for inputting a high frequency signal, a transistor for amplifying the input high frequency signal, an output terminal for outputting the amplified high frequency signal, and a matching circuit connected between the transistor and the output terminal, comprising: a step of calculating high frequency characteristics of the amplifier circuit based on element values ​​of the matching circuit using an equivalent circuit of the transistor; a step of calculating, when the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, at least one of a current value and a voltage value at a predetermined point in the equivalent circuit based on the element values ​​using the equivalent circuit; calculating a degree of degradation of the electrical characteristics of the transistor based on the at least one value and using data associating the at least one value with a degree of degradation of the electrical characteristics of the transistor; the step of calculating at least one value includes a step of calculating at least two values ​​from among a first value of at least one of a voltage value and a current value at a first end where a voltage value of a load line is minimum in a current-voltage characteristic of a current value at an end of a current source in the equivalent circuit and a voltage value at both ends of the current source, a second value of at least one of a voltage value and a current value at a second end where a voltage value of the load line is maximum, and a third value of at least one of a DC current component and a DC voltage component on the load line, a calculation program, wherein the step of calculating the degradation degree includes a step of calculating degradation degrees of at least two electrical characteristics of the transistor based on the at least two values, respectively;

2. causing a computer to execute a step of determining whether the calculated deterioration degree is a desired deterioration degree; 2. The calculation program according to claim 1, which causes a computer to execute the steps of: when it is determined that the calculated degree of degradation is not the desired degree of degradation, changing the element value and calculating the high-frequency characteristics based on the changed element value; calculating at least one of the values; calculating the degree of degradation; and determining whether the degree of degradation is the desired degree of degradation.

3. 3. The calculation program according to claim 1, wherein the step of calculating at least one of the values ​​includes a step of calculating at least one of a current value at an end of a current source in the equivalent circuit and a voltage value at both ends of the current source as the at least one of the values.

4. 2. The calculation program according to claim 1, wherein the step of calculating the degradation degree includes a step of calculating the worst degradation degree of the two electrical characteristics as the degradation degree of the electrical characteristics of the transistor.

5. the step of calculating at least one value includes the steps of calculating the first value, the second value, and the third value; 5. The calculation program according to claim 1, wherein the step of calculating the degree of deterioration includes a step of calculating the degree of deterioration of three electrical characteristics of the transistor based on the first value, the second value, and the third value, respectively.

6. the transistor is an FET having a gate connected to the input terminal and a drain connected to the matching circuit, The calculation program according to claim 1 , wherein the current source is a drain current source in the FET.

7. the step of calculating the at least one value includes a step of calculating a fourth value of at least one of a current value at an end of at least one of a diode between the gate and the source and a diode between the gate and the drain in the equivalent circuit and a voltage value across both ends of the at least one of the diodes; 7. The calculation program according to claim 6, wherein the step of calculating the degradation degree includes a step of calculating a degradation degree of the electrical characteristics of the FET based on the fourth value.

8. obtaining an operating temperature of the transistor; 8. The calculation program according to claim 1, wherein the step of calculating the degree of degradation of the electrical characteristics of the transistor includes a step of calculating the degree of degradation of the electrical characteristics of the transistor based on the at least one value and the operating temperature using data correlating the at least one value, the operating temperature, and the degree of degradation of the electrical characteristics of the transistor.

9. an amplifier circuit including an input terminal for inputting a high frequency signal, a transistor for amplifying the input high frequency signal, an output terminal for outputting the amplified high frequency signal, and a matching circuit connected between the transistor and the output terminal, comprising: a step of calculating high frequency characteristics of the amplifier circuit based on element values ​​of the matching circuit using an equivalent circuit of the transistor; a step of calculating, when the calculated high-frequency characteristics of the amplifier circuit are desired characteristics, at least one of a current value and a voltage value at a predetermined point in the equivalent circuit based on the element values ​​using the equivalent circuit; calculating a degree of degradation of the electrical characteristics of the transistor based on the at least one value and using data correlating the at least one value with a degree of degradation of the electrical characteristics of the transistor; Including, the step of calculating at least one value includes a step of calculating at least two values ​​from among a first value of at least one of a voltage value and a current value at a first end where a voltage value of a load line is minimum in a current-voltage characteristic of a current value at an end of a current source in the equivalent circuit and a voltage value at both ends of the current source, a second value of at least one of a voltage value and a current value at a second end where a voltage value of the load line is maximum, and a third value of at least one of a DC current component and a DC voltage component on the load line, the step of calculating the degree of deterioration includes a step of calculating degrees of deterioration of at least two electrical characteristics of the transistor based on the at least two values, respectively; A computational method implemented on a computer.

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