Voltage Regulator Circuit

Abstract

To provide a current-voltage conversion circuit which has good linearity of conversion characteristics and allows for reduction in footprint and power consumption.SOLUTION: A current-voltage conversion circuit 1 comprises a first current mirror circuit 21, a load resistance 31, and a pull-up circuit constituted of a second current mirror circuit 22 and a pull-up resistance 32, and an output of the first current mirror circuit 21 is connected to a reference potential via the load resistance 31 and is connected to an output of the second current mirror circuit 22 via the pull-up resistance 32. In the current-voltage conversion circuit 1, a variable current Iv is inputted to the first current mirror circuit 21, and a voltage Vout has the magnitude varied via the pull-up resistance 32 in accordance with the current Iv and is outputted. Further, a reference current IRef is inputted to the second current mirror circuit 22, and thereby the output voltage Vout is shifted toward a supply voltage VDD.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a current-voltage conversion circuit. The road The present invention relates to a voltage regulation circuit. [Background technology]

[0002] Terahertz wireless communication technology, which enables broadband and high-speed communication, is expected to be put to practical use for the efficient use of radio wave resources. Communication systems typically include multiple antennas and RF front-ends connected to each antenna. Low-cost CMOS integrated circuits (CMOS) are a promising choice for these RF front-ends. High-precision control of the radio waves is required for low-power terahertz wireless communication, which requires highly accurate adjustment of the voltages of the component circuits within the numerous CMOS integrated circuits connected to the antennas. However, the large variations in the characteristics of MOSFETs (metal-oxide semiconductor field-effect transistors) in CMOS integrated circuits make it difficult to achieve the high-precision output voltage adjustment required for terahertz operation. Furthermore, because the voltage adjustment circuits have to adjust a large number of voltages, they must be small in area and consume low power. Furthermore, miniaturization requires keeping the power supply voltage low.

[0003] As an example, as shown in FIG. 11, a voltage regulation circuit 110 generates an analog current I v a D / A converter incorporating a variable current source 104 that outputs a current I v The voltage V corresponding to that magnitude out The D / A converter is a current-to-voltage converter 101 that converts the analog current I v This is preferable because the increase and decrease in the voltage is stable (for example, Non-Patent Documents 1 and 2). nThe BT decoder 143 is configured by connecting (2-1) unit current sources 141 in parallel and outputs a signal to switch ON / OFF the switching element 142 provided for each unit current source 141. The BT decoder 143 converts binary-coded digital signals B1, B2, ..., Bn into thermometer-coded digital signals T1, T2, ..., T(2 n The current-voltage conversion circuit 101 includes a pair of current mirror circuits 121 each having two transistors and a load resistor 131 connected to the output of the current mirror circuit 121 (see, for example, Patent Document 1). v Input the voltage V out Output.

[0004] Such a current-voltage conversion circuit 101 converts a voltage V out As the supply voltage V DD As the output voltage approaches , the linearity of the conversion characteristics decreases, and the maximum output voltage V out_MAX ( <V DD ) and the power supply voltage V DD By increasing the operating range, the power supply voltage V DD For low voltage, the linearity is good, or the number of gradations is 2. n However, the power supply voltage V DD On the other hand, the variable current source 104 of the thermometer code type D / A converter has a gradation number of 2. n Therefore, in order to improve the linearity of the conversion characteristics, a current-voltage conversion circuit has been proposed that uses a cascode current mirror having two stages of transistors or a circuit that includes an OP-AMP (for example, Non-Patent Document 3 and Patent Document 2). Also, a circuit that converts the voltage level using an OP-AMP has been proposed (for example, Patent Document 3). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-5272 [Patent Document 2] Japanese Patent Application Laid-Open No. 2000-114891 [Patent Document 3] Patent No. 5997620 [Non-patent literature]

[0006] [Non-Patent Document 1] Tyler Moody, Saiyu Ren, Robert Ewing, "10 bit current steering DAC in 90 nm technology", NAECON 2014 - IEEE National Aerospace and Electronics Conference, 2014, pp. 337-341 [Non-patent document 2] Kyaw Kyaw, Randall L. Geiger, “Multi-dimensional Approach to High Resolution and High Speed ​​Binary-to-Thermometer Decoding”, The 16th International Conference on Microelectronics, 2004, pp. 509-512 [Non-patent document 3] B. Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill, pp. 135-143, 2001 Summary of the Invention [Problem to be solved by the invention]

[0007] A current-to-voltage conversion circuit using a cascode current mirror or an OP-AMP improves the linearity of the conversion characteristics, but the power supply voltage V DDFurthermore, circuits with OP-AMPs consume more power and require a larger area for the anti-oscillation capacitors.

[0008] The present invention has been made in view of the above problems, and provides a current-voltage conversion circuit that has good linearity in conversion characteristics, and that can be reduced in area and power consumption. The road Prepared 、 An object of the present invention is to provide a highly accurate voltage adjustment circuit. [Means for solving the problem]

[0009] The inventors of the present invention have come up with the idea of ​​adding a resistor and a current mirror as a pull-up circuit to a current-voltage conversion circuit that includes a current mirror and a load resistor. The voltage adjustment circuit includes a current-voltage conversion circuit, and a first current source and a second current source that input a current to the current-voltage conversion circuit, the first current source inputting a current and the current-voltage conversion circuit outputting a voltage. the current-voltage conversion circuit includes a first current mirror circuit, a first resistor, a second current mirror circuit, and a second resistor; outputting the voltage via the second resistor; The output of the first current mirror circuit is connected to a reference potential via the first resistor, and is also connected to the output of the second current mirror circuit via the second resistor. , the first current source is A current is supplied to the first current mirror circuit. of input It is a variable current source that , the second The current source is a constant current source or a variable current source that inputs a current to the second current mirror circuit. do.

[0010] The voltage regulation circuit according to the present invention Furthermore, the first current source is a thermometer code type Variable Current At the source be. Alternatively, in another voltage adjustment circuit according to the present invention, the first current source receives a digital signal to change the magnitude of the current, and the second current source receives a digital signal to switch between outputting and not outputting current or change the magnitude of the current so as to correspond to each of two or more voltage ranges obtained by dividing the output range of the voltage. [Effects of the Invention]

[0011] According to the present invention, a current-voltage conversion circuit with good linearity and small area and low power consumption is provided. Equipped with A highly accurate voltage regulation circuit can be obtained. [Brief explanation of the drawings]

[0012] [Figure 1]1 is a circuit diagram illustrating the structure of a voltage adjustment circuit including a current-voltage conversion circuit according to a first embodiment of the present invention. [Figure 2] 1 is a circuit diagram illustrating the structure of a D / A converter of a voltage adjustment circuit according to an embodiment of the present invention. [Figure 3] 10A and 10B are diagrams illustrating the conversion characteristics of a conventional current-voltage conversion circuit. [Figure 4] 2A and 2B are diagrams illustrating the conversion characteristics of the current-voltage conversion circuit according to the first embodiment of the present invention. [Figure 5] FIG. 3 is a circuit diagram illustrating the structure of a voltage adjustment circuit according to a first modified example of the first embodiment of the present invention. [Figure 6] FIG. 4 is a circuit diagram illustrating the structure of a voltage adjustment circuit according to a second modified example of the first embodiment of the present invention. [Figure 7] FIG. 4 is a circuit diagram illustrating the structure of a voltage adjustment circuit according to a second embodiment of the present invention. [Figure 8] FIG. 10 is a circuit diagram illustrating the structure of a voltage adjustment circuit according to a modified example of the second embodiment of the present invention. [Figure 9] 4 is a graph showing a current-voltage conversion characteristic obtained by simulation of the voltage adjustment circuit according to the first embodiment of the present invention. [Figure 10] 10 is a graph showing a current-voltage conversion characteristic obtained by simulation of a voltage adjustment circuit according to a second embodiment of the present invention. [Figure 11] FIG. 1 is a circuit diagram illustrating the structure of a conventional voltage regulator circuit. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention will be described in detail below with reference to the accompanying drawings, in which like reference numerals are used to designate elements having the same or similar structure, and the description thereof will be omitted where appropriate.

[0014] [Voltage adjustment circuit] As shown in Fig. 1, a voltage adjustment circuit 10 according to an embodiment of the present invention includes a current-voltage conversion circuit 1, a D / A converter 40 (see Fig. 2) incorporating a variable current source 4, and a constant current source 5. The current-voltage conversion circuit 1 includes a first current mirror circuit (first current mirror circuit) 21, a load resistor (first resistor) 31, a second current mirror circuit (second current mirror circuit) 22, and a pull-up resistor (second resistor) 32, and the output of the first current mirror circuit 21 is connected to a reference potential via the load resistor 31, and is also connected to the output of the second current mirror circuit 22 via the pull-up resistor 32. The variable current source 4 supplies a current I v is input, and the constant current source 5 outputs a current I Ref The voltage adjustment circuit 10 adjusts V0 (=0V), V1, V2, ..., Vn based on n-bit digital signals B1, B2, ..., Bn. N-1 2 n Gradation voltage V out Output (N=2 n The voltage adjustment circuit 10 is applied to, for example, an RF front end connected to an antenna for terahertz band wireless communication, and therefore, although it depends on the specifications, for example, the maximum output voltage V N-1 =0.9 to 3.3V, and the number of gradations is designed to be about 64 to 1024 (6 to 10 bits). Each element will be explained in detail below.

[0015] [First embodiment] (Current-voltage conversion circuit) The current-voltage conversion circuit 1 according to the first embodiment of the present invention converts the current I v The first current mirror circuit 21 receives the input of the reference voltage V and has its output connected to a reference potential via a load resistor 31. The current-voltage conversion circuit 1 further includes a second current mirror circuit 22 and a pull-up resistor 32 connected to its output as a pull-up circuit. outIn other words, in the current-voltage conversion circuit 1, the output of the first current mirror circuit 21 is branched into two, a load resistor 31 is connected between one of the branches and a reference potential, and a pull-up resistor 32 is connected between the other branch and the output of the second current mirror circuit 22. In the current-voltage conversion circuit 1, the first current mirror circuit 21 outputs a current I v is input to the second current mirror circuit 22, and a current I Ref When is selectively input, the current I v and the magnitude of the current I Ref The magnitude of the voltage V is based on the presence or absence of input out Output.

[0016] The first current mirror circuit 21 is a transistor pair consisting of two transistors M1 and M2 with their gates connected in common, and has a basic structure in which the transistor M1 on the input side (mirror source) is diode-connected. The second current mirror circuit 22 has a structure similar to that of the first current mirror circuit 21. The transistors are preferably MOSFETs (metal-oxide semiconductor field-effect transistors), and a voltage V out In order to set the minimum value of V to 0V (reference potential), a PMOS transistor is used. The four transistors M1, M2, M3, and M4 in the current mirror circuits 21 and 22 are connected to the same power supply voltage V DD There are no particular restrictions on the size (gate length, gate width) of the current-voltage converter circuit 1 as long as it operates at a power supply voltage V and can be manufactured on the same substrate. The dimensions (gate length, gate width) are designed to obtain the desired characteristics for the current-voltage converter circuit 1. Generally, in a current mirror circuit, the gate lengths of the transistor pair are set to be the same and the gate width is adjusted to accurately obtain the input and output current ratio. DD is the maximum output voltage V of the current-voltage conversion circuit 1 N-1 Designed based on, for example, V N-1 = 3.0V, then V DD =3.3 to 3.6 V is applied. Similarly, it is preferable that the load resistor 31 and the pull-up resistor 32 also have a structure that can be manufactured on the same substrate as the current mirror circuits 21 and 22, and the resistance values ​​of each are designed so as to obtain desired characteristics.

[0017] (D / A converter) The D / A converter 40 converts the current I v The D / A converter 40 is preferably a thermometer code type (see Non-Patent Documents 1 and 2). As an example, as shown in FIG. 2, m sets (2 n-1 -1≦m<2 n -1) The variable current source 4 is configured by connecting in parallel. The switching element 42 is assumed to be turned OFF (shut off) when a signal '0' is input, and turned ON (conducting) when a signal '1' is input. With this configuration, the variable current source 4 outputs I0 (=0 A), I1, I2, ..., I m Analog current I of (m+1) gradation v In addition, the current output from one unit current source 41 is (I m / m). The D / A converter 40 further includes a BT (Binary to Thermometer) decoder 43, which converts the binary-coded digital signals B1, B2, ..., Bn into thermometer-coded digital signals T1, T2, ..., Tm and digital signal Tk'. The signals T1, T2, ..., Tm switch the ON / OFF states of the switching elements 42 of the variable current source 4. The signal Tk' switches the ON / OFF state of the constant current source 5 (described later). As described above, the D / A converter 40 employs the thermometer-code system, and while it has a relatively large number of elements, it has good differential nonlinearity (DNL). Even if there are variations in the characteristics of the unit current sources 41, it can obtain a monotonically changing output in response to switching of the digital signals B1, B2, ..., Bn, making it suitable for CMOS. The number m of unit current sources 41 will be explained later in the section on driving a voltage adjustment circuit.

[0018] (constant current source) The constant current source 5 outputs a constant current (reference current) I RefTo this end, the constant current source 5 includes a current source 51 and a switching element 52 that can be switched ON / OFF by a signal Tk' output by the BT decoder 43. The switching element 52, like the switching element 42 of the variable current source 4, is turned OFF (blocked) when a signal '0' is input, and turned ON (conducting) when a signal '1' is input. The reference current I Ref is set to a certain level so as not to be affected by the off-leak current, noise, characteristic variations, etc. of the transistors of the second current mirror circuit 22. Ref On the other hand, as will be described later, it is preferable to size the two transistors of the second current mirror circuit 22 so that they operate in the saturation region.

[0019] (Conversion characteristics of current-voltage conversion circuit) The conversion characteristics of the current-voltage conversion circuit according to this embodiment will be described. First, a conventional current-voltage conversion circuit 101 having a simple configuration shown in FIG. 11 will be described as an example. The drain current (output current of the current mirror circuit 121) of the transistor M2 on the output side (mirrored destination, right side in FIG. 11) of the current mirror circuit 121 is expressed as I Mir The resistance value (load resistance) of the load resistor 131 is expressed as R L The output voltage V of the current-voltage conversion circuit 101 is expressed as out is expressed by the following equation (1): Ideally, the current mirror circuit 121 is configured such that the drain current I Mir is the drain current of the transistor M1 on the input side (mirror source, left side in Figure 11), v Since it is proportional to (I Mir =α1I v , α1: constant), the ideal output voltage V out_ideal is V out_ideal =α1R L I v As shown by the dashed line in Figure 3, the input current I v However, in reality, as shown by the solid line, the input current I v As the output voltage V out (α1R L I v) becomes smaller, the difference gradually widens, and linearity decreases. V out =R L I Mir ···(1)

[0020] Here, for the PMOS transistor M1 on the input side of the current mirror circuit 121, L1 is the gate length, W1 is the gate width, and λ1 is the channel length modulation coefficient, and for the PMOS transistor M2 on the output side, L2 is the gate length, W2 is the gate width, and λ2 is the channel length modulation coefficient. The common threshold voltage of the transistors M1 and M2 is V th , the gate-source voltage is V GS The source-drain voltage of the output transistor M2 is expressed as V DS Then, the input side transistor M1, due to the diode connection, has a source-drain voltage that is equal to the gate-source voltage V GS Since this is the same as the saturated region, the relationship of the following equation (2) holds. Note that μ is the carrier mobility, C OX : Gate oxide film capacitance per unit area. On the other hand, for the output transistor M2, the source-drain voltage V DS does not necessarily match the input transistor, so the source-drain voltage V DS and pinch-off voltage (effective gate voltage) (V GS -V th ) changes, resulting in a saturated region shown in the following equation (3) and a non-saturated region (linear region) shown in the following equation (4). DS |=V DD -V out Therefore, V out <V DD -(V GS -V th ) in the saturated region, V out >V DD -(V GS -V th ) is the non-saturated region.

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[0021] The output voltage V out becomes smaller (V out <V DD -(V GS -V th )) such that the input current I v In this case, from equations (2) and (3), the output current I Mir is expressed by the following equation (5). Furthermore, ideally, it is assumed here that the channel length modulation effect is sufficiently small (λ1 ≒ 0, λ2 ≒ 0). Then, as expressed by the following equation (6), the output current I Mir is the input current I v In addition, the constant α1 is expressed by the following equation (7). From equations (6) and (7), I Mir ≒α1I v Therefore, V out ≒V out_ideal =α1R L I v However, in reality, due to the channel length modulation effect of transistors M1 and M2, the source-drain voltages (V GS ,V DS ) and the output current I Mir is the input current I v Not proportional to (I Mir <α1I v ), the current-voltage conversion characteristics are not completely linear.

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[0022] Input current I v increases, and the output voltage V out (V out >V DD -(V GS -V th )), then, from equation (4), the output current I Mir However, the source-drain voltage V DS It also depends on (α1I v ) becomes smaller than the input current I v As the pinch-off voltage (V GS -V th) also increases, but from equation (1), the pinch-off voltage (V GS -V th ) is √I v Since it increases almost proportionally to the input current I v As the output current I Mir The increase in V gradually slows down and eventually reaches a plateau. As a result, the output voltage V out is the ideal value V out_ideal (=α1R L I v ) and the voltage V out_MAX ( <V DD ) and reaches a ceiling at this output voltage limit, V out_MAX is called the limit output voltage. out is the limit value V out_MAX When it approaches this range, the linearity deteriorates significantly and the input current I v In addition, the output transistor M2 has a source-drain voltage V DS is the pinch-off voltage (V GS -V th ), when the ON resistance is sufficiently small compared to (1 / β2|V GS -V th |), it is expressed by the following equation (8). β2 is the gain coefficient of the output transistor M2 (β2 = (W2 / L2)μC OX ) From the following equation (8) and equation (2), the power supply voltage V DD and the output voltage V out Difference with |V DS | is the output voltage V out is the limit value V out_MAX As it approaches, it is expressed by the following equation (9).

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[0023] In contrast to this, the current-voltage conversion circuit 1 according to this embodiment operates as follows. Note that the drain current of the output-side transistor M2 of the first current mirror circuit 21 (the output current of the first current mirror circuit 21) is I Mir, the drain current of the output side transistor M4 of the second current mirror circuit 22 (the output current of the second current mirror circuit 22, the pull-up current) is I p , the resistance value (load resistance) of the load resistor 31 is R L , the resistance value of pull-up resistor 32 (pull-up resistor) is R p The output voltage V of the current-voltage conversion circuit 1 is out is expressed by the following equation (10): At this time, the input current (reference current) I of the second current mirror circuit 22 by the constant current source 5 is set to 0 so that the output side transistor M4 of the second current mirror circuit 22 is in the saturated region. Ref It is preferable to set I p ≒α2I Ref Therefore, the following equation (10) can be replaced with the following equation (11). The constant α2 is expressed by the following equation (12). The input side transistor M3 of the second current mirror circuit 22 is expressed as L3: gate length, W3: gate width, and the output side transistor M4 is expressed as L4: gate length, W4: gate width. Then, when the switching element 52 of the constant current source 5 is turned OFF (I Ref = 0A, hereafter referred to as pull-up circuit OFF) to ON (pull-up circuit ON), the output voltage V out But ((R L +R p )I p ) increases, and the power supply voltage V DD In Figure 4, the conversion characteristics with the pull-up circuit OFF are shown by a black solid line, and the conversion characteristics with the pull-up circuit ON are shown by a gray solid line.

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[0024] In this way, the current-voltage conversion circuit 1 changes the output voltage V out can be shifted as shown by the white arrow in Figure 4, and when the pull-up circuit is OFF, it outputs a low voltage range, and when it is ON, it outputs a high voltage range. out =V0(=0V)~V out_MAX´, when the pull-up circuit is ON, V out =(R L +R p )I p ~V out_MAX When the pull-up circuit is OFF, the following equation (13) is satisfied, so if the first current mirror circuit 21 and the load resistor 31 have the same structure as the current-voltage conversion circuit 101, the same output voltage V out Therefore, the limit output voltage V out_MAX ´ is expressed by equation (9). V out =R L I Mir (I Ref =0A) (13)

[0025] On the other hand, when the pull-up circuit is ON, the limit output voltage V out_MAX The common threshold voltage of the transistors M3 and M4 of the second current mirror circuit 22 is V th , the gate-source voltage is V GS2 The source-drain voltage of the output transistor M4 is expressed as V DS2 For the input transistor M3, the gain coefficient is β3 (= (W3 / L3)μC OX ) and assuming that the channel length modulation effect is sufficiently small, the following equation (14) holds: out_MAX When outputting |V DS2 | is the minimum value. As mentioned above, the reference current I Ref When you enter V DS2 ≒V GS2 Therefore, the following equation (15) is established from the following equation (14). When the following equation (15) is compared with the equation (9) for the conventional current-voltage conversion circuit 101, the reference current I Ref is the limit output voltage of the current-voltage conversion circuit 101, that is, the limit output voltage V when the pull-up circuit is OFF. out_MAX When the output current I Mir (=V out_MAX ´ / R L ), then |V DS2of the output side transistor M2 of the current mirror circuit 121 of the current-voltage conversion circuit 101. DS As a result, the limit output voltage V out_MAX supply voltage V DD can be approached.

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[0026] Reference current I Ref may be large enough to place the output transistor M4 of the second current mirror circuit 22 in a non-saturated region. DS2 <V GS2 -V th Therefore, the following equation (16) holds. Therefore, the reference current I Ref By making this sufficiently small, the limit output voltage V out_MAX supply voltage V DD In addition, the pull-up current I p is the reference current I Ref becomes smaller than α2 times (I p <α2I Ref ).

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[0027] The current-voltage conversion circuit 1 has an output voltage V out is the limit value V out_MAX ´,V out_MAX As the value approaches the limit value V out_MAX ´,V out_MAX In the vicinity, the input current I v Therefore, the output voltage V out The maximum value V for use in the low voltage range and high voltage range j ,V N-1is set to a range where the degree of degradation in linearity is within an acceptable range. In other words, the current-voltage conversion circuit 1 out The maximum value V N-1 As mentioned above, the limit output voltage V out_MAX is larger than before, so the power supply voltage V DD The current-voltage conversion circuit 1 can output a voltage with good linearity over a wide range, including voltages closer to V. out The output voltage V out The maximum value V j However, the output voltage V out The minimum value of ((R L +R p )I p ) or more, and it is preferable to provide an additional margin. Figure 4 shows the voltage adjustment range when the pull-up circuit is ON and OFF, and the current I v The input range is indicated by a double arrow.

[0028] (Voltage regulation circuit driving method) A method for driving the voltage regulator circuit according to this embodiment will be described with reference to FIG. 4 and, where appropriate, FIG. 1 and FIG. 2. The voltage regulator circuit 10 adjusts the voltage from V0 (=0 V) to V N-1 (≦V out_MAX ) up to 2 n The voltage of the gradation is output, and ideally (V N-1 / (2 n -1)) stepwise change of output voltage V out Switch.

[0029] As described above, the current-voltage conversion circuit 1 controls the output voltage V out The voltage is shifted to two stages: high voltage and low voltage. j range, and the high voltage range is V k ~V N-1 Set the range of (1≦j≦2 n -2, 1≦k≦j+1, N=2 n ,0V <Vj ≦V out_MAX ´,(R L +R p )I p ≦V k <V N-1 ≦V out_MAX ) and in the low voltage range, V out =V0 (=0V) Input current I v I0(=0A), V out =V j The input current I v I j (I0 j ≦I m On the other hand, in the high voltage range, V out =V k The input current I v I d , V out =V N-1 The input current I v I e (I0≦I d e ≦I m ) where N-1-k=ed, and therefore d=k+e-N+1. Furthermore, the current I j ,I e The larger of these is the maximum current I output by variable current source 4. m In Figure 4, I j e Therefore, I e =I m Let's say.

[0030] As a result, the voltage adjustment circuit 10 adjusts the voltage V i In order to output the i-th gradation, the switching element 52 is turned off and the variable current source 4 outputs the current I i Therefore, the BT decoder 43 sets the signal Tk' to '0' and outputs it to the constant current source 5, and sets the first i-th signals T1, T2, ..., Tm to '1' and the (i+1)th and subsequent signals to '0' and outputs them to the variable current source 4. On the other hand, the voltage V of the i-th gradation (k≦i≦N−1) in the high voltage range i ​​​To output, turn on the switching element 52, and set the variable current source 4 to output the current I at the (i-(k-d))-th gradation. i-k+d Turn on (i-(k-d))(=i-(N-1-e)) switching elements 42 so as to output the current I at the (i-(k-d))-th gradation. Therefore, the BT decoder 43 outputs the signal Tk´ as '1' to the constant current source 5, and outputs signals T1, T2, …, Tm to the variable current source 4, where the first (i-(k-d)) signals are set to '1' and the signals after the (i-(k-d)+1)-th are set to '0'. For simplicity of explanation, assuming the number of gradations is 16 (n = 4), j = 7, k = 8, and d = 2, Table 1 shows the binary code digital signals B1, B2, B3, B4, the thermometric code digital signals T1, T2, …, T9, and the signal T8´ input to the switching element 52.

[0031] <00…0601>

Table 1

[0032] The low voltage range and the high voltage range preferably have a closer ratio to the output voltage V out range and the input current I v range, and ideally they are the same, that is, (V j -V0) / (I j -I0)=(V N-1 -V k ) / (I e -I d ) is satisfied. Also, (I d -I0)(=I d ) and (I e -I j ) are preferably closer to integer multiples of (I m / m), and ideally they are equal to integer multiples of (I m / m). With such a configuration, the voltage adjustment circuit 10 can linearly change the output voltage V out in steps of (V N-1 / (2 n -1)). Note that the output voltage V outThe width of the ranges is not particularly specified, and they may be equally distributed, or one may be set to a wider range than the other. For the sake of simplicity, in FIG. 4, k=j+1 is used as the output voltage V used in the low voltage range and the high voltage range. out do not overlap, and the voltage adjustment range is divided into two equal parts, low voltage and high voltage. k-1 -V0=V m -V k , so k=2 n-1 Furthermore, (V j -V0) / (I j -I0)=(V N-1 -V k ) / (I m -I d ) I j -I0=I m -I d , i.e. I k-1 =I m -I d Let's say.

[0033] The voltage regulator circuit 10 has an output voltage V that overlaps the low and high voltage ranges. out The narrower the range of (I d -I0)(=I d ) and |I e -I j The smaller | is, the smaller the current I output by the variable current source 4 v The number of gradations (m+1) is the output voltage V out Number of gradations: 2 n , the output voltage V out does not overlap (k=j+1), I d =I0(=0A) and I e =I j =I m , that is, the output voltage V out If the range of is evenly distributed, m is the minimum value (2 n-1 -1). In this case, k=2 n-1 Therefore, the switching element 52 can be switched ON / OFF directly by the digital signal B(n-1).

[0034] (Variation) The voltage regulation circuit 10 is n Gradation output voltage V0, V1, V2, …, V N-1 For all, the current per gray level I v Specifically, in the high voltage range, especially the limit output voltage V where linearity becomes low, out_MAX In the vicinity, one gradation is represented by the current I v With this configuration, the power supply voltage V DD It is possible to output with good linearity up to a value closer to

[0035] The voltage regulator circuit 10 uses a reference current I instead of the constant current source 5. Ref A variable current source (not shown) may be provided that outputs the reference current I by switching the magnitude of the reference current I in two or more steps. Ref The variable current source that outputs the pull-up current I is configured by connecting two or more sets of current sources 51 with switching elements 52 in parallel, similar to the variable current source 4. However, the output current of each current source 51 does not have to be the same, and the pull-up current I output by the second current mirror circuit 22 p The reference current I with the desired magnitude Ref The reference current I Ref By switching the magnitude of V in two steps, for example, out I Ref With this configuration, the current I can be shifted to three levels (low voltage, medium voltage, and high voltage), including 0A. v The number of gradations (m+1) is expressed as the output voltage V out Number of gradations: 2 n can be made smaller.

[0036] In the current-voltage conversion circuit according to the above embodiment, even if the current input to each of the first and second current mirror circuits is 0 A, a minute current may be output because the transistor on the input side is diode-connected, and the output voltage may not reach 0 V (reference potential). To address this, a transistor is inserted as a switching element in the current mirror circuit. A current-voltage conversion circuit according to a modification of the first embodiment of the present invention will now be described with reference to FIGS. 5 and 6.

[0037] 5, a current-voltage conversion circuit 1A according to a first modification of the first embodiment of the present invention includes a first current mirror circuit (first current mirror circuit) 21A, a load resistor (first resistor) 31, a current mirror circuit (second current mirror circuit) 22A, and a pull-up resistor (second resistor) 32, and the output of the first current mirror circuit 21A is connected to a reference potential via the load resistor 31, and is also connected to the output of the second current mirror circuit 22A via the pull-up resistor 32. Furthermore, a voltage adjustment circuit 10A including the current-voltage conversion circuit 1A supplies a current I v and a second current mirror circuit 22A that supplies a reference current I Ref The inverter further includes a constant current source 5 to which the

[0038] The first current mirror circuit 21A is configured by connecting two transistor pairs in series, each consisting of two transistors with their gates connected in common. The transistor M1 on the source side (upper input) is diode-connected, and an external signal T0B is input to the gates of the transistor pair M7 and M8 on the drain side (lower input). The second current mirror circuit 22A has the same configuration as the first current mirror circuit 21A, and an external signal T0B is input to the gates of the transistor pair M9 and M10 on the drain side. In other words, the current-voltage conversion circuit 1A is configured by adding transistors M7, M8, M9, and M10 as switching elements to the drain sides of the transistors M1, M2, M3, and M4 of the current mirror circuits 21 and 22, each consisting of a single transistor pair. The transistors M7, M8, M9, and M10 are preferably designed to be in a non-saturated region when ON (conducting), thereby ensuring a sufficiently small source-drain voltage.

[0039] The signal T0B input to the current mirror circuits 21A and 22A is V out When outputting 0V, the power supply voltage V DD is input to turn the transistors M7, M8, M9, and M10 OFF (shut off). At other times, 0V is input to the signal T0B to turn the transistors M7, M8, M9, and M10 ON (conducting). The signal T0B can be configured to be output from the BT decoder 43 in the same way as the signal Tk'. The current-voltage conversion circuit 1A according to this modification satisfies the condition T0B=V DD When , the only current that flows is the off-leak current, which is essentially zero, and V out =0 V. At this time, the signals T1, T2, ..., Tm and the signal Tk' do not have to be '0'.

[0040] In the current-voltage conversion circuit 1A according to this modification, the second current mirror circuit 22A is configured by connecting transistors in series in two stages, and therefore the output voltage V out Power supply voltage V DD The voltage drop is large compared to the limit value Vout_MAX Therefore, in order to suppress the voltage drop, the source-drain voltage of the transistors M9 and M10 is designed to be sufficiently small as described above, and the reference current I Ref It is preferable to set it small.

[0041] It is also possible to employ a configuration in which the transistor serving as the switching element is not connected in series with the transistor of the current mirror circuit. As shown in Fig. 6, a current-voltage conversion circuit 1B according to a second modification of the first embodiment of the present invention includes a first current mirror circuit (first current mirror circuit) 21B, a load resistor (first resistor) 31, a current mirror circuit (second current mirror circuit) 22B, and a pull-up resistor (second resistor) 32, and the output of the first current mirror circuit 21B is connected to a reference potential via the load resistor 31, and is also connected to the output of the second current mirror circuit 22B via the pull-up resistor 32. In addition, a voltage adjustment circuit 10B including the current-voltage conversion circuit 1B supplies a current I v and a second current mirror circuit 22A that supplies a reference current I Ref The inverter further includes a constant current source 5 to which the

[0042] The first current mirror circuit 21B is configured by connecting a transistor M7 in parallel to the transistor M1 on the input side of the current mirror circuit 21 of the current-voltage conversion circuit 1 (see FIG. 1) according to the embodiment, and has a structure in which an external signal T0 is input to the gate of the transistor M7. The second current mirror circuit 22B has the same structure as the first current mirror circuit 21B, and an external signal T0 is input to the gate of a transistor M9 connected in parallel to the transistor M3 on the input side of the current mirror circuit 22. The transistors M7 and M9 are preferably designed to be in a non-saturated region in the ON (conducting) state, and to have a sufficiently small source-drain voltage.

[0043] The signal T0 input to the current mirror circuits 21B and 22B is V outWhen outputting 0V, 0V is input to turn on transistors M7 and M9. Otherwise, the signal T0 is equal to the power supply voltage V DD is input to turn off the transistors M7 and M9. The signal T0 can be configured to be output from the BT decoder 43 in the same way as the signal Tk'. The current-voltage conversion circuit 1B according to this modification satisfies the condition T0=V DD When T0=0V, the transistors M7 and M9 are not present, and the current-voltage conversion circuit 1 operates in the same manner as the current-voltage conversion circuit 1 according to the previous embodiment. On the other hand, when T0=0V, the transistors M1 and M2 in the first current mirror circuit 21B receive the power supply voltage V DD Similarly, in the second current mirror circuit 22B, the transistors M3 and M4 have their gates connected to the power supply voltage V DD As a result, the current flowing through the current-voltage conversion circuit 1B becomes only the off-leak current, which is essentially zero, and V out =0V. At this time, the signals T1, T2, ..., Tm and the signal Tk' are set to '0' (I v =0A, I Ref =0A).

[0044] The current-voltage conversion circuit according to the modification of the first embodiment may be configured to include, for example, a first current mirror circuit 21A and a second current mirror circuit 22B. In this case, the signal T0B is input to the first current mirror circuit 21A, and the signal T0 is input to the second current mirror circuit 22B.

[0045] Second Embodiment In the current-voltage conversion circuit according to the first embodiment, the linearity of the current-voltage conversion characteristics is incomplete even in the input current range in which the transistor of the first current mirror circuit is in the saturated region due to the channel length modulation effect of the transistor. Therefore, the linearity is improved by configuring the first current mirror circuit as a cascode current mirror circuit. A current-voltage conversion circuit according to a second embodiment of the present invention will now be described with reference to FIG. 7.

[0046] (Current-voltage conversion circuit) 7, a current-voltage conversion circuit 1C according to the second embodiment of the present invention includes a first current mirror circuit (first current mirror circuit) 21C, which is a cascode current mirror circuit, a load resistor (first resistor) 31, a second current mirror circuit (second current mirror circuit) 22, and a pull-up resistor (second resistor) 32. The output of the first current mirror circuit 21C is connected to a reference potential via the load resistor 31, and is also connected to the output of the second current mirror circuit 22 via the pull-up resistor 32. A voltage adjustment circuit 10C including the current-voltage conversion circuit 1C supplies a current I v and a second current mirror circuit 22 that supplies a reference current I Ref That is, the voltage adjustment circuit 10C has a configuration in which the first current mirror circuit 21 of the current-voltage conversion circuit 1 of the voltage adjustment circuit 10 according to the first embodiment is replaced with a first current mirror circuit 21C.

[0047] The first current mirror circuit 21C is a cascode current mirror circuit of a general structure, in which two pairs of transistors, each consisting of two transistors with their gates connected in common, are connected in series, and the input-side transistors M1 and M5 of each pair are diode-connected. The transistors M5 and M6, together with the transistors M1 and M2 and the transistors M3 and M4 of the second current mirror circuit 22, are connected to the same power supply voltage V DD There are no particular limitations as long as they operate within a certain range and can be manufactured on the same substrate, and the dimensions (gate length, gate width) and the like are designed so that the desired characteristics are obtained for the current-voltage conversion circuit 1C. Generally, they are designed so that the following equation (17) holds: For transistor M1, L1 is the gate length and W1 is the gate width; for transistor M2, L2 is the gate length and W2 is the gate width; for transistor M5, L5 is the gate length and W5 is the gate width; and for transistor M6, L6 is the gate length and W6 is the gate width.

number

[0048] According to the first current mirror circuit 21C, the channel length modulation effect of the drain-side (lower) transistor pair M5, M6 is reduced in the saturation region, and the error between the source-drain voltages is eliminated. As a result, the output current I Mir Input current I v The error for the input current I is suppressed and the saturation region is reached. v In this case, the linearity of the current-voltage conversion characteristic of the current-voltage conversion circuit 1C is improved. Note that, since the first current mirror circuit 21C has two stages of transistors connected in series, the current-voltage conversion circuit 1C has a higher linearity of the output voltage V out Power supply voltage V DD The voltage drop is large compared to the limit value V out_MAX However, the current-voltage conversion circuit 1C, like the current-voltage conversion circuit 1, is provided with a pull-up circuit configured by the second current mirror circuit 22 and the pull-up resistor 32, and thus the limit output voltage V out_MAX power supply voltage V DD can be approached.

[0049] The voltage regulator circuit 10C according to this embodiment, like the voltage regulator circuit 10 according to the first embodiment, adjusts the output voltage V out can be shifted in two stages: high voltage and low voltage.

[0050] (Variation) The voltage adjustment circuit 10C may include a variable current source (not shown) instead of the constant current source 5, as in the first embodiment. Also, in the current-voltage conversion circuit 1C, the current mirror circuits 21C and 22 may include switching elements, as in the modified example of the first embodiment shown in FIG. 5 or FIG. 6. Specifically, the current-voltage conversion circuit 1C includes a second current mirror circuit 22A or a second current mirror circuit 22B, and the first current mirror circuit 21C has transistors M7 and M8 inserted on the drain side of the transistors M5 and M6, and inputs a signal T0B to the gates. Alternatively, the first current mirror circuit 21C may include a power supply voltage V DD A transistor M7 is inserted between the drain of the transistor M5 and the drain of the transistor M5, and a signal T0 is input to the gate of the transistor M7.

[0051] In the current-voltage conversion circuit, the first current mirror circuit may be a low-voltage cascode current mirror circuit. As shown in Fig. 8, a current-voltage conversion circuit 1D according to a modification of the second embodiment of the present invention includes a first current mirror circuit (first current mirror circuit) 21D that is a low-voltage cascode current mirror circuit, a load resistor (first resistor) 31, a second current mirror circuit (second current mirror circuit) 22, and a pull-up resistor (second resistor) 32. The output of the first current mirror circuit 21D is connected to a reference potential via the load resistor 31, and is also connected to the output of the second current mirror circuit 22 via the pull-up resistor 32. The current-voltage conversion circuit 1D further includes a bias voltage generation resistor 33 inserted at the input of the first current mirror circuit 21D (between the first current mirror circuit 21D and the variable current source 4). The first current mirror circuit 21D includes two series-connected transistor pairs, each consisting of two transistors with their gates connected in common. The gates of the source-side (upper) transistor pair M1 and M2 are connected to the drain of the input-side (mirror source) transistor M5 on the drain-side (lower) side. In the first current mirror circuit 21D, a bias voltage is applied to the gates of the drain-side transistor pair M5 and M6. Here, as an example, a bias voltage generating resistor 33 is inserted into the output of the variable current source 4, and a bias voltage is output from between the variable current source 4 and the bias voltage generating resistor 33.

[0052] Similar to the voltage regulation circuit 10 according to the first embodiment, the voltage regulation circuit 10D may include a variable current source (not shown) instead of the constant current source 5. Also, similar to the current-voltage conversion circuit 1C according to the second embodiment, the current mirror circuits 21D and 22 of the current-voltage conversion circuit 1D may include switching elements, as in the modified example of the first embodiment shown in FIG. 5 or FIG. 6.

[0053] The above has described embodiments for implementing the voltage regulator circuit and current-voltage converter circuit according to the present invention, but below we will explain examples that confirmed the effects of the present invention. Note that the present invention is not limited to these examples and the above-described embodiments, and various modifications are possible within the scope of the claims. [Example]

[0054] As Example 1, a current-voltage conversion circuit 1 according to the first embodiment of the present invention shown in FIG. 1 was designed, and a simulation of the current-voltage conversion was performed using a SPICE-based circuit simulator (Spectre). In Example 1, the first current mirror circuit 21 and the second current mirror circuit 22 had the same structure, each equipped with two PMOSs compatible with a power supply voltage of 1.0 V. In the current mirror circuits 21 and 22, the PMOS on the output side had a gate width twice that of the PMOS on the input side, and the PMOSs had the same gate length (α1=2, α2=2). The power supply voltage V DD = 1.0V, the output voltage V out The minimum value is about 0.4V DD (=0.40V), the load resistance R L =1.421kΩ, pull-up resistor R p = 2.842 kΩ, and the reference current I Ref In addition, in comparison with the current-voltage conversion circuit 1 of Example 1, a comparative example 1 (I Ref =360 μA), and the conventional current-voltage conversion circuit 101 (Conventional Example 1-1: R L = 1.421 kΩ, Conventional Example 1-2: R L=2.842kΩ) was used as the comparison target.

[0055] For Example 1, Comparative Example 1, and Conventional Examples 1-1 and 1-2, the power supply voltage V DD =1.0V, input current I v = Output voltage V in the range of 0 to 500 μA out The current-voltage conversion characteristics are shown in Figure 9.

[0056] As shown in FIG. 9, in Example 1 according to the present invention, by switching the pull-up circuit ON / OFF, the power supply voltage V DD In addition, in Comparative Example 1 without a pull-up resistor, the minimum output voltage was higher and the range of voltage that could be output was narrower in the high voltage range with the pull-up circuit turned on than in Example 1. In this simulation, the output voltage V out When the voltage is near 0V, the current I p became larger than the ideal value (I p >2I Ref ). [Example]

[0057] As Example 2, a current-voltage conversion circuit 1C according to the second embodiment of the present invention shown in FIG. 7 was designed, and a simulation of the current-voltage conversion was carried out in the same manner as in Example 1. In Example 2, the second current mirror circuit 22 had the same structure as in Example 1. The first current mirror circuit 21C was a cascode current mirror circuit in which two pairs of transistors (two PMOS) constituting the first current mirror circuit 21 in Example 1 were connected in two stages. The load resistance R L =1.421kΩ, pull-up resistor R p = 7.105 kΩ, and the reference current I Ref In addition, in comparison with the current-voltage conversion circuit 1A of the second embodiment, a comparative example 2 (I Ref=270 μA), and Conventional Example 2 (R L =2.842kΩ) was used as the comparison target.

[0058] For Example 2, Comparative Example 2, and Conventional Example 2, the power supply voltage V DD =1.0V, input current I v = Output voltage V in the range of 0 to 300 μA out The current-voltage conversion characteristics are shown in Figure 10.

[0059] As shown in FIG. 10, in the second embodiment of the present invention, as in the first embodiment, the power supply voltage V DD Good linearity was obtained up to a high voltage range closer to 100 V, and the linearity was even better than that of Example 1. Furthermore, in Comparative Example 2 without a pull-up resistor, similar to Comparative Example 1, the minimum output voltage was higher and the output voltage range was narrower in the high voltage range with the pull-up circuit turned on than in Example 2. [Explanation of symbols]

[0060] 10, 10A, 10B, 10C, 10D Voltage adjustment circuit 1,1A,1B,1C,1D Current-to-voltage conversion circuit 21, 21A, 21B, 21C, 21D First current mirror circuit (first current mirror circuit) 22, 22A, 22B Second current mirror circuit (second current mirror circuit) 31 Load Resistor (First Resistor) 32 Pull-up resistor (second resistor) 40 D / A converter 4 Variable Current Source 5 Constant current source

Claims

1. A voltage adjustment circuit comprising a current-voltage conversion circuit, and a first current source and a second current source that input a current to the current-voltage conversion circuit, wherein the first current source inputs a current and the current-voltage conversion circuit outputs a voltage, the current-voltage conversion circuit includes a first current mirror circuit, a first resistor, a second current mirror circuit, and a second resistor, and outputs the voltage via the second resistor, the output of the first current mirror circuit being connected to a reference potential via the first resistor and being connected to the output of the second current mirror circuit via the second resistor; the first current source is a variable current source that inputs a current to the first current mirror circuit and changes the magnitude of the current in response to a digital signal; The second current source is a voltage adjustment circuit that is a constant current source that inputs a current to the second current mirror circuit and switches between outputting and not outputting a current in response to a digital signal so as to correspond to each of two or more voltage ranges into which the output voltage range is divided, or a variable current source that changes the magnitude of the current.

2. A voltage adjustment circuit comprising a current-voltage conversion circuit, and a first current source and a second current source that input a current to the current-voltage conversion circuit, wherein the first current source inputs a current and the current-voltage conversion circuit outputs a voltage, the current-voltage conversion circuit includes a first current mirror circuit, a first resistor, a second current mirror circuit, and a second resistor, and outputs the voltage via the second resistor, the output of the first current mirror circuit being connected to a reference potential via the first resistor and being connected to the output of the second current mirror circuit via the second resistor; the first current source is a variable current source that inputs a current to the first current mirror circuit in a thermometer code system; The second current source is a voltage adjustment circuit that is a constant current source or a variable current source that inputs a current to the second current mirror circuit.

3. A voltage regulation circuit as described in claim 1, wherein the first current source is controlled by a thermometer code corresponding to the output and non-output of current by the second current source or the magnitude of the current.

4. The current-voltage conversion circuit is a voltage adjustment circuit described in any one of claims 1 to 3, wherein at least one of the first current mirror circuit and the second current mirror circuit has two or more transistors connected in series.

5. The current-voltage conversion circuit is a voltage adjustment circuit as described in Claim 4, wherein the first current mirror circuit is a cascode current mirror circuit.

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