Burst code stream data phase recovery method, system, device and storage medium

Abstract

The present application discloses a data phase recovery method, system, device and storage medium for burst code stream, which includes: when it is detected that a data burst transmission occurs in the target counterpart device and the data pause signal is in an invalid state, increasing the data transmission bandwidth until the CDR completes data locking within a preset time specified by the transmission protocol, and when it is detected that the CDR completes data locking, decreasing the increased data transmission bandwidth. In the embodiment of the present application, by combining fast locking and slow tracking, the data transmission bandwidth is increased only within a preset time specified by the protocol, and the bandwidth is not continuously increased, so that the link stability is not significantly affected, and the locking time requirement is met while the link stability is met.

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to a Chinese patent application filed with the China Patent Office on December 28, 2021, with application number 202111630018.6 and title "Method, system, device and storage medium for data phase recovery of burst code stream," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of communications technology, and more particularly to a method, system, device and storage medium for recovering data phase from a burst code stream. [Background technology]

[0003] To take advantage of the enormous bandwidth of optical communications, current communications often use time-division multiplexing technology to multiplex low-speed signals onto high-speed optical fiber. However, due to the complexity of network synchronization, it is difficult to achieve perfect synchronization of signals on different time slots, and there will always be more or less frequency or phase differences. This places special requirements on the clock and data recovery (CDR) on the receiving side. High-speed serial buses generally use data-encoded clock information embedded in the transmitted data stream, which is then extracted at the receiving end through clock recovery and used to sample the data. Therefore, clock recovery circuits are extremely important for the transmission and reception of high-speed serial signals.

[0004] In particular, many communication services often require the transmission of burst data, which has a burst characteristic. These burst data have random transmission times, short durations, and other characteristics. Therefore, the receiver of clock recovery for burst data not only needs high-speed clock and data recovery capabilities (generally requiring a clock frequency of 1 GHz or higher), but also very high speeds (generally within a few hundred nanoseconds). Clock recovery for such burst data is usually called burst clock and data recovery (BCDR). Figure 1 shows the structure of a conventional CDR. As shown in Figure 1, the CDR clock recovery circuit's principle is to track clock drift and jitter at the upper-layer transmitter side to ensure accurate data sampling. The receiver module in the CDR circuit first maps the byte signals sent by the upper-layer protocol into DC-balanced encoding and then serializes the 10-bit encoded result using parallel-to-serial conversion, ensuring the high speed required for serialization and parallel-to-serial conversion. A low-jitter clock is provided by a phase-locked loop. The transmitter module converts the high-speed CMOS-level serial code stream into a noise-resistant differential signal and transmits it to the receiver via a backplane connection or fiber optic channel. On the receiving side, the receiver module converts the received low-swing differential signal into a CMOS-level serial signal. The CDR extracts the clock signal from the serial signal to achieve optimal sampling of the serial signal. The serial-to-parallel converter then converts the serial signal into parallel data using the recovered clock. The parallel data is decoded and reduced to a byte signal, which is then sent to the upper-layer protocol chip to complete the entire information transmission process.

[0005] In the XGS-PON protocol, data sent from the remote device occurs in burst interrupts and burst transmissions, so it is required that the CDR at the receiving end is stable and can complete locking of the recovered data within the time specified by the protocol. However, the inventors have discovered that existing CDRs are designed to follow data changes according to a fixed bandwidth, and in order to quickly lock data in a short period of time, the bandwidth must be increased. However, at the same time, increasing the bandwidth reduces link stability, and reducing the bandwidth makes it impossible to meet the locking time requirements specified in the protocol. Summary of the Invention

[0006] The present application provides a data phase recovery method, system, device and storage medium for burst code stream, the main purpose of which is to complete CDR data locking within the time specified by the protocol.

[0007] The technical solution of this application is as follows: The data phase recovery method for burst code stream includes: When it is detected that a data burst transmission has occurred in the target counterpart device and the data pause signal is in an invalid state, increasing the data transmission bandwidth until the CDR completes data locking within a preset time specified by the transmission protocol; When it is detected that the CDR has completed data locking, the increased data transmission bandwidth is reduced.

[0008] Another technical solution of the present application is as follows: A data phase recovery system for a burst code stream includes: a high-speed locking module for increasing a data transmission bandwidth until the CDR completes data locking within a preset time defined by a transmission protocol when it is detected that a data burst transmission has occurred in the target counterpart device and that the data pause signal is in an invalid state; and a slow tracking module for reducing the increased data transmission bandwidth when it is detected that the CDR has completed data locking.

[0009] Another technical solution of the present application is as follows: a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, When it is detected that a data burst transmission has occurred in the target counterpart device and the data pause signal is in an invalid state, increasing the data transmission bandwidth until the CDR completes data locking within a preset time specified by a transmission protocol; When it is detected that the CDR has completed data locking, a step of reducing the increased data transmission bandwidth is implemented.

[0010] Another technical solution of the present application is as follows: providing a computer storage medium, the computer storage medium storing a computer program, and when the computer program is executed by a processor, When it is detected that a data burst transmission has occurred in the target counterpart device and the data pause signal is in an invalid state, increasing the data transmission bandwidth until the CDR completes data locking within a preset time specified by a transmission protocol; When it is detected that the CDR has completed data locking, a step of reducing the increased data transmission bandwidth is implemented.

[0011] In the data phase recovery method, system, device, and storage medium for burst code streams proposed in this application, when a data burst transmission occurs, the data transmission bandwidth is increased within a preset time period specified by the XGS-PON protocol. As the bandwidth increases, the amount of data that can be transmitted per unit time increases, allowing the CDR circuit to achieve fast data locking. After fast locking is completed, the increased data transmission bandwidth is reduced to the normal data transmission bandwidth, and data tracking by the CDR is then completed. In the embodiment of this application, fast locking and slow tracking are combined to increase the data transmission bandwidth only within the preset time period specified by the protocol, rather than continuously increasing the bandwidth, which does not significantly affect link stability and satisfies the locking time requirement while maintaining link stability. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing the structure of a CDR in the prior art. [Figure 2] 4 is a flowchart of a data phase recovery method for a burst code stream provided by an embodiment of the present application; [Figure 3] 1 is a diagram of the CDR structures provided by the examples of the present application. [Figure 4] 3 is a flowchart of a data phase recovery method for a burst code stream provided by a preferred embodiment of the present application; [Figure 5] 1 is a structural schematic diagram of a data phase recovery system for a burst code stream provided by an embodiment of the present application; [Figure 6] 1 is a structural schematic diagram of a computer device provided in an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0013] The realization of the objects, functional features and advantages of the present application will be further explained with reference to the accompanying drawings in conjunction with examples.

[0014] It should be understood that the specific examples described herein are merely for purposes of interpretation of the present application and are not intended to limit the present application.

[0015] FIG. 2 is a flowchart of a data phase recovery method for a burst code stream provided by an embodiment of the present application. As shown in FIG. 2, the method includes:

[0016] Figure 3 is a structural diagram of a CDR provided by an embodiment of the present application. As shown in Figure 3, the CDR in the embodiment of the present application adds a PI configuration port (PI_CTRL), a PI real-time monitoring port (PI_READ), and a PI pause count port (FREEZE) to the conventional CDR architecture. Specifically, three pins are extracted from the interpolator of the CDR circuit, which are respectively used for the PI configuration port, the PI real-time monitoring port, and the PI pause count port. The PI configuration port is used as a PI write port and is used to assign a value to the real-time phase of the interpolator. The PI real-time monitoring port is used to read the PI value in real time and is regarded as reading the real-time phase value of the interpolator. The PI pause count port is used to set the value of the artificial data pause signal.

[0017] S210, when detecting that a data burst transmission occurs in the target counterpart device and detecting that the data pause signal is in an invalid state, increasing the data transmission bandwidth until the CDR completes data locking within a preset time specified by a transmission protocol; When it is detected that a data burst transmission has occurred in the target counterpart device, the target counterpart device is the device connected to the CDR, and there may be multiple devices connected to the CDR. In the embodiment of this application, one connected device is selected as the target counterpart device, and the target counterpart device is used as an example for explanation, and the execution process of other connected devices is similar.

[0018] After detecting that a data burst transmission has occurred in the target counterpart device, the state of the data pause signal is detected. If the data pause signal is invalid, the initially set data transmission bandwidth is increased within the time specified by the XGS-PON protocol. After the data transmission bandwidth is increased, the amount of data that can be transmitted within that unit time increases, and data locking by the CDR can be accelerated.

[0019] In the embodiment of the present application, by increasing the data transmission bandwidth within the preset time, data can be locked at high speed within the preset time defined by the XGS-PON protocol.

[0020] S220, if it is detected that the CDR has completed data locking, reduce the increased data transmission bandwidth.

[0021] When it is detected that the CDR has completed data locking, the data transmission bandwidth is the bandwidth after it has been increased. Maintaining a large data transmission bandwidth will reduce link stability, so in order to maintain link stability, the increased data transmission bandwidth is reduced. Here, the reduction may mean reducing the increased data transmission bandwidth or changing the increased data transmission bandwidth to its initial value.

[0022] In the embodiment of the present application, by reducing the data transmission bandwidth outside the preset time, slow tracking of locking data can be realized and link stability can be ensured.

[0023] The data phase recovery method for burst code streams proposed in this application increases the data transmission bandwidth within a preset time period specified by the XGS-PON protocol when a data burst transmission occurs. The increased bandwidth allows for a larger amount of data to be transmitted per unit time, allowing the CDR circuit to achieve fast data locking. After fast locking is complete, the increased data transmission bandwidth is reduced to the normal data transmission bandwidth, and the CDR completes data tracking. In this embodiment, fast locking and slow tracking are combined to increase the data transmission bandwidth only within the preset time period specified by the protocol, rather than continuously increasing the bandwidth. This does not significantly affect link stability, and the locking time requirement is met while maintaining link stability.

[0024] Based on the above embodiment, preferably, when it is detected that a data burst transmission has occurred in the target counterpart device and the data pause signal is in an invalid state, before increasing the data transmission bandwidth until the CDR completes data locking within a preset time defined by the transmission protocol: Reading the real-time phase value of the interpolator in the CDR; The method further includes determining a state of a CDR based on the real-time phase value, and assigning the phase value of the interpolator to a preset phase value if it is determined that the CDR is not in a converged state.

[0025] Specifically, before fast locking, the following steps can be taken to promote the convergence of the CDR, shorten the CDR convergence time, and further shorten the fast data locking time of the CDR. The steps are specifically as follows: The real-time phase value, i.e., the PI value, of the interpolator is read through the PI_READ port. For the same target device, the real-time phase values ​​when the CDR has converged at different times should not differ significantly. The difference is caused by changes in voltage and environmental temperature during each data transmission process. Therefore, based on the read real-time phase value, it can be determined whether the CDR is in a converged state. Specifically, the interval in which the phase value is located when the CDR is in a converged state is determined empirically. If the real-time phase value currently being transmitted is within this interval, it is determined that the CDR is in a converged state; otherwise, it is determined that the CDR is not in a converged state.

[0026] When the CDR is in a converged state, no operation is performed; when the CDR is in a non-converged state, the real-time phase value is adjusted based on the preset phase value, thereby speeding up the convergence time of the CDR and further shortening the data locking time of the CDR.

[0027] Based on the above embodiment, preferably, the preset phase value is obtained based on the phase value of the interpolator when CDR converges at different historical points in time of burst data transmission by the target counterpart device.

[0028] Specifically, for the same target counterpart device, the real-time phase values ​​when the CDR converges at different times should not be significantly different. In the embodiment of the present application, a preset phase value is selected based on the real-time phase values ​​when the CDR converges at different times, and the preset phase value is assigned to the real-time phase value to adjust the real-time phase of the interpolator.

[0029] Based on the above example, preferably, The method further includes setting an initial phase value of an interpolator in a CDR to the preset phase value when a data burst transmission occurs for the first time in the target counterpart device.

[0030] When a data burst transmission occurs for the first time in the target remote device, the initial phase value of the interpolator in the CDR is set to the preset phase value.

[0031] Based on the above embodiment, preferably, the data pause signal includes an artificial data pause signal; setting the artificial data pause signal to an enabled state when it is detected that a data burst interrupt has occurred in the target remote device; The method further includes stopping the phase counting of the CDR when the artificial data pause signal is detected to be valid.

[0032] Specifically, the data pause signal includes an artificial data pause signal, which means an artificial setting signal, and the working state of the CDR can be controlled by manually setting this signal. In specific implementation, when it is detected that a data burst interrupt occurs in the target counterpart device, the artificial data pause signal is set to enabled, that is, the artificial data pause signal is set via the FREEZE port, and after the port is set to enabled, the CDR stops phase counting.

[0033] In the prior art, when a data burst interrupt occurs, the CDR operation is not stopped by artificial setting, so the phase value continues to rotate in the CDR, which makes the CDR very susceptible to hanging up. In the embodiment of the present application, by artificially setting a data pause signal, the CDR phase counting can be stopped, and the CDR hanging up after a data interrupt can be prevented.

[0034] Based on the above embodiment, preferably, the data pause signal includes an abnormal data pause signal; If an abnormality in the CDR is detected, the abnormal data pause signal is set to valid; The method further includes stopping the phase counting of the CDR when it is detected that the abnormal data pause signal is valid.

[0035] In the embodiment of the present application, the data pause signal further includes an abnormal data pause signal, which is used to detect natural abnormalities in the CDR. When a CDR abnormality is detected, the abnormal data pause signal is set to active, and the phase counting of the CDR is stopped even when the abnormal data pause signal is active.

[0036] Based on the above example, preferably, The method further includes setting all of the data pause signals to invalid when the end of the data burst transmission is detected.

[0037] Specifically, when the data burst transmission is completed, both the artificial data pause signal and the abnormal data pause signal are set to an invalid state, and a state for preparing for the next data burst is prepared.

[0038] FIG. 4 is a flowchart of a data phase recovery method for a burst code stream provided by a preferred embodiment of the present application. As shown in FIG. 4, the method includes: S410, performing system initialization, setting the initial values ​​of corresponding signals, and setting the initial phase value of the interpolator to a preset phase value; S420, during data burst transmission, detecting whether FREEZE and SIGDET are in an invalid state, and if they are in an invalid state, performing subsequent operations; S430: reading a real-time phase value of the interpolator via PI_READ, and determining whether the CDR is in a converged state based on the real-time phase value; if not, setting the real-time phase value to a preset phase value via PI_CTRL; S440, increasing the data transmission bandwidth and realizing high-speed locking within a preset time specified by the protocol; S450, after data locking is completed, reduce the data transmission bandwidth to realize data slow tracking; S460: if a data burst interrupt is detected, enable FREEZE and terminate data transmission; if an abnormality in CDR is detected, enable SIGDET and terminate data transmission.

[0039] As described above, the embodiment of the present application provides a data phase recovery method for burst code streams. When data burst transmission occurs, the data transmission bandwidth is increased within a preset time period specified by the XGS-PON protocol. The larger the bandwidth, the more data can be transmitted per unit time. This allows the CDR circuit to achieve fast data locking. After fast locking is complete, the increased data transmission bandwidth is reduced to the normal data transmission bandwidth, and the CDR completes data tracking. In the embodiment of the present application, fast locking and slow tracking are combined to increase the data transmission bandwidth only within a preset time period specified by the protocol, rather than continuously increasing the bandwidth. This does not significantly affect link stability, and the locking time requirement is met while maintaining link stability. Then, by adjusting the real-time phase value based on the preset phase value, the convergence time of the CDR can be accelerated, and the data locking time of the CDR can be further shortened.

[0040] Finally, in the prior art, when a data burst interrupt occurs, the CDR operation is not stopped by artificial setting, so the phase value continues to rotate in the CDR, which makes the CDR very susceptible to hanging up. In the embodiment of the present application, by artificially setting a data pause signal, the phase count of the CDR can be stopped, and the CDR hanging up after a data interrupt can be prevented.

[0041] FIG. 5 is a structural schematic diagram of a data phase recovery system for a burst code stream provided by an embodiment of the present application. As shown in FIG. 5, the system includes a fast locking module 510 and a slow tracking module 520; The fast locking module 510 is used to increase the data transmission bandwidth until the CDR completes data locking within a preset time specified by a transmission protocol when it is detected that a data burst transmission occurs in the target counterpart device and the data pause signal is in an invalid state; The slow tracking module 520 is used to reduce the increased data transmission bandwidth when it is detected that the CDR has completed data locking.

[0042] This embodiment is a system embodiment corresponding to the above method, and its implementation process is similar to the above method embodiment. For details, please refer to the above method embodiment, and the system embodiment will not be repeated here.

[0043] Based on the above embodiment, preferably, further comprising a reading module and a determining module; The reading module is used to read a real-time phase value of an interpolator in a CDR; The determining module is used to determine the state of the CDR based on the real-time phase value, and assign the phase value of the interpolator to a preset phase value if it determines that the CDR is not in a converged state.

[0044] Based on the above embodiment, preferably, the preset phase value is obtained based on the phase value of the interpolator when CDR converges at different historical points in time of burst data transmission by the target counterpart device.

[0045] Based on the above embodiment, preferably, the system further comprises an initialization module; The initialization module is used to set the initial phase value of the interpolator in the CDR to the preset phase value when a data burst transmission occurs for the first time in the target counterpart device.

[0046] Based on the above embodiment, preferably, the data pause signal includes an artificial data pause signal, and further includes an artificial pause module and a first stop module; the artificial pause module is used to set the artificial data pause signal to valid when it is detected that a data burst interrupt occurs in the target counterpart device; The first stop module is used to stop the phase counting of the CDR when the artificial data pause signal is detected to be valid.

[0047] Based on the above embodiment, preferably, the data pause signal includes an abnormal data pause signal, and further includes an abnormal data pause module and a second stop module; the abnormal data pause module is used to set the abnormal data pause signal to valid when an abnormality of the CDR is detected; The second stop module is used to stop the phase counting of the CDR when it is detected that the abnormal data pause signal is valid.

[0048] Based on the above embodiment, preferably, further includes a reset unit; The reset unit is used to set all the data pause signals to invalid when the end of a data burst transmission is detected.

[0049] The modules in the burst code stream data phase recovery system can be implemented in part or entirely by software, hardware, or a combination thereof. The modules can be integrated into a processor in a computer system in the form of hardware, or can be independent, or can be stored in a memory in a computer system in the form of software, so that the processor can easily perform the operations corresponding to the modules.

[0050] FIG. 6 is a structural schematic diagram of a computer device provided by an embodiment of the present application. The computer device may be a server, and its internal structural diagram is shown in FIG. 6. The computer device includes a processor, a memory, a network interface, and a database, all connected via a system bus. The processor of the computer device is used to provide computing and control functions. The memory of the computer device includes a computer storage medium and an internal memory. An operating system, computer programs, and a database are stored in the computer storage medium. The internal memory provides an operating environment for the operating system and computer programs stored in the computer storage medium. The database of the computer device stores data generated or acquired during the process of executing the burst code stream data phase recovery method, such as data pause signals and preset times. The network interface of the computer device is used to communicatively connect to an external terminal via a network. The computer program is executed by the processor to implement the burst code stream data phase recovery method.

[0051] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the burst code stream data phase recovery method in the above embodiment are implemented, or when the processor executes the computer program, the functions of each module / unit in the burst code stream data phase recovery system embodiment are implemented.

[0052] In one embodiment, a computer storage medium is provided, storing a computer program, the computer-readable storage medium may be non-volatile or volatile, which, when executed by a processor, implements the steps of the burst code stream data phase recovery method in the above embodiment, or implements the functions of each module / unit in the burst code stream data phase recovery system embodiment.

[0053] Those skilled in the art will understand that the implementation of all or part of the steps in the above-described method embodiments can be achieved by a computer program that instructs relevant hardware, and that the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the steps of the above-described method embodiments. Herein, any reference to memory, storage, database, or other medium used in the embodiments provided by this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of example and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0054] As will be apparent to those skilled in the art, for convenience and simplicity of explanation, the division of each functional unit or module has been described as an example, but in actual applications, the above functions can be assigned to be performed by different functional units or modules as needed, i.e., the internal structure of the device can be divided into different functional units or modules to achieve all or part of the above functions.

[0055] The above examples are only used to illustrate the technical solutions of the present application and are not intended to be limiting. Although the present application has been described in detail with reference to the above examples, those skilled in the art may still make modifications to the technical solutions described in each of the above examples or make equivalent substitutions to some technical features, and these modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each of the examples of the present application, and all shall be included in the protection scope of the present application.

Claims

1. A method for recovering data phase of a burst code stream executed by a receiving communication device, comprising: When the receiving communication device detects that a data burst transmission occurs in a target counterpart device as a transmitting communication device and detects that a data pause signal is in an invalid state, the receiving communication device increases the data transmission bandwidth of the CDR until the CDR of the receiving communication device completes data locking within a preset time specified by a transmission protocol; When the receiving communication device detects that the CDR has completed data locking, the receiving communication device reduces the increased data transmission bandwidth of the CDR; The data pause signal includes an artificial data pause signal or an abnormal data pause signal. A method for recovering data phase from a burst code stream.

2. If it is detected that a data burst transmission has occurred in the target counterpart device and a data pause signal is in an invalid state, before increasing the data transmission bandwidth until the CDR completes data locking within a preset time defined by the transmission protocol, reading a real-time phase value of an interpolator in the CDR; 2. The method for recovering data phase of a burst code stream according to claim 1, further comprising: determining a state of a CDR based on the real-time phase value; and assigning the phase value of the interpolator to a preset phase value if it is determined that the CDR is not in a converged state.

3. 3. The method for recovering data phase of a burst code stream according to claim 2, wherein the preset phase value is obtained based on phase values ​​of the interpolator when CDR converges at different historical points in time of burst data transmission by the target counterpart device.

4. 4. The method for recovering a data phase of a burst code stream according to claim 3, further comprising the step of: setting an initial phase value of an interpolator in a CDR to the preset phase value when a data burst transmission occurs for the first time in the target opposite device.

5. If the data pause signal includes an artificial data pause signal, when detecting that a data burst interrupt has occurred in the target counterpart device, setting the artificial data pause signal to an enabled state; 2. The method of claim 1, further comprising the step of: a CDR stopping phase counting when said artificial data pause signal is detected to be valid.

6. If the data pause signal includes an abnormal data pause signal, If an abnormality of the CDR is detected, setting the abnormal data pause signal to valid; 2. The method of claim 1, further comprising the step of: a CDR stopping phase counting when the abnormal data pause signal is detected to be valid.

7. 7. The method for recovering data phase of a burst code stream according to claim 1, further comprising the step of: setting all said data pause signals to invalid when an end of data burst transmission is detected.

8. A data phase recovery system for a burst code stream provided in a receiving communication device, comprising: a fast locking module for increasing the data transmission bandwidth of the CDR of the receiving communication device until the CDR of the receiving communication device completes data locking within a preset time defined by a transmission protocol when the receiving communication device detects that a data burst transmission has occurred in a target counterpart device as a transmitting communication device and detects that a data pause signal is in an invalid state; a slow tracking module for reducing the increased data transmission bandwidth of the CDR when the receiving communication device detects that the CDR has completed data locking; The data pause signal includes an artificial data pause signal or an abnormal data pause signal. Data phase recovery system for burst code streams.

9. A computer device provided in a receiving communication device, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, When the receiving communication device detects that a data burst transmission has occurred in the target counterpart device as a transmitting communication device and detects that the data pause signal is in an invalid state, the receiving communication device increases the data transmission bandwidth of the CDR until the CDR of the receiving communication device completes data locking within a preset time specified by a transmission protocol; When the receiving communication device detects that the CDR has completed data locking, the receiving communication device reduces the increased data transmission bandwidth of the CDR; The data pause signal includes an artificial data pause signal or an abnormal data pause signal. Computer equipment.

10. When it is detected that a data burst transmission has occurred in the target counterpart device and the data pause signal is in an invalid state, before increasing the data transmission bandwidth, the CDR completes data locking within a preset time defined by the transmission protocol. reading the real-time phase value of the interpolator in the CDR; 10. The computer apparatus of claim 9, further comprising: determining a state of a CDR based on the real-time phase value; and assigning a phase value of the interpolator to a preset phase value if it is determined that the CDR is not in a converged state.

11. 11. The computer device of claim 10, wherein the preset phase value is obtained based on phase values ​​of the interpolator when CDR converges at different historical points in time of burst data transmission by the target counterpart device.

12. The computer device of claim 11 , further comprising: setting an initial phase value of an interpolator in a CDR to the preset phase value when a data burst transmission occurs for the first time in the target counterpart device.

13. the data pause signal comprises an artificial data pause signal; setting the artificial data pause signal to an enabled state when it is detected that a data burst interrupt has occurred in the target remote device; 10. The computer apparatus of claim 9, further comprising: stopping phase counting of a CDR when the artificial data pause signal is detected to be valid.

14. the data pause signal includes an abnormal data pause signal; If an abnormality in the CDR is detected, the abnormal data pause signal is set to valid; 10. The computer apparatus of claim 9, further comprising: stopping phase counting of a CDR when the abnormal data pause signal is detected to be valid.

15. The computer device of any one of claims 9 to 14, further comprising: setting all said data pause signals to invalid when an end of a data burst transmission is detected.

16. A computer storage medium, comprising: a computer program stored therein, the computer program being executed by a processor of the receiving communication device; When the receiving communication device detects that a data burst transmission has occurred in the target counterpart device as a transmitting communication device and detects that the data pause signal is in an invalid state, the receiving communication device increases the data transmission bandwidth of the CDR until the CDR of the receiving communication device completes data locking within a preset time specified by a transmission protocol; When the receiving communication device detects that the CDR has completed data locking, the receiving communication device reduces the increased data transmission bandwidth of the CDR; The data pause signal includes an artificial data pause signal or an abnormal data pause signal. Computer storage media.

17. When it is detected that a data burst transmission has occurred in the target counterpart device and the data pause signal is in an invalid state, before increasing the data transmission bandwidth, the CDR completes data locking within a preset time defined by the transmission protocol. reading the real-time phase value of the interpolator in the CDR; 17. The computer storage medium of claim 16, further comprising: determining a state of a CDR based on the real-time phase value; and assigning a phase value of the interpolator to a preset phase value if it is determined that the CDR is not in a converged state.

18. 18. The computer storage medium of claim 17, wherein the preset phase value is obtained based on phase values ​​of the interpolator when CDR converged at different historical points in time of burst data transmission by the target counterpart device.

19. 20. The computer storage medium of claim 18, further comprising: setting an initial phase value of an interpolator in a CDR to the preset phase value when a data burst transmission occurs for the first time in the target counterpart device.

20. the data pause signal comprises an artificial data pause signal; setting the artificial data pause signal to an enabled state when it is detected that a data burst interrupt has occurred in the target remote device; 17. The computer storage medium of claim 16, further comprising stopping phase counting of a CDR when the artificial data pause signal is detected to be valid.

21. the data pause signal includes an abnormal data pause signal; If an abnormality in the CDR is detected, the abnormal data pause signal is set to valid; 17. The computer storage medium of claim 16, further comprising stopping phase counting of a CDR when the abnormal data pause signal is detected to be valid.

22. The computer storage medium of any one of claims 16 to 21, further comprising setting all said data pause signals to invalid when an end of a data burst transmission is detected.

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