Multilayer ceramic capacitor packaging

Abstract

To provide a multilayer ceramic capacitor package for reducing a surface crack of a multilayer ceramic capacitor during packaging.SOLUTION: A multilayer ceramic capacitor package 100 in which a plurality of multilayer ceramic capacitors 10 are stored, comprises: a long-length-shaped carrier tape 200 provided with a plurality of recessed pockets 210 that are arranged in a longitudinal direction at equal intervals; a long-length-shaped cover tape 300 that is attached to the carrier tape 200 so as to cover openings of the plurality of pockets 210; and the plurality of multilayer ceramic capacitors 10 stored in the plurality of pockets 210, respectively. According to multilayer ceramic capacitors 10 adjacent to each other among the plurality of multilayer ceramic capacitors 10, a density difference between surfaces on opening sides of the pockets 210 is 0% or more and 4% or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor packaging body. [Background technology]

[0002] A long or strip-shaped multilayer ceramic capacitor package compatible with a mounter for automatic mounting is known as a packaging form for multilayer ceramic capacitors (see, for example, Patent Document 1). Such a multilayer ceramic capacitor package includes a carrier tape having a plurality of recessed pockets arranged at equal intervals in the longitudinal direction, and a cover tape attached to the carrier tape so as to cover the openings of the plurality of pockets. A multilayer ceramic capacitor is housed in each of the plurality of pockets. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-145340 Summary of the Invention [Problem to be solved by the invention]

[0004] In such a multilayer ceramic capacitor package, when a mounter is used to mount the multilayer ceramic capacitor on a mounting board or the like, the mounter adsorbs the surface of the multilayer ceramic capacitor from the opening side of the pocket, and the multilayer ceramic capacitor is removed from the pocket, which can sometimes cause the surface of the multilayer ceramic capacitor to crack.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor package that can reduce cracks on the surface of a multilayer ceramic capacitor during mounting. [Means for solving the problem]

[0006] The present inventors have discovered that one of the causes of cracks on the surface of a multilayer ceramic capacitor when the multilayer ceramic capacitor is mounted on a mounting board or the like using a mounter is variations in the density of the surface on the opening side of the pocket in the multilayer ceramic capacitor.

[0007] Therefore, the multilayer ceramic capacitor packaging according to the present invention is a multilayer ceramic capacitor packaging containing a plurality of multilayer ceramic capacitors, and includes: a long carrier tape having a plurality of recessed pockets arranged at equal intervals in the longitudinal direction; a long cover tape attached to the carrier tape so as to cover the openings of the plurality of pockets; and the plurality of multilayer ceramic capacitors respectively contained in the plurality of pockets. The difference in density of the surfaces on the opening sides of the pockets between adjacent multilayer ceramic capacitors among the plurality of multilayer ceramic capacitors is 0% or more and 4% or less. [Effects of the Invention]

[0008] According to the present invention, cracks on the surface of the multilayer ceramic capacitor can be reduced during mounting. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view showing a multilayer ceramic capacitor packaging body according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor packaging body shown in FIG. [Figure 3] FIG. 3 is a schematic perspective view of the multilayer ceramic capacitor shown in FIGS. 1 and 2. [Figure 4] 4 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 3 taken along line IV-IV. [Figure 5] 4 is a cross-sectional view taken along line VV of the multilayer ceramic capacitor shown in FIG. [Figure 6] FIG. 4 is a schematic perspective view of only the element body of the multilayer ceramic capacitor shown in FIG. [Figure 7]7 is a schematic perspective view of a laminate chip that is a precursor of a laminate that constitutes a part of the element part shown in FIG. 6. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0011] (multilayer ceramic capacitors) First, the multilayer ceramic capacitor housed in the multilayer ceramic capacitor packaging according to this embodiment will be described with reference to Figs. 3 to 7. Fig. 3 is a schematic perspective view of a multilayer ceramic capacitor 10 according to this embodiment. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor 10 shown in Fig. 3 taken along line IV-IV, and Fig. 5 is a cross-sectional view of the multilayer ceramic capacitor 10 shown in Fig. 3 taken along line VV. Fig. 6 is a schematic perspective view of only the element part 11 of the multilayer ceramic capacitor 10 shown in Fig. 3, and Fig. 7 is a schematic perspective view of a laminate chip 22 which is a precursor of the laminate 12 which constitutes a part of the element part 11 shown in Fig. 6.

[0012] As shown in FIGS. 3 to 5, the multilayer ceramic capacitor 10 is an electronic component having a generally rectangular parallelepiped shape as a whole, and includes a body portion 11 and a pair of external electrodes 16.

[0013] 3 and 4, a pair of external electrodes 16 are spaced apart from each other and cover the outer surfaces of both ends in a predetermined direction of the element body 11. Each of the pair of external electrodes 16 is made of a conductive film.

[0014] More specifically, the pair of external electrodes 16 is formed, for example, by a laminated film of a sintered metal layer and a plating layer. The sintered metal layer is formed by baking a paste of, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, or Au. The plating layer is formed, for example, by a Ni plating layer and a Sn plating layer covering the Ni plating layer. The plating layer may alternatively be a Cu plating layer or an Au plating layer. The pair of external electrodes 16 may also be formed only by a plating layer. Furthermore, a conductive resin paste may also be used for the pair of external electrodes 16.

[0015] As shown in Figures 4 to 6, the element body 11 includes a laminate 12 made up of dielectric layers 13 and internal electrode layers 14 alternately stacked in a predetermined direction, and a pair of additional dielectric portions 15 covering predetermined portions of the laminate 12. The dielectric layers 13 are an example of ceramic layers, and the internal electrode layers 14 are an example of internal electrodes. The additional dielectric portions 15 are sometimes referred to as side gap portions.

[0016] The dielectric layer 13 and the additional dielectric portion 15 are formed of a ceramic material mainly composed of, for example, barium titanate. The dielectric layer 13 and the additional dielectric portion 15 may also contain Mn compounds, Mg compounds, Si compounds, Co compounds, Ni compounds, rare earth compounds, and the like, as secondary components of the ceramic powder that is the raw material for the ceramic green sheets. On the other hand, the internal electrode layer 14 is preferably formed of a metal material typified by, for example, Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0017] 4, one of a pair of internal electrode layers 14 adjacent to each other along the stacking direction with the dielectric layer 13 sandwiched therebetween is electrically connected to one of a pair of external electrodes 16 inside the multilayer ceramic capacitor 10, and the other of the pair of internal electrode layers 14 adjacent to each other along the stacking direction with the dielectric layer 13 sandwiched therebetween is electrically connected to the other of the pair of external electrodes 16 inside the multilayer ceramic capacitor 10. This results in a structure in which multiple capacitor elements are electrically connected in parallel between the pair of external electrodes 16.

[0018] The material of the dielectric layer 13 and the additional dielectric portion 15 is not limited to the ceramic material mainly composed of barium titanate described above, and other ceramic materials with high dielectric constants (e.g., those mainly composed of CaTiO3, SrTiO3, CaZrO3, etc.) may be selected as the material of the dielectric layer 13 and the additional dielectric portion 15. Moreover, it is not necessarily necessary for the material of the dielectric layer 13 and the material of the additional dielectric portion 15 to be the same, and ceramic materials having different main components may be used as the materials of the dielectric layer 13 and the additional dielectric portion 15. Furthermore, a resin material, which is a non-ceramic material, may be used as the additional dielectric portion 15. Meanwhile, the material of the internal electrode layer 14 is not limited to the metal material described above, and other conductive materials may be selected as the material of the internal electrode layer 14.

[0019] 3 to 5, the terms representing the orientation of the multilayer ceramic capacitor 10 are defined as follows: the direction in which a pair of external electrodes 16 are arranged is defined as the length direction L of the multilayer ceramic capacitor 10; the direction in which the dielectric layers 13 and the internal electrode layers 14 are stacked is defined as the thickness direction T (hereinafter also referred to as the stacking direction); and the direction perpendicular to both the length direction L and the thickness direction T is defined as the width direction W.

[0020] Furthermore, of the six outer surfaces of the approximately rectangular parallelepiped-shaped multilayer ceramic capacitor 10, a pair of outer surfaces positioned opposite each other in the length direction L are defined as end faces 10a, a pair of outer surfaces positioned opposite each other in the thickness direction T are defined as main faces 10b, and a pair of outer surfaces positioned opposite each other in the width direction W are defined as side faces 10c.

[0021] 6 and 7, the pair of outer surfaces of the element body 11 and the pair of outer surfaces of the laminate chip 22 corresponding to the pair of end faces 10a of the multilayer ceramic capacitor 10 are defined as end faces 11a and end faces 22a, respectively; the pair of outer surfaces of the element body 11 and the pair of outer surfaces of the laminate chip 22 corresponding to the pair of main faces 10b of the multilayer ceramic capacitor 10 are defined as main faces 11b and main faces 22b, respectively; and the pair of outer surfaces of the element body 11 and the pair of outer surfaces of the laminate chip 22 corresponding to the pair of side faces 10c of the multilayer ceramic capacitor 10 are defined as side faces 11c and side faces 22c, respectively.

[0022] 3 to 5, the multilayer ceramic capacitor 10 according to this embodiment has an elongated, approximately rectangular parallelepiped shape configured so that the outer dimension along the length direction L is the longest. Representative values ​​of the outer dimension along the thickness direction T and the outer dimension along the width direction W of the multilayer ceramic capacitor 10 (usually, the outer dimension along the thickness direction T is equivalent to the outer dimension along the width direction W) preferably satisfy "W / T≧1.06W+0.14." Specific W×T dimensions are, for example, 0.3 mm×0.5 mm, 0.5 mm×0.8 mm, etc.

[0023] 6, the pair of additional dielectric portions 15 cover a pair of outer surfaces of the laminate 12 positioned opposite each other in the width direction W so as to form a pair of side surfaces 11c of the element body portion 11. On the other hand, the pair of end faces 11a of the element body portion 11 are mainly formed by the pair of outer surfaces of the laminate 12 positioned opposite each other in the length direction L, and the pair of main surfaces 11b of the element body portion 11 are mainly formed by the pair of outer surfaces of the laminate 12 positioned opposite each other in the thickness direction T.

[0024] 7, in this embodiment, the laminate 12 is formed from a laminate chip 22 having a substantially rectangular parallelepiped shape as shown in the figure, by laminating and dividing a plurality of material sheets, each having a conductive pattern 24 that will become the internal electrode layer 14 printed on the surface of a ceramic green sheet 23 for lamination that will become the dielectric layer 13. The conductive pattern 24 is an example of an internal electrode pattern.

[0025] A portion of the conductive patterns 24 arranged in a stack is selectively exposed on a pair of end faces 22a of the laminate chip 22. More specifically, on each of the pair of end faces 22a of the laminate chip 22, one end in the length direction L of the conductive pattern 24 to be connected to the external electrode 16 formed so as to cover the corresponding end face 22a is exposed.

[0026] Meanwhile, on the pair of side surfaces 22c of the laminate chip 22, all of the ends in the width direction W of the laminated conductive patterns 24 are exposed. Also, on the pair of side surfaces 22c of the laminate chip 22, all of the ends in the width direction W of the laminated conductive patterns 24 are aligned in the stacking direction T. As a result, as shown in Fig. 5, in the multilayer ceramic capacitor 10, the ends in the width direction W of the multiple internal electrode layers 14 are aligned in the stacking direction T so as to be located within a range of, for example, 5 µm in the width direction W.

[0027] Ceramic green coating sheets that will become additional dielectric portions 15 are attached to the pair of side surfaces 22c of laminate chip 22 so as to cover them. As a result, the ends in the width direction W of conductive patterns 24 that are exposed on the pair of side surfaces 22c of laminate chip 22 are covered with the ceramic green coating sheets, and laminate chip 22 with the attached ceramic green coating sheets is then thermocompressed and fired to produce element portion 11 as shown in FIG.

[0028] The thickness of the dielectric layer 13 on the main surface 11b of the element body 11, i.e., the main surface 10b of the multilayer ceramic capacitor 10, is 5 μm or more and 30 μm or less, and more preferably 5 μm or more and 20 μm or less. The thickness of the dielectric layer 13 on the main surface 10b is the thickness from the main surface 10b to the internal electrode layer 14 located closest to the main surface 10b. On the other hand, the thickness of the additional dielectric portion 15 on the side surface 11c of the element body 11, i.e., the side surface 10c of the multilayer ceramic capacitor 10, is 5 μm or more and 30 μm or less, and more preferably 5 μm or more and 20 μm or less. The thickness of the additional dielectric portion 15 on the side surface 10c is the thickness from the side surface 10c to the end of the internal electrode layer 14 on the side surface 10c side.

[0029] In the multilayer ceramic capacitor 10 described above, the dielectric layers at the portions located at both ends in the width direction W of the element portion 11 are made of coating ceramic green sheets that are attached so as to cover a pair of outer surfaces that face each other in the width direction W of the laminate 12, and that become the additional dielectric portions 15 after firing. Therefore, by making the thickness of the attached coating ceramic green sheets sufficiently thin, the thickness of the dielectric layers at the portions that form the side surfaces 10c of the multilayer ceramic capacitor 10 can be narrowed.

[0030] Therefore, by adopting this structure, it is possible to increase the effective area (the area of ​​the portion where a pair of adjacent internal electrode layers 14 facing each other with the dielectric layer 13 sandwiched between them in the stacking direction) by increasing the size of the internal electrode layers 14 along the width direction W relative to the size of the capacitor, thereby making it possible to create a multilayer ceramic capacitor that is smaller in size and has a larger capacity than conventional ones.

[0031] In such a multilayer ceramic capacitor 10, the density, or in other words, porosity, may differ between the main surface 10b and the side surface 10c due to differences in thickness or materials between the dielectric layer 13 on the main surface 10b and the additional dielectric portion 15 on the side surface 10c. The density is "100 (volume %) - porosity (volume %)," where "porosity (volume %)" refers to the average value of 20 or more measurements of the pore area observed within a 10 μm x 10 μm plane when the polished cross-section of the sintered element is observed with a scanning electron microscope (SEM). By increasing the number of measurements, it is possible to approximate the porosity of the entire sintered element. As described above, there is a correlation between density and porosity, and furthermore, the simplest method for determining the difference in density is to determine the difference in porosity. Therefore, in the following, we will focus on the porosity of the main surface and side surface instead of the density of the main surface and side surface, and consider the difference in density to be equivalent to the difference in porosity.

[0032] For example, according to the thickness and material of the dielectric layer 13 on the main surface 10b described above, the porosity of the main surface 10b is 1% or more and 4% or less. In other words, the compactness of the main surface 10b is 96% or more and 99% or less. Furthermore, according to the thickness and material of the additional dielectric portion 15 on the side surface 10c described above, the porosity of the side surface 10c is 0% or more and 0.5% or less. In other words, the compactness of the side surface 10c is 99.5% or more and 100% or less. This means that the difference between the compactness of the main surface 10b and the compactness of the side surface 10c is 0.5% or more. In other words, there is a difference in compactness, or in other words, porosity, between the main surface 10b and the side surface 10c of the multilayer ceramic capacitor 10 of at least 0.5%. The porosity of the main surface 10b may be 0% or more and 0.5% or less, the porosity of the side surface 10c may be 1% or more and 4% or less, and the difference in density between the main surface 10b and the side surface 10c may be 0.5% or more.

[0033] Furthermore, the respective densities of the two main surfaces 10b, in other words, the porosities, may be approximately the same. Similarly, the respective densities of the two side surfaces 10c, in other words, the porosities, may be approximately the same. Furthermore, the difference in the densities of the two main surfaces 10b may be smaller than the difference between the densities of the main surface 10b and the side surfaces 10c. Similarly, the difference in the densities of the two side surfaces 10c may be smaller than the difference between the densities of the main surface 10b and the side surfaces 10c.

[0034] (Multilayer ceramic capacitor packaging) Next, a multilayer ceramic capacitor packaging body according to this embodiment, which houses the above-mentioned multilayer ceramic capacitor 10, will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view showing the multilayer ceramic capacitor packaging body 100 according to this embodiment, and Fig. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor packaging body 100 shown in Fig. 1. As shown in Fig. 1 and Fig. 2, the multilayer ceramic capacitor packaging body 100 includes a carrier tape 200, a cover tape 300, and a plurality of multilayer ceramic capacitors 10.

[0035] The carrier tape 200 is a long or strip-shaped member. The carrier tape 200 has a plurality of pockets 210 formed thereon at equal intervals in the longitudinal direction. The pockets 210 are recesses for accommodating the multilayer ceramic capacitors 10 and have openings for removing the multilayer ceramic capacitors. The material of the carrier tape 200 is not particularly limited, but resin, paper, or the like may be used.

[0036] A typical multilayer ceramic capacitor carrier tape 200 has 5,000 or more pockets. That is, a typical multilayer ceramic capacitor packaging 100 accommodates 5,000 or more multilayer ceramic capacitors 10. Since the multilayer ceramic capacitors are arranged in a row in this manner, the multilayer ceramic capacitor packaging 100 is sometimes referred to as a multilayer ceramic capacitor string.

[0037] The cover tape 300 is a long or strip-shaped member. The cover tape 300 is attached to the carrier tape 200 so as to cover the openings of the multiple pockets 210. This seals each multilayer ceramic capacitor 10 in each pocket 210. The cover tape 300 is attached to the carrier tape 200 in a releasable manner. The material of the cover tape 300 is not particularly limited, but resin, paper, or the like may be used.

[0038] The plurality of multilayer ceramic capacitors 10 are housed in the plurality of pockets 210 of the carrier tape 200, respectively. Specifically, all of the multilayer ceramic capacitors 10 are arranged so that one of the pair of main surfaces 10b is located on the opening side of the pocket 210. As a result, the difference in density of the surfaces on the opening side of the pocket 210 between adjacent multilayer ceramic capacitors 10 is 0% to 4%, and preferably 0% to 3%. Furthermore, the difference in density of the surfaces on the opening side of the pocket 210 between all of the multilayer ceramic capacitors 10 is within the range of 0% to 4%, and preferably 0% to 3%.

[0039] Alternatively, all of the multilayer ceramic capacitors 10 are arranged so that one of the pair of side surfaces 10c is located on the opening side of the pocket 210. As a result, the difference in density of the surfaces on the opening sides of the pockets 210 between adjacent multilayer ceramic capacitors 10 is 0% or more and 0.5% or less. Furthermore, the difference in density of the surfaces on the opening sides of the pockets 210 is within the range of 0% or more and 0.5% or less for all of the multilayer ceramic capacitors 10.

[0040] In the above-described multilayer ceramic capacitor packaging 100, the multilayer ceramic capacitors 10 are taken out one by one from the pocket 210 of the carrier tape 200 and mounted on a mounting substrate or the like. Specifically, the cover tape 300 is gradually peeled off from the carrier tape 200 in the longitudinal direction. Next, a mounter is used to suction the surface of the multilayer ceramic capacitor 10 through the opening of the pocket 110 of the carrier tape 200, and the multilayer ceramic capacitor 10 is taken out from the pocket 210 of the carrier tape 200. Next, the mounter's suction is released, and the multilayer ceramic capacitor 10 is mounted on a mounting substrate or the like.

[0041] Here, conventionally, when a multilayer ceramic capacitor is mounted on a mounting board or the like using a mounter, the surface of the multilayer ceramic capacitor is attracted by the mounter from the opening side of the pocket, and as a result, when the multilayer ceramic capacitor is removed from the pocket, the surface of the multilayer ceramic capacitor may crack.

[0042] The present inventors have found that one of the causes of this problem is variation in the density of the surface on the opening side of the pocket 210 in the multilayer ceramic capacitor 10, in other words, variation in porosity. More specifically, the present inventors have found that the cause is variation in the density of the main surface and the side surface of the multilayer ceramic capacitor 10 having the above-mentioned side gap portion, in other words, variation in porosity, and variation in whether the surface on the opening side of the pocket 210 in the multilayer ceramic capacitor 10 is the main surface or the side surface.

[0043] The multilayer ceramic capacitor 10 accommodated in the pocket 210 is held by the mounter with a constant suction force. The optimal value of the constant suction force varies depending on the surface density of the multilayer ceramic capacitor 10, i.e., the porosity. If the suction force is set assuming a highly dense surface, i.e., a surface with low porosity, when a less dense surface, i.e., a surface with high porosity, is held with this suction force, the suction force may be too strong and the less dense surface, i.e., the surface with high porosity, may crack. Alternatively, if the mounting force of the mounter is set assuming a highly dense surface, i.e., a surface with low porosity, when mounted with this force, the mounting force may be too strong and the less dense surface, i.e., the surface with high porosity, may crack. Therefore, it is preferable that the surface density, i.e., the porosity, of the opening side of the pocket 210 does not vary.

[0044] Therefore, according to the multilayer ceramic capacitor packaging 100 of this embodiment, the difference in surface density on the opening side of the pocket 210 between adjacent multilayer ceramic capacitors 10 among the plurality of multilayer ceramic capacitors 10 is 0% to 4%, and preferably 0% to 3%. For example, all of the multilayer ceramic capacitors 10 are arranged so that their main surfaces 10b are located on the surface side on the opening side of the pocket 210. Alternatively, all of the multilayer ceramic capacitors 10 are arranged so that their side surfaces 10c are located on the opening side of the pocket 210. This makes the surface density on the opening side of the pocket 210 of the plurality of multilayer ceramic capacitors 10, in other words, the porosity, uniform. Therefore, when the multilayer ceramic capacitors 10 are adsorbed and mounted using a mounter, cracks on the surface of the multilayer ceramic capacitors 10 can be reduced.

[0045] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible. [Explanation of symbols]

[0046] 10 Multilayer ceramic capacitors 11 Body 12 Laminate 13 Dielectric layer 14 Internal electrode layer 15 Additional dielectric section 16 External electrode 100 Multilayer ceramic capacitor packaging 200 Carrier Tape 210 pockets 300 Cover Tape

Claims

1. A multilayer ceramic capacitor package containing a plurality of multilayer ceramic capacitors, a carrier tape having a long shape and a plurality of recessed pockets arranged at equal intervals in the longitudinal direction; a cover tape having an elongated shape and attached to the carrier tape so as to cover the openings of the plurality of pockets; the plurality of multilayer ceramic capacitors housed in the plurality of pockets, respectively; Equipped with a difference in density of the surface on the opening side of the pocket between adjacent multilayer ceramic capacitors among the plurality of multilayer ceramic capacitors is 0% or more and 4% or less; Each of the plurality of multilayer ceramic capacitors is a dielectric made of a ceramic material, a plurality of internal electrodes embedded in the dielectric, and a pair of external electrodes connected to the plurality of internal electrodes; a pair of main surfaces facing each other in a stacking direction of the plurality of internal electrodes, a pair of side surfaces facing each other in a width direction intersecting the stacking direction, and a pair of end surfaces facing each other in a length direction intersecting the stacking direction and the width direction, the pair of end surfaces being provided with the pair of external electrodes; In the plurality of multilayer ceramic capacitors, the surface on the opening side of the pocket is one of the pair of main surfaces, the porosity of the pair of main surfaces of the multilayer ceramic capacitor is 1% or more and 4% or less; Multilayer ceramic capacitor packaging.

2. A multilayer ceramic capacitor package containing a plurality of multilayer ceramic capacitors, a carrier tape having a long shape and a plurality of recessed pockets arranged at equal intervals in the longitudinal direction; a cover tape having an elongated shape and attached to the carrier tape so as to cover the openings of the plurality of pockets; the plurality of multilayer ceramic capacitors housed in the plurality of pockets, respectively; Equipped with a difference in density of the surface on the opening side of the pocket between adjacent multilayer ceramic capacitors among the plurality of multilayer ceramic capacitors is 0% or more and 4% or less; Each of the plurality of multilayer ceramic capacitors is a dielectric made of a ceramic material, a plurality of internal electrodes embedded in the dielectric, and a pair of external electrodes connected to the plurality of internal electrodes; a pair of main surfaces facing each other in a stacking direction of the plurality of internal electrodes, a pair of side surfaces facing each other in a width direction intersecting the stacking direction, and a pair of end surfaces facing each other in a length direction intersecting the stacking direction and the width direction, the pair of end surfaces being provided with the pair of external electrodes; In the plurality of multilayer ceramic capacitors, the surface on the opening side of the pocket is one of the pair of side surfaces, the porosity of the pair of side surfaces of the multilayer ceramic capacitor is 0% or more and 0.5% or less; Multilayer ceramic capacitor packaging.

3. In each of the plurality of multilayer ceramic capacitors, ends of the internal electrodes in the width direction are aligned in the stacking direction so as to be located within a range of 5 μm in the width direction; The difference between the density of the pair of main surfaces and the density of the pair of side surfaces is 0.5% or more. The multilayer ceramic capacitor package according to claim 1 or 2.

4. the number of the plurality of pockets and the number of the plurality of multilayer ceramic capacitors is 5000 or more; In the plurality of multilayer ceramic capacitors, the difference in density of the surfaces on the opening sides of the pockets is within a range of 0% to 4%. The multilayer ceramic capacitor packaging body according to any one of claims 1 to 3.

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