Clock signal generation circuit, DC / DC converter, PWM signal generation device and vehicle

Abstract

To reduce radiation noise.SOLUTION: A clock signal generating circuit comprises: a triangular wave generation circuit (111) configured to generate a triangular wave signal (S111); a pseudo-random number generation circuit (112) configured to generate a pseudo-random number signal (S112); a limiter circuit (113) configured to execute a limitation process of limiting an amount of change per unit time in the pseudo-random number signal and generate the pseudo-random number signal subjected to the limitation process as a limiter signal (S113); a linear arithmetic circuit (114) configured to generate a frequency control signal (S114) by performing a linear arithmetic operation on the triangular wave signal and the limiter signal; and an oscillator (120) configured to generate a clock signal (S122) having a frequency corresponding to the frequency control signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a clock signal generation circuit, a DC / DC converter, a PWM signal generation device, and a vehicle. [Background technology]

[0002] Clock signal generation circuits that generate clock signals are incorporated into various devices. For example, there is a DC / DC converter that performs DC-DC conversion using the frequency of the clock signal as the switching frequency. Most clock signals are rectangular waveform signals with a fixed frequency. However, when the frequency of a clock signal is fixed, the radiation noise at that frequency increases.

[0003] Spread spectrum technology is a technique for suppressing the effects of radiated noise. Spread spectrum technology spreads noise over a wide band, making it possible to substantially suppress the effects of noise. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-153637 Summary of the Invention [Problem to be solved by the invention]

[0005] However, there is room for improvement in current spread spectrum techniques for clock signals.

[0006] An object of the present disclosure is to provide a clock signal generation circuit, a DC / DC converter, a PWM signal generation device, and a vehicle that contribute to reducing radiation noise. [Means for solving the problem]

[0007] The clock signal generation circuit according to the present disclosure includes a triangular wave generation circuit configured to generate a triangular wave signal, a pseudo-random number generation circuit configured to generate a pseudo-random number signal, a limiter circuit configured to perform a limiting process that places a limit on the amount of change in the pseudo-random number signal per unit time and generate the pseudo-random number signal that has undergone the limiting process as a limiter signal, a linear calculation circuit configured to generate a frequency control signal by linearly calculating the triangular wave signal and the limiter signal, and an oscillator configured to generate a clock signal having a frequency corresponding to the frequency control signal.

[0008] Another clock signal generation circuit according to the present disclosure includes a triangular wave generation circuit configured to generate a triangular wave signal, a pseudo-random number generation circuit configured to generate a pseudo-random number signal, a linear operation circuit configured to generate a linear operation result signal by linearly operating the triangular wave signal and the pseudo-random number signal, a limiter circuit configured to perform a limiting process to limit the amount of change in the linear operation result signal per unit time and to generate the linear operation result signal that has undergone the limiting process as a frequency control signal, and an oscillator configured to generate a clock signal having a frequency corresponding to the frequency control signal. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a clock signal generation circuit, a DC / DC converter, a PWM signal generation device, and a vehicle that contribute to reducing radiation noise. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a configuration diagram of a DC / DC converter according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a waveform diagram of a triangular wave signal according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a waveform diagram of a pseudorandom number signal according to the first embodiment of the present disclosure. [Figure 4]FIG. 4 is a diagram illustrating the operation of the limiter circuit according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating the operation of the limiter circuit according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating the operation of the limiter circuit according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a waveform diagram of a frequency control signal according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing the power spectrum of radiation noise according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a configuration diagram of a DC / DC converter according to the second embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating the operation of the limiter circuit according to the second embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram illustrating the operation of the limiter circuit according to the second embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram illustrating the operation of the limiter circuit according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a configuration diagram of a linear feedback register according to a third embodiment of the present disclosure. [Figure 14] FIG. 14 is a configuration diagram of a DC / DC converter according to a fourth embodiment of the present disclosure. [Figure 15] FIG. 15 is an external perspective view of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 16] FIG. 16 is a configuration diagram of a PWM signal generating device according to a fifth embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing a state in which a semiconductor device is installed in a vehicle according to the sixth embodiment of the present disclosure. [Figure 18] FIG. 18 is a configuration diagram of a DC / DC converter according to a first reference example. [Figure 19] FIG. 19 is a configuration diagram of a DC / DC converter according to a second reference example. [Figure 20]FIG. 20 is a diagram showing the power spectrum of radiation noise according to the first reference example. [Figure 21] FIG. 21 is a diagram showing the power spectrum of radiation noise according to the second reference example. [Figure 22] FIG. 22 is a configuration diagram of a DC / DC converter according to a third reference example. [Figure 23] FIG. 23 is a diagram for explaining the reason why the frequency of the generated clock signal is unevenly distributed in a part of the modulation region according to the fourth reference example. DETAILED DESCRIPTION OF THE INVENTION

[0011] <<Reference example>> 18 shows the configuration of a DC / DC converter 1100 according to a first reference example. The DC / DC converter 1110 includes an oscillator 1110 and a power conversion circuit 1120. In each of the reference examples including the first reference example, the oscillator is considered to be included in the components of the DC / DC converter, but it is also possible to consider that the oscillator is connected to the DC / DC converter, in which case it can be understood that the power conversion circuit itself corresponds to the DC / DC converter.

[0012] In the converter 1100, a fixed-frequency rectangular wave signal 1112 output from an oscillator 1110 is supplied as a clock signal to a power conversion circuit 1120. The power conversion circuit 1120 switches an input voltage Vin using the frequency of the clock signal as a switching frequency, thereby generating an output voltage Vout. The input voltage Vin and the output voltage Vout are different DC voltages. In the configuration of FIG. 18, large noise occurs at the frequency of the clock signal, and this noise causes deterioration of EMI (Electro Magnetic Interference) characteristics.

[0013] FIG. 19 shows the configuration of a DC / DC converter 1200 according to a second reference example. The converter 1200 includes an SSCG control circuit 1210, an oscillator 1220, and a power conversion circuit 1230. The power conversion circuit 1230 is the same circuit as the power conversion circuit 1120 shown in FIG. 18. A triangular wave signal 1212 is output from a triangular wave generating circuit 1211 provided in the control circuit 1210. The triangular wave signal 1212 is a digital triangular wave signal. The oscillator 1220 supplies a clock signal 1222 having a frequency corresponding to the triangular wave signal 1212 to the power conversion circuit 1230. The oscillator 1220 includes a DAC (digital-analog converter) that receives the triangular wave signal 1212, and the frequency of the clock signal 1222 is determined based on the output of the DAC. By modulating the frequency of the clock signal 1222 based on the triangular wave signal 1212, radiation noise at the switching frequency is reduced in the second reference example compared to the first reference example. However, in the second reference example, new noise occurs at the frequency of the triangular wave and the frequency of the harmonics of the triangular wave, which becomes a new cause of deterioration in EMI characteristics.

[0014] Fig. 20 shows a power spectrum SPC1 of the radiation noise generated in the DC / DC converter 1100, and Fig. 21 shows a power spectrum SPC2 of the radiation noise generated in the DC / DC converter 1200. Here, it is assumed that the switching frequency is fixed at approximately 4.5 MHz (megahertz) in the first reference example, and that the center frequency of the clock signal is set to approximately 4.5 MHz in the second reference example. It is also assumed that the frequency of the triangular wave is set to approximately 1 kHz (kilohertz).

[0015] 20 and 21, a dashed line 2100 indicating a specific power is shown for convenience. Dashed line 2210 shown in FIG. 21 corresponds to the power of the frequency component of the triangular wave in spectrum SPC2. Dashed line 2220 corresponds to the power of the first harmonic component of the triangular wave in spectrum SPC2. Dashed lines 2210 and 2220 will be referred to later. In comparison with the first reference example, it can be seen that noise near the center frequency of the clock signal is reduced in the second reference example. On the other hand, it can be seen that new noise (corresponding to dashed oval portions 2110 and 2120 in FIG. 21) is generated at the frequency of the triangular wave and the frequencies of the harmonics of the triangular wave in the second reference example.

[0016] FIG. 22 shows the configuration of a DC / DC converter 1300 according to a third reference example. The converter 1300 includes an SSCG control circuit 1310, an oscillator 1320, and a power conversion circuit 1330. The power conversion circuit 1330 is similar to the power conversion circuit 1120 shown in FIG. 18. A pseudorandom number signal 1312 representing a digital pseudorandom number is output from a pseudorandom number generation circuit 1311 provided in the control circuit 1310. The oscillator 1320 supplies a clock signal 1322 having a frequency corresponding to the pseudorandom number signal 1312 to the power conversion circuit 1330. The oscillator 1320 includes a DAC that receives the pseudorandom number signal 1312, and the frequency of the clock signal 1322 is determined based on the output of the DAC. Therefore, the frequency of the clock signal 1322 is modulated based on the pseudorandom number signal 1312. Therefore, in comparison with the second reference example, the third reference example can reduce noise at the frequency of the triangular wave and the frequencies of the harmonics of the triangular wave.

[0017] However, in the third reference example, the input value to the DAC changes randomly within the range of values ​​that the pseudo-random number can take. This can cause the input value to the DAC to fluctuate greatly instantaneously, resulting in the frequency of the clock signal 1322 fluctuating greatly instantaneously. The sudden fluctuation in the frequency of the clock signal can cause an increase in noise.

[0018] By limiting the amount of change per input value to the DAC, it is possible to suppress noise factors. However, when this limit is applied, there is a concern that the frequency of the generated clock signal may be unevenly distributed in a certain region within the modulation region. The third reference example (FIG. 22) to which this limit is applied is referred to as the fourth reference example, and the uneven distribution will be explained focusing on the fourth reference example.

[0019] 23, a polygonal line 1410 represents the time-series change in the input value to the DAC in the fourth reference example. Since the clock signal has a frequency that corresponds to the input value to the DAC, the polygonal line 1410 can also be said to represent the time-series change in the frequency of the clock signal in the fourth reference example.

[0020] The range of values ​​that a pseudo-random number can take corresponds to the modulation region of the clock signal frequency. Essentially, the input value to a DAC changes randomly within the range of values ​​that the pseudo-random number can take. However, if a limit is placed on the amount of change per input value to a DAC, the input value to the DAC tends to be unevenly distributed within a portion of the above range. This corresponds to the frequency of the clock signal tending to be unevenly distributed within a certain region within the modulation region.

[0021] As a specific example, consider a case where a pseudorandom number has a value within a numerical range of 1 to 255, and the frequency of the clock signal increases from a first frequency to a second frequency as the pseudorandom number value increases from 1 to 255. In this case, if the amount of change per input value to the DAC is limited to 10 or less, and the initial input value to the DAC is 128, the next input value to the DAC will fall within the range of 128 ± 10. The input value to the DAC will continue to fluctuate within ±10. Depending on the pseudorandom number generation conditions, the input value to the DAC may be near 1 or near 255, but probabilistically, the input value to the DAC will tend to be biased toward the initial value (128). This bias reduces the spread of the clock signal frequency, resulting in poor EMI performance.

[0022] <<Proposed technology compared with reference example>> Taking these into consideration, the applicant has developed a method of combining modulation by a triangular wave and modulation by a pseudo-random number, and then limiting the amount of modulation.

[0023] Hereinafter, examples of embodiments of the present disclosure relating to this technique will be described in detail with reference to the drawings. In each of the referenced drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or reference numerals referring to information, signals, physical quantities, elements, or parts, and may omit or abbreviate the names of the information, signals, physical quantities, elements, or parts corresponding to the symbols or reference numerals. For example, the triangular wave signal referred to by "S111" (see FIG. 1) described below may be written as triangular wave signal S111 or abbreviated as signal S111, but they all refer to the same thing.

[0024] An explanation will be provided for some terms used in describing the embodiments of the present disclosure. Ground refers to a reference conductive portion having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductive portion is formed of a conductor such as metal. The 0V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a change from a low level to a high level is called an up edge (or rising edge), and a change from a high level to a low level is called a down edge (or falling edge).

[0025] For any transistor configured as a FET (field-effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0026] Hereinafter, the on and off states of any transistor may be simply expressed as on and off. Connections between multiple parts that form a circuit, such as any circuit elements, wiring (lines), and nodes, may be understood to refer to electrical connections unless otherwise specified.

[0027] <<First Embodiment>> A first embodiment of the present disclosure will be described. Fig. 1 is a configuration block diagram of a DC / DC converter (DC / DC conversion device) 100 according to the first embodiment. The DC / DC converter 100 includes a control circuit 110, which is a control circuit for an SSCG (Spread Spectrum Clock Generator), an oscillator 120, and a power conversion circuit 130. The control circuit 110 and the oscillator 120 form a clock signal generation circuit that generates a frequency-spread clock signal. Here, it is considered that the clock signal generation circuit and the power conversion circuit 130 form a DC / DC converter, but it may also be considered that the power conversion circuit 130 itself is a DC / DC converter, and the clock signal generation circuits (110, 120) are connected to the DC / DC converter.

[0028] The control circuit 110 includes a triangular wave generating circuit 111 , a pseudo-random number generating circuit 112 , a limiter circuit 113 , and a linear arithmetic circuit 114 .

[0029] The triangular wave generating circuit 111 generates and outputs a triangular wave signal S111. The triangular wave signal S111 is a digital signal that indicates a triangular wave, and therefore the value of the triangular wave signal S111 is a digital value. Figure 2 shows the waveform of the triangular wave signal S111. The minimum and maximum values ​​of the triangular wave signal S111 are represented by LL1 and HH1, respectively. The maximum value HH1 is greater than the minimum value LL1. The triangular wave generating circuit 111 performs the following triangular wave generating unit operation at a predetermined period P TRI Repeatedly execute.

[0030] In a triangular wave generating unit operation, the triangular wave generating circuit 111 starts from a state in which the value of the triangular wave signal S111 coincides with a predetermined minimum value LL1, and monotonically increases the value of the triangular wave signal S111 linearly at a predetermined increase rate from the minimum value LL1 to a predetermined maximum value HH1. In the triangular wave generating unit operation, when the value of the triangular wave signal S111 reaches the maximum value HH1, the triangular wave generating circuit 111 monotonically decreases the value of the triangular wave signal S111 linearly at a predetermined decrease rate from the maximum value HH1 to the minimum value LL1. Thereafter, the above-described triangular wave generating unit operation is repeated. One triangular wave generating unit operation is performed in a period P TRI Since this takes place over a period of 1 / 5 minutes, the frequency of the triangular wave signal S111 is (1 / P TRI )

[0031] The pseudorandom number generating circuit 112 generates and outputs a pseudorandom number signal S112. The pseudorandom number signal S112 is a digital signal indicating a pseudorandom number, and therefore the value of the pseudorandom number signal S112 is a digital value. The pseudorandom number generating circuit 112 can be configured by a linear feedback shift register. Figure 3 shows an example of the waveform of the pseudorandom number signal S112. The pseudorandom number generating circuit 112 generates and outputs a pseudorandom number signal S112 at a predetermined period P PR The value of the pseudorandom signal S112 is updated with a period P PR is the period P TRI The update period of the value of the triangular wave signal S111 is a period P PR or the period P PR It may be m times or (1 / m) times of , where m is an integer of 2 or more.

[0032] Period PPR The time corresponding to the length will be hereinafter referred to as unit time P PR Sometimes, the pseudo-random number generation circuit 112 updates and outputs the value of the pseudo-random number signal S112 at the period of unit time P PR (that is, every time unit time P PR elapses). It can be said that the minimum value and the maximum value in the value of the pseudo-random number signal S112 are represented by LL2 and HH2, respectively. The maximum value HH2 is larger than the minimum value LL2. The pseudo-random number generation circuit 112 generates a pseudo-random number having a value within the range from the minimum value LL2 to the maximum value HH2, and generates and outputs a pseudo-random number signal S112 having the value of the generated pseudo-random number.

[0033] [[ID=ll]]The pseudo-random number signal S112 output from the pseudo-random number generation circuit 112 is input to the limiter circuit 113. The limiter circuit 113 executes a limiting process on the input pseudo-random number signal S112, and generates and outputs the pseudo-random number signal S112 that has undergone the limiting process as a limiter signal S113. Similar to the pseudo-random number signal S112, the limiter signal S113 is also a digital signal. The limiter circuit 113 updates and outputs the value of the limiter signal S113 every time the value of the pseudo-random number signal S112 is updated (therefore, at the period of unit time P PR ).

[0034] The limiting process by the limiter circuit 113 is a process of adding a limit to the amount of change of the pseudo-random number signal S112 per unit time P PR . The amount of change per unit time P of the pseudo-random number signal S112 output from the pseudo-random number generation circuit 112 is at most (HH2 - LL2). In the limiting process by the limiter circuit 113, the magnitude of the amount of change of the pseudo-random number signal S112 per unit time P PR is limited to be not more than a predetermined limit value LIM, and the pseudo-random number signal S112 after the limitation is output as the limiter signal S113. Here, “0 < LIM < HH2 - LL2” holds.

[0035] ​​The limiting process will now be explained. The value of the nth pseudorandom number signal S112 output from the pseudorandom number generation circuit 112 is represented by "S112[n]", and the value of the nth limiter signal S113 output from the limiter circuit 113 is represented by "S113[n]" (see FIG. 4). n is an arbitrary natural number. The limiter circuit 113 generates a value S113[n] based on the value S112[n]. The relationship between the value S112[n+1] and the value S113[n+1] will be explained assuming a case CS1 in which "S112[n]=S113[n]" holds for the values ​​of the nth signals S112 and S113.

[0036] As shown in FIG. 4, in case CS1, when the first inequality "|S112[n+1]-S112[n]|≦LIM" is satisfied, "S113[n+1]=S112[n+1]". When the first inequality is satisfied, the unit time P PR Since the magnitude of the change in the pseudo-random number signal S112 in a hit is equal to or less than the limit value LIM, no particular limit is imposed. Note that in case CS1, the first inequality is equivalent to the inequality "|S112[n+1]-S113[n]|≦LIM".

[0037] As shown in FIG. 5, when the second inequality "(S112[n+1]-S112[n])>LIM" is satisfied in case CS1, "S113[n+1]=S113[n]+LIM" is satisfied. As shown in FIG. 6, when the third inequality "(S112[n]-S112[n+1])>LIM" is satisfied in case CS1, "S113[n+1]=S113[n]-LIM" is satisfied. When the second or third inequality is satisfied, the unit time P PR A limit is imposed because the magnitude of the change in the pseudorandom number signal S112 in a hit exceeds the limit value LIM. Note that in case CS1, the second inequality is equivalent to the inequality "(S112[n+1]-S113[n])>LIM", and the third inequality is equivalent to the inequality "(S113[n]-S112[n+1])>LIM".

[0038] The limiting process by the limiter circuit 113 does not limit the amount of change in the signal S112 when it is generated by the circuit 112, but limits the amount of change in the signal S112 after it is output from the circuit 112. Therefore, the unit time P PR While the amount of change in the signal S112 per unit time P may exceed the limit value LIM, PR The amount of change in the signal S113 per unit time P is equal to or less than the limit value LIM. PR It can be said that the limiter signal S113 is generated as a signal in which the amount of change in the unit time P is limited to a limit value LIM or less. PR The amount of change per unit time P PR It corresponds to the magnitude (absolute value) of the change in hit.

[0039] Referring again to FIG. 1, the triangular wave signal S111 output from the triangular wave generating circuit 111 and the limiter signal S113 output from the limiter circuit 113 are input to the linear arithmetic circuit 114. The linear arithmetic circuit 114 generates a frequency control signal S114 by linearly calculating the triangular wave signal S111 and the limiter signal S113. The generated frequency control signal S114 is output to the oscillator 120. The linear arithmetic circuit 114 calculates a frequency control signal S114 over a unit time P PR The value of the frequency control signal S114 is updated and output every 10 seconds.

[0040] Here, it is assumed that the linear operation performed by the linear operation circuit 114 is addition. In this case, in the linear operation, the linear operation circuit 114 adds one of the triangular wave signal S111 and the limiter signal S113 to the other, and generates and outputs the addition result as the frequency control signal S114. The frequency control signal S114 is a digital signal, and at any timing, the value of the frequency control signal S114 is represented by the sum of the value of the triangular wave signal S111 and the value of the limiter signal S113. However, if this sum exceeds the maximum value of the numerical range that can be expressed by the frequency control signal S114 (if a so-called overflow occurs), the value of the frequency control signal S114 is set to this maximum value.

[0041] 7 shows an example of the frequency control signal S114. While having the characteristics of the triangular wave signal S111 and the pseudo-random number signal S112, the amount of change per time (unit time T PR A signal with a limited amount of change in the frequency (or per unit time) is generated as the frequency control signal S114.

[0042] The oscillator 120 includes a DAC 121 and a VCO 122, and generates and outputs a clock signal (a clock signal S122 described below) having a frequency according to the frequency control signal S114.

[0043] The DAC121 is a digital-to-analog converter. The frequency control signal S114 output from the linear arithmetic circuit 114 is input to the DAC121. The DAC121 performs a DA conversion process (digital-to-analog conversion process) to convert the input digital signal into an analog signal. Therefore, the DAC121 converts the digital frequency control signal S114 into an analog frequency control signal S121 through the DA conversion process and outputs it. The frequency control signal S121 is a voltage signal, and has an analog voltage value according to the value of the frequency control signal S114. The execution cycle of the DA conversion process in the DAC121 is a period P PR It can be the same as:

[0044] The frequency control signal S121 output from the DAC 121 is input to the VCO 122. The VCO 122 is a voltage-controlled oscillator. The VCO 122 converts the frequency control signal S121 to a frequency f122 and generates and outputs a clock signal S122 having the frequency f122. The clock signal S122 is a signal that alternates between high and low levels. The frequency f122 increases as the voltage value of the frequency control signal S121 increases and decreases as the voltage value of the frequency control signal S121 decreases. The frequency f122 is modulated (spread) in accordance with the voltage value of the frequency control signal S121, with the center frequency of the clock signal S122 as the reference. Note that the amount of change in the frequency f122 per unit change in the voltage value of the frequency control signal S121 may be constant throughout the entire range of change of the frequency f122.

[0045] The power conversion circuit 130 receives an input voltage V from a voltage source (not shown). IN When the input voltage V IN is converted to DC / DC to produce the output voltage V OUT Generates and outputs the input voltage V IN and output voltage V OUT are DC voltages having different voltage values. A clock signal S122 is input to the power conversion circuit 130. The DC / DC converter 100 is a switching regulator, and the power conversion circuit 130 uses the frequency of the clock signal S122 as a switching frequency to regulate the input voltage V IN By switching the output voltage V OUT get.

[0046] Fig. 8 shows the power spectrum SPC3 of the radiation noise generated in the DC / DC converter 100. Here, as in the above-mentioned reference examples, it is assumed that the center frequency of the clock signal is set to approximately 4.5 MHz. It is also assumed that the frequency of the triangular wave signal S111 is set to approximately 1 kHz (kilohertz). The dashed lines 2210 and 2220 shown in Fig. 8 are the same as those shown in Fig. 21 and are provided for comparison between Fig. 8 and Fig. 21.

[0047] As can be seen from a comparison between FIG. 8 and FIG. 21, the power of the triangular wave frequency component and the triangular wave harmonic component in the power spectrum of the radiated noise is reduced in the configuration of this embodiment compared to the fourth reference example described above. It is also clear that the power near the switching frequency is reduced compared to each reference example. As described above, according to this embodiment, the frequency of the clock signal can be effectively spread, thereby reducing radiated noise. In this case, radiated noise caused by modulation by the triangular wave can be suppressed, and radiated noise that may occur due to abrupt changes in the value of the pseudorandom number can also be suppressed.

[0048] [Example EX1_1] An example EX1_1 belonging to the first embodiment will be described. The linear calculation by the linear calculation circuit 114 may be subtraction. In this case, in the linear calculation, the linear calculation circuit 114 subtracts one of the triangular wave signal S111 and the limiter signal S113 from the other, and generates and outputs the subtraction result as the frequency control signal S114. Basically, it is sufficient to subtract the limiter signal S113 from the triangular wave signal S111. In the following, when the linear calculation is subtraction, it is assumed that the limiter signal S113 is subtracted from the triangular wave signal S111 (the same applies to example EX1_2 described later). At any timing, the value of the frequency control signal S114 is the difference between the triangular wave signal S111 and the limiter signal S113, and this difference is a value obtained by subtracting the value of the limiter signal S113 from the value of the triangular wave signal S111. However, if the difference falls below the minimum value of the range of values ​​that can be expressed by the frequency control signal S114 (if a so-called underflow occurs), the value of the frequency control signal S114 is set to the minimum value.

[0049] [Example EX1_2] An example EX1_2 belonging to the first embodiment will be described. In the example EX1_2, a specific example regarding the signals S111 to S114 will be given.

[0050] In Example EX1_2, the triangular wave signal S111 is an 8-bit digital signal, and the pseudo-random number signal S112 is a 4-bit digital signal. Therefore, in decimal notation, the triangular wave signal S111 has an integer value of 0 or more and 255 or less, and the pseudo-random number signal S112 has an integer value of 0 or more and 15 or less in decimal notation. That is, (LL1, HH1) = (0, 255) and (LL2, HH2) = (0, 15) (FIG. 2 and FIG. 3). However, the number of bits of each of the triangular wave signal S111 and the pseudo-random number signal S112 can be arbitrarily deformed. "LL2 = 1" may also be used.

[0051] The limit value LIM in the limiter circuit 113 satisfies "0 < LIM < HH2 - LL2", and as an example, "LIM = 8". In the case of "LIM = 8", the change amount of the limiter signal S113 per unit time P PR That is, the change amount per hit of the limiter signal S113, that is, the change amount per hit in the value of the limiter signal S113, is limited to 8 or less.

[0052] In Example EX1_2, the frequency control signal S114 is an 8-bit digital signal. Therefore, in decimal notation, the frequency control signal S114 has an integer value of 0 or more and 255 or less. That is, the numerical range that can be expressed by the frequency control signal S114 is in the range of 0 or more and 255 or less.

[0053] When the linear operation in the linear operation circuit 114 is addition, the linear operation circuit 114 adds one of the triangular wave signal S111 and the limiter signal S113 to the other, and generates and outputs the addition result as the frequency control signal S114. When the sum of the value of the triangular wave signal S111 and the value of the limiter signal S113 exceeds the maximum value (here, 255) of the numerical range that can be expressed by the frequency control signal S114, the value of the frequency control signal S114 is set to the maximum value.

[0054] When the linear operation in linear operation circuit 114 is subtraction, linear operation circuit 114 subtracts one of triangular wave signal S111 and limiter signal S113 from the other, and generates and outputs the subtraction result as frequency control signal S114. When the difference between triangular wave signal S111 and limiter signal S113 (more specifically, the value obtained by subtracting the value of limiter signal S113 from the value of triangular wave signal S111) is below the minimum value (0 in this case) of the range of values ​​that can be expressed by frequency control signal S114, the value of frequency control signal S114 is set to that minimum value.

[0055] The number of bits of the frequency control signal S114 can be changed arbitrarily, and the number of bits of the frequency control signal S114 may be greater than the number of bits of the triangular wave signal S111.

[0056] <<Second embodiment>> A second embodiment of the present disclosure will now be described. Fig. 9 is a configuration block diagram of a DC / DC converter (DC / DC conversion device) 200 according to the second embodiment. The DC / DC converter 200 includes a control circuit 210, which is a control circuit for an SSCG (Spread Spectrum Clock Generator), an oscillator 220, and a power conversion circuit 230. The control circuit 210 and the oscillator 220 form a clock signal generation circuit that generates a clock signal that has been frequency spread. Here, it is considered that the clock signal generation circuit and the power conversion circuit 230 form a DC / DC converter, but it may also be considered that the power conversion circuit 230 itself is a DC / DC converter, and the clock signal generation circuits (210, 220) are connected to the DC / DC converter.

[0057] The control circuit 210 includes a triangular wave generating circuit 211 , a pseudo-random number generating circuit 212 , a linear arithmetic circuit 213 , and a limiter circuit 214 .

[0058] The triangular wave generating circuit 211 generates and outputs a triangular wave signal. The triangular wave generating circuit 211 is the same as the triangular wave generating circuit 111 (see FIG. 1) shown in the first embodiment. However, the triangular wave signal generated by the triangular wave generating circuit 211 and output from the triangular wave generating circuit 211 will be referred to as a triangular wave signal S211. The triangular wave signal S211 is a signal having the same characteristics as the triangular wave signal S111 shown in the first embodiment, and therefore has a predetermined period P TRI The value fluctuates between a minimum value LL1 and a maximum value HH1 (see FIG. 2).

[0059] The pseudorandom number generation circuit 212 generates and outputs a pseudorandom number signal. The pseudorandom number generation circuit 212 is the same as the pseudorandom number generation circuit 112 shown in the first embodiment (see FIG. 1). However, the pseudorandom number signal generated by and output from the pseudorandom number generation circuit 212 is referred to as a pseudorandom number signal S212. The pseudorandom number signal S212 is a signal having the same characteristics as the pseudorandom number signal S112 shown in the first embodiment, and therefore the minimum and maximum values ​​of the pseudorandom number signal S212 are LL2 and HH2, respectively (see FIG. 3). The pseudorandom number generation circuit 212 generates and outputs a pseudorandom number signal S212 over a unit time P PR period (i.e., unit time P PR The value of the pseudorandom number signal S212 is updated and output every time the time elapses.

[0060] The linear calculation circuit 213 receives the triangular wave signal S211 output from the triangular wave generation circuit 211 and the pseudo-random number signal S212 output from the pseudo-random number generation circuit 212. The linear calculation circuit 213 performs a linear calculation on the triangular wave signal S211 and the pseudo-random number signal S212 to generate a linear calculation result signal S213. The generated linear calculation result signal S213 is output to the limiter circuit 214. The linear calculation circuit 213 updates the value of the linear calculation result signal S213 every time the value of the pseudo-random number signal S212 is updated. That is, the linear calculation circuit 213 updates the value of the linear calculation result signal S213 every time the value of the pseudo-random number signal S212 is updated. PR The value of the linear operation result signal S213 is updated and output every .

[0061] Here, it is assumed that the linear operation performed by the linear operation circuit 213 is an addition. In this case, in the linear operation, the linear operation circuit 213 adds one of the triangular wave signal S211 and the pseudo-random number signal S212 to the other, and generates and outputs the addition result as the linear operation result signal S213. The linear operation result signal S213 is a digital signal, and at any timing, the value of the linear operation result signal S213 is represented by the sum of the value of the triangular wave signal S211 and the value of the pseudo-random number signal S212. However, if this sum exceeds the maximum value of the range of values ​​that can be expressed by the linear operation result signal S213 (if a so-called overflow occurs), the value of the linear operation result signal S213 is set to this maximum value.

[0062] The limiter circuit 214 receives the linear operation result signal S213 output from the linear operation circuit 213. The limiter circuit 214 performs a limiting process on the input linear operation result signal S213, and generates and outputs the linear operation result signal S213 that has undergone the limiting process as a signal S214. The signal S214 is a frequency control signal. However, following the first embodiment, the signal S214 can also be called a limiter signal. Like the linear operation result signal S213, the frequency control signal S214 is also a digital signal. The limiter circuit 214 updates the value of the frequency control signal S214 every time the value of the linear operation result signal S213 is updated. That is, the limiter circuit 214 updates the value of the frequency control signal S214 every time the value of the linear operation result signal S213 is updated. PR The value of the frequency control signal S214 is updated and output every 10 seconds.

[0063] The limiting process by the limiter circuit 214 is performed in a unit time P PR This is a process of limiting the amount of change in the linear operation result signal S213 per unit time P PR If it is assumed that the value of the signal S211 is constant, the amount of change in the hit is at most (HH2-LL2). PRThe amount of change in the linear operation result signal S213 per hit is limited to be no greater than a predetermined limit value LIM, and the linear operation result signal S213 after this limitation is output as the frequency control signal S214. Here, "0 < LIM < HH2 - LL2" holds.

[0064] An explanation of the limiting process will be added. Let the value of the n-th linear operation result signal S213 output from the linear operation circuit 213 be represented by "S213[n]", and the value of the n-th frequency control signal S214 output from the limiter circuit 214 be represented by "S214[n]" (see FIG. 10). n is an arbitrary natural number. The limiter circuit 214 generates the value S214[n] based on the value S213[n]. Assuming a case CS2 where "S213[n] = S214[n]" holds for the values of the n-th signals S213 and S214, the relationship between the value S213[n + 1] and the value S214[n + 1] will be explained.

[0065] As shown in FIG. 10, in case CS2, when the fourth inequality "|S213[n + 1] - S213[n]| ≦ LIM" holds, then "S214[n + 1] = S213[n + 1]". When the fourth inequality holds, per unit time P PR Since the amount of change in the linear operation result signal S213 per hit is no greater than the limit value LIM, no particular limitation is imposed. Incidentally, in case CS2, the fourth inequality is equivalent to the inequality "|S213[n + 1] - S214[n]| ≦ LIM".

[0066] As shown in FIG. 11, in case CS2, when the fifth inequality "(S213[n + 1] - S213[n]) > LIM" holds, then "S214[n + 1] = S214[n] + LIM". As shown in FIG. 12, in case CS2, when the sixth inequality "(S213[n] - S213[n + 1]) > LIM" holds, then "S214[n + 1] = S214[n] - LIM". When the fifth or sixth inequality holds, per unit time P PRThe change in the linear operation result signal S213 at the hit exceeds the limit value LIM, so a limit is imposed. Note that in case CS2, the fifth inequality is equivalent to the inequality "(S213[n+1]-S214[n])>LIM", and the sixth inequality is equivalent to the inequality "(S214[n]-S213[n+1])>LIM".

[0067] The limiting process by the limiter circuit 214 does not limit the amount of change in the signal S213 when it is generated by the circuit 213, but limits the amount of change in the signal S213 after it is output from the circuit 213. Therefore, the unit time P PR While the amount of change in the signal S213 per unit time P may exceed the limit value LIM, PR Therefore, the limiter circuit 214 is configured to limit the signal S214 that is based on the output of the linear operation circuit 213 (i.e., the signal based on the linear operation result signal S213 output from the linear operation circuit 213) and that is PR It can be said that a signal in which the amount of change per unit time P is limited to a limit value LIM or less is generated as the frequency control signal S214. PR The amount of change per unit time P PR It corresponds to the magnitude (absolute value) of the change in hit.

[0068] The frequency control signal S214 is a signal similar to the frequency control signal S114 shown in Fig. 7. While having the characteristics of the triangular wave signal S211 and the pseudo-random number signal S212, the amount of change per time (unit time T PR A signal with a limited perturbation (amount of change per perturbation) is generated as the frequency control signal S214.

[0069] The oscillator 220 includes a DAC 221 and a VCO 222, and generates and outputs a clock signal (a clock signal S222 described below) having a frequency according to the frequency control signal S214. The DAC 221 and the VCO 222 may be the same as the DAC 121 and the VCO 122 (see FIG. 1) shown in the first embodiment, but the operation and configuration of the DAC 221 and the VCO 222 will be described in relation to the frequency control signal S214.

[0070] The DAC221 is a digital-to-analog converter. The frequency control signal S214 output from the linear arithmetic circuit 214 is input to the DAC221. The DAC221 performs a DA conversion process (digital-to-analog conversion process) to convert the input digital signal into an analog signal. Therefore, the DAC221 converts the digital frequency control signal S214 into an analog frequency control signal S221 through the DA conversion process and outputs it. The frequency control signal S221 is a voltage signal, and has an analog voltage value according to the value of the frequency control signal S214. The execution cycle of the DA conversion process in the DAC221 is a period P PR It can be the same as:

[0071] The frequency control signal S221 output from the DAC221 is input to the VCO222. The VCO222 is a voltage controlled oscillator. The VCO222 converts the frequency control signal S221 to a frequency f222 and generates and outputs a clock signal S222 having the frequency f222. The clock signal S222 is a signal that alternates between high and low levels. The frequency f222 increases as the voltage value of the frequency control signal S221 increases and decreases as the voltage value of the frequency control signal S221 decreases. The frequency f222 is modulated (spread) in accordance with the voltage value of the frequency control signal S221, with the center frequency of the clock signal S222 as the reference. Note that the amount of change in the frequency f222 per unit change in the voltage value of the frequency control signal S221 may be constant throughout the entire range of change of the frequency f222.

[0072] The power conversion circuit 230 receives an input voltage V from a voltage source (not shown).IN The input voltage V IN is converted to DC / DC to produce the output voltage V OUT Generates and outputs the input voltage V IN and output voltage V OUT are DC voltages having different voltage values. A clock signal S222 is input to the power conversion circuit 230. The DC / DC converter 200 is a switching regulator, and the power conversion circuit 230 uses the frequency of the clock signal S222 as a switching frequency to convert the input voltage V IN By switching the output voltage V OUT get.

[0073] The configuration according to the second embodiment also provides the same functions and effects as the first embodiment.

[0074] [Example EX2_1] An example EX2_1 belonging to the second embodiment will be described. The linear calculation by the linear calculation circuit 213 may be subtraction. In this case, in the linear calculation, the linear calculation circuit 213 subtracts one of the triangular wave signal S211 and the pseudo-random number signal S212 from the other, and generates and outputs the subtraction result as a linear calculation result signal S213. Basically, it is sufficient to subtract the pseudo-random number signal S212 from the triangular wave signal S211. In the following, when the linear calculation is subtraction, it is assumed that the pseudo-random number signal S212 is subtracted from the triangular wave signal S211 (the same applies to example EX2_2 described later). At any timing, the value of the linear calculation result signal S213 is the difference between the triangular wave signal S211 and the pseudo-random number signal S212, and this difference is a value obtained by subtracting the value of the pseudo-random number signal S212 from the value of the triangular wave signal S211. However, if the difference falls below the minimum value of the range of values ​​that can be expressed by the linear operation result signal S213 (if a so-called underflow occurs), the value of the linear operation result signal S213 is set to the minimum value.

[0075] [Example EX2_2] An example EX2_2 belonging to the second embodiment will be described. In the example EX2_2, a specific example regarding the signals S211 to S214 will be given.

[0076] In Example EX2_2, the triangular wave signal S211 is an 8-bit digital signal, and the pseudo-random number signal S212 is a 4-bit digital signal. Therefore, in decimal notation, the triangular wave signal S211 has an integer value between 0 and 255, and the pseudo-random number signal S212 has an integer value between 0 and 15, inclusive. That is, (LL1, HH1) = (0, 255) and (LL2, HH2) = (0, 15). However, the number of bits of the triangular wave signal S211 and the pseudo-random number signal S212 can be changed arbitrarily. LL2 = 1 may also be used.

[0077] In Example EX2_2, the linear operation result signal S213 and the frequency control signal S214 are each an 8-bit digital signal. Therefore, each of the signals S213 and S214 has an integer value in decimal notation between 0 and 255. In other words, the range of values ​​that can be expressed by the signal S213 and the signal S214 is between 0 and 255, respectively.

[0078] When the linear operation in the linear operation circuit 213 is addition, the linear operation circuit 213 adds one of the triangular wave signal S211 and the pseudo-random number signal S212 to the other, and generates and outputs the addition result as the linear operation result signal S213. When the sum of the value of the triangular wave signal S211 and the value of the pseudo-random number signal S212 exceeds the maximum value (255 in this case) of the range of values ​​that can be expressed by the linear operation result signal S213, the value of the linear operation result signal S213 is set to that maximum value.

[0079] When the linear operation in the linear operation circuit 213 is subtraction, the linear operation circuit 213 subtracts one of the triangular wave signal S211 and the pseudo-random number signal S212 from the other, and generates and outputs the subtraction result as a linear operation result signal S213. When the difference between the triangular wave signal S211 and the pseudo-random number signal S212 (more specifically, the value obtained by subtracting the value of the pseudo-random number signal S212 from the value of the triangular wave signal S211) is below the minimum value (0 in this case) of the range of values ​​that can be expressed by the linear operation result signal S213, the value of the linear operation result signal S213 is set to that minimum value.

[0080] The limit value LIM in the limiter circuit 214 satisfies "0 < LIM < HH2 - LL2" and, as an example, is "LIM = 8". When "LIM = 8", the change amount of the frequency control signal S214 per unit time P PR That is, the change amount of the frequency control signal S214 per hit, namely the change amount per hit in the value of the frequency control signal S214, is limited to 8 or less.

[0081] Furthermore, the number of bits of the linear operation result signal S213 can be arbitrarily deformed, and the number of bits of the linear operation result signal S213 may be made larger than the number of bits of the triangular wave signal S211. The same applies to the frequency control signal S214.

[0082] <<Third Embodiment>> The third embodiment of the present disclosure will be described. The pseudo-random number generation circuits 112 and 212 can be formed using any linear feedback register. FIG. 13 shows a pseudo-random number generation circuit 300 as an example of the pseudo-random number generation circuit 112 or 212. The pseudo-random number generation circuit 300 is a linear feedback register including D-type flip-flops (hereinafter referred to as DFFs) 310[1] to 310[8], exclusive OR circuits (hereinafter referred to as XORs) 321 to 323, and an initial value setting unit 330.

[0083] Each DFF has a D input terminal, a Q output terminal, a clock input terminal, and a reset input terminal. The DFF holds the value of the signal supplied to the D input terminal in synchronization with the up edge (or down edge) of the synchronous clock signal input to the clock input terminal. The DFF outputs a signal indicating the held value from the Q output terminal. A common synchronous clock signal (not shown) is supplied to the DFFs 310[1] to 310[8]. The signal output from the Q output terminal of the DFF 310[i] is represented by the symbol "X[i]". The signal X[i] takes a value of "0" or "1". i represents an arbitrary natural number.

[0084] For an integer i that satisfies "1≦i≦7", the output signal X[i] of DFF310[i] is input to the D input terminal of DFF310[i+1]. XOR321 outputs a signal indicating the exclusive OR of the output signal X[4] of DFF310[4] and the output signal X[5] of DFF310[5]. XOR322 outputs a signal indicating the exclusive OR of the output signal of XOR321 and the output signal X[6] of DFF310[6]. XOR323 outputs a signal indicating the exclusive OR of the output signal of XOR322 and the output signal X[8] of DFF310[8]. The output signal of XOR323 is input to the D input terminal of DFF310[1].

[0085] An 8-bit digital signal is formed by signals X[1] to X[8]. In a digital signal of multiple bits, signal X[i+1] indicates the value of the bit higher than signal X[i]. Therefore, in the 8-bit digital signal, signal X[1] indicates the value of the least significant bit, and signal X[8] indicates the value of the most significant bit. The initial value setting unit 330 sets the initial value (here, "1" in decimal notation) of the 8-bit digital signal. An initial value is set for the 8-bit digital signal in response to input of a predetermined start trigger to the pseudorandom number generation circuit 300, and thereafter the value of the 8-bit digital signal is updated at the cycle of the synchronous clock signal. The feedback polynomial in the pseudorandom number generation circuit 300 is "X 8 +X 6 +X 5 +X 4 +1”.

[0086] A digital signal of any number of bits extracted from the above 8-bit digital signal can be used as the pseudorandom number signal S112 or S212 (see FIG. 1 or FIG. 9). For example, when the pseudorandom number signal S112 is a 4-bit digital signal as in the above-mentioned embodiment EX1_2, a digital signal consisting of signals X[1] to X[4] may be used as the pseudorandom number signal S112. Similarly, when the pseudorandom number signal S212 is a 4-bit digital signal as in the above-mentioned embodiment EX2_2, a digital signal consisting of signals X[1] to X[4] may be used as the pseudorandom number signal S212.

[0087] <<Fourth Embodiment>> A fourth embodiment of the present disclosure will be described. In the fourth embodiment, a configuration example of a DC / DC converter using the clock signal generation circuit according to the first or second embodiment will be described.

[0088] 14 is a configuration diagram of a DC / DC converter 400 according to a fourth embodiment. The DC / DC converter 400 converts an input voltage V IN By converting the input voltage V IN Output voltage V OUT It is configured as a step-down DC / DC converter that generates an input voltage V IN and output voltage V OUT is a positive DC voltage. The DC / DC converter 400 has an input voltage V IN is applied to the input terminal IN, and the output voltage V OUT The output terminal OUT to which the voltage is applied, the ground terminal GND having the ground potential, and the switch voltage V SW The ground terminal GND and the switch terminal SW are provided on the lower potential side than the input terminal IN.

[0089] The DC / DC converter 400 includes a clock signal generating circuit 410 , a switching control circuit 420 , an output stage circuit 430 , a rectifying and smoothing circuit 440 , and a feedback voltage generating circuit 450 .

[0090] The clock signal generation circuit 410 supplies a clock signal CLK to the switching control circuit 420. The clock signal generation circuit 410 may include the control circuit 110 and oscillator 120 (see FIG. 1) in the first embodiment, in which case the clock signal S122 from the oscillator 120 becomes the clock signal CLK. Alternatively, the clock signal generation circuit 410 may include the control circuit 210 and oscillator 220 (see FIG. 9) in the second embodiment, in which case the clock signal S222 from the oscillator 220 becomes the clock signal CLK. The circuits 420, 430, 440, and 450 configure a power conversion circuit equivalent to the above-mentioned power conversion circuit 130 or 230 (see FIG. 1 or 9). In the DC / DC converter 400, the power conversion circuit converts an input voltage V IN The output voltage V is switched at a switching frequency according to the clock signal CLK. OUT Generate.

[0091] The DC / DC converter 400 can be configured using a semiconductor device. FIG. 15 shows an example of the appearance of a semiconductor device 480. The semiconductor device 480 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the semiconductor device 480. The semiconductor chip is encapsulated in a housing (package) made of resin to form the semiconductor device 480. The circuits 410, 420, and 430 can be included in the semiconductor integrated circuit. The circuits 440 and 450 may be provided outside the semiconductor device 480. However, the circuit 450 can be provided inside the semiconductor device 480.

[0092] The output stage circuit 430 includes a half-bridge circuit formed of a series circuit of a high-side transistor 431 and a low-side transistor 432. The rectifying and smoothing circuit 440 includes an inductor 441 and an output capacitor 442.

[0093] The DC / DC converter 400 performs DC / DC conversion by synchronous rectification using transistors 431 and 432. The transistors 431 and 432 are configured as N-channel MOSFETs. Note that a modification is also possible in which the transistor 431 is configured as a P-channel MOSFET. Furthermore, the transistor 432 can be replaced with a diode, in which case the DC / DC converter 400 performs DC / DC conversion by asynchronous rectification.

[0094] The drain of the transistor 431 is connected to the input terminal IN, and therefore to the input voltage V IN The source of the transistor 431 and the drain of the transistor 432 are connected together at a switch terminal SW. The source of the transistor 432 is connected to the ground terminal GND (i.e., connected to the ground). The voltage applied to the switch terminal SW is called the switch voltage and is represented by the symbol "V SW The switch terminal SW is connected to one end of the inductor 441, and the other end of the inductor 441 is connected to the output terminal OUT. OUT An output capacitor 442 is connected between the output terminal OUT and the ground.

[0095] In Fig. 14, "LD" represents a load connected between the output terminal OUT and the ground. The load LD is the output voltage V OUT The current flowing through the inductor 441 is called the inductor current and is represented by the symbol "I L " is expressed as

[0096] The feedback voltage generating circuit 450 generates an output voltage V using a series circuit of multiple resistors arranged between the output terminal OUT and ground. OUT The divided voltage is generated and fed back to the feedback voltage V FB to the switching control circuit 420. However, the output voltage V OUT The feedback voltage V FB In this case, the feedback voltage generating circuit 450 is removed from the DC / DC converter 400.

[0097] The switching control circuit 420 controls and sets the state of the output stage circuit 430 to any one of an output high state, an output low state, and a both-off state. In the output high state, the transistor 431 is on and the transistor 432 is off. In the output low state, the transistor 431 is off and the transistor 432 is on. In the both-off state, the transistors 431 and 432 are both off. The transistors 431 and 432 are never both on.

[0098] The switching control circuit 420 controls the output voltage V OUT information (i.e., feedback voltage V FB ) and the inductor current I L Based on this information, the transistors 431 and 432 are alternately turned on and off (i.e., the state of the output stage circuit 430 is switched between the output high state and the output low state), thereby controlling the output voltage V OUT to a predetermined target voltage V TG That is, the switching control circuit 420 can drive the transistors 431 and 432 by a so-called current mode control method. For example, the current flowing through the transistor 431 during the ON period of the transistor 431 is stabilized by the inductor current I L In the switching control by the switching control circuit 420, the transistors 431 and 432 are alternately turned on and off, which is a concept including the presence of both off states in consideration of dead time and the like between the transition between the output low state and the output high state.

[0099] The above switching control effectively reduces the input voltage V IN The voltage V is a square wave whose level fluctuates between the ground level and the ground level. SW The switch voltage V SW is rectified and smoothed by the rectifying and smoothing circuit 440 to produce a DC output voltage V OUT is obtained.

[0100] The switching control circuit 420 determines the switching frequency of the transistors 431 and 432 based on the clock signal CLK output from the clock signal generation circuit 410. Specifically, the switching control circuit 420 switches the state of the output stage circuit 430 from an output low state to an output high state in synchronization with the rising edge of the clock signal CLK, and then performs a unit operation of switching the state of the output stage circuit 430 from an output high state to an output low state based on another signal (not shown). This unit operation is repeated by the switching control. The switching control circuit 420 controls the output voltage V OUT information (i.e., feedback voltage V FB ) and inductor current I L and other information. That is, the switching frequency of the transistors 431 and 432 is controlled based on the clock signal CLK, and the output duty is controlled based on the other signals. The output duty represents the ratio of the period during which the output stage circuit 430 is in the output high state to the sum of the period during which the output stage circuit 430 is in the output high state and the period during which the output stage circuit 430 is in the output low state. Therefore, the switching control of the switching control circuit 420 corresponds to PWM control (pulse width modulation control).

[0101] Here, the output voltage V OUT information (i.e., feedback voltage V FB ) and inductor current I L However, the inductor current I L Without referring to the information of the output voltage V OUT information (i.e., feedback voltage V FB ) may be used in the switching control circuit 420 to control the state of the output stage circuit 430 based on the

[0102] Furthermore, although the DC / DC converter 400 configured as a step-down DC / DC converter has been taken as an example, the DC / DC converter 400 can also be configured as a step-up DC / DC converter or a step-up / step-down DC / DC converter.

[0103] <<Fifth Embodiment>> A fifth embodiment of the present disclosure will be described. The clock signal generation circuit shown in the first or second embodiment is not limited to DC / DC converters, but can be applied to any device that requires a clock signal.

[0104] For example, a PWM signal generating device 500 shown in Fig. 16 can be configured. PWM is an abbreviation for pulse width modulation. The PWM signal generating device 500 includes a clock signal generating circuit 510 and a PWM circuit 520.

[0105] The clock signal generation circuit 510 supplies a clock signal CLK to the PWM circuit 520. The clock signal generation circuit 510 may include the control circuit 110 and the oscillator 120 (see FIG. 1) in the first embodiment, in which case the clock signal S122 from the oscillator 120 becomes the clock signal CLK. Alternatively, the clock signal generation circuit 510 may include the control circuit 210 and the oscillator 220 (see FIG. 9) in the second embodiment, in which case the clock signal S222 from the oscillator 220 becomes the clock signal CLK.

[0106] The PWM circuit 520 generates and outputs a PWM signal based on the clock signal CLK. The PWM signal is a signal whose pulse width is modulated in units of one cycle of the clock signal CLK. More specifically, the PWM signal is a rectangular wave signal having a predetermined frequency and alternating between high and low signal levels. In each cycle of the PWM signal, the period during which the PWM signal level is high is the pulse width. The PWM circuit 520 can adjust the pulse width of the PWM signal in units of the length of one cycle of the clock signal CLK. That is, the pulse width of the PWM signal is set to a length of p cycles of the clock signal CLK (p is a natural number), and the PWM circuit 520 can adjust the pulse width of the PWM signal by arbitrarily setting the value of p.

[0107] The PWM signal can be used for various purposes in any device that has the PWM signal generating device 500. For example, the PWM signal generating device 500 can be incorporated into a power supply device that generates an output voltage from an input voltage, and the output voltage can be adjusted according to the pulse width of the PWM signal.

[0108] <<Sixth Embodiment>> A sixth embodiment of the present disclosure will be described. As shown in FIG. 17 , a semiconductor device 610 having the clock signal generation circuit described in the first or second embodiment may be mounted on a vehicle 600 such as an automobile. The semiconductor device 480 in FIG. 15 is an example of the semiconductor device 610 in FIG. 17 . In addition to the semiconductor device 610, the vehicle 600 includes an engine (not shown) that generates power for propelling the vehicle 600, and a battery (not shown) formed of a secondary battery. The engine includes an internal combustion engine or a motor. The semiconductor device 610 is driven based on the output voltage of the battery. The semiconductor device 610 may be incorporated into an ECU (Electronic Control Unit) mounted on the vehicle 600. The ECU incorporating the semiconductor device 610 may be, for example, a device that controls the traveling of the vehicle 600, or a device that controls any electrical component (such as an audio device or an air conditioner) installed on the vehicle 600. The semiconductor device 610 may be incorporated into any electrical component installed on the vehicle 600.

[0109] <<Additional notes>> The following is a supplementary explanation of the above points. In the Japanese language used in this specification, "pseudo" and "pseudo" are synonymous and can be used interchangeably.

[0110] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0111] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0112] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0113] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0114] A clock signal generation circuit (see FIG. 1) according to one aspect of the present disclosure has a configuration (first configuration) including a triangular wave generation circuit (111) configured to generate a triangular wave signal (S111), a pseudo-random number generation circuit (112) configured to generate a pseudo-random number signal (S112), a limiter circuit (113) configured to perform a limiting process that places a limit on the amount of change in the pseudo-random number signal per unit time and generate the pseudo-random number signal that has undergone the limiting process as a limiter signal (S113), a linear calculation circuit (114) configured to generate a frequency control signal (S114) by linearly calculating the triangular wave signal and the limiter signal, and an oscillator (120) configured to generate a clock signal (S122) having a frequency corresponding to the frequency control signal.

[0115] According to the first configuration, the frequency of the clock signal can be effectively spread, thereby reducing radiation noise. In this case, the use of pseudo-random numbers can suppress radiation noise caused by triangular waves. Furthermore, the limiting process can also suppress radiation noise that can be caused by sudden changes in the value of the pseudo-random numbers.

[0116] In the clock signal generation circuit according to the first configuration, the pseudo-random number generation circuit may update and output the value of the pseudo-random number signal periodically at the unit time, and the limiter circuit may generate as the limiter signal a signal based on the output of the pseudo-random number generation circuit, the amount of change of which per unit time is limited to a predetermined value or less (second configuration).

[0117] In the clock signal generating circuit according to the first or second configuration, the linear arithmetic circuit may be configured (third configuration) to add one of the triangular wave signal and the limiter signal to the other or subtract one from the other in the linear arithmetic.

[0118] A clock signal generation circuit (see FIG. 9) according to another aspect of the present disclosure has a configuration (fourth configuration) including: a triangular wave generation circuit (211) configured to generate a triangular wave signal (S211); a pseudo-random number generation circuit (212) configured to generate a pseudo-random number signal (S212); a linear operation circuit (213) configured to generate a linear operation result signal (S213) by linearly operating the triangular wave signal and the pseudo-random number signal; a limiter circuit (214) configured to execute a limiting process that limits the amount of change in the linear operation result signal per unit time and generate the linear operation result signal that has undergone the limiting process as a frequency control signal (S214); and an oscillator (220) configured to generate a clock signal (S222) having a frequency corresponding to the frequency control signal.

[0119] According to the fourth configuration, the frequency of the clock signal can be effectively spread, thereby reducing radiation noise. In this case, the use of pseudo-random numbers can suppress radiation noise caused by triangular waves. Furthermore, the limiting process can suppress radiation noise that can be caused by sudden changes in the value of the pseudo-random numbers.

[0120] In the clock signal generation circuit according to the fourth configuration, the pseudo-random number generation circuit may update and output the value of the pseudo-random number signal at a period of the unit time, the linear arithmetic circuit may update and output the value of the linear arithmetic result signal at a period of the unit time, and the limiter circuit may generate, as the frequency control signal, a signal that is based on the output of the linear arithmetic circuit and whose amount of change per unit time is limited to a predetermined value or less (fifth configuration).

[0121] In the clock signal generating circuit according to the fourth or fifth configuration, the linear arithmetic circuit may be configured (sixth configuration) to add one of the triangular wave signal and the pseudo-random number signal to the other or subtract one from the other in the linear arithmetic.

[0122] A DC / DC converter (100, 200) according to the present disclosure has a configuration (seventh configuration) including a clock signal generation circuit (110 and 120, 210 and 220) according to any one of the first to sixth configurations, and a power conversion circuit (130, 230) configured to generate a second DC voltage by switching a first DC voltage at a switching frequency according to the clock signal.

[0123] A PWM signal generating device (500) according to the present disclosure has a configuration (eighth configuration) including a clock signal generating circuit (510) according to any one of the first to sixth configurations, and a pulse width modulation circuit (520) configured to generate a pulse width modulated signal based on the clock signal.

[0124] A vehicle (600) according to the present disclosure has a configuration (ninth configuration) in which a semiconductor device (610) having the clock signal generating circuit according to any one of the first to sixth configurations is mounted. [Explanation of symbols]

[0125] 100, 200 DC / DC converter 110, 210 control circuit 111, 211 Triangular wave generation circuit 112, 212 Pseudorandom number generator 113, 214 Limiter circuit 114, 213 Linear arithmetic circuits 120, 220 oscillators 121, 221 DAC 122, 222 VCOs 130, 230 Power conversion circuit 300 Linear Feedback Shift Register 400 DC / DC Converter 410 Clock signal generation circuit 420 Switching Control Circuit 430 Output stage circuit 440 Rectifier smoothing circuit 450 Feedback voltage generation circuit 500 PWM signal generator 510 Clock signal generation circuit 520 PWM circuit 600 vehicles 610 Semiconductor devices

Claims

1. a triangular wave generating circuit configured to generate a triangular wave signal; a pseudorandom number generator configured to generate a pseudorandom signal; a limiter circuit configured to perform a limiting process to limit the amount of change in the pseudorandom number signal per unit time, and to generate the pseudorandom number signal that has undergone the limiting process as a limiter signal; a linear arithmetic circuit configured to generate a frequency control signal by linearly arithmetically operating the triangular wave signal and the limiter signal; an oscillator configured to generate a clock signal having a frequency responsive to the frequency control signal. , clock signal generation circuit.

2. the pseudorandom number generating circuit updates and outputs the value of the pseudorandom number signal periodically at the unit time; The limiter circuit generates, as the limiter signal, a signal based on the output of the pseudorandom number generation circuit, the amount of change of which per unit time is limited to a predetermined value or less.

2. The clock signal generating circuit according to claim 1.

3. The linear operation circuit adds one of the triangular wave signal and the limiter signal to the other or subtracts one of the triangular wave signal and the limiter signal from the other in the linear operation.

3. The clock signal generating circuit according to claim 1 or 2.

4. a triangular wave generating circuit configured to generate a triangular wave signal; a pseudorandom number generator configured to generate a pseudorandom signal; a linear operation circuit configured to perform a linear operation on the triangular wave signal and the pseudorandom number signal to generate a linear operation result signal; a limiter circuit configured to perform a limiting process to limit a change amount of the linear operation result signal per unit time, and to generate the linear operation result signal that has been subjected to the limiting process as a frequency control signal; an oscillator configured to generate a clock signal having a frequency responsive to the frequency control signal. , clock signal generation circuit.

5. the pseudorandom number generating circuit updates and outputs the value of the pseudorandom number signal periodically at the unit time; the linear operation circuit updates and outputs the value of the linear operation result signal at intervals of the unit time; The limiter circuit generates, as the frequency control signal, a signal based on the output of the linear arithmetic circuit, the amount of change per unit time of which is limited to a predetermined value or less.

5. The clock signal generating circuit according to claim 4.

6. The linear operation circuit adds one of the triangular wave signal and the pseudorandom number signal to the other or subtracts one of the triangular wave signal and the pseudorandom number signal from the other in the linear operation.

6. The clock signal generating circuit according to claim 4 or 5.

7. A clock signal generating circuit according to any one of claims 1 to 6; a power conversion circuit configured to generate a second DC voltage by switching a first DC voltage at a switching frequency according to the clock signal. , DC / DC converter.

8. A clock signal generating circuit according to any one of claims 1 to 6; a pulse width modulation circuit configured to generate a pulse width modulated signal based on the clock signal. , PWM signal generation device.

9. A semiconductor device having the clock signal generating circuit according to any one of claims 1 to 6 is mounted. ,vehicle.

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