Memory cell circuit, memory cell array structure and manufacturing method thereof

Abstract

To provide a memory cell circuit capable of effectively reducing a gate induction drain leak current, and effectively improving a data holding property, a memory cell array structure, and a manufacturing method therefor.SOLUTION: A memory cell circuit 100 comprises: a transistor M1; a transistor M2; and a capacitor CS. The transistor M1 includes a first end part electrically coupled to a bit wire BL, and a gate of the transistor M1 is electrically coupled to a primary word wire WLm. The transistor M2 includes a first end part electrically coupled to a second end part of the transistor M1, and the gate of the transistor M2 is electrically coupled to an assistance word wire WLa. A first end part of a capacitor is electrically coupled to a node SN, and the node SN is electrically coupled to the second end part of a second transistor. The second end part of the capacitor receives a reference voltage via a common electrode board PLT.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a memory cell circuit, a memory cell array structure, and a manufacturing method thereof, and more particularly to a memory cell circuit, a memory cell array structure, and a manufacturing method thereof for a dynamic random access memory. [Background technology]

[0002] In the prior art, dynamic random access memory cell circuits are often implemented using a one-transistor, one-capacitor (1T1C) architecture. In such memory cell circuit structures, when the transistor is turned off and enters the data storage period, so-called gate-induced drain leakage (GIDL) often occurs due to the band-to-band tunneling effect in the gate-drain overlap region of the transistor. This leakage current causes the charge stored in the capacitor to leak, resulting in the loss of stored data and reducing the data retention of the memory device. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure provides a memory cell circuit, a memory cell array structure, and a manufacturing method thereof that can effectively reduce gate-induced drain leakage (GIDL) that can occur during a data retention period. [Means for solving the problem]

[0004] The memory cell circuit of the present disclosure includes a first transistor, a second transistor, and a capacitor. The first transistor has a first end electrically coupled to a bit line, and a gate of the first transistor is electrically coupled to a primary word line. The second transistor has a first end electrically coupled to the second end of the first transistor, and a gate of the second transistor is electrically coupled to an auxiliary word line. The first end of the capacitor is electrically coupled to the second end of the second transistor, and the second end of the capacitor receives a reference voltage.

[0005] The memory cell array structure of the present disclosure includes a plurality of channel pillars, a plurality of first conductive structures, at least one second conductive structure, and a plurality of capacitors. The channel pillars are arranged in an array to form a plurality of channel pillar rows and a plurality of channel pillar columns. The first conductive structures are electrically coupled to the channel pillar rows or the channel pillar columns, respectively, and each of the first conductive structures surrounds a first portion of a channel pillar in each of the channel pillar rows or each of the channel pillar columns. Each of the first conductive structures forms a common gate for a plurality of first transistors in each of the channel pillar rows or each of the channel pillar columns. The second conductive structures are electrically coupled to the channel pillar rows or the channel pillar columns, respectively, and each of the second conductive structures surrounds a second portion of a channel pillar in each of the channel pillar rows or each of the channel pillar columns. Each of the second conductive structures forms a common gate for a plurality of second transistors in each of the channel pillar rows or each of the channel pillar columns. The first and second portions have a spacing distance between them. The capacitors are electrically coupled to ends of the channel pillars adjacent to the at least one second conductive structure, respectively.

[0006] A method for manufacturing a memory cell array structure according to the present disclosure includes the following operations: forming a plurality of channels on a wafer, the wafer being comprised of a plurality of silicon layers and a plurality of silicon germanium layers stacked alternately; masking a gate region of the wafer, and removing the silicon germanium layer in source and drain regions of the wafer to form a plurality of source structures and a plurality of drain structures, respectively; masking the source and drain regions of the wafer, and dividing the gate region into a first division and a second division; forming a plurality of first conductive structures and at least one second conductive structure in the first division and the second division, respectively, each of the first conductive structures being a first common gate of a plurality of first transistors, and each of the second conductive structures being a second common gate of a plurality of second transistors. [Effects of the Invention]

[0007] Based on the above, a second transistor is further disposed between the first transistor and the capacitor through the memory cell circuit of the dynamic random access memory cell of the present disclosure. During the data retention period, in the memory cell circuit of the present disclosure, a higher bias is applied to the second transistor than to the first transistor, thereby effectively reducing the gate-induced drain leakage current that may occur and effectively improving data retention. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a schematic diagram of a memory cell circuit according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a schematic diagram of a gate-induced drain leakage condition of a memory cell circuit according to an embodiment of the present disclosure. [Figure 3A] 1 is a structural schematic diagram of a memory cell circuit according to an embodiment of the present disclosure; [Figure 3B] 1 is a structural schematic diagram of a memory cell circuit according to an embodiment of the present disclosure; [Figure 4A] FIG. 2 is a three-dimensional view of a memory cell array structure according to an embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic diagram of an equivalent circuit of the embodiment shown in FIG. 4A. [Figure 5A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 5B] FIG. 5B is an equivalent circuit diagram of the embodiment shown in FIG. 5A. [Figure 6A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 6B] FIG. 6B is an equivalent circuit diagram of the embodiment shown in FIG. 6A. [Figure 7] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 8A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 8B] 8B is a top view of a partial structure of a different implementation of the memory cell array structure of the embodiment of FIG. 8A. [Figure 8C] 8B is a top view of a partial structure of a different implementation of the memory cell array structure of the embodiment of FIG. 8A. [Figure 9] 1 is a flowchart of a method for manufacturing a memory cell array according to an embodiment of the present disclosure. [Figure 10A] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10B] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10C] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10D] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10E] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10F] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10G] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10H] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10I] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10J] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10K] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10L] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10M] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10N] FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 10O]FIG. 1 is a schematic diagram of a process flow for a memory cell array according to an embodiment of the present disclosure. [Figure 11A] FIG. 1 is a schematic diagram of a process flow for the circuit configuration of a memory cell array according to an embodiment of the present disclosure. [Figure 11B] FIG. 1 is a schematic diagram of a process flow for the circuit configuration of a memory cell array according to an embodiment of the present disclosure. [Figure 11C] FIG. 1 is a schematic diagram of a process flow for the circuit configuration of a memory cell array according to an embodiment of the present disclosure. [Figure 12A] 10A-10C illustrate implementation details of a method for forming a capacitor of a memory cell array according to an embodiment of the present disclosure. [Figure 12B] 10A-10C illustrate implementation details of a method for forming a capacitor of a memory cell array according to an embodiment of the present disclosure. [Figure 12C] 10A-10C illustrate implementation details of a method for forming a capacitor of a memory cell array according to an embodiment of the present disclosure. [Figure 13A] FIG. 2 is a side view of a channel pillar in a memory cell array structure according to an embodiment of the present disclosure. [Figure 13B] FIG. 2 is a side view of a channel pillar and conductive structures in a memory cell array structure according to an embodiment of the present disclosure. [Figure 14A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 14B] FIG. 14B is a top view of the memory cell array structure in the embodiment of FIG. 14A. [Figure 15A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 15B] FIG. 15B is a top view of the memory cell array structure in the embodiment of FIG. 15A. [Figure 16] FIG. 10 is a three-dimensional view of another implementation of a memory cell array structure of an embodiment of the present disclosure. [Figure 17] FIG. 10 is a three-dimensional view of another implementation of a memory cell array structure of an embodiment of the present disclosure. [Figure 18] FIG. 10 is a three-dimensional view of another implementation of a memory cell array structure of an embodiment of the present disclosure. [Figure 19A]FIG. 10 is a three-dimensional view of another implementation of a memory cell array structure of an embodiment of the present disclosure. [Figure 19B] FIG. 19B is a top view of the memory cell array structure in the embodiment of FIG. 19A. [Figure 20] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 21] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 22] FIG. 10 is a top view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 23A] FIG. 1 is a top view of an implementation of a memory cell array structure according to an embodiment of the present disclosure. [Figure 23B] FIG. 1 is a top view of an implementation of a memory cell array structure according to an embodiment of the present disclosure. [Figure 23C] FIG. 1 is a top view of an implementation of a memory cell array structure according to an embodiment of the present disclosure. [Figure 24A] FIG. 1 is a top view of an implementation of a memory cell array structure according to an embodiment of the present disclosure. [Figure 24B] FIG. 1 is a top view of an implementation of a memory cell array structure according to an embodiment of the present disclosure. [Figure 24C] FIG. 1 is a top view of an implementation of a memory cell array structure according to an embodiment of the present disclosure. [Figure 25] 1 is a schematic diagram of a three-dimensional structure of a memory device according to an embodiment of the present disclosure. [Figure 26A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 26B] FIG. 26B is a top view of the memory cell array structure of FIG. 26A. [Figure 27] FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 28] FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 29] FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 30] FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 31]FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 32] FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 33] FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 34A] FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present disclosure. [Figure 34B] FIG. 34B is a top view of the memory cell array structure of FIG. 34A. [Figure 34C] FIG. 34B is a diagram of another implementation of the memory cell array structure of FIG. 34A. [Figure 35] FIG. 2 is a schematic diagram of a memory device according to another embodiment of the present disclosure. [Figure 36A] FIG. 2 is a top view of a memory cell array structure according to an embodiment of the present disclosure. [Figure 36B] FIG. 2 is a top view of a memory cell array structure according to an embodiment of the present disclosure. [Figure 36C] FIG. 2 is a top view of a memory cell array structure according to an embodiment of the present disclosure. [Figure 37] FIG. 2 is a top view of a memory device according to an embodiment of the present disclosure. [Figure 38A] FIG. 2 is a top view of a memory device according to an embodiment of the present disclosure. [Figure 38B] FIG. 2 is a top view of a memory device according to an embodiment of the present disclosure. [Figure 39] FIG. 10 is a schematic diagram of a layout structure of a memory device according to another embodiment of the present disclosure. [Figure 40A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 40B] FIG. 40B is a top view of the memory cell array structure in the FIG. 40A embodiment of the present disclosure. [Figure 41A] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 41B] FIG. 41B is a top view of the memory cell array structure in the FIG. 41A embodiment of the present disclosure. [Figure 42] FIG. 2 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 43] FIG. 10 is a cross-sectional view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 44] FIG. 2 is a three-dimensional view of a memory cell array structure according to an embodiment of the present disclosure. [Figure 45] FIG. 2 is a three-dimensional view of a memory cell array structure according to an embodiment of the present disclosure. [Figure 46A] FIG. 2 is a three-dimensional view of a memory cell array structure according to an embodiment of the present disclosure. [Figure 46B] FIG. 46B is a top view of the memory cell array structure in the embodiment of FIG. 46A. [Figure 47] FIG. 10 is a top view of a memory cell array structure according to another embodiment of the present disclosure. [Figure 48A] FIG. 1 is a schematic diagram of a memory chip according to an embodiment of the present disclosure. [Figure 48B] FIG. 48B is a partially enlarged schematic diagram of region Z1 of the memory chip of FIG. 48A. DETAILED DESCRIPTION OF THE INVENTION

[0009] Throughout this specification (including the claims), the term "electrically couple" and variations thereof are used broadly and encompass both direct and indirect electrical connections. The term "electrically coupled" includes joining two members to one another directly or indirectly via a conductive material (e.g., metal or copper traces), and also encompasses electrically connecting and coupling between two members that interact electrically for the flow of signals via indirect connections, such as capacitively and inductively coupling each other through a dielectric layer.

[0010] For example, if the present disclosure describes a first device being electrically coupled to a second device, it should be interpreted that the first device may be directly electrically connected to the second device, or the first device may be indirectly electrically connected to the second device via another device.

[0011] Referring to FIG. 1, FIG. 1 is a schematic diagram of a memory cell circuit according to an embodiment of the present disclosure. The memory cell circuit 100 includes a transistor M1, a transistor M2, and a capacitor CS. The memory cell circuit 100 is a dynamic random access memory cell. The transistor M1 is a primary transistor. A first end of the transistor M1 is electrically coupled to a bit line BL. A gate of the transistor M1 is electrically coupled to a primary word line WLm. The transistor M2 functions as an auxiliary transistor. A first end of the transistor M2 is electrically coupled to a second end of the transistor M1, and a gate of the transistor M2 is electrically coupled to an auxiliary word line WLa. A second end of the transistor M2 is electrically coupled to a node SN, which is electrically coupled to a first end of a capacitor CS, and a second end of the capacitor CS is electrically coupled to a common electrode plate PLT. The common electrode plate PLT may receive a reference voltage.

[0012] In this embodiment, transistor M1 is electrically coupled in series between transistor M2 and bit line BL, and transistor M2 is positioned in series between transistor M1 and capacitor CS. Furthermore, the gate of transistor M1 is located near bit line BL and away from capacitor CS. The gate of transistor M2 is located near capacitor CS and away from bit line BL.

[0013] The transistors M1 and M2 may receive bias voltages via the primary word line WLm and the auxiliary word line WLa, respectively. During a normal access operation, the transistors M1 and M2 are turned on in response to the received bias voltages, and data may be written to the capacitor CS via the bit line BL or read from the capacitor CS to the bit line BL. During a data retention period, the transistor M1 may be turned off in response to a bias voltage (e.g., a negative voltage) received via the word line WLm. The transistor M2 may receive a bias voltage (which may be higher than the bias voltage received by the word line WLm, or may be a positive voltage) received by the word line WLm. In this way, a gate-induced drain leakage phenomenon that may occur at the node SN during the data retention period may be effectively reduced.

[0014] Referring now to FIG. 2, FIG. 2 is a schematic diagram of gate-induced drain leakage states of a memory cell circuit according to an embodiment of the present disclosure. In FIG. 2, state 210 represents an energy band diagram in a case where the memory cell circuit does not include an auxiliary transistor. State 220 represents an energy band diagram of the memory cell circuit 100. In state 210, when a low bias voltage (e.g., a negative voltage) is applied to the word line of the transistor, a relatively high bias voltage is applied to the node SN. This causes a band-to-band tunneling current BTBT to occur between the valence band Ev and the conduction band Ec during the transition between the gate and the node SN of the transistor. This band-to-band tunneling current BTBT may leak charge from the capacitor, generating a leakage current. The band-to-band tunneling current BTBT may occur when an electric field stress is applied between the gate of the transistor and the silicon subtractor.

[0015] In state 220, node SN is electrically coupled to transistor M2, which functions as an auxiliary transistor. Under the conditions that a relatively low bias voltage, possibly lower than the threshold voltage Vt, is applied to the main word line of the main transistor (transistor M1), a relatively high bias voltage, possibly higher than the threshold voltage Vt, is applied to the auxiliary word line of the auxiliary transistor (transistor M2), and a high bias voltage is also applied to node SN, the energy overlap between the valence band Ev of transistor M2 and the conduction band Ec of node SN can be shortened during the transition of the gate of the auxiliary transistor and node SN. Therefore, the available width of the band-to-band tunneling current BTBT generated by this energy overlap can be effectively reduced. In this way, the gate-induced drain leakage current can be effectively reduced.

[0016] 3A and 3B, which are structural schematic diagrams of a memory cell circuit according to an embodiment of the present disclosure. FIG. 3A is a three-dimensional view of the structures of a first transistor and a second transistor, and FIG. 3B is a cross-sectional view of a capacitor. In FIG. 3A, memory cell circuit structure 300 includes a channel pillar 310, a conductive structure 320, and a conductive structure 330. Conductive structure 320 surrounds a first portion of channel pillar 310 and forms the gate of the first transistor (primary transistor). Gate oxide layer 321 is sandwiched between conductive structure 320 and channel pillar 310. Conductive structure 330 wraps around a second portion of channel pillar 310 and forms the gate of the second transistor (auxiliary transistor). Gate oxide layer 331 is sandwiched between conductive structure 330 and channel pillar 310.

[0017] In this embodiment, there is a spacing SPC between the conductive structure 320 and the conductive structure 330. The conductive structure 320 is configured to be electrically coupled to a primary word line, and the conductive structure 330 is configured to be electrically coupled to an auxiliary word line. Meanwhile, on the channel pillar 310, an end portion (drain) adjacent to the conductive structure 330 may be electrically coupled to a node SN, which is also electrically coupled to a capacitor. In addition, on the channel pillar 310, an end portion (source) adjacent to the conductive structure 320 may be electrically coupled to a bit line BL. The term "adjacent" is used to describe two objects that are near, adjacent to, or close to each other, but do not necessarily need to be in contact with each other. Two adjacent objects may be physically coupled together or may be separated by a distance without any intervening similar objects. 3A, as an example, the end portion (drain) is adjacent to conductive structure 330 and the end portion (source) is adjacent to conductive structure 320, which means that the end portion (drain) is closer to conductive structure 310 than the end portion (source). In other words, here the end portion electrically coupled to node SN is located near conductive structure 330 but away from conductive structure 320, and the end portion electrically coupled to line BL is located near conductive structure 320 but away from conductive structure 330.

[0018] In this embodiment, the material of the channel pillar 310 may be silicon, GaAs, SiC, or other suitable semiconductor materials for establishing a channel, and the conductive structure 320 and the conductive structure 330 may be any conductive structure in a semiconductor manufacturing process, without being particularly limited.

[0019] Conductive structure 320 and conductive structure 330 may divide channel pillar 310 into two regions, region P1 and region P3. Region P1 and conductive structure 330 may form the gate of transistor M2, as shown in FIG. 1. Conductive structure 320 may form the gate of transistor M1, as shown in FIG. 1. In this embodiment, region P1 and region P3 may each be doped as a drain or source. Region P1 and region P3 may have the same conductivity type. In this embodiment, the gate control channel may be undoped or doped with a dopant of the opposite type to the pillar ends for threshold voltage adjustment.

[0020] In other embodiments, the entire channel pillar 310 may be a uniformly doped region that can be either N-type or P-type. Such a configuration is commonly referred to as a junctionless device. For example, in this embodiment, the channel pillar 310 may be obtained by performing an etching operation on epitaxially grown Si and bulk Si wafers during the manufacturing process, and the epitaxially grown Si or bulk Si wafer may have N-type or P-type conductivity. Therefore, the entire channel pillar 310 may be a uniformly doped region of N-type or P-type.

[0021] In the present disclosure, any method can be used to dope the two end portions or the entire channel pillar 310, and there is no particular limitation.

[0022] In FIG. 3B , the memory cell circuit structure 300 further includes a pillar-shaped capacitor CS. The capacitor CS includes a plurality of conductive films CC1 to CC5 and a plurality of dielectric layers CI1 to CI4. The conductive films CC1 and CC5 contact the node SN to form a first electrode of the capacitor CS and extend in the direction D1. The conductive film CC4 is disposed between the conductive films CC1 and CC5. The conductive films CC2 and CC3 are disposed outside the conductive films CC1 and CC5, respectively. The conductive films CC2, CC4, and CC3 are electrically coupled to each other at end portions away from the node SN and to a common electrode plate PLT to form a second electrode of the capacitor CS.

[0023] In addition, a dielectric layer CI1 is formed between the conductive coating CC2 and the conductive coating CC1, a dielectric layer CI2 is formed between the conductive coating CC3 and the conductive coating CC5, a dielectric layer CI3 is formed between the conductive coating CC4 and the conductive coating CC1, and a dielectric layer CI4 is formed between the conductive coating CC4 and the conductive coating CC5. In this embodiment, the conductive coating CC1 and the conductive coating CC5 are internal conductive coatings, and the conductive coating CC2, the conductive coating CC3, and the conductive coating CC4 are external conductive coatings. Here, the conductive coating CC2, the conductive coating CC1, the conductive coating CC4, the conductive coating CC5, and the conductive coating CC3 are arranged in an interleaved manner.

[0024] In this embodiment, the cross section of the capacitive column forming the capacitor CS may be circular, rectangular, or polygonal, and is not particularly limited.

[0025] 3A and 3B illustrate a dual-gate DRAM cell comprising a semiconductor pillar electrically arranged in series between a capacitor and a bit line terminal configured to connect to a bit line. A first gate surrounds the pillar proximate the capacitor, and a second gate surrounds the pillar proximate the bit line terminal. A gate dielectric is disposed between the first gate and the pillar, and a gate dielectric is disposed between the second gate and the pillar. The pillars can be arranged vertically (perpendicular to the substrate) in one example and horizontally (parallel to the substrate) in another example. The first gate can be integrated with or otherwise electrically coupled to a first word line conductor, and the second gate can be integrated with or otherwise electrically coupled to a second word line conductor. An integrated circuit including the dual-gate DRAM cell includes a word line bias circuit configured to apply a first gate bias to the first word line and a second gate bias to the second word line. The first gate bias and the second gate bias are set voltage levels described herein that suppress current leakage from the capacitor when the cell is not selected for access in operation of the memory. In one bias arrangement for deselecting the cell, the first gate bias is set at a higher level than the second gate bias. Generally, the first gate bias is set to suppress current leakage due to band-to-band tunneling in the pillar when the second gate bias is set to turn off current in the pillar to deselect the cell.

[0026] Referring to FIGS. 4A and 4B, FIG. 4A is a three-dimensional view of a memory cell array structure according to an embodiment of the present disclosure. FIG. 4B is a schematic diagram of an equivalent circuit of the embodiment shown in FIG. 4A. The memory cell array structure 400 includes a plurality of channel pillars 410, a plurality of first conductive structures 420-1 to 420-3, a plurality of second conductive structures 430-1 to 430-3, a plurality of third conductive structures 440-1 to 440-3, and a plurality of capacitors CSA. The channel pillars 410 are arranged in an array. Each of the channel pillars 410 extends along the Z-axis direction. This embodiment takes a 3×3 array as an example. The channel pillars 410 may form three channel pillar columns and three channel pillar rows. Here, as an example, the X-axis direction is the row direction and the Y-axis direction is the column direction. The first conductive structures 420-1 to 420-3 each surround a first portion of each of the channel pillars 410 in the three channel pillar rows. The first conductive structures 420-1 to 420-3 are configured to form a common gate for a plurality of first transistors (primary transistors) in the corresponding channel pillar row. The second conductive structures 430-1 to 430-3 each surround a second portion of each of the channel pillars 410 in the channel pillar row and form a common gate for a plurality of second transistors (auxiliary transistors) in the corresponding channel pillar row. Corresponding to the same channel pillar 410, the first conductive structures 420-1 to 420-3 are vertically arranged in the Z-axis direction, respectively, as the second conductive structures 430-1 to 430-3. Second conductive structure 430-1 to second conductive structure 430-3 may be disposed above first conductive structure 420-1 to first conductive structure 420-3, respectively.

[0027] The first conductive structure 420-1 to the first conductive structure 420-3 are electrically coupled to a plurality of primary word lines, and the second conductive structure 430-1 to the second conductive structure 430-3 are electrically coupled to a plurality of auxiliary word lines, respectively. In this embodiment, the first conductive structure 420-1 to the first conductive structure 420-3 and the second conductive structure 430-1 to the second conductive structure 430-3 all extend along the same direction (X-axis direction).

[0028] In addition, a plurality of capacitors CSA are disposed above each channel pillar 410, and each capacitor CSA and each channel pillar 410 is electrically coupled to a node SN. The upper end portions of the capacitors CSA may be electrically coupled in common to a common electrode plate (not shown). Here, the capacitors CSA may have a columnar structure.

[0029] In this embodiment, each of the third conductive structures 440-1 to 440-3 extends along the Y-axis direction and is electrically coupled to a plurality of channel pillar rows formed by the channel pillars 410. The third conductive structures 440-1 to 440-3 are configured to be electrically coupled to a plurality of bit lines, respectively. The extension direction of the third conductive structures 440-1 to 440-3 is different from the extension direction of the first conductive structures 420-1 to 420-3, and may be, for example, perpendicular to each other or at an angle to each other, although the angle is not limited to 90 degrees.

[0030] 4B, taking a 2x2 array as an example, the memory cell array structure may include memory cell circuits MC1 to MC4. Memory cell circuits MC1 and MC2 are arranged in the same first row, memory cell circuits MC3 and MC4 are arranged in the same second row, memory cell circuits MC1 and MC3 are arranged in the same first column, and memory cell circuits MC2 and MC4 are arranged in the same second column. Memory cell circuit MC1 includes transistors M11 and M12 and a capacitor CS1. Memory cell circuit MC2 includes transistors M21 and M22 and a capacitor CS2. Memory cell circuit MC3 includes transistors M31 and M32 and a capacitor CS3. Memory cell circuit MC4 includes transistors M41, M42 and a capacitor CS4.

[0031] Taking memory cell circuit MC1 as an example, a capacitor CS1, a transistor M12, and a transistor M11 are sequentially arranged between a common electrode plate PLT and a bit line BL1. The gate of transistor M11 (primary transistor) is electrically coupled to a main word line WLm1, and the gate of transistor M12 (auxiliary transistor) is electrically coupled to an auxiliary word line WLa1.

[0032] Since the auxiliary word lines WLa1 and WLa2 and the primary word lines WLm1 and WLm2 all extend in the X-axis direction, the adjacently arranged primary transistors M11 and M21 may be electrically coupled to the same primary word line WLm1, the adjacently arranged auxiliary transistors M12 and M22 may be electrically coupled to the same auxiliary word line WLa1, the adjacently arranged primary transistors M31 and M41 may be electrically coupled to the same primary word line WLm2, and the adjacently arranged auxiliary transistors M32 and M42 may be electrically coupled to the same auxiliary word line WLa2. Since the bit lines BL1 and BL2 extend along the Y-axis direction, the memory cell circuits MC1 and MC3 may be electrically coupled to the same bit line BL1, and the memory cell circuits MC2 and MC4 may be electrically coupled to the same bit line BL2.

[0033] 5A and 5B, FIG. 5A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 5B is an equivalent circuit diagram of the embodiment shown in FIG. 5A. The memory cell array structure 500 includes a plurality of channel pillars 510, a plurality of first conductive structures 520, a plurality of second conductive structures 530, a plurality of third conductive structures 540, and a plurality of capacitors CSA. In this embodiment, the channel pillars 510 extend along the Y-axis direction, forming, for example, a 3×4 array. As an example, assuming that the X-axis direction is the row direction and the Z-axis direction is the column direction, the memory cell array structure 500 may have three channel pillar columns and four channel pillar rows. Each of the first conductive structures 520 may surround the same first portion of the channel pillars 510 in the channel pillar column. Each of the second conductive structures 530 may surround the same second portion of the channel pillars 510 in the channel pillar column. Each first conductive structure 520 may form a common gate for multiple primary transistors of the enclosed channel pillar 510. Each second conductive structure 530 may form a common gate for multiple auxiliary transistors of the enclosed channel pillar 510. The first conductive structures 520 may each be electrically coupled to a primary word line WLm. Alternatively, in other embodiments of the present disclosure, the first conductive structures 520 may be commonly electrically coupled to the same primary word line. In addition, the second conductive structures 530 may each be electrically coupled to an auxiliary word line WLa, or in other embodiments of the present disclosure, the second conductive structures 530 may be commonly electrically coupled to the same auxiliary word line. In this embodiment, each of the first conductive structures 520 extends along the Z-axis and is spaced apart from one another along the X-axis. Similarly, each of the second conductive structures 530 extends along the Z-axis and is spaced apart from one another along the X-axis.

[0034] Additionally, in the channel pillar 510, end portions adjacent to the first conductive structure 520 may each be electrically coupled to a third conductive structure 540. In this embodiment, the third conductive structure 540 may extend along the X-axis direction. Through a plurality of conductive plugs 541 extending along the Z-axis, the third conductive structure 540 may be electrically coupled to the bit line BL through conductive vias VA1 and VA2 along the Z-axis direction, respectively. Note that in this embodiment, the third conductive structure 540 may form a structure called a step structure or staircase.

[0035] In this embodiment, the primary word lines WLm and the auxiliary word lines WLa may be arranged in a first metal layer at the same height, and the bit lines BL may be arranged in a separate second metal layer, which may be higher than the first metal layer.

[0036] The channel pillar 510 may have a plurality of capacitors CSA formed adjacent to end portions of the second conductive structure 530. The other end portions of the capacitors CSA may be commonly electrically coupled to a common electrode plate PLT.

[0037] 5B , taking a 2×2 memory cell array as an example, the memory cell array structure 500 may be divided into a first layer structure L1 and a second layer structure L2. The first layer structure L1 may have a first memory cell circuit formed of transistors M11, M12, and capacitor CS1, and a second memory cell circuit formed of transistors M21, M22, and capacitor CS2. The second layer structure L2 may have a third memory cell circuit formed of transistors M31, M32, and capacitor CS3, and a fourth memory cell circuit formed of transistors M41, M42, and capacitor CS4.

[0038] In FIG. 5B , in a first layer structure L1, transistors M11, M12, and capacitor CS1 are arranged along the Y-axis direction to form a memory cell circuit. Transistors M21, M22, and capacitor CS2 are also arranged along the Y-axis direction to form another memory cell circuit. Bit line BL2 is electrically coupled to transistors M11 and M21 along the Y-axis direction. Primary word lines WLm1 and WLm2 are electrically coupled to conductors arranged along the Z-axis, respectively, and are electrically coupled to the gates of transistors M11 and M21, respectively, so that transistors M11 and M21 function as primary transistors. Auxiliary word lines WLa1 and WLa2 are electrically coupled to conductors arranged along the Z-axis, respectively, and are electrically coupled to the gates of transistors M12 and M22, respectively, so that transistors M12 and M22 function as auxiliary transistors.

[0039] In the second layer structure L2, transistors M31, M32, and capacitor CS3 are arranged along the X-axis direction to form a memory cell circuit. Transistors M41, M42, and capacitor CS4 are arranged along the X-axis direction to form another memory cell circuit. Bit line BL1 is electrically coupled to transistors M31 and M41 along the Y-axis direction. Primary word lines WLm1 and WLm2 are electrically coupled to the gates of transistors M31 and M41, respectively, and transistors M31 and M41 function as primary transistors. Auxiliary word lines WLa1 and WLa2 are electrically coupled to the gates of transistors M32 and M42, respectively, and transistors M32 and M42 function as auxiliary transistors.

[0040] Incidentally, the capacitors CS1 to CS4 are also electrically coupled in common to the common electrode plate PLT. The common electrode plate PLT may extend across the first layer structure L1 and the second layer structure L2.

[0041] 6A and 6B, FIG. 6A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 6B is an equivalent circuit diagram of the embodiment shown in FIG. 6A. The memory cell array structure 600 includes a plurality of channel pillars 610, a plurality of first conductive structures 620, a plurality of second conductive structures 630, a plurality of third conductive structures 640, and a plurality of capacitors CSA. In this embodiment, the channel pillars 610 extend along the Y-axis direction, forming, for example, a 3×4 array. Here, as an example, the X-axis direction is also the row direction, and the Z-axis direction is the column direction.

[0042] The memory cell array structure 600 in FIG. 6A has a structure similar to the memory cell array structure 500 in FIG. 5A. Unlike the memory cell array structure 500, in the memory cell array structure 600, each first conductive structure 620 and each second conductive structure 630 extend along the X-axis direction. The first conductive structures 620 are arranged one above the other along the Z-axis direction, each surrounding a first portion of a channel pillar row, and the second conductive structures 630 are also arranged one above the other along the Z-axis direction, each surrounding a second portion of a channel pillar row. Each third conductive structure 640 extends along the Z-axis direction and is electrically coupled to an end portion of a corresponding channel pillar row adjacent to the first conductive structure 620. The third conductive structures 640 are separately arranged along the X-axis direction.

[0043] In the embodiment of the present disclosure, the first conductive structure 620 forms a structure called a step structure or staircase, and the second conductive structure 630 forms another structure called a step structure or staircase. The first conductive structure 620 is electrically coupled to a plurality of conductive plugs 621 via step surfaces, and is electrically coupled to a plurality of primary word lines WLm via the conductive plugs 621 and a plurality of conductive vias. The second conductive structure 630 is electrically coupled to a plurality of conductive plugs 631 via step surfaces, and is electrically coupled to a plurality of auxiliary word lines WLa via the conductive plugs 631 and a plurality of conductive vias.

[0044] Additionally, each third conductive structure 640 is electrically coupled to a respective bit line BL along the Z-axis direction via a conductive via VA1 and a conductive via VA2. The bit lines BL may be arranged in parallel along the X-axis direction, and each bit line BL may extend along the Y-axis direction. The third conductive structures 640 may be bit line conductive plugs. Each of the third conductive structures 640 may be substantially the same size, which may result in uniform bit line capacitance and improve performance of data sensing operations. The third conductive structures 640 are separately arranged along the X-axis direction and electrically coupled to corresponding conductive vias VA1 and VA2. The bit lines BL are arranged in a second metal layer and are higher than the primary word line WLm and the auxiliary word line WLa, which are arranged in the first metal layer. In another embodiment, the bit lines BL may be arranged in the first metal layer, and the primary word line WLm and the auxiliary word line WLa are arranged in a second metal layer higher than the first metal layer.

[0045] 6B , taking a 2×2 memory cell array as an example, the memory cell array structure 600 may be divided into a first layer structure L1 and a second layer structure L2. The first layer structure L1 may have a first memory cell circuit formed of transistors M11, M12, and capacitor CS1, and a second memory cell circuit formed of transistors M21, M22, and capacitor CS2. The second layer structure L2 may have a third memory cell circuit formed of transistors M31, M32, and capacitor CS3, and a fourth memory cell circuit formed of transistors M41, M42, and capacitor CS4.

[0046] The equivalent circuit of the memory cell array structure 600 is substantially the same as the equivalent circuit of the memory cell array structure 500. The difference is that in the memory cell array structure 600, conductors electrically coupled to bit lines BL1 and BL2 extend along the Z-axis direction. The bit line BL1 is electrically coupled to transistors M11 and M31, and the bit line BL2 is electrically coupled to transistors M21 and M41. Additionally, the gates of the transistors M11 and M21 are electrically coupled in common to a primary word line WLm1 extending along the X-axis direction, the gates of the transistors M12 and M22 are electrically coupled in common to an auxiliary word line WLa1 extending along the X-axis direction, the gates of the transistors M31 and M41 are electrically coupled in common to a primary word line WLm2 extending along the X-axis direction, and the gates of the transistors M32 and M42 are electrically coupled in common to an auxiliary word line WLa2 extending along the X-axis direction.

[0047] Referring to FIG. 7, FIG. 7 is a three-dimensional diagram of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure 700 includes a plurality of channel pillars 710, a plurality of first conductive structures 720, one second conductive structure 730, a plurality of third conductive structures 740, and a plurality of capacitors CSA. In this embodiment, the channel pillars 710 extend along the Y-axis direction, forming, for example, a 4×4 array. As an example, assuming that the X-axis direction is the row direction and the Y-axis direction is the column direction, the memory cell array structure 700 may have four channel pillar columns and four channel pillar rows. The number of first conductive structures 720 may be four, each surrounding a first portion of the four channel pillars 710 in each channel pillar row. Each of the first conductive structures 720 extends along the X-axis direction. Note that in this embodiment, there is only one second conductive structure 730 that is electrically coupled to and surrounds the second portions of all the channel pillars 710.

[0048] The first conductive structures 720 are electrically coupled to a plurality of primary word lines, respectively.

[0049] In an embodiment of the present disclosure, by electrically coupling all the channel pillars 710 using the second conductive structure 730, the gates of the auxiliary transistors in all the memory cell circuits can be commonly electrically coupled to the same auxiliary word line. This can effectively reduce the complexity of the circuit layout of the memory cell array structure 700. In this embodiment, the size of the second conductive structure 730 is larger than that of each of the first conductive structures 720. The number of channel pillars 710 surrounded by the second conductive structure 730 is greater than the number of channel pillars 710 surrounded by each of the first conductive structures 720. In other embodiments, the second conductive structure 730 can be divided into smaller segments, and each segment of the second conductive structure 730 can surround a different group of channel pillars 710. However, the number of channel pillars 710 surrounded by each segment of the second conductive structure 730 is still greater than the number of channel pillars 710 surrounded by each of the first conductive structures 720.

[0050] Incidentally, the third conductive structures 740 are electrically coupled to end portions of the plurality of channel pillar rows adjacent to the first conductive structures 720. Each of the third conductive structures 740 may extend along the Y-axis direction.

[0051] Referring to FIGS. 8A to 8C, FIG. 8A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIGS. 8B and 8C are top views of a partial structure of a different implementation of the memory cell array structure according to the embodiment of FIG. 8A. In FIG. 8A, the memory cell array structure 800 includes a plurality of channel pillars 810, a plurality of first conductive structures 820, a plurality of second conductive structures 830, a plurality of third conductive structures 840, and a plurality of capacitors CSAs. In this embodiment, the channel pillars 810 extend along the Y-axis direction, forming, for example, a 5×4 array. Each channel pillar 810 is electrically coupled to a plurality of capacitors CSAs, each extending in the same direction as each channel pillar 810. The capacitors CSAs are also commonly electrically coupled to a common electrode plate PLT. The third conductive structures 840 are electrically coupled to bit lines via a plurality of conductive plugs 841.

[0052] Here, as an example, the X-axis direction is the row direction, and the Z-axis direction is the column direction. In this embodiment, the channel pillars 810 may form five channel pillar columns and four channel pillar rows. Five first conductive structures 820 are electrically coupled to first portions of the five channel pillar columns, respectively, surrounding the first portions of the five channel pillar columns. Five second conductive structures 830 are electrically coupled to second portions of the five channel pillar columns, respectively, surrounding the second portions of the five channel pillar columns. In this embodiment, as shown in FIG. 8B , the positions of two adjacent first conductive structures 820 are staggered, and the positions of two adjacent second conductive structures 830 are also staggered. 8B , in the reference plane (XY plane) viewed from above, the arrangement positions of two adjacent first conductive structures 820 are shifted, and the arrangement positions of two adjacent second conductive structures 830 are shifted, thereby effectively shortening the spacing distance P1 between two adjacent channel pillars 810 and increasing the circuit layout density. In other words, the first conductive structures 820 are divided into two groups, and the first conductive structures 820 in the first group are arranged separately along the X-axis direction, and the first conductive structures 820 in the second group are also arranged separately along the X-axis direction but are further offset along the Y-axis direction from the first conductive structures 820 in the first group. The second conductive structures 830 are arranged in the same manner as the first conductive structures 820.

[0053] 8C, the number of second conductive structures 830 may be one. One second conductive structure 830 simultaneously surrounds all of the channel pillars 810 and forms a common gate for multiple auxiliary transistors. In this embodiment, the spacing distance P2 between two adjacent channel pillars 810 is also effectively reduced, which may increase the circuit layout density.

[0054] Referring to FIG. 9, FIG. 9 is a flowchart of a method for manufacturing a memory cell array according to an embodiment of the present disclosure. In step S910, multiple channels are formed on a wafer. The wafer is formed by alternately stacking multiple channel layers and multiple sacrificial layers. In this embodiment, the channel layers are silicon layers, and the sacrificial layers are silicon germanium layers. The number of channels may be determined according to the number of memory cells in the memory cell array. Then, in step S920, a gate region of the wafer is masked, and the sacrificial layers in the source and drain regions of the wafer are removed to form multiple source structures and multiple drain structures, respectively. By removing the sacrificial layers in the source and drain regions, multiple channel pillars may be formed in the source and drain regions. A portion of each channel pillar located in the source region may be configured to form a respective source structure, and a portion of each channel pillar located in the drain region may be configured to form a respective drain structure.

[0055] In step S930, the source and drain regions of the wafer are masked, and the gate region is divided into a first division and a second division. Furthermore, by removing the sacrificial layer in the first division and the second division, a plurality of channel pillars may be formed in the first division and the second division, respectively. Next, in step S940, a plurality of first conductive structures and one or more second conductive structures may be formed in the first division and the second division, respectively, such that the first conductive structures surround first portions of the channel pillars and the second conductive structures surround second portions of the channel pillars. Each of the first conductive structures may form a first common gate of a plurality of first transistors, and each of the second conductive structures may form a second common gate of a plurality of second transistors.

[0056] In an embodiment of the present disclosure, the method for manufacturing a memory cell array further includes forming a plurality of third conductive structures and electrically coupling each of the third conductive structures to a source structure. Each of the third conductive structures is electrically coupled to a source structure column or a source structure row arranged on the same line. The third conductive structures are configured to be electrically coupled to a plurality of bit lines, respectively.

[0057] In an embodiment of the present disclosure, the method for manufacturing a memory cell array further includes forming a plurality of capacitors, each electrically coupled to a channel pillar and bounded by an end portion of the second gate structure.

[0058] For details of the method for fabricating a memory cell array, please refer to Figures 10A to 10O. Figures 10A to 10O are schematic diagrams of a process flow for a memory cell array according to an embodiment of the present disclosure. In Figure 10A, a wafer 1000 is obtained by epitaxy. The wafer 1000 has a silicon substrate SiSub. The silicon substrate SiSub is formed by alternating multiple silicon layers 1012 and multiple silicon germanium layers 1011.

[0059] In Fig. 10B, a channel etching operation is performed on the wafer 1000 to create a plurality of channels 1020 in the wafer 1000. In Fig. 10C, a shallow trench isolation (STI) insulating layer STI is formed on the wafer 1000. Next, in Fig. 10D, a gate region GZ is defined in the wafer 1000, and a dummy gate structure DG1 and a dummy gate structure DG2 are formed in the gate region GZ.

[0060] 10E, spacer structures SPR2, SPR1, and SPR3 are formed between the dummy gate structures DG1 and DG2, outside the dummy gate structures DG1, and outside the dummy gate structures DG2, respectively. The spacer structures SPR2, SPR1, and SPR3 may be dielectric structures.

[0061] 10F, a dielectric layer ILD1 covers and masks the gate region GZ in the wafer 1000. In addition, a dielectric layer ILD2 covers two side surfaces of the wafer 1000, exposing the source region SZ and the drain region DZ in the wafer.

[0062] 10G, an etching operation may be performed on the wafer 1000 to remove the silicon germanium layer in the source region SZ and the drain region DZ of the wafer 1000 to form a plurality of channel pillars CHP. Also, the channel pillars CHP may be plasma doped to form highly doped regions to form source and drain structures.

[0063] In FIG. 10H, a dielectric layer ILD2 is provided to cover the source and drain regions of the wafer 1000. In FIG. 10I, the dielectric layer ILD1 covering the gate region GZ of the wafer 1000 is removed, and the dummy gate structure in the gate region GZ is removed. In FIG. 10J, the spacing effect of the spacer structures SPR2, SPR1, and SPR3 can define a first portion GP1 and a second portion GP2 in the gate region. Furthermore, by removing the silicon germanium layer in the first portion GP1 and the second portion GP2, multiple channel pillars may be formed in the first portion GP1 and the second portion GP2, and each channel pillar may be a nanowire or a nanosheet. Note that for ease of observation, the dielectric layer ILD2 that originally masks the wafer 1000 is not depicted in FIG. 10J.

[0064] In FIG. 10K, a gate oxide layer may be formed on multiple channel pillars in the first portion GP1 and the second portion GP2 of the wafer 1000. Next, multiple conductive structures MS1 and MS2 may be formed on the gate oxide layer, with the conductive structures MS1 being isolated from each other and the conductive structures MS2 being isolated from each other by means known to those skilled in the art. The conductive structures MS1 surround the channel pillars in the first portion GP1 of the wafer 1000, and the conductive structures MS2 surround the channel pillars in the second portion GP2 of the wafer 1000. The conductive structures MS1 are configured to form a common gate for multiple primary transistors, and the conductive structures MS2 are configured to form a common gate for multiple auxiliary transistors. In this embodiment, the conductive structures MS1 may be arranged vertically one above the other along the Z-axis direction, with a spacing between adjacent two conductive structures MS1 so that they do not contact each other. The conductive structures MS2 may be arranged vertically one above the other along the Z-axis direction, with a spacing between adjacent two conductive structures MS2 so that they do not contact each other. Also, in other embodiments of the present disclosure, the conductive structures MS2 may be electrically coupled to each other to form a single conductive structure.

[0065] In FIG. 10L, a dielectric layer ILD3 is formed on the wafer 1000, the dielectric layer ILD3 completely covering the surface of the wafer 1000.

[0066] 10M, a plurality of third conductive structures MS3 are formed on the wafer 1000. Here, the third conductive structures MS3 are electrically coupled to end portions of a plurality of channel pillars adjacent to the first conductive structures MS1. In this embodiment, the third conductive structures MS3 extend vertically and are conductive plug structures. The third conductive structures MS3 are configured to be electrically coupled to bit lines.

[0067] 10M, the wafer 1000 includes a plurality of dummy channel pillars DNW, which may also be referred to as dummy nanowires or dummy nanosheets, and these dummy channel pillars DNW may function as support structures for supporting the first conductive structure MS1 and the second conductive structure MS2.

[0068] 10N, the first conductive structure MS1 and the second conductive structure MS2 form a stepped structure, where the stepped surfaces of the stepped first conductive structure MS1 may be electrically coupled to primary word lines in an upper layer via a plurality of vertically arranged conductive plugs CV1, and the stepped surfaces of the stepped second conductive structure MS2 may be electrically coupled to auxiliary word lines in an upper layer via a plurality of vertically arranged conductive plugs CV2.

[0069] 10O, for the sake of clarity, the dummy channel pillars DNW of the stepped first conductive structure MS1 and the stepped second conductive structure MS2 are not shown, and in this embodiment, the dummy channel pillars DNW are still retained on the wafer 1000.

[0070] 11A to 11C are schematic diagrams of a process flow for the circuit structure of a memory cell array according to an embodiment of the present disclosure. The memory cell array 1100 can be divided into a transistor zone TZ and a capacitor zone CPZ. The memory cell array 1100 has a plurality of channel pillars 1110. In FIG. 11A, no capacitors are formed in the capacitor zone CPZ of the memory cell array 1100. In FIG. 11B, a dielectric layer ILD is formed on the transistor zone TZ of the memory cell array 1100, and the dielectric layer ILD masks the transistor zone TZ of the memory cell array 1100. Next, as shown in FIG. 11C, a plurality of capacitors CSA are formed in the capacitor zone CPZ of the memory cell array 1100. The capacitors CSA are each electrically coupled to the channel pillars 1110.

[0071] 12A to 12C show implementation details of a method for forming a capacitor of a memory cell array according to an embodiment of the present disclosure. In FIG. 12A , for each capacitor CSA, an internal electrode 1240 may be formed on two sides of a plurality of channel pillars 1200, and the internal electrode 1240 may cover the channel pillar 1200. In other words, the internal electrode 1240 forms and covers the outer surface of the channel pillar 1200 in the capacitor zone. In this embodiment, the channel pillar 1200 is electrically coupled to the transistor zone of the memory cell array via a node SN. In FIG. 12B , a portion of the region of the channel pillar 1200 covered by the internal conductive film 1240 may be removed. Next, as shown in FIG. 12C , a dielectric layer 1230 is formed on two sides of the internal conductive film 1240, and an external conductive film 1210 and an external conductive film 1220 are formed outside the dielectric layer 1230. The outer conductive film 1220 is formed between two adjacent conductive films 1240. In other words, the outer conductive film 1220 is surrounded by the inner conductive film 1240, which is further surrounded by the outer conductive film 1210. Furthermore, the outer conductive film 1220 and the outer conductive film 1210 are electrically coupled to each other. Furthermore, end portions of the outer conductive film 1220 and the outer conductive film 1210 that are electrically coupled to each other may be electrically coupled to a common electrode plate at the side, away from the node SN.

[0072] 13A and 13B, FIG. 13A is a side view of a channel pillar in a memory cell array structure according to an embodiment of the present disclosure. FIG. 13B is a side view of a channel pillar and a conductive structure in a memory cell array structure according to an embodiment of the present disclosure. In FIG. 13A, a plurality of channel pillars 1310 made of silicon material are arranged in an array. The vertical distance T1 between two adjacent channel pillars 1310 may be determined by the thickness of the SiGe layer between the silicon layers forming the channel pillars 1310. In an embodiment of the present disclosure, to prevent the conductive structures 1320 surrounding each channel pillar 1310 (shown in FIG. 13B) from contacting each other, the thickness of the silicon germanium layer that functions as a sacrificial layer in the manufacturing process may be greater than twice the sidewall thickness T3 of the conductive structures 1320.

[0073] On the other hand, among the channel pillars 1310 each surrounded by a conductive structure 1320, the distance T2 between two adjacent channel pillars 1310 on a horizontal line may be less than twice the thickness T3 of the conductive structure 1320.

[0074] 14A and 14B, FIG. 14A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 14B is a top view of the memory cell array structure according to the embodiment of FIG. 14A. FIG. 14A shows two memory cell array structures 1410 and 1420. The structures of the memory cell array structure 1410 and the memory cell array structure 1420 are similar to the circuit structure of the memory cell array structure 500 in FIG. 5A. In this embodiment, the capacitor CSA1 in the memory cell array structure 1410 is electrically coupled to one side of the common electrode plate PLT, and the capacitor CSA2 in the memory cell array structure 1420 is electrically coupled to the other side of the common electrode plate PLT. The capacitors CSA1 and CSA2 receive the same reference voltage via the common electrode plate PLT.

[0075] Additionally, in the memory cell array structure 1410, a first conductive structure 1412 extends along the Z-axis and forms a common gate for a plurality of primary transistors. The first conductive structure 1412 is electrically coupled to a primary word line WLm1. A second conductive structure 1413 extends along the Z-axis and forms a common gate for a plurality of auxiliary transistors. The second conductive structure 1413 is electrically coupled to an auxiliary word line WLa1. The primary word line WLm1 and the auxiliary word line WLa1 may extend along the X-axis.

[0076] In the memory cell array structure 1420, a first conductive structure 1422 extends along the Z-axis and forms a common gate for a plurality of primary transistors. The first conductive structure 1422 is electrically coupled to a primary word line WLm2. A second conductive structure 1423 extends along the Z-axis and forms a common gate for a plurality of auxiliary transistors. The second conductive structure 1423 is electrically coupled to an auxiliary word line WLa2. The primary word line WLm2 and the auxiliary word line WLa2 may extend along the X-axis.

[0077] Note that the third conductive structure 1414 electrically coupled to the memory cell array structure 1410 extends along the X-axis direction and is electrically coupled to a bit line BL via a conductive plug 1414-1 (extending along the Z-axis direction). The third conductive structure 1424 electrically coupled to the memory cell array structure 1420 also extends along the X-axis direction and is electrically coupled to the same bit line BL via a conductive plug 1424-1 (extending along the Z-axis direction). The bit line BL may extend across the common electrode plate PLT and be coupled between the memory cell array structure 1410 and the memory cell array structure 1420. The third conductive structure 1414 of the memory cell array structure 1410 and the third conductive structure 1424 of the memory cell array structure 1420 are mirror images of each other along the common electrode plate PLT.

[0078] Fig. 14B is a top view of Fig. 14A. For clarity, Fig. 14B does not depict the bit line BL, the primary word line WLm1 and the primary word line WLm2, and the auxiliary word line WLa1 and the auxiliary word line WLa2 shown in Fig. 14A.

[0079] 15A and 15B, FIG. 15A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 15B is a top view of the memory cell array structure according to the embodiment of FIG. 15A. In FIG. 15A, there are two memory cell array structures 1510 and 1520. The structure of either memory cell array structure 1510 or memory cell array structure 1520 is similar to the circuit structure of memory cell array structure 500 in FIG. 5A.

[0080] Unlike FIG. 14A , in this embodiment, memory cell array structure 1510 and memory cell array structure 1520 share a common third conductive structure 1514. Third conductive structure 1514 is simultaneously electrically coupled to the source regions of memory cell array structure 1510 and memory cell array structure 1520 and is electrically coupled to a common bit line BL via a vertical conductive plug. Memory cell array structure 1510 and memory cell array structure 1520 are arranged symmetrically with respect to third conductive structure 1514. First conductive structure 1512 and first conductive structure 1522 form common gates of multiple primary transistors of memory cell array structure 1510 and memory cell array structure 1520, respectively, and are electrically coupled to primary word line WLm1 and primary word line WLm2, respectively. Second conductive structure 1513 and second conductive structure 1523 form common gates of multiple auxiliary transistors of memory cell array structure 1510 and memory cell array structure 1520, respectively, and are electrically coupled to auxiliary word line WLa1 and auxiliary word line WLa2, respectively. Capacitor CSA1 of memory cell array structure 1510 is electrically coupled to common electrode plate PLT1, and capacitor CSA2 of memory cell array structure 1520 is electrically coupled to common electrode plate PLT2.

[0081] 15B is a top view of FIG. 15A. For clarity, FIG. 15B does not depict the bit lines BL, primary word lines WLm1 and WLm2, and auxiliary word lines WLa1 and WLa2 shown in FIG. 15A. In this embodiment, not only the memory cell array structure 1510 and the memory cell array structure 1520 but also the metal wiring for the primary word lines WLm1 and WLm2 and the auxiliary word lines WLa1 and WLa2 are arranged symmetrically with respect to the third conductive structure 1514. In other embodiments, the layout of the metal wiring is not limited to this.

[0082] 16, which is a three-dimensional view of another implementation of a memory cell array structure according to an embodiment of the present disclosure. FIG. 16 illustrates the integration of a memory cell array structure 1640 from a plurality of memory cell array structures 1610. The memory cell array structure 1610 and the memory cell array structure 1620 may be constructed according to the implementation of FIG. 14A, and the memory cell array structure 1630 and the memory cell array structure 1640 may also be constructed according to the implementation of FIG. 14A. In addition, the array structures constructed by the memory cell array structure 1610 and the memory cell array structure 1620 and the memory cell array structure 1630 and the memory cell array structure 1640, respectively, may be combined with each other and may be insulated from each other via dielectric spacers DS.

[0083] In this embodiment, the common electrode plates PLT1 and PLT2 shared by the memory cell array structure 1610 and the memory cell array structure 1620 may be insulated from each other via a dielectric spacer DS. Therefore, when the common electrode plates PLT1 and PLT2 receive the same reference voltage, a wire WIR may be provided across the dielectric spacer DS to electrically couple the common electrode plates PLT1 and PLT2. The memory cell array structure 1610 and the memory cell array structure 1630 are mirror-symmetrical along the dielectric spacer DS. Similarly, the memory cell array structure 1620 and the memory cell array structure 1640 are mirror-symmetrical along the dielectric spacer DS. The symmetrical staircase structures of the memory cell array structure 1610 and the memory cell array structure 1630 can be formed simultaneously, thereby reducing process complexity.

[0084] 17, which is a three-dimensional view of another implementation of a memory cell array structure according to an embodiment of the present disclosure. FIG. 17 illustrates the integration of a memory cell array structure 1740 from a plurality of memory cell array structures 1710. The memory cell array structures 1710 and 1720 are constructed according to the implementation of FIG. 14A, and the memory cell array structures 1730 and 1740 are also constructed according to the implementation of FIG. 14A. In addition, the array structures formed by the memory cell array structures 1710 and 1720, and the memory cell array structures 1730 and 1740, respectively, may be combined with each other and may be insulated from each other via dielectric spacers DS.

[0085] 16, in this embodiment, the step of forming the dielectric spacers DS may be earlier than the step of forming the common electrode plate PLT. Therefore, the common electrode plate PLT in this embodiment may not be divided into multiple parts by the dielectric spacers DS. Therefore, the memory cell array structures 1710 to 1740 may receive the same reference voltage through the shared common electrode plate PLT without extra metal wiring.

[0086] 18, which is a three-dimensional view of another implementation of a memory cell array structure according to an embodiment of the present disclosure. The memory cell array structure in FIG. 18 is an integration of a plurality of memory cell array structures 1810 to 1840. The memory cell array structure 1810 and the memory cell array structure 1820 are constructed according to the implementation of FIG. 15A, and the memory cell array structure 1830 and the memory cell array structure 1840 are also constructed according to the implementation of FIG. 15A. In addition, the array structures constructed by the memory cell array structure 1810 and the memory cell array structure 1820, and the memory cell array structure 1830 and the memory cell array structure 1840, respectively, may be combined with each other and may be insulated from each other via dielectric spacers DS.

[0087] In this embodiment, the capacitors of the memory cell array structure 1810 and the memory cell array structure 1830 may be electrically coupled to the same common electrode plate PLT1, while the capacitors of the memory cell array structure 1820 and the memory cell array structure 1840 may be electrically coupled to the same common electrode plate PLT2. The common electrode plates PLT1 and PLT2 are located at different positions. In addition, the third conductive structures of the memory cell array structure 1810 and the memory cell array structure 1830 are formed simultaneously and then separated in the subsequent step of forming the dielectric spacer DS. This reduces process complexity. The third conductive structure of the memory cell array structure 1810 is shared with the memory cell array structure 1820. The third conductive structure of the memory cell array structure 1830 is shared with the memory cell array structure 1840.

[0088] 19A and 19B, FIG. 19A is a three-dimensional view of another implementation of a memory cell array structure according to an embodiment of the present disclosure. FIG. 19B is a top view of the memory cell array structure according to the embodiment of FIG. 19A. The memory cell array structure in FIG. 19A integrates multiple memory cell array structures 1910 to 1940. Memory cell array structures 1910 to 1940 are similar to the memory cell array structure shown in FIG. 17. Unlike the previous embodiment, in this embodiment, multiple conductive array vias TAVW1 may be provided at the locations of first conductive structures 1912 and second conductive structures 1913 adjacent to memory cell array structure 1910, and multiple conductive array vias TAVW2 may be provided at the locations of first conductive structures 1942 and second conductive structures 1943 adjacent to memory cell array structure 1940. Furthermore, a plurality of conductive array vias TAVB2 may be provided at the location of the third conductive structure adjacent to the memory cell array structure 1920, and a plurality of conductive array vias TAVB1 may be provided at the location of the third conductive structure adjacent to the memory cell array structure 1930.

[0089] Conductive array vias TAVW1 function as a medium for electrically coupling the gates of transistors in memory cell array structure 1910 to corresponding primary and auxiliary word lines, respectively. Conductive array vias TAVW2 function as a medium for electrically coupling the gates of transistors in memory cell array structure 1940 to corresponding primary and auxiliary word lines, respectively. Conductive array vias TAVB1 function as a medium for electrically coupling the sources of transistors in memory cell array structure 1930 to corresponding bit lines, respectively. Conductive array vias TAVB2 function as a medium for electrically coupling the sources of transistors in memory cell array structure 1920 to corresponding bit lines, respectively.

[0090] In this embodiment, the conductive array vias TAVW1, TAVW2, TAVB1, and TAVB2 may be arranged in blank spaces of the memory cell array structures that have no nearby circuits, eliminating the need for extra space for layout. The conductive array vias TAVW1 and TAVW2 may be arranged adjacent to the capacitors of the corresponding memory cell array structures 1910 and 1940, thereby improving area efficiency without wasting space near the capacitors. Furthermore, the conductive array vias TAVW1 and TAVW2 may be arranged along the extension direction of the capacitors. The conductive array vias TAVB1 and TAVB2 are arranged near the third conductive structures of the memory cell array structures 1920 and 1930, thereby effectively improving signal transmission efficiency between the memory cell arrays and the corresponding bit lines. In other embodiments, additional conductive array vias TAVW1 / TAVW2 / TAVB1 / TAVB2 can be implemented in all memory cell array structures.

[0091] Referring to FIG. 20, FIG. 20 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. In FIG. 20, the memory cell array structure 2000 may have a structure similar to that shown in FIG. 17. Unlike the previous embodiment, in this embodiment, multiple pads PD1 may be formed on the bit lines BL of the memory cell array structure 2000. The memory cell array structure 2000 may be electrically coupled to a chip on another wafer 2001 via the pads PD1. The wafer 2001 may include peripheral circuits related to the memory cell array structure 2000, and the wafer 2001 may be electrically coupled to the pads PD1 via multiple pads PD2 formed on the wafer 2001 for signal and power transmission. Similarly, corresponding pads may be formed above the primary word lines and auxiliary word lines. In this embodiment, the connection between the pads PD1 in the memory cell array structure 2000 and the pads PD2 on the wafer 2001 may be performed through a wafer bonding process.

[0092] According to the arrangement of this embodiment, the pads PD1 may be evenly distributed at many positions on the bit lines BL, or may be disposed above the capacitors. This ensures sufficient space for wiring in the memory cell array structure 2000 and allows the space above the capacitors to be utilized. In this embodiment, the pads PD1 and PD2 may be copper pads.

[0093] Referring to FIG. 21, FIG. 21 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. In FIG. 21, the memory cell array structure 2100 may have a structure similar to that shown in FIG. 17. Note that the plurality of third conductive structures 2114, 2124, and 2144 of the memory cell array structure 2100 form a step structure. Furthermore, in this embodiment, the step structure of the third conductive structures 2114, 2124, and 2144 may be a minimum incremental layer cost (MiLC) step structure. The increment of each layer on the step may be determined according to the size of the conductive plug to be provided. In this manner, the step structure of the third conductive structures 2114, 2124, and 2144 may have a minimum dimension in the length of the bottom of the step (e.g., length LS), thereby reducing the required volume of the circuit layout.

[0094] 22, which is a top view of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure in FIG. 22 is formed from a plurality of memory cell array structures 2211 to a memory cell array structure 2243. The embodiment in FIG. 22 may be formed by combining the embodiments in FIG. 15A and FIG. 16. The memory cell array structure 2211 and the memory cell array structure 2212 share the same common electrode plate PLT1, the memory cell array structure 2212 and the memory cell array structure 2213 share the same third conductive structure 22C1, the memory cell array structure 2221 and the corresponding memory cell array structure share the same common electrode plate PLT2, the memory cell array structure 2223 and the corresponding memory cell array structure share the same third conductive structure 22C2, the memory cell array structure 2231 and the corresponding memory cell array structure share the same common electrode plate PLT3, the memory cell array structure 2233 and the corresponding memory cell array structure share the same third conductive structure 22C3, the memory cell array structure 2241 and the corresponding memory cell array structure share the same common electrode plate PLT4, and the memory cell array structure 2243 and the corresponding memory cell array structure share the same third conductive structure 22C4. Meanwhile, the memory cell array structures 2213 to 2243 are electrically coupled to common electrode plates PLT5, PLT6, PLT7, and PLT8, respectively.

[0095] 22 may be appropriately expanded according to requirements, and may be electrically coupled to each other by sharing a common electrode plate or a third conductive structure, thereby effectively increasing the layout density of the memory cell array.

[0096] 23A to 23C, which are top views of implementations of multiple memory cell array structures according to embodiments of the present disclosure. In FIG. 23A, a memory cell array structure 2301 includes a common electrode plate PLT, a plurality of channel pillars 2311 and 2312, a plurality of capacitors CSA1 and CSA2, first conductive structures 2321 and 2324, second conductive structures 2331 and 2332, and third conductive structures 2341 and 2344. Capacitors CSA1 and CSA2 are electrically coupled to two sides of the common electrode plate PLT, respectively, and are arranged symmetrically with respect to the common electrode plate PLT. Channel pillars 2311 and 2312 are electrically coupled to capacitors CSA1 and CSA2, respectively. The second conductive structures 2331 surround the channel pillars 2311 respectively to form the gates of the auxiliary transistors, and the second conductive structures 2332 surround the channel pillars 2312 respectively to form the gates of the auxiliary transistors.

[0097] In this embodiment, the channel pillars 2311 may be electrically coupled together to form a first subsection 2311-1 and a second subsection 2311-2. Similarly, the channel pillars 2312 may be electrically coupled together to form a first subsection 2312-1 and a second subsection 2312-2. The first conductive structures 2321 to 2324 surround the first subsection 2311-1, the second subsection 2311-2, the first subsection 2312-1, and the second subsection 2312-2, respectively, and form the gates of multiple primary transistors.

[0098] The third conductive structure 2341 to the third conductive structure 2344 may be electrically coupled to the first subsection 2311-1, the second subsection 2311-2, the first subsection 2312-1, and the second subsection 2312-2, respectively. In this embodiment, each of the third conductive structure 2341 to the third conductive structure 2344 may form a stepped structure. A step surface of the stepped structure may be electrically coupled to a conductive plug (e.g., conductive plug 23411). The third conductive structure 2341 to the third conductive structure 2344 may be electrically coupled to a plurality of bit lines via the conductive plugs. In this embodiment, the third conductive structure 2341 to the third conductive structure 2344 are formed along the extension direction of the capacitors CSA1 and CSA2, so that the stepped structure can be widely expanded by utilizing wasted space. This can improve area efficiency.

[0099] In Figure 23B, memory cell array structure 2302 has a similar structure to memory cell array structure 2301. Unlike Figure 23A, channel pillar 2311 and channel pillar 2312 of memory cell array structure 2302 only have second subsections 2311-2 and 2312-2. Conductive structure 2322 and conductive structure 2324 surround second subsections 2311-2 and 2312-2, respectively, and form gates of multiple primary transistors, respectively. In this embodiment, all steps of the third conductive structure can extend along one side of the capacitor, and the space on the other side of the capacitor can be used for a different purpose.

[0100] 23C , memory cell array structure 2303 includes common electrode plates PLT1 and PLT2, a plurality of channel pillars 2311 and 2312, a plurality of capacitors CSA1 and CSA2, a first conductive structure 2320, a second conductive structure 2331 and 2332, and a third conductive structure 2340. One end portion of capacitor CSA1 is electrically coupled to common electrode plate PLT1, and the other end portion of capacitor CSA1 is electrically coupled to channel pillar 2311. Meanwhile, one end portion of capacitor CSA2 is electrically coupled to common electrode plate PLT2, and the other end portion of capacitor CSA2 is electrically coupled to channel pillar 2312. Second conductive structures 2331 surround channel pillars 2311, respectively, and form gates of a plurality of auxiliary transistors. The second conductive structures 2332 each surround a channel pillar 2312 and form the gates of a plurality of auxiliary transistors. In this embodiment, the channel pillars 2311 and 2312 are electrically coupled to each other between the second conductive structures 2331 and 2332 to form a common channel pillar. The first conductive structures 2320 surround the common channel pillar and form the gates of the primary transistors.

[0101] Meanwhile, the third conductive structure 2340 is electrically coupled to the common channel pillar. A step structure may be formed on two side surfaces of the third conductive structure 2340. The step surfaces on the step structure may be electrically coupled to a plurality of conductive plugs 234C and may be electrically coupled to a plurality of bit lines via the conductive plugs 234C. The step surfaces on the step structure extend along the extension direction of the capacitors CSA1 and CSA2. In this embodiment, the step heights of the step surfaces on the two side surfaces of the third conductive structure 2340 are different from each other. However, in other embodiments, the step heights of the step surfaces on the two side surfaces of the third conductive structure 2340 may be the same.

[0102] 24A to 24C, which are top views of implementations of multiple memory cell array structures according to embodiments of the present disclosure. In FIG. 24, memory cell array structure 2401 includes multiple channel pillar columns 2411 and 2412, multiple conductive structures 2421, 2422, 2431, 2432, 2441, and 2442, multiple capacitors CSA1 and CSA2, and common electrode plates PLT1 and PLT2. In this embodiment, common electrode plate PLT1 has multiple openings h1, and common electrode plate PLT2 has multiple openings h2. Capacitor CSA1 may pass through openings h1 and common electrode plate PLT1 and be electrically coupled to common electrode plate PLT2, and capacitor CSA2 may pass through openings h2 and common electrode plate PLT2 and be electrically coupled to common electrode plate PLT1, forming an interdigitated arrangement.

[0103] Additionally, each of channel pillar 2411 and channel pillar 2412 may be a U-shaped channel pillar. Conductive structure 2421 and conductive structure 2431 may surround different portions of channel pillar 2411 and form gates of multiple transistors. Conductive structure 2422 and conductive structure 2432 may surround different portions of channel pillar 2412 and form gates of multiple transistors. Conductive structure 2441 is electrically coupled to channel pillar 2411, respectively, and conductive structure 2442 is electrically coupled to channel pillar 2412, respectively. Conductive structure 2441 may be formed in the space between adjacent capacitors CSA1, and conductive structure 2442 may be formed in the space between adjacent capacitors CSA2, thereby reducing the space required for the layout.

[0104] In this embodiment, the conductive structure 2441 and the conductive structure 2442 may have a step structure. As in the previous embodiment, the step surface may be electrically coupled to a conductive plug (the rectangular block portion in the drawing). The conductive structure 2441 and the conductive structure 2442 may be electrically coupled to a bit line via the conductive plug.

[0105] The memory cell array structure 2402 in Figure 24B is similar to the memory cell array structure 2401 described above. The difference is that, taking adjacent channel pillars 2411-1 and 2411-2 as an example, conductive structure 2421 surrounds two different portions of the same channel pillar 2411-1, while conductive structure 2431 surrounds different channel pillars 2411-1 and 2411-2. Taking opposite adjacent channel pillars 2412-1 and 2412-2 as an example, conductive structure 2422 surrounds two different portions of the same channel pillar 2412-1, while conductive structure 2432 surrounds different channel pillars 2412-1 and 2412-2.

[0106] 24C , memory cell array structure 2403 includes a plurality of channel pillar columns 2411 and 2412, a plurality of conductive structures 2421, 2422, 2431, 2432, 2441, and 2442, a plurality of capacitors CSA1 and CSA2, and common electrode plates PLT1 and PLT2. Similar to memory cell array structure 2401, common electrode plates PLT1 and PLT2 have a plurality of openings h1 and a plurality of openings h2, respectively. Capacitor CSA1 may be electrically coupled to common electrode plate PLT2 through opening h1, and capacitor CSA2 may be electrically coupled to common electrode plate PLT1 through opening h2.

[0107] In this embodiment, channel pillar 2411 and channel pillar 2412 may form an M-shape. In FIG. 24C , conductive structure 2431 may surround the upper and lower branches of channel pillar 2411 and form the gate of the auxiliary transistor. Conductive structure 2421 may surround the central branch of channel pillar 2411 and form the gate of the primary transistor. Additionally, conductive structure 2422 may surround the upper and lower branches of channel pillar 2412 and form the gate of the auxiliary transistor. Conductive structure 2432 may surround the central branch of channel pillar 2412 and form the gate of the primary transistor.

[0108] Similar to the previous embodiment, the conductive structure 2441 and the conductive structure 2442 may be stepped, and the stepped surfaces may be electrically coupled to conductive plugs (rectangular blocks in the drawings). The conductive structure 2441 and the conductive structure 2442 may be electrically coupled to bit lines via the conductive plugs.

[0109] Referring to FIG. 25, FIG. 25 is a schematic diagram of a three-dimensional structure of a memory device according to an embodiment of the present disclosure. A memory cell array structure 2500 may be disposed between a top plate 2501 and a bottom plate 2502. The top plate 2501 may include a plurality of transistors to form one or more circuits, and the bottom plate 2502 may also include a plurality of transistors to form one or more circuits. In this embodiment, the top plate 2501 may include a plurality of peripheral circuits, such as a word line decoder, a page buffer, a platform controller, and a charge pump. The bottom plate 2502 may include a plurality of peripheral circuits, such as a control logic circuit, a data transmission path, and an input / output circuit.

[0110] A third conductive structure in memory cell array structure 2500 may be electrically coupled to conductive vias CN1 and CN2 through conductive plugs, and then electrically coupled to circuits on top plate 2501 and bottom plate 2502 through conductive vias CN1 and CN2.

[0111] 26A and 26B, FIG. 26A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 26B is a top view of the memory cell array structure of FIG. 26A. The memory cell array structure in FIG. 26A is formed from two memory cell array structures 2601 and 2602 shown in FIG. 6A. The memory cell array structure 2601 and the memory cell array structure 2602 are electrically coupled to each other via a common third conductive structure 2640 (see FIG. 26B). The memory cell array structure 2601 includes a plurality of capacitors CSA1, a channel pillar 2611, a first conductive structure 2621, and a second conductive structure 2631. The memory cell array structure 2602 includes a plurality of capacitors CSA2, a channel pillar 2612, a first conductive structure 2622, and a second conductive structure 2632. In this embodiment, the first conductive structure 2621 forms the gates of a plurality of primary transistors in the memory cell array structure 2601, the second conductive structure 2631 forms the gates of a plurality of auxiliary transistors in the memory cell array structure 2601, the first conductive structure 2622 forms the gates of a plurality of primary transistors in the memory cell array structure 2602, and the second conductive structure 2632 forms the gates of a plurality of auxiliary transistors in the memory cell array structure 2602. Furthermore, the first conductive structure 2621 and the first conductive structure 2622 and the second conductive structure 2631 and the second conductive structure 2632 may all be formed as a structure called a step structure or a staircase. The first conductive structure 2621 and the first conductive structure 2622 are electrically coupled to the primary word line via conductive plug 26211 and conductive plug 26221, respectively, and the second conductive structure 2631 and the second conductive structure 2632 are electrically coupled to the auxiliary word line via conductive plug 26311 and conductive plug 26321, respectively.

[0112] A third conductive structure 2640 shared by memory cell array structure 2601 and memory cell array structure 2602 may be electrically coupled to a bit line via a conductive plug 2641 .

[0113] In this embodiment, capacitors CSA1 and CSA2, and channel pillars 2611 and 2612 may extend along the Y-axis direction, first conductive structures 2621 and 2622, and second conductive structures 2631 and 2632 may extend along the X-axis direction, and conductive plugs 26211, 26221, 26311, 26321, and 2641 may extend along the Z-axis direction.

[0114] Referring to Figure 27, Figure 27 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure in Figure 27 may also be formed from two memory cell array structures 2701 and 2702 shown in Figure 6A. What differs from Figure 26A is that the memory cell array structure 2701 and the memory cell array structure 2702 share a common electrode plate PLT. The capacitor CSA1 in the memory cell array structure 2701 and the capacitor CSA2 in the memory cell array structure 2702 are electrically coupled to two opposite sides of the common electrode plate PLT, respectively.

[0115] In memory cell array structure 2701, first conductive structure 2721 surrounds channel pillar 2711 to form the gate of the primary transistor, and second conductive structure 2731 surrounds channel pillar 2711 to form the gate of the auxiliary transistor. Both first conductive structure 2721 and second conductive structure 2731 have a stepped structure. The stepped surfaces of first conductive structure 2721 and second conductive structure 2731 are electrically coupled to conductive plug 27211 and conductive plug 27311, respectively, and are electrically coupled to the primary word line and auxiliary word line via conductive plug 27211 and conductive plug 27311, respectively. In memory cell array structure 2702, first conductive structure 2722 surrounds channel pillar 2712 to form the gate of the primary transistor, and second conductive structure 2732 surrounds channel pillar 2712 to form the gate of the auxiliary transistor. Both the first conductive structure 2722 and the second conductive structure 2732 have a step structure. The step surfaces of the first conductive structure 2722 and the second conductive structure 2732 are electrically coupled to the conductive plugs 27221 and 27321, respectively, and are electrically coupled to the primary word line and the auxiliary word line via the conductive plugs 27221 and 27321, respectively.

[0116] Additionally, memory cell array structure 2701 and memory cell array structure 2702 may be electrically coupled to bit lines via normalized (stepless) conductive plugs 27411 and 27421.

[0117] 28, which is a schematic diagram of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure in FIG. 28 is formed of a plurality of memory cell array structures 2801 to 2804. The memory cell array structure 2801 and the memory cell array structure 2802 may be combined with each other to form a first section structure S1 according to the embodiment of FIG. 27, and the memory cell array structure 2803 and the memory cell array structure 2804 may be combined with each other to form a second section structure S2 according to the embodiment of FIG. 27. In this embodiment, the memory cell array structure 2801 and the memory cell array structure 2802 share a common electrode plate PLT1, and the memory cell array structure 2803 and the memory cell array structure 2804 share a common electrode plate PLT2.

[0118] Isolation can be achieved by disposing a dielectric spacer DS between the first section structure S1 and the second section structure S2. In this embodiment, the common electrode plate PLT1 and the common electrode plate PLT2 may independently receive the same or different reference voltages.

[0119] In this embodiment, the step structures of the conductive structures of the memory cell array structure 2801 and the memory cell array structure 2803 are symmetrical with respect to the dielectric spacer DS. Similarly, the step structures of the conductive structures of the memory cell array structure 2802 and the memory cell array structure 2804 are symmetrical with respect to the dielectric spacer DS. In this manner, the conductive plugs for electrically coupling to the word lines can also have a relatively symmetrical structure.

[0120] Referring to FIG. 29, FIG. 29 is a schematic diagram of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure in FIG. 29 is formed of a plurality of memory cell array structures 2901 to 2904. The memory cell array structure in FIG. 29 is similar to the memory cell array structure in FIG. 28. The difference is that in FIG. 29, a wire WIR may be formed between the common electrode plate PLT1 and the common electrode plate PLT2 by back end of line (BEoL) processing to electrically couple the common electrode plate PLT1 and the common electrode plate PLT2. In this way, the common electrode plate PLT1 and the common electrode plate PLT2 receive the same reference voltage via the wire WIR, which can reduce the wiring complexity of the memory cell array structure.

[0121] Referring to FIG. 30, FIG. 30 is a schematic diagram of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure in FIG. 30 is formed of a plurality of memory cell array structures 3001 to 3004. The memory cell array structure in FIG. 30 is similar to the memory cell array structure in FIG. 29. The difference is that in FIG. 30, a common electrode plate PLT is formed after the dielectric spacer, and the dielectric spacer may be divided into two dielectric spacers, DS1 and DS2. In this case, the memory cell array structures 3001 to 3004 may share the same common electrode plate PLT, and no additional wire is required to connect the common electrode plates.

[0122] 31, which is a schematic diagram of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure in FIG. 31 is formed of a plurality of memory cell array structures 3101 to 3108. Memory cell array structures 3101 to 3104 may be constructed as in the embodiment shown in FIG. 29 or 30. Memory cell array structures 3105 to 3108 may be constructed by mirroring memory cell array structures 3101 to 3104.

[0123] Referring to FIG. 32, FIG. 32 is a schematic diagram of a memory cell array structure according to another embodiment of the present disclosure. The memory cell array structure in FIG. 32 is formed of a plurality of memory cell array structures 3201 to 3208. The arrangement of the memory cell array structures 3201 to 3208 is similar to that of the embodiment in FIG. 31. That is, due to the mirrored arrangement, in this embodiment, the adjacently arranged memory cell array structure 3203 and memory cell array structure 3025 share the same primary word line WLm1 and auxiliary word line WLa1, and the adjacently arranged memory cell array structure 3204 and memory cell array structure 3026 share the same primary word line WLm2 and auxiliary word line WLa2, which is beneficial for the control operation of word line signals. In this embodiment, the BEoL metal wiring for sharing the primary word line and auxiliary word line is demonstrated as a U-shaped wiring. Moreover, the wiring of the primary word line is a mirror image of the wiring of the auxiliary word line. In other embodiments, the shape of the wiring is not limited thereto.

[0124] Referring to FIG. 33, FIG. 33 is a schematic diagram of a memory cell array structure according to another embodiment of the present disclosure. FIG. 33 is an implementation example of a metal oxide semiconductor field effect transistor under-array (CMOS under-array, CuA) manufacturing process. The memory cell array structure in FIG. 33 is formed of memory cell array structure 3301 to memory cell array structure 3304. A plurality of conductive array vias TAVW and conductive array vias TAVB may be arranged around and in spaces between memory cell array structure 3301 to memory cell array structure 3304. The conductive array TAVW is a medium for electrically coupling word lines (including primary word lines and auxiliary word lines) to memory cell array structure 3301 to memory cell array structure 3304, and the conductive array TAVB is a medium for electrically coupling bit lines to memory cell array structure 3301 to memory cell array structure 3304. In this embodiment, the conductive array vias TAVW are arranged adjacent to capacitors in memory cell array structure 3301 to memory cell array structure 3304, which may result in higher space efficiency. In this embodiment, both the conductive array vias TAVW and the conductive array vias TAVB can be placed in the free space on the wafer without increasing the layout area.

[0125] 34A and 34B, FIG. 34A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 34B is a top view of the memory cell array structure of FIG. 34A. The memory cell array structure 3400 includes a plurality of capacitors CSA, a channel pillar 3410, a first conductive structure 3420, a second conductive structure 3430, and a plurality of conductive plugs 3421, 3431, and 3441. Different from the previous embodiment, in this embodiment, the conductive plug 3421 electrically coupled to the first conductive structure 3420 and the conductive plug 3431 electrically coupled to the second conductive structure 3430 may be formed on different sides. In this manner, the complexity of the word line layout of the memory cell array structure 3400 may be effectively reduced.

[0126] 34C, which is a diagram of another implementation of the memory cell array structure of FIG. 34A. In FIG. 34C, the first conductive structure 3420 and the second conductive structure 3430 may further extend in a U-shape and extend to two sides of the capacitor CSA along the extension direction of the capacitor CSA (e.g., the Y-axis direction). In this manner, conductive plugs 3431 and conductive plugs 3421 are formed on two symmetrical side surfaces of the capacitor CSA, which can increase the integration density in the Y-axis direction.

[0127] Referring to FIG. 35, FIG. 35 is a schematic diagram of a memory device according to another embodiment of the present disclosure. The memory device 3500 includes a wafer 3520 and a memory cell array structure 3510. A plurality of pads PD1 may be formed on the word lines and bit lines of the memory cell array structure 3510. A plurality of pads PD2 may be formed on the surface of the wafer 3520. The wafer 3520 and the memory cell array structure 3510 may be electrically coupled by a wafer bonding process using the pads PD2 and PD1. The wafer 3520 is configured to accommodate a plurality of peripheral circuits of the memory cell array structure 3510.

[0128] In this embodiment, the pad PD1 is formed directly above the capacitor CSA in the memory cell array structure 3510, which can improve space utilization efficiency.

[0129] The pads PD1 and PD2 may be copper pads.

[0130] 36A to 36C, which are top views of memory cell array structures according to several embodiments of the present disclosure. The memory cell array structure in FIG. 36A includes two memory cell array structures, a memory cell array structure 3601 and a memory cell array structure 33602, arranged side by side. The structures of the memory cell array structure 3601 and the memory cell array structure 3602 are the same as the memory cell array structure 3400 shown in FIG. 34C, and the related details will not be repeated here.

[0131] In this embodiment, in the memory cell array structure 3601, a conductive plug 36111 electrically coupled to the first conductive structure 3611 may be formed on a first side (e.g., an upper side) of the memory cell array structure 3601, and a conductive plug 36211 electrically coupled to the second conductive structure 3621 may be formed on a second side (e.g., a lower side) of the memory cell array structure 3601. In the memory cell array structure 3602, a conductive plug 36121 electrically coupled to the first conductive structure 3612 may be formed on a first side (e.g., an upper side) of the memory cell array structure 3602, and a conductive plug 36221 electrically coupled to the second conductive structure 3622 may be formed on a second side (e.g., a lower side) of the memory cell array structure 3602. With this arrangement, there may be a gap between the conductive plug 36211 and the conductive plug 36121 formed by the first conductive structure 3611, and they may not be directly adjacent to each other.

[0132] 36B also shows memory cell array structures 3601 and 3602 having the same structure, arranged side by side. The memory cell array structures 3601 and 3602 are insulated from each other via dielectric spacers DS. In this arrangement, the first conductive structure 3611 and the second conductive structure 3621 in the memory cell array structure 3601 have a stepped structure on the first side (upper side), and the first conductive structure 3612 and the second conductive structure 3622 in the memory cell array structure 3602 have a stepped structure on the second side (lower side). Conductive plugs 36111 and 36211 for electrical coupling to word lines are electrically coupled to the step structures of the first conductive structure 3611 and the second conductive structure 3621, respectively, and conductive plugs 36121 and 36221 for electrical coupling to word lines are electrically coupled to the step structures of the first conductive structure 3612 and the second conductive structure 3622, respectively. In this embodiment, the step structures are simultaneously formed, and then a dielectric spacer DS insulates the step structures to form the first conductive structure 3611 and the first conductive structure 3612 and the second conductive structure 3621 and the second conductive structure 3622. The process complexity is greatly reduced.

[0133] FIG. 36C shows an array of four identical memory cell array structures 3601 to 3604. In this embodiment, the memory cell array structure 3601 and the memory cell array structure 3603 are arranged side by side and insulated from each other via a dielectric spacer DS1. The memory cell array structure 3602 and the memory cell array structure 3604 are arranged side by side and insulated from each other via a dielectric spacer DS2. In addition, the memory cell array structure 3601 and the memory cell array structure 3602 extend along the same first direction D1 and are electrically coupled to two side surfaces of the common electrode plate PLT, respectively. The memory cell array structure 3603 and the memory cell array structure 3604 extend along the same first direction D1 and are electrically coupled to two side surfaces of the common electrode plate PLT, respectively.

[0134] In this embodiment, the extension direction of the common electrode plate PLT may be perpendicular to the direction D1, and the dielectric spacers DS1 and DS2 may extend along the direction D1.

[0135] 37, which is a top view of a memory device according to another embodiment of the present disclosure. Memory device 3700 includes a plurality of memory cell array structures 3701 to 3704 and peripheral circuitry 3705. In this embodiment, memory cell array structures 3701 to 3704 share peripheral circuitry 3705. Memory cell array structures 3701 to 3704 are arranged around peripheral circuitry 3705. Sense amplifiers may be arranged in peripheral circuitry 3705 and may be adjacent to bit lines of memory cell array structures 3701 to 3704.

[0136] Peripheral circuit 3705 may include associated circuits corresponding to each of the plurality of sense amplifiers of memory cell array structure 3701 to memory cell array structure 3704. Peripheral circuit 3705 is electrically coupled to the bit lines of memory cell array structure 3701 to memory cell array structure 3704 via bit line buses BB1 to BB4, respectively, and is electrically coupled to the word lines of memory cell array structure 3701 to memory cell array structure 3704 via word line buses WB1 to WB4, respectively. Peripheral circuit 3705 is disposed adjacent to the stepped structures of the conductive structures of memory cell array structure 3701 to memory cell array structure 3704, which may effectively reduce the wiring lengths required for bit line buses BB1 to BB4 and word line buses WB1 to WB4. Furthermore, by arranging the memory cell array structures 3701 to 3704 symmetrically with respect to the peripheral circuit 3705, the consistency of the wiring lengths from the bit line bus BB1 to the bit line bus BB4 and from the word line bus WB1 to the word line bus WB4 can be improved, and the transmission time difference between the transmitted bit line signals and word line signals can be normalized.

[0137] Referring to FIG. 38A, FIG. 38A is a top view of a memory device according to another embodiment of the present disclosure. This is a continuation of the embodiment of FIG. 37. The memory device 3800 in FIG. 38A may be an expanded version of the embodiment of FIG. 37. The memory device 3800 includes a plurality of memory cell array structures 3801 and 3802, a plurality of peripheral circuits 3805, and addressing circuits 3803 and 3804. The peripheral circuits 3805 may be arranged in a row and disposed in the middle of the memory device 3800. The memory cell array structure 3801 is arranged in a row and is disposed on a first side (top side) of the peripheral circuits 3805. The memory cell array structure 3802 is arranged in another row and is disposed on a second side (bottom side) of the peripheral circuits 3805.

[0138] Addressing circuitry 3803 and addressing circuitry 3804 are disposed on opposing third and fourth sides of memory device 3800, respectively.

[0139] In this embodiment, the peripheral circuit 3805 may be shared by four surrounding memory cell array structures 3801 and 3802, and the relevant details are the same as those in the embodiment in Figure 37. The addressing circuit 3803 and the addressing circuit 3804 may control the operation of all circuits on each peripheral circuit 3805. An address information transmission path may be formed between the addressing circuit 3803 and the addressing circuit 3804, and the address information transmission path is configured to transmit global address information.

[0140] Referring to FIG. 38B, FIG. 38B is a top view of a memory device according to another embodiment of the present disclosure. In FIG. 38B, compared with FIG. 38A, the memory device 3800′ may further include an addressing circuit 3806 disposed in the middle of the memory device 3800′, dividing the aligned memory cell array structures into a plurality of memory cell array structures 3801-1, 3801-2, 3802-1, and 3802-2. Similarly, the peripheral circuit 3805 may be divided into two parts by the addressing circuit 3806. In this embodiment, a first address information transmission path may be generated between the addressing circuit 3803 and the addressing circuit 3806, and a second address information transmission path may be generated between the addressing circuit 3804 and the addressing circuit 3806. As is apparent from FIG. 38B, the length of the address information transmission path may be effectively shortened compared with the embodiment in FIG. 38A.

[0141] 39 is a schematic diagram of the layout structure of a memory device according to another embodiment of the present disclosure. The memory device 3900 includes a plurality of memory cell array structures 39011 to 390MN, addressing circuits 3911 to 3913, a plurality of bit line sense amplifiers BLSA, a plurality of word line drivers WLd, and a plurality of control circuits 3920. The memory cell array structures 39011 to 390MN are arranged in an array, and the addressing circuits 3912 and 3913 are disposed on two sides (e.g., the upper and lower sides) of the array formed by the memory cell array structures 39011 to 390MN, respectively, and the addressing circuits 3912 and 3913 extend along a direction D1. The addressing circuit 3911 is disposed in the center of the array formed by the memory cell array structures 39011 to 390MN and extends along a direction D2. The direction D1 is perpendicular to the direction D2.

[0142] Here, the arrangement of the bit line sense amplifiers BLSA and the word line drivers WLd will be referred to in the memory cell array structure 39011. The memory cell array structure 39011 has a connection structure ST1 and a connection structure ST2. The connection structure ST1 is configured to be electrically coupled to a word line corresponding to the memory cell array structure 39011, and the connection structure ST2 is configured to be electrically coupled to a bit line corresponding to the memory cell array structure 39011. At least one of the connection structure ST1 and the connection structure ST2 may have a step structure. Details of the implementation of the step-structure connection structure on the memory cell array structure 39011 have been described in detail in the above embodiments and will not be repeated here.

[0143] Corresponding to the memory cell array structure 39011, the word line driver WLd may be arranged adjacent to the connection structure ST1, and the bit line sense amplifier BLSA may be arranged adjacent to the connection structure ST2, which may effectively reduce the complexity of the wiring and shorten the length required for the wiring.

[0144] The arrangement of the bit line sense amplifiers and word line drivers for each of the memory cell array structures 39011 to 390MN can be referred to the arrangement of the memory cell array structure 39011, bit line sense amplifiers BLSA, and word line drivers WLd described above, and will not be repeated here.

[0145] Due to the above arrangement, there are blank areas between the memory cell array structure 39022, the memory cell array structure 39023, the memory cell array structure 39032, and the memory cell array structure 39033, which can be used to place the control circuit 3920. In this embodiment, the control circuit 3920 may be a regional control circuit, and the addressing circuits 3911 to 3913 may be global addressing circuits.

[0146] 40A and 40B, FIG. 40A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 40B is a top view of the memory cell array structure according to the embodiment of FIG. 40A of the present disclosure. In FIG. 40A, two memory cell array structures 4001 and 4002 are integrated with each other. The structures of the memory cell array structure 4001 and the memory cell array structure 4002 are similar to those of the embodiment of FIG. 27, except that in this embodiment, the memory cell array structure 4001 and the memory cell array structure 4002 are electrically coupled to a plurality of common electrode plates PLT1 to PLT3. Here, taking the case where the Z-axis direction is the column direction and the X-axis direction is the row direction as an example, each of the common electrode plates PLT1 to PLT3 extends along the Z-axis direction. Each of the common electrode plates PLT1 to PLT3 is electrically coupled to the capacitor CSA1 in the same column and the capacitor CSA2 in the same column in the memory cell array structure 4001 and the memory cell array structure 4002.

[0147] In this embodiment, the bit lines corresponding to the common electrode plates PLT1 to PLT3 are divided into multiple sections. Under this arrangement, the reference voltage lines (e.g., ground voltage transmission lines) for the common electrode plates PLT1 to PLT3 can be completed in synchronization with the manufacturing process of the bit lines, reducing manufacturing costs and effectively reducing internal forces caused by imbalances in the channel pillars in the semiconductor structure. Furthermore, different bias voltages can be applied to the multiple common electrode plates, increasing the operational variability of the semiconductor structure.

[0148] In other embodiments of the present disclosure, the plurality of ground voltage transmission lines corresponding to the common electrode plates PLT1 to PLT3 may be electrically coupled to each other.

[0149] 41A and 41B, FIG. 41A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 41B is a top view of the memory cell array structure according to the embodiment of FIG. 41A of the present disclosure. In FIG. 41A, two memory cell array structures 4101 and 4102 are integrated with each other. Memory cell array structure 4101 includes a capacitor CSA1, a channel pillar 4111, a first conductive structure 4121, a second conductive structure 4131, and a third conductive structure 4141. Memory cell array structure 4102 includes a capacitor CSA2, a channel pillar 4112, a first conductive structure 4132, a second conductive structure 4122, and a third conductive structure 4142. Capacitor CSA1 of memory cell array structure 4101 and capacitor CSA2 of memory cell array structure 4102 are electrically coupled in common to a common electrode plate PLT. The structures of the memory cell array structure 4101 and the memory cell array structure 4102 have been described in detail in the above embodiments and will not be repeated here.

[0150] In this embodiment, the first conductive structure 4121 and the first conductive structure 4132, the second conductive structure 4131 and the second conductive structure 4122, and the third conductive structure 4141 and the third conductive structure 4142 may all be formed with a stepped structure. With this method, whether the channel pillar 4111 and the channel pillar 4112 are arranged at a high position or a low position, the stepped surfaces of the third conductive structure 4141 and the third conductive structure 4142 are directly connected to the corresponding bit lines via conductive plugs, which can effectively reduce the withstand capacitance delay (RC delay) at the end of the bit lines.

[0151] Referring to FIG. 42, FIG. 42 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. In FIG. 42, two memory cell array structures 4201 and 4202 are integrated with each other. The construction methods of the memory cell array structure 4201 and the memory cell array structure 4202 are similar to those in FIG. 41A and will not be repeated here. Note that in this embodiment, the memory cell array structure 4202 is taken as an example in which the third conductive structure 4142 forms a step structure. The relatively low step surface may be electrically coupled to a conductive plug 41421 and electrically coupled to a bit line BL_D through the conductive plug 41421. The relatively high step surface may be electrically coupled to a conductive plug 41422 and electrically coupled to a bit line BL_U through the conductive plug 41422. In an embodiment of the present disclosure, the bit line BL_D and the bit line BL_U may be electrically coupled to a common primary bit line.

[0152] Referring to FIG. 43, FIG. 43 is a cross-sectional view of a memory cell array structure according to another embodiment of the present disclosure. In FIG. 43, two memory cell array structures 4301 and 4302 are integrated with each other. Taking the memory cell array structure 4302 as an example, the stepped third conductive structure 4330 of the memory cell array structure 4302 may be directly electrically coupled to the bit lines BL_U and BL_D extending along the Z-axis direction. In this embodiment, the channel pillar 4132-1 arranged at a relatively high level is electrically coupled to the bit line BL_U, and the channel pillar 4132-2 arranged at a relatively low level is electrically coupled to the bit line BL_D. The bit lines BL_U and BL_D may be formed by an epitaxy growth process.

[0153] Referring to FIG. 44, FIG. 44 is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. In FIG. 44, two memory cell array structures 4401 and 4402 are integrated with each other. The memory cell array structures 4401 and 4402 are electrically coupled to a word line driver WLd. In this embodiment, taking the memory cell array structure 4401 as an example, a first conductive structure 4421 having a step structure may be electrically coupled to transmission wires MR1 ​​to MR4 via conductive plugs and electrically coupled to a primary word line via the transmission wires MR1 ​​to MR4. When the multiple first conductive structures 4421 are different in high and low levels, the lengths of the electrically coupled conductive plugs corresponding to the high and low levels of the first conductive structures 4421 are unequal. Thus, in an embodiment of the present disclosure, the arrangement may be such that the first conductive structure 4421 at the lowest level is electrically coupled to the shortest transmission wire MR1, the first conductive structure 4421 at the second lowest level is electrically coupled to the second shortest transmission wire MR2, the first conductive structure 4421 at the second highest level is electrically coupled to the second longest transmission wire MR3, and the first conductive structure 4421 at the highest level is electrically coupled to the longest transmission wire MR4.

[0154] The above arrangement can equalize the RC delay in word line signaling.

[0155] In addition, in the memory cell array structure 4401 and the memory cell array structure 4402, the connection methods between the second conductive structure 4431 and the second conductive structure 4422, as well as the first conductive structure 4421 and the auxiliary word line and the primary word line may also be implemented in the above-mentioned manner to improve the stability of signal transmission in terms of transmission time.

[0156] Referring to FIG. 45, FIG. 45 is a three-dimensional view of a memory cell array structure of another embodiment of the present disclosure. The memory cell array structure 4500 includes a plurality of capacitors CSA, a plurality of channel pillars 4510, a plurality of first conductive structures 4520, a single second conductive structure 4530, and a plurality of third conductive structures 4540. The memory cell array structure 4500 of this embodiment has a structure similar to the memory cell array structure 500 in FIG. 5A . The difference is that the memory cell array structure 4500 has only one second conductive structure 4530. The second conductive structure 4530 surrounds all the channel pillars 4510 and is electrically coupled to a common auxiliary word line WLa. In this embodiment, the auxiliary transistors in all memory cell circuits corresponding to all the channel pillars 4510 may be turned on or off simultaneously.

[0157] Additionally, the first conductive structures 4520 are electrically coupled to a plurality of primary word lines WLm, respectively, and the third conductive structures 4540 are electrically coupled to a plurality of bit lines BL, respectively.

[0158] 46A and 46B, FIG. 46A is a three-dimensional view of a memory cell array structure according to another embodiment of the present disclosure. FIG. 46B is a top view of the memory cell array structure according to the embodiment of FIG. 46A. The memory cell array structure 4600 includes a plurality of capacitors CSA, a plurality of channel pillars 4610, a plurality of first conductive structures 4620, a single second conductive structure 4630, and a plurality of third conductive structures 4640. The single second conductive structure 4630 surrounds all of the channel pillars 4610 and is electrically coupled to a common auxiliary word line WLa.

[0159] Unlike the previous embodiment, the first conductive structure 4620 in this embodiment may have an L-shaped structure. A first portion P1 of the first conductive structure 4620 extends along the X-axis direction, and a second portion P2 of the first conductive structure 4620 extends along the Y-axis direction to the side of the memory cell array structure 4600. The second portion P2 of the first conductive structure 4620 may be electrically coupled to a plurality of primary word lines WLm.

[0160] 47, which is a top view of a memory cell array structure according to another embodiment of the present disclosure. In FIG. 47, there are two memory cell array structures: 4701 and 4702. Each of the memory cell array structures 4701 and 4702 has a similar structure to the memory cell array structure 4600. A second conductive structure 4731 on the memory cell array structure 4701 may be electrically coupled to a second conductive structure 4732 on the memory cell array structure 4702 through a BEoL metal layer, and a conductive array via TAV is electrically coupled to the BEoL metal layer and then used to transfer a bias to the second conductive structure 4731 and the second conductive structure 4732 simultaneously.

[0161] Referring to FIGS. 48A and 48B, FIG. 48A is a schematic diagram of a memory chip according to an embodiment of the present disclosure. FIG. 48B is a partially enlarged schematic diagram of region Z1 of the memory chip of FIG. 48A. In FIG. 48A, a memory chip 4800 includes a plurality of memory cell blocks 48011 to 48052 arranged in an array. Each of the memory cell blocks 48011 to 48052 includes a plurality of three-dimensional stacked memory cell array structures 4801. The memory cell array structure 4801 in this embodiment may be any of the above-described embodiments and is not particularly limited. As shown in FIG. 48B, a capacitor CC1 in the memory cell array structure may extend along the X-axis direction. A plurality of buffer regions 4811 to 4814 are further arranged on the memory chip 4800. A plurality of dummy circuits DMC may be included in any of the buffer regions 4811 to 4814. The dummy circuits DMC include at least a capacitor DC1 extending along the Y-axis direction, as shown in FIG. 48B. Buffer regions 4811 to 4814 may be arranged on the dicing lanes of the memory chip 4800. By arranging capacitors DC1 extending along the Y-axis, stresses generated during the manufacturing process of the entire memory chip can be balanced, and defects in the channel pillars of the memory cell blocks due to stress imbalance can be avoided. The above-mentioned dummy circuits DMC can be manufactured simultaneously with the memory cell array structure in memory cell blocks 48011 to 48052.

[0162] The present invention also includes an electronic terminal device, which includes the memory cell circuit described above. The electronic terminal device can be a solid-state drive (SSD), a personal computer, a laptop, a tablet, a digital camera, a Universal Serial Bus (USB), a smartphone, a personal navigation device, a game console, an e-book reader, a server, or an Internet of Things (IoT) device, etc.

[0163] In summary, in the memory cell circuit of the present disclosure, an auxiliary transistor is arranged between a capacitor and a primary transistor, and by applying different bias voltages to the main transistor and the auxiliary transistor, it is possible to effectively reduce gate-induced drain leakage (GIDL) that may occur. [Industrial Applicability]

[0164] The memory cell circuit and memory cell array structure and the manufacturing method thereof of the present invention can be applied to a dynamic random access memory. [Explanation of symbols]

[0165] 100, MC-MC4: memory cell circuit 1000, 2001, 3520: Wafer 1011: Silicon germanium layer 1012: Silicon layer 1100: Memory cell array 1410, 1420, 1510, 1520, 1610-1640, 1710-1740, 1810-1840, 1910-1940, 2000, 2211-2243, 2301, 2302, 2401, 2402, 2403, 2500, 2601, 2602, 2701, 2702, 2801, 2802, 2803, 2804, 2901-2904, 3001-3004, 3101-3108, 3201- 3208, 3301-3302, 3400, 3510, 3601-3604, 3701-3704, 3801, 3802, 3801-1, 3801-2, 3802-1, 3802-2, 39011-390MN, 4001, 4002, 4101, 4102, 4201, 4202, 4301, 4302, 4401, 4402, 4500, 4600, 4701, 4702, 4801: Memory cell array structure 210, 220: Status 2311-1, 2311-2, 2312-1, 2312-2: Subsections 2501: Upper board 2502: Lower board 300, 400, 500, 600, 700, 800: Memory cell array structure 310, 410, 510, 610, 710, 810, 2311, 2312, 2411, 2412, 2411-1, 2411-2, 2412-1, 2412-2, 2611, 2612, 4111, 4132-1, 4132-2, 4510, 4610: Channel pillar 320, 330, 520, 530, 540, 620, 630, 640, 720, 730, 740, 820, 830, 840, 1320, 1412, 1413, 1414, 1422, 1423, 1424, 1512, 1522 , 1514, 1513, 1523, MS1, MS2, MS3, 420-1-440-3, 2114, 2124, 2124, 22C1-22C3, 2320-2324, 2331, 2332, 2340-2344, 2421, 2422, 2431, 2432, 2441, 2442, 2621, 2631, 2622, 2632, 2640, 2721, 2722, 2731, 2732, 3420, 3430, 3611, 3621, 3612, 3622, 4121, 4131, 4141, 4122, 4132, 4142, 4330, 4421, 4431, 4432, 4422, 4520, 4530, 4540, 4620, 4630, 4640, 4731, 4732: Conductive structure 331: Gate oxide film 3500, 3700, 3800, 3800′, 3900: Memory devices 3705, 3805: Peripheral circuits 3803, 3804, 3912, 3913: Addressing circuits 4800: Memory chip 48011-48052: Memory cell blocks 4811-4814: Buffer area 621, 631, CV1, 1414-1, 1414-2, 234C, 27211, 27311, 27221, 27321, 27411, 27421, 3421, 3431, 3441, 36111, 36211, 36121, 36221, 41421, 41422: Conductive plug BB1-BB4, WB1-WB4: Bus BL, BL1, BL2, BL_D, BL_U: bit lines BTBT, BTBT′: Band-to-band tunneling current CC1-CC5, 1210, 1220, 1240: Conductive coating CHP, DNW, 1110, 1200: Channel Pillar CI1-CI4, 1230: Dielectric layer CN1, CN2: Conductive vias CPZ: Capacitor Zone CS, CS1-CS4, CSA, CSA1, CSA2, CC1, DC1: Capacitors DG1, DG2: Gate structure DMC: Dummy circuit DS, DS1, DS2: Dielectric spacers DZ: Drain region Ec: conduction band Ev: valence band GP1, GP2: Partial GZ: gate region h1, h2: opening ILD1, ILD2, ILD: dielectric layers L1, L2: Structure LS: Length M1, M2, M11-M42: Transistors P1, P2: Interval distance PD1, PD2: Pads PLT, PLT1-PLT8: Common electrode plate S1: First section structure S2: Second section structure S910-S940: Step BLSA: Bit Line Sense Amplifier SiSub: Silicon substrate SN: Node SPC:Spacing SPR2, SPR1, SPR3: spacer structure ST1, ST2: Connection structure STI: Shallow Trench Isolation SZ: Source region T1, T2, T3: distance TAVW1, TAVW2, TAVB1, TAVB2, TAVW, TAVB, TAV: Conductive array via TZ: Transistor Zone VA1, VA2: Conductive vias WIR, MR1-MR4: Transmission wires WLa, WLa1, WLa2: auxiliary word lines WLd: Word line driver WLm, WLm1, WLm2: Primary word line X, Y, Z: Axes

Claims

1. a first transistor having a first end electrically coupled to a bit line, the gate of the first transistor being electrically coupled to a primary word line; a second transistor having a first end electrically coupled to the second end of the first transistor, the gate of the second transistor being electrically coupled to an auxiliary word line; a capacitor having an end electrically coupled to the second end of the second transistor, another end of the capacitor receiving a reference voltage; Equipped with A memory cell circuit, wherein the gate of the first transistor receives a first bias voltage and the gate of the second transistor receives a second bias voltage, the second bias voltage being greater than the first bias voltage.

2. A channel pillar and a first conductive structure surrounding the channel pillar and forming the gate of the first transistor, the first conductive structure being electrically coupled to the primary word line; a second conductive structure surrounding the channel pillar and forming the gate of the second transistor, the second conductive structure being electrically coupled to the auxiliary word line, with a spacing distance between the first conductive structure and the second conductive structure; the capacitor electrically coupled to an end of the channel pillar adjacent the second conductive structure; The memory cell circuit of claim 1 , comprising:

3. a first gate oxide layer formed between the first conductive structure and the channel pillar; a second gate oxide layer formed between the second conductive structure and the channel pillar; The memory cell circuit of claim 2 further comprising:

4. The capacitor is a plurality of outer conductive films, one end of each of the outer conductive films being electrically coupled to a common electrode plate; a plurality of internal conductive coatings, each of the internal conductive coatings being disposed between two adjacent external conductive coatings; a plurality of dielectric layers formed between each of the outer conductive coatings and adjacent ones of the inner conductive coatings; The memory cell circuit of claim 2 , comprising:

5. a plurality of channel pillars arranged in an array to form a plurality of channel pillar rows and a plurality of channel pillar columns; a plurality of first conductive structures electrically coupled to the plurality of channel pillar rows or the plurality of channel pillar columns, respectively, each of the plurality of first conductive structures surrounding a first portion of a channel pillar in each of the plurality of channel pillar rows or each of the plurality of channel pillar columns, each of the plurality of first conductive structures forming a common gate of a plurality of first transistors in each of the plurality of channel pillar rows or each of the plurality of channel pillar columns; at least one second conductive structure electrically coupled to the plurality of channel pillar rows or the plurality of channel pillar columns, each of the at least one second conductive structure surrounding a second portion of a channel pillar in each of the plurality of channel pillar rows or each of the plurality of channel pillar columns, wherein each of the at least one second conductive structure forms a common gate of a plurality of second transistors in each of the plurality of channel pillar rows or each of the plurality of channel pillar columns, and there is a spacing distance between the first portion and the second portion of the at least one second conductive structure; a plurality of capacitors each electrically coupled to an end portion of a channel pillar adjacent to the at least one second conductive structure; Equipped with a first conductive structure electrically coupled to a plurality of primary word lines, a second conductive structure electrically coupled to a plurality of auxiliary word lines, a common gate of the plurality of first transistors receiving a first bias voltage, and a common gate of the plurality of second transistors receiving a second bias voltage, the second bias voltage being greater than the first bias voltage;

6. 6. The memory cell array structure of claim 5, further comprising a plurality of third conductive structures each electrically coupled to the channel pillar column or the channel pillar row, and each electrically coupled to a plurality of bit lines.

7. The memory cell array structure of claim 6 , wherein the third conductive structure forms a step structure.

8. the extending direction of each of the first conductive structures is the same as the extending direction of each of the second conductive structures; 7. The memory cell array structure of claim 6, wherein an extension direction of each of said first conductive structures is different from an extension direction of each of said third conductive structures.

9. 6. The memory cell array structure of claim 5, further comprising a common plate electrically coupled to said capacitor, said common plate receiving a reference voltage.

10. 6. The memory cell array structure of claim 5, wherein the first conductive structure forms a first step structure and the second conductive structure forms a second step structure.

11. Each of the capacitors a plurality of first conductive films, one end of each of the first conductive films being electrically coupled to a common electrode plate; a plurality of second conductive films, each of the second conductive films being disposed between two adjacent first conductive films; a plurality of dielectric layers formed between each of the first conductive films and each adjacent one of the second conductive films; The memory cell array structure of claim 5 , comprising:

12. 6. The memory cell array structure of claim 5, wherein when the quantity of the at least one second conductive structure is 1, the second conductive structure is electrically coupled to the channel pillar row and forms a common gate of the second transistors in the channel pillar row.

13. 6. The memory cell array structure according to claim 5, wherein, on a reference plane, the arrangement positions of two adjacent first conductive structures are offset from each other, and the arrangement positions of two adjacent second conductive structures are offset from each other.

14. 6. The memory cell array structure of claim 5, wherein a distance between two adjacent channel pillars in a vertical direction is greater than twice the sidewall thickness of each of the first conductive structures, and a distance between two adjacent channel pillars in a horizontal direction is less than twice the thickness of each of the first conductive structures.

15. forming a plurality of channels on a wafer, the wafer being comprised of a plurality of alternating channel layers and a plurality of sacrificial layers; masking a gate region of the wafer and removing the sacrificial layers in source and drain regions of the wafer to form a plurality of source structures and a plurality of drain structures, respectively; masking the source and drain regions of the wafer and dividing the gate region into a first division and a second division; forming a plurality of first conductive structures and at least one second conductive structure in the first division and the second division, respectively, wherein each of the first conductive structures is a first common gate of a plurality of first transistors and each of the second conductive structures is a second common gate of a plurality of second transistors; forming a plurality of third conductive structures, each of the third conductive structures electrically coupled to the source structures, each of the third conductive structures electrically coupled to a source structure column or a source structure row; 2. A method for manufacturing a memory cell array structure, comprising:

16. When each of the third conductive structures is electrically coupled to the row of source structures, the manufacturing method includes: The method of claim 15 further comprising forming a step structure with the third conductive structure.

17. 16. The method of claim 15, further comprising forming a plurality of conductive plugs on the third conductive structures, respectively, so that the third conductive structures are electrically coupled to a plurality of bit lines via the conductive plugs, respectively.

18. When each of the third conductive structures is electrically coupled to the column of source structures, the manufacturing method includes: forming a first step structure with the first conductive structure; forming a second step structure with the second conductive structure; The method of claim 15 further comprising:

19. forming a plurality of first conductive plugs on the first conductive structures, respectively, such that the first conductive structures are electrically coupled to a plurality of primary word lines via the first conductive plugs; forming a plurality of second conductive plugs on the second conductive structures, respectively, so that the second conductive structures are electrically coupled to a plurality of auxiliary word lines via the second conductive plugs; The method of claim 18 further comprising:

20. The method of claim 18 further comprising forming a plurality of capacitors, each of the capacitors being electrically coupled to the drain structure.

21. The step of forming the capacitor includes: forming a plurality of inner conductive films on a surface of the drain structure; forming a plurality of dielectric layers on a surface of the inner conductive coating; forming a plurality of outer conductive coatings on a surface of the dielectric layer; The method of claim 20, comprising:

22. After forming the inner conductive coating on the surface of the drain structure, The method of claim 21 further comprising removing a portion of the drain structure between the inner conductive coatings.

23. 16. The manufacturing method according to claim 15, wherein a thickness of the sacrificial layer is greater than twice the thickness of a sidewall of the first conductive structure, and a distance between two adjacent channel pillars on a horizontal line among the channel pillars each surrounded by the first conductive structure is less than twice the thickness of the first conductive structure.

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